Relay protection test processing method and device, electronic equipment and storage medium

Abstract

The application discloses a kind of relay protection test processing method, device, electronic equipment and storage medium, wherein, the method comprises: central processing unit sends configuration parameter to field programmable gate array by fast channel interface, the field programmable gate array carries out clock synchronization according to the configuration parameter;After detecting that the clock synchronization is completed, power system message is received by the field programmable gate array, and the power system message is written in dynamic random access memory;The central processing unit reads the power system message from the dynamic random access memory, and determines to be transmitted data stream according to the power system message, and sends the to be transmitted data stream by the field programmable gate array.Based on the above technical scheme, the accurate processing and seamless switching of digital-analog mixed signal are realized, and the accurate synchronization control of digital-analog signal is realized, to ensure the consistency of digital and analog output.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electric power, and particularly relates to a processing method and device for relay protection test, electronic equipment and storage medium. BACKGROUND

[0002] A relay protection tester is an instrument for detecting and verifying a relay protection device, which plays a crucial role in an electric power system and is used to ensure safe and reliable operation of the electric power system. The relay protection tester tests and evaluates the relay protection device by simulating various signals and fault conditions in the electric power system, and can generate various fault conditions and test scenarios by simulating current, voltage and other parameters in the electric power system.

[0003] However, most of the conventional relay protection testers adopt an imported chip scheme, excessively rely on imported chips, and cannot adapt to harsh field environments in actual electric power system application scenarios. SUMMARY

[0004] The present application provides a processing method and device for relay protection test, electronic equipment and storage medium, which realizes accurate processing and seamless switching of digital-analog mixed signals, and realizes accurate synchronization control of digital-analog signals, thereby ensuring consistency of digital and analog outputs.

[0005] According to an aspect of the present application, a processing method for relay protection test is provided, which comprises the following steps:

[0006] The central processor sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters;

[0007] After detecting that the clock synchronization is completed, the field programmable gate array receives an electric power system message and writes the electric power system message into a dynamic random access memory;

[0008] The central processor reads the electric power system message from the dynamic random access memory, determines a to-be-transmitted data stream according to the electric power system message, and sends the to-be-transmitted data stream through the field programmable gate array.

[0009] According to another aspect of the present application, a processing device for relay protection test is provided, which comprises the following steps:

[0010] The synchronization test module comprises a central processor, a field programmable gate array and a fast channel interface.

[0011] The message receiving module is configured to receive a power system message through the field programmable gate array after detecting that the clock synchronization is completed, and write the power system message into a dynamic random access memory.

[0012] The data sending module is configured to read the power system message from the dynamic random access memory by the central processing unit, determine a data stream to be transmitted according to the power system message, and send the data stream to be transmitted through the field programmable gate array.

[0013] According to another aspect of the present application, an electronic device is provided, which comprises:

[0014] at least one processor; and

[0015] a memory connected to the at least one processor in communication; wherein

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the processing method for the relay protection test according to any one of the embodiments of the present application.

[0017] According to another aspect of the present application, a computer readable storage medium is provided, which stores computer instructions for enabling a processor to implement the processing method for the relay protection test according to any one of the embodiments of the present application when executed.

[0018] The technical solution of the embodiments of the present application sends configuration parameters to a field programmable gate array through a fast channel interface by a central processing unit, the field programmable gate array performs clock synchronization according to the configuration parameters, and receives a power system message through the field programmable gate array after detecting that the clock synchronization is completed, and writes the power system message into a dynamic random access memory, and then the central processing unit reads the power system message from the dynamic random access memory, determines a data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array. Based on the above technical solution, accurate processing and seamless switching of digital-analog mixed signals are realized, and accurate synchronization control of digital-analog signals is realized, thereby ensuring the consistency of digital and analog outputs.

[0019] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the technical solution in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0021] Figure 1 is a flow chart of a processing method of relay protection test according to the embodiment one of the present application;

[0022] Figure 2 is a schematic diagram of message receiving according to the embodiment one of the present application;

[0023] Figure 3 is a schematic diagram of data sending according to the embodiment one of the present application;

[0024] Figure 4 is a design diagram of internal timing synchronization of field programmable gate array according to the embodiment one of the present application;

[0025] Figure 5 is a structural schematic diagram of a processing device of relay protection test according to the embodiment two of the present application;

[0026] Figure 6 is a structural schematic diagram of an electronic device according to the embodiment three of the present application. DETAILED DESCRIPTION

[0027] In order to make the technical solution in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0028] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include all the steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] Embodiment one

[0030] Figure 1 A flow chart of a processing method of a relay protection test is provided for embodiment one of the present application. The embodiment can be applicable to the case where a central processing unit and a field programmable gate array provided in a relay tester process system messages and output data streams. The method can be executed by a relay protection test processing device, which can be realized in the form of hardware and / or software, and can be configured in an electronic device. As shown in the figure, the method comprises the following steps. Figure 1

[0031] S110, the central processing unit sends configuration parameters to the field programmable gate array through a fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters.

[0032] The central processing unit can be understood as an operation and control core provided in the relay tester, which is responsible for reading instructions, decoding instructions and executing instructions. The fast channel interface can be a high-speed serial computer expansion bus standard. The configuration parameters can be parameters for instructing the field programmable gate array to perform clock synchronization, which can include clock frequency, count start value and the like. The field programmable gate array is an SRAM type field programmable gate array based on FMSH-K7 series.

[0033] Specifically, the central processing unit sends configuration parameters to the field programmable gate array through the fast channel interface. The configuration parameters can include clock frequency, phase adjustment, data format and the like, which are used to guide the field programmable gate array to perform clock synchronization and other related operations. After the field programmable gate array receives the configuration parameters sent by the central processing unit through the fast channel interface, it performs clock synchronization according to the parameters. It should be noted that clock synchronization is the key to ensure the coordinated work of each module inside the field programmable gate array and between the field programmable gate array and other system components. For example, the field programmable gate array first receives the configuration parameters sent by the central processing unit through the fast channel interface. The field programmable gate array parses the received configuration parameters and extracts the key information required for clock synchronization. Then, according to the parsed configuration parameters, the field programmable gate array adjusts the frequency, phase and the like of its internal clock to realize clock synchronization with other system components. For example, the CPU issues parameters through PCIE, the FPGA parses the parameters, then sets the clock source according to the parameters, adjusts the count according to the clock source, and outputs the synchronization signal according to the clock source

[0034] ​It should be noted that the relay tester in the embodiment of the application can be composed of an ARM+FPGA main control core board unit, the ARM adopts an advanced domestic MPU manufacturer Rockchip-RK3568, the RK3568 is a general-purpose SoC of a medium and high-end positioning produced by Rockchip, adopts an advanced 22nm process technology, integrates a 4-core arm architecture A55 processor and a Mali G522EE graphic processor, supports 4K decoding and 1080P encoding. The RK3568 supports various types of peripheral interfaces such as SATA / PCIE / USB3.0. The RK3568 is mainly responsible for the man-machine interface, real-time algorithm and message processing. The high-speed pcie interface provides real-time communication. The FPGA is mainly responsible for protocol conversion, outputs the ARM calculation result to the power amplifier device through digital-to-analog conversion DAC, and outputs the calculation result in the form of a message, strictly ensuring the synchronous output of analog and digital quantities. High-precision voltage and current output, low-jitter message transmission are realized, which meets the needs of various protection devices for the increase in quantity. Rich external interfaces are provided to interact with other devices to exchange data. Various time synchronization modes are suitable for multi-machine synchronization test requirements in various occasions. According to the requirements of high precision and wide frequency band for relay protection test, a domestic chip with 24bit high precision is selected as the core device. And through the FPGA, the digital signals obtained by the ADC sampling are processed such as filtering and correction, further improving the signal-to-noise ratio and dynamic range of the sampling signals. According to different ADC characteristics and noise environment, the FPGA is used to realize adaptive filtering algorithm, and the filter parameters are dynamically adjusted to achieve the best filtering effect.

[0035] S120, after detecting that the clock synchronization is completed, receiving a power system message through the field programmable gate array, and writing the power system message into a dynamic random access memory.

[0036] The power system message can be understood as a message generated in the process of power system fault simulation, for example, it can be an FT3, SMV, GOOSE message, etc. The dynamic random access memory can be an internal memory provided in the relay tester and can directly exchange data with the central processing unit, for example, it can be a dynamic random access memory of DDR3 specification.

[0037] Specifically, the field programmable gate array first confirms that the clock synchronization has been successfully completed, which can be confirmed by checking the synchronization signal, phase difference or timestamp, etc. to ensure that all related components are running in the same clock domain, and then the clock synchronization is completed. After determining that the clock synchronization is completed, the field programmable gate array is ready to receive the message from the power system. Before accepting the message, the receiving buffer can be configured, the interrupt or polling mechanism can be set to detect the newly arrived message, etc. The field programmable gate array receives the message from the power system through its interface, such as an Ethernet interface, a serial communication interface, etc. The message can contain various types of data, such as measurement values, state information, control instructions, etc. Before writing the message into the dynamic random access memory, the field programmable gate array may need to initialize or configure the dynamic random access memory first. This includes setting the working mode, refresh rate and other parameters of the dynamic random access memory. The field programmable gate array writes the verified power system message into the dynamic random access memory.

[0038] On the basis of the above technical solution, after the field programmable gate array receives the power system message, the field programmable gate array adds message identification information to the head of the power system message.

[0039] Among them, the message identification information at least includes one of time stamp, frame count value, channel, rate and type.

[0040] Specifically, the field programmable gate array receives FT3, SMV, GOOSE and other messages, and adds time stamp, frame count value, channel, rate, type and other information to the message header, thereby ensuring the accuracy and integrity of the message.

[0041] On the basis of the above technical solution, the field programmable gate array stores the power system message into the primary cache based on the field programmable gate array, and sends a trigger signal to the state machine after the storage is completed. The state machine writes the power system message into the dynamic random access memory according to the trigger signal.

[0042] Among them, the primary cache can be understood as a temporary storage area for message data.

[0043] Specifically, when the field programmable gate array receives the power system message, it first temporarily stores the message data in the internal primary cache (such as FIFO, dual-port RAM, etc.), which serves as a temporary storage area and can quickly receive and temporarily store the message data, providing a buffer for subsequent processing. When the message data is completely stored in the primary cache, the field programmable gate array sends a trigger signal to the state machine. The trigger signal is a flag used to inform the state machine that new message data needs to be further processed and written into the DRAM. After receiving the trigger signal sent by the field programmable gate array, the state machine enters the corresponding processing state. The state machine is a key component that controls data flow and state transition, and can determine the next operation according to the trigger signal and the current system state. Under the control of the state machine, the field programmable gate array starts reading the message data from the primary cache and writes these data into the DRAM through the DRAM interface.

[0044] On the basis of the above technical solution, the state machine writes the power system message into the dynamic random access memory according to the trigger signal, including: after receiving the trigger signal, the state machine determines the storage state of the secondary cache, and in the case that the storage state is idle, the power system message is transferred to the secondary cache; the power system message is written into the dynamic random access memory through the secondary cache.

[0045] Specifically, after the state machine receives the trigger signal, it checks the storage state of the secondary cache to ensure that there is enough space in the secondary cache to store the message data before transferring the data to the secondary cache, avoiding data overflow or overwrite. If the storage state of the secondary cache is idle, i.e., there is enough space to store new message data, the state machine instructs the field programmable gate array to transfer the power system message from the primary cache to the secondary cache. By temporarily storing data in the secondary cache, message data can be further buffered, and data access conflicts when directly writing to the DRAM can be reduced. If the storage state of the secondary cache is not idle, i.e., the space is insufficient or has been occupied, the state machine needs to take appropriate processing measures, including waiting for the secondary cache to release space, overwriting old data (according to the importance of data and update strategy), or reporting an error to the system and requesting further instructions. When the power system message is successfully transferred to the secondary cache, the state machine coordinates the data transmission between the secondary cache and the DRAM, i.e., the state machine instructs the secondary cache to write the message data into the DRAM. When the message data is successfully written into the DRAM, the state machine updates the system state and sends a write completion signal to the field programmable gate array. At the same time, the state machine also updates the storage state information of the secondary cache to facilitate the processing of subsequent message data.

[0046] For example, the state machine can be implemented by a state machine circuit, and the trigger signal can be a trigger signal generated by a trigger circuit. Figure 2As shown, after receiving FT3, SMV, GOOSE message, etc., the time stamp and frame count value, channel, rate, type and other information are added to the head of the message and stored in the primary RAM. After the RAM of each path stores an array of information, a trigger signal is initiated to inform that data is coming, and then the state machine judges whether the current secondary RAM currently has other road RAM storage operation, and if so, the other road waits. After the secondary RAM has data, the write data information to the DDR3 is initiated, and the CPU is notified of the data after the write is completed, and waits for the CPU to take the data.

[0047] S130, the central processor reads the power system message from the dynamic random access memory, and determines the to-be-transmitted data stream according to the power system message, and sends the to-be-transmitted data stream through the field programmable gate array.

[0048] Among them, the to-be-transmitted data stream can be understood as the to-be-sent data generated by the central processor after processing the message.

[0049] Specifically, the central processor first sends a read request to the DRAM through the address bus according to the storage address of the power system message in the DRAM. After receiving the read request, the DRAM locates the corresponding storage unit according to the address information provided by the address line, and transmits the stored power system message data to the central processor through the data bus. Then, after the central processor receives the power system message data transmitted from the DRAM, it stores it in the internal register or cache. The central processor parses and processes the received power system message, extracts key information such as the format, content, and destination of the data packet, and determines the data stream to be transmitted according to the content and analysis results of the power system message, including filtering specific measurement data, state information, control instructions, etc. It should be noted that the central processor can also format, encode or encrypt the data according to the current state of the system and the requirements of the communication protocol. The central processor transmits the processed to-be-transmitted data stream to the field programmable gate array through the internal bus. After the field programmable gate array receives the to-be-transmitted data stream transmitted by the central processor, it sends these data streams to the target receiver through the external interface (such as Ethernet interface, serial communication interface, etc.) according to the pre-configured transmission strategy and data forwarding rule

[0050] On the basis of the above technical scheme, the central processor reads the power system message from the dynamic random access memory, including: the field programmable gate array sends the data read instruction to the central processor when detecting that the dynamic random access memory has the power system message; the central processor reads the power system message from the dynamic random access memory in response to the data read instruction.

[0051] Specifically, the field programmable gate array continuously monitors the access state and data storage of the DRAM, checks the data flag of a specific address region in the DRAM to determine whether the power system message has been stored in the DRAM, and generates a data read instruction when the field programmable gate array detects the power system message in the DRAM, wherein the instruction contains necessary information such as the storage address of the message in the DRAM and the read length. The field programmable gate array sends the generated data read instruction to the central processing unit through an internal communication bus or other interfaces. After receiving the data read instruction sent by the field programmable gate array, the central processing unit decodes and processes the instruction, obtains the storage position of the message in the DRAM and the read requirement, and sends a read request to the DRAM through an address bus according to the data read instruction, and specifies the address range to be read. The RAM responds to the read request of the central processing unit, and transmits the stored power system message data to the central processing unit through a data bus. The central processing unit receives the data and stores them in internal registers or caches.

[0052] On the basis of the above technical scheme, the field programmable gate array sends the to-be-transmitted data stream, comprising: the field programmable gate array divides the to-be-transmitted data stream according to transmission configuration information, and stores the divided to-be-transmitted data stream in a cache; and the field programmable gate array reads the to-be-transmitted data stream from the cache according to internal time and outputs the to-be-transmitted data stream according to the appointed time.

[0053] Specifically, according to the transmission configuration information, the field programmable gate array divides the to-be-transmitted data stream into a plurality of smaller data blocks or data packets, and then writes the divided data packets into the cache in sequence, waits for subsequent reading and output, and then the field programmable gate array reads the to-be-transmitted data stream from the cache according to internal time and outputs the to-be-transmitted data stream according to the appointed time. For example, as shown in Figure 3 The CPU first sends the configuration to the FPGA, and then sends the data stream, and then the FPGA groups and caches the multi-channel data stream according to the configuration, and finally the FPGA takes and outputs the data according to the internal time according to the appointed time.

[0054] It should be noted that the present application uses a high-performance FPGA to realize hardware acceleration and precise time control, to ensure the synchronization of digital and analog signals, as shown in Figure 4As shown, the clock synchronization design is to ensure the precise synchronization of ADC sampling and DAC output, as well as the timing consistency of various modules inside the FPGA. The built-in PLL (Phase-Locked Loop) or DCM (Clock Management Module) of the FPGA is used to generate and distribute precise clock signals. Through the design of the clock tree, it is ensured that all modules work within the same clock domain, or through clock conversion to ensure the correct transmission of data across clock domains. Data buffers are used to store ADC sampling data and DAC output data, ensuring the order and integrity of the data. The Block RAM or distributed RAM of the FPGA is used to implement the data buffer, and the specific data structure uses FIFO to store the corresponding data, ensuring the sequential processing and synchronization of the data. In order to further improve the reliability of the system, the FPGA will also filter the ADC sampling data through an adaptive filter. The adaptive filtering algorithm based on FPGA uses the least mean square (LMS) algorithm. The LMS algorithm is an adaptive filtering algorithm suitable for FPGA implementation, suitable for real-time signal processing, and its basic principle is to adjust the filter coefficients by minimizing the mean square value of the error signal, including: initializing the filter coefficients: selecting an initial value, usually zero or a small random number such as a value between 0 and 1, as the initial value of the filter coefficients. Sample the input signal: read the input signal from the ADC sampling data, ensuring that the sampling frequency meets the Nyquist sampling theorem to avoid aliasing. Calculate the current error signal: calculate the difference between the output signal and the expected signal, through the formula Calculate the difference between the output signal and the expected signal, where e(n) is the error signal, d(n) is the expected signal, wk(n) is the kth filter coefficient, and x(n) is the input signal. Adjust the filter coefficients according to the error signal: use the LMS update rule to adjust the filter coefficients. Based on the formula w k (n+1)=w k (n)+μe(n)x(n-k) adjusts the filter coefficients, where μ is the step parameter, which controls the convergence speed and stability of the algorithm. Repeat the above steps to continuously update the filter coefficients until the predetermined number of iterations or the error meets the requirements. Select an appropriate step parameter μ and filter length N.

[0055] The technical scheme of the embodiment of the application is that the central processor sends configuration parameters to the field programmable gate array through the fast channel interface, the field programmable gate array performs clock synchronization according to the configuration parameters, and after detecting that the clock synchronization is completed, the field programmable gate array receives power system messages and writes the power system messages into the dynamic random access memory, then the central processor reads the power system messages from the dynamic random access memory, determines a data stream to be transmitted according to the power system messages, and sends the data stream to be transmitted through the field programmable gate array. Based on the above technical scheme, accurate processing and seamless switching of digital-analog mixed signals are realized, and accurate synchronization control of digital-analog signals is realized, thereby ensuring consistency of digital and analog outputs.

[0056] Embodiment two

[0057] Figure 2 A structural schematic diagram of a processing device for relay protection test is provided for the second embodiment of the application. As shown in the figure, the device comprises a synchronization test module 510, a message receiving module 520 and a data sending module 530; wherein, Figure 5

[0058] The synchronization test module 510 is configured to send configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters.

[0059] The message receiving module 520 is configured to, after detecting that the clock synchronization is completed, receive power system messages through the field programmable gate array, and write the power system messages into the dynamic random access memory.

[0060] The data sending module 530 is configured to read the power system messages from the dynamic random access memory by the central processor, determine a data stream to be transmitted according to the power system messages, and send the data stream to be transmitted through the field programmable gate array.

[0061] On the basis of the above technical scheme, the message receiving module is configured to store the power system messages into a primary cache based on the field programmable gate array, and send a trigger signal to a state machine after the storage is completed; the state machine writes the power system messages into the dynamic random access memory according to the trigger signal.

[0062] On the basis of the above technical scheme, the message receiving module is configured to, after the state machine receives the trigger signal, determine a storage state of a secondary cache, and in the case that the storage state is idle, store the power system messages into the secondary cache; the power system messages are written into the dynamic random access memory through the secondary cache.​

[0063] On the basis of the above technical scheme, the data sending module is used for sending the data reading instruction to the central processing unit when the field programmable gate array detects that the power system message exists in the dynamic random access memory.

[0064] On the basis of the above technical scheme, the data sending module is used for dividing the to-be-transmitted data stream according to the transmission configuration information, and storing the divided to-be-transmitted data stream into the cache; and the field programmable gate array reads the to-be-transmitted data stream from the cache according to the internal time and outputs the to-be-transmitted data stream according to the appointed time.

[0065] On the basis of the above technical scheme, the message receiving module is used for adding message identification information to the head of the power system message, wherein the message identification information at least includes one of a time stamp, a frame count value, a channel, a rate and a type.

[0066] On the basis of the above technical scheme, the field programmable gate array is an SRAM type field programmable gate array based on the FMSH-K7 series.

[0067] The technical scheme of the embodiment of the present application sends the configuration parameters to the field programmable gate array through the central processing unit through the fast channel interface, the field programmable gate array performs clock synchronization according to the configuration parameters, and after detecting that the clock synchronization is completed, the field programmable gate array receives the power system message and writes the power system message into the dynamic random access memory, and then the central processing unit reads the power system message from the dynamic random access memory, determines the to-be-transmitted data stream according to the power system message, and sends the to-be-transmitted data stream through the field programmable gate array. Based on the above technical scheme, accurate processing and seamless switching of digital-analog mixed signals are realized, accurate synchronization control of digital-analog signals is realized, and consistency of digital and analog outputs is ensured.

[0068] The processing device for relay protection test provided in the embodiment of the present application can execute the processing method for relay protection test provided in any embodiment of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0069] Embodiment three

[0070] Figure 6A structural diagram of an electronic device 10 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application described and / or claimed in this document.

[0071] As shown in Figure 6 The electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., communicatively connected to the at least one processor 11, where the memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer programs stored in the read-only memory (ROM) 12 or loaded into the random access memory (RAM) 13 from the storage unit 18. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0072] Various components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc., an output unit 17, such as various types of displays, speakers, etc., a storage unit 18, such as a magnetic disk, an optical disk, etc., and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0073] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the process method of the relay protection test.

[0074] In some embodiments, the processing method of the relay protection test can be implemented as a computer program tangibly embodied in a computer readable storage medium, e.g., storage unit 18. In some embodiments, portions or all of the computer program can be loaded onto the electronic device 10 via, e.g., ROM 12 and / or communication unit 19. When the computer program is loaded onto RAM 13 and executed by processor 11, one or more steps of the processing method of the relay protection test described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the processing method of the relay protection test by any other suitable means, e.g., by means of firmware.

[0075] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0076] Computer programs used to implement the processes of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program, when executed, implements the functions / acts specified in the flowcharts and / or block diagrams. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0077] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0078] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0079] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0080] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0081] It should be understood that the various forms of flow shown above can be reordered, added to, or have steps deleted. For example, the steps described in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0082] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for processing relay protection test, characterized in that: include: The central processing unit sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters; After detecting that the clock synchronization is completed, receiving a power system message through the field programmable gate array and writing the power system message into a dynamic random access memory; The central processing unit reads the power system message from the dynamic random access memory, determines a data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

2. The method according to claim 1, characterized in that Writing the power system message into a dynamic random access memory includes: storing the power system message in a primary cache based on the field programmable gate array, and sending a trigger signal to a state machine after storage is completed; The state machine writes the power system message into a dynamic random access memory according to the trigger signal.

3. The method according to claim 2, characterized in that The state machine writes the power system message into a dynamic random access memory according to the trigger signal, comprising: After receiving the trigger signal, the state machine determines the storage state of the secondary cache, and if the storage state is idle, transfers the power system message to the secondary cache; The power system message is written into the dynamic random access memory through the secondary cache.

4. The method according to claim 1, wherein The central processing unit reads the power system message from the dynamic random access memory, including: The field programmable gate array sends a data read instruction to the central processing unit when detecting that the power system message exists in the dynamic random access memory; The central processing unit reads the power system message from the dynamic random access memory in response to the data read instruction.

5. The method according to claim 1, wherein The sending the data stream to be transmitted through the field programmable gate array includes: The field programmable gate array divides the data stream to be transmitted according to the transmission configuration information, and stores the divided data stream to be transmitted in a cache; The field programmable gate array reads the data stream to be transmitted from the cache according to internal timing and at an agreed time and outputs the data stream.

6. The method according to claim 1, characterized in that After receiving the power system message through the field programmable gate array, the method further includes: The field programmable gate array adds message identification information to the header of the power system message, wherein the message identification information includes at least one of a time stamp, a frame count value, a channel, a rate, and a type.

7. The method according to claim 1, characterized in that The field programmable gate array is an SRAM field programmable gate array based on the FMSH-K7 series.

8. A processing device for relay protection testing, characterized in that: include: Synchronous test module, the central processing unit sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters; a message receiving module, configured to receive a power system message through the field programmable gate array after detecting that the clock synchronization is completed, and write the power system message into a dynamic random access memory; The data sending module is configured to read the power system message from the dynamic random access memory, determine the data stream to be transmitted according to the power system message, and send the data stream to be transmitted through the field programmable gate array.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to execute the processing method for relay protection testing according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the processing method for relay protection testing according to any one of claims 1 to 7 when executed.

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