Fault analysis device and fault analysis method

Abstract

The invention relates to a fault analysis apparatus and a fault analysis method. A failure analysis device is for analyzing a failure of a semiconductor device equipped with a logic circuit and a memory circuit. The system has a storage device and a processor. The storage device stores fault bit data obtained by testing the memory circuit and fault diagnosis data obtained by performing fault diagnosis on a test result of the logic circuit. The processor extracts a fault I / O value from the fault bit data, extracts data of a memory connection port, which is a connection port to the memory circuit, from an estimated fault portion included in the fault diagnosis data, and determines that the fault I / O value matches / does not match a port ID included in the data of the memory connection port.

Description

Technical Field

[0001] The invention relates to fault equipment and a fault analysis method. Background Art

[0002] The disclosed techniques are listed below.

[0003] [Patent Document 1] U.S. Patent Application No. 11288435

[0004] Patent document 1 shows a fault analysis device capable of improving fault analysis efficiency. The fault analysis device uses a layout tool to display the location of the physical coordinates of the fault bit in the memory and the logical fault part to associate the memory fault with the logical fault. Under this association, the fault analysis device extracts the logical fault part having the shortest total distance to the multiple fault bits from the multiple logical fault parts, and determines that the extracted logical fault part is related. Summary of the invention

[0005] Generally, logic fault analysis and memory fault analysis are performed independently because the analysis methods are different from each other. On the other hand, in recent years, semiconductor devices in which logic circuits and memory circuits are mixed are widely used, for example, SoC (System on Chip) for vehicles. When testing this logic circuit in a semiconductor device, the memory circuit can be pointed out as an estimated fault part. Specifically, for example, a port in the logic circuit for accessing the memory circuit can be pointed out as an estimated fault part.

[0006] However, in this case, the faulty part that is the root cause of the fault occurrence does not always exist in the logic circuit, but may also exist in the memory circuit. Similarly, if a fault bit is generated by testing a memory circuit in a semiconductor device, the faulty part that is the root cause of the fault bit may not always exist in the memory circuit, but may exist in the logic circuit.

[0007] Therefore, in each case, in order to identify or narrow down the faulty part, for example, a certain wide area, it is necessary to perform emission analysis or the like. However, emission analysis leads to an increase in analysis man-hours. On the other hand, in order to increase the yield of semiconductor devices, it is necessary to identify the faulty part and narrow down the range. Therefore, it is desirable to identify the faulty part without emission analysis or the like, or an effective analysis method capable of narrowing down the range.

[0008] As one method, for example, as shown in Patent Document 1, there is a method for identifying a logical fault portion having the shortest total distance from a plurality of fault bits as a fault portion associated with the fault bit. However, in some layouts, the fault bit may be associated with the longest fault portion at a certain distance from the fault bit among the plurality of logical fault portions, rather than with the shortest fault portion at a certain distance from the fault bit. Therefore, in practice, it is necessary to perform proofreading between the layout and the circuit diagram, etc. separately, and an increase in analysis man-hours may occur.

[0009] In addition, when a faulty part is identified by distance calculation based on physical coordinates, for example, in a case such as shrinking a semiconductor device, there is a possibility that an error occurs. Specifically, for example, the physical coordinates on the layout tool calculated based on the faulty bit may deviate from the physical coordinates of the faulty bit in the actual semiconductor device. This is because, for example, in GDS-II or the like, which is a standard format for layout data, when shrinking is performed, rounding errors occur in the coordinates. Therefore, if an error occurs in the physical coordinates on the layout tool, the distance calculation may not be performed correctly.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] Therefore, the fault analysis device of the embodiment is used to analyze the fault of a semiconductor equipped with a logic circuit and a memory circuit, and has a storage device and a processor. The storage device stores the fault bit data obtained by testing the memory circuit and the fault diagnosis data obtained by fault diagnosis of the test result of the logic circuit. The processor extracts the fault I / O value from the fault bit data, extracts the data of the memory connection port, which is the connection port to the memory circuit, from the estimated fault part included in the fault diagnosis data, and determines the match / mismatch between the fault I / O value and the port ID included in the data of the memory connection port.

[0012] By using the failure analysis device of the embodiment, the efficiency of failure analysis can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram showing a configuration example of a failure analysis system according to the first embodiment.

[0014] Figure 2 is shown by using Figure 1 A functional block diagram of a configuration example of a main part of a failure analysis device implemented by the configuration.

[0015] Figure 3 It is shown Figure 2 Diagram of the main processing contents of the estimated fault part limitation unit.

[0016] Figure 4A is shown Figure 2 FIG. 1 is a diagram of an exemplary process of limiting the estimated fault portion by the estimated fault portion limiting unit in FIG. 1 .

[0017] Figure 4B yes Figure 4A 0 is a specific example of the process details shown in , and is a diagram showing an example of a schematic layout around an estimated faulty portion.

[0018] Figure 5 The present invention is a diagram showing the use of the failure analysis method according to the first embodiment. Figure 1 and Figure 2 A flowchart of an example of the processing content of the failure analysis system is shown in FIG.

[0019] Figure 6 It is shown Figure 5 This is a flowchart showing an example of the subsequent processing contents.

[0020] Figure 7 is a schematic diagram showing a configuration example of a failure analysis system according to the second embodiment.

[0021] Figure 8 is shown by using Figure 7 A functional block diagram of a configuration example of a main part of a failure analysis device implemented by the configuration.

[0022] Fig. 9 It is shown Figure 7 and Figure 8 A plot of example EDA data.

[0023] Fig. 10A It is shown Figure 8 A diagram of an exemplary process for limiting the estimated fault portion in the estimated fault portion limiting section.

[0024] Fig. 10B yes Fig. 10A 0 is a specific example of the process details shown in , and is a diagram showing an example of a schematic layout around an estimated faulty portion.

[0025] Fig.11 The failure analysis method according to the second embodiment is shown in FIG. Figure 5 This is a flowchart showing an example of the subsequent processing contents. DETAILED DESCRIPTION

[0026] In the following embodiments, for convenience, the embodiments are described by dividing them into multiple parts or embodiments, but unless otherwise specified, they are not independent of each other, and one part or embodiment involves modified examples, details, supplementary explanations, etc. of some or all of the other parts or embodiments.

[0027] In the following embodiments, the number of elements and the like (including the number of elements, values, quantities, ranges, etc.) is not limited to a specific number, but may be not less than or equal to a specific number, unless otherwise specified and is clearly limited to a specific number in principle.

[0028] Furthermore, in the following embodiments, it is needless to say that constituent elements (including element steps and the like) are not essential except for cases where they are particularly specified and cases where they are considered to be obviously essential in principle.

[0029] Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of components, etc., it is assumed that the shapes, etc. are substantially similar or similar to the shapes, etc., unless they are specifically specified and are considered to be obviously necessary in principle. The same provisions apply to the above-mentioned numerical values ​​and ranges.

[0030] In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals, and repeated descriptions thereof are omitted. In the following embodiments, descriptions of the same or similar parts will not be repeated in principle unless particularly necessary.

[0031] (First embodiment)

[0032] (Configuration of the fault analysis system)

[0033] Figure 1 is a schematic diagram showing a configuration example of a failure analysis system according to the first embodiment. Figure 1 The failure analysis system shown in FIG. 1 includes an LSI (Large Scale Integration) tester 100, a communication network 200, a computer 300, and a display device 350. The communication network 200 may be, for example, a wired LAN (Local Area Network) or a wireless LAN, for connecting the LSI tester 100 and the computer 300. The display device 350 may be, for example, a liquid crystal display or an organic (electroluminescent) display, etc., and displays various information based on instructions from the computer 300.

[0034] For example, the LSI tester 100 is composed of a logic tester and the like. In addition, the device to be tested is a semiconductor device equipped with a logic circuit and a memory circuit. For example, the memory circuit is an SRAM and the like. The LSI tester 100 tests the logic circuit and the memory circuit installed in the semiconductor device. In this case, for example, a memory BIST (built-in self-test) circuit as a part of the logic circuit is used to test the memory circuit. The LSI tester 100 transmits the logic failure data 325 as the test result of the logic circuit and the failure bit data 322 as the test result of the memory circuit to the computer 300 through the communication network 200.

[0035] The computer 300 includes a processor 310 and a storage device 320. The storage device 320 includes, for example, a hard disk drive, an SSD (Solid State Drive), a nonvolatile storage device such as a flash memory, and a volatile storage device such as a RAM (Random Access Memory). The storage device 320 stores a fault analysis tool 329 and a layout tool 330 as programs. When the processor 310 executes the fault analysis tool 329 and the layout tool 330, the computer 300 functions as an error analysis device.

[0036] The storage device 320 also stores as data the failure bit data 322 and the logic failure data 325 from the LSI tester 100. In addition to this, the storage device 320 stores memory circuit data 321, physical address data 323, memory failure data 324, failure diagnosis data 326, data 327 of a memory connection port, and layout data 328. The layout data 328 is used by the layout tool 330 to display the layout of the semiconductor device on the display device 350, for example.

[0037] Figure 2 is shown by using Figure 1 A functional block diagram of a configuration example of a main part of a failure analysis device implemented by the configuration. Figure 2 The failure analysis device 400 shown in FIG. 4 is a device for analyzing failures of a semiconductor device including a memory circuit and a logic circuit. The failure analysis device 400 includes a physical address conversion unit 331, a failure I / O extraction unit 332, a failure mode classification unit 333, a memory failure data generation unit 334, a logic failure diagnosis unit 335, a memory connection port (MCP) extraction unit 336, an estimated failure part restriction unit 337, and a display control unit 338.

[0038] The physical address conversion unit 331, the fault I / O extraction unit 332, the fault mode classification unit 333, the memory fault data generation unit 334, the logical fault diagnosis unit 335, the memory connection port (MCP) extraction unit 336, and the estimated fault part limitation unit 337 are implemented by the processor 310 executing the fault analysis tool 329 stored in the storage device 320. The display control unit 338 is implemented by executing the layout tool 330 in which the memory 310 is stored in the storage device 320.

[0039] The failure analysis device 400 stores memory circuit data 321, failure bit data 322, physical address data 323, memory failure data 324, logical failure data 325, failure diagnosis data 326, and data 327 of a memory connection port shown in the figure. The failure bit data 322 includes a failure logic address LADR and a failure I / O value FIO obtained by testing a memory circuit device using the LSI tester 100 to identify a failure memory cell.

[0040] The memory circuit data 321 includes, for example, a fault logical address LADR and information requiring conversion of a fault I / O value FIO into a fault physical address PADR. The physical address conversion unit 331 converts the fault logical address LADR and the fault I / O value FIO into the fault physical address PADR using the memory circuit data 321. The logical address is an address input to the memory circuit and is an address indicating the logical arrangement order of memory cells in a memory array in the memory circuit. On the other hand, the physical address is an address indicating the physical placement order of memory cells in the memory array.

[0041] That is, in a memory array, logic is usually not assigned to the physical arrangement of memory cells in order. When performing fault analysis, the physical arrangement or arrangement order of the faulty memory cells is required. Therefore, the physical address conversion unit 331 performs conversion to the faulty physical address PADR by, for example, inputting the faulty logical address LADR and the faulty I / O value FIO into a predetermined arithmetic expression based on the memory circuit data 321. The physical address conversion unit 331 generates physical address data 323 including the faulty physical address PADR.

[0042] The fault I / O extraction unit 332 extracts the fault I / O value FIO from the fault bit data 322 in parallel with the processing of the physical address conversion unit 331. Based on the fault physical address PADR included in the physical address data 323 and the fault I / O value FIO extracted by the fault I / O extraction unit 332, the fault mode classification unit 333 classifies the fault bit into one of the plurality of fault modes FMD.

[0043] The multiple failure modes FMD include bit failure mode, line failure mode and I / O module failure mode. The bit failure mode is a mode in which a failure bit exists in isolation. The line failure mode is a mode in which multiple failure bits reside on the same bit line or the same word line in the memory array. The I / O module failure mode is a mode when a predetermined number or more of bit line failures occur at least twice or more in the same I / O port, for example.

[0044] The memory failure data generation unit 334 generates the memory failure data 324 by integrating the failure physical address PADR from the physical address conversion unit 331 , the failure I / O value FIO from the failure I / O extraction unit 332 , and the failure mode FMD from the failure mode classification unit 333 .

[0045] The logic fault diagnosis unit 335 performs fault diagnosis on the logic circuit device tested by the LSI tester 100, that is, performs fault diagnosis on the logic fault data 325. Then, the logic fault diagnosis unit 335 generates fault diagnosis data 326 obtained by the fault diagnosis. Specifically, in testing the logic circuit device, the output pattern for various input patterns is generally observed by the LSI tester 100 to determine whether the output pattern matches / does not match the expected value pattern. The logic fault diagnosis unit 335 comprehensively diagnoses the determination result of the match / mismatch, and determines in detail the ports, logic cells, and logic wiring in the logic circuit in the estimated fault part.

[0046] At this time, in the logic fault diagnosis unit 335, the memory connection port is a connection port to the memory circuit in the logic circuit, and there is a case where the estimated fault part is determined. The fault diagnosis data 326 is data including list information of the estimated fault part. The logic fault diagnosis unit 335 is implemented by a fault analysis tool 329, a part of a tool of a generally known EDA (electronic design automation). The EDA tool can also generate an entry mode considering the fault detection rate.

[0047] The memory connection port extraction unit 336 extracts the data 327 of the memory connection port MCP from the estimated fault part included in the fault diagnosis data 326. Specifically, the memory connection port extraction unit 336 determines whether the memory connection port MCP is included as the estimated fault part in the fault diagnosis data 326, and performs the extraction process when the memory connection port MCP is included. Although the details will be described later, the estimated fault part restriction unit 337 restricts the estimated fault part based on the memory fault data 324 and the data 327 of the memory connection port.

[0048] The display control unit 338 displays the information of the estimated faulty part limited by the estimated faulty part limiting unit 337 on the display device 350. At this time, the display control unit 338 can display, for example, a layout screen of a semiconductor device or the like in which the estimated faulty part is emphasized on the display device 350 by inputting the information of the estimated faulty part with respect to the layout tool 330.

[0049] (Details of estimated faulty part limiting unit)

[0050] Figure 3 It is shown Figure 2A diagram showing an example of main processing contents of the estimated faulty portion limiting unit 337 in FIG. Figure 3 Shows Figure 1 and Figure 2 The memory connection port data 327 is an example of the memory fault data 324. The memory connection port data 327 is also a part of the fault diagnosis data 326. Figure 3 The data 327 of the memory connection port in the example includes score information 361 , instance name 362 , and memory module name 364 .

[0051] The score information 361 indicates the diagnosis of the logic fault diagnosis unit 335, that is, the high reliability of the estimated fault part. The memory module name 364 is a name determined for each configuration of the memory circuit device. For example, when a plurality of memory circuits having a specific memory module name 364 are installed in a semiconductor device, the instance name 362 is a name determined for each individual memory circuit.

[0052] The instance name 362 includes information about the MCP of the port attached to the memory. The information indicating the memory connection port MCP is composed of identification information 363, identification information "Q" indicating an output port in this example, a port ID value PID of the port, and "46" in this example. The identification information distinguishes an input port from a memory circuit or an output port to a memory circuit.

[0053] Meanwhile, the memory fault data 324 includes a fault physical address PADR, a fault mode FMD, a memory mode name 366, a fault I / O value FIO, and an instance name 365. The memory mode name 366 and the instance name 365 are similar to those of the memory connection port data 327 described above. However, unlike the instance name 362 in the memory connection port data 327, the instance name 365 does not include information indicating the memory connection port MCP. In addition, the memory mode name 366 and the instance name 365 are described in the fault bit data 322 as information to be tested.

[0054] Here, the estimated fault part limiting unit 337 compares the identities of the instance name 362 and the memory module name 364 in the data 327 of the memory connection port with the instance name 365 and the memory module name 366 in the memory fault data 324. Then, when the instance name and the memory module name are identical to each other, the estimated fault part limiting unit 337 determines a match / mismatch between the fault I / O value FIO included in the memory fault data 324 and the port ID value PID included in the data 327 of the memory connection port.

[0055] When designing a semiconductor device, the port ID value PID is generally determined by a value based on the I / O value of the memory circuit to define the connection relationship between the logic circuit and the memory circuit. Therefore, when the fault I / O value FIO matches the port ID value PID, the estimated fault portion generated in the logic circuit and the fault bit generated at the I / O port "46" of the memory circuit are associated with "Q

[46] " which is the memory connection port MCP in this embodiment.

[0056] In addition, Figure 3 In the example memory fault data 324 shown in , the fault mode FMD is an I / O module fault mode. Specifically, in this case, due to a fault of the memory connection port MCP in the logic circuit or a fault on the signal transmission path of the port, it is very likely that the I / O module fault has occurred in the memory circuit. On the other hand, from the perspective of memory fault analysis, if only the memory fault data 324 is referred to, it is not easy to identify or narrow down the faulty part that causes the I / O module fault. In addition, from the perspective of logic fault analysis, although the memory connection port MCP is included in the estimated faulty part, the memory connection port MCP is not always the faulty part.

[0057] Therefore, specifically, when an I / O module failure occurs, it is beneficial to verify the faulty I / O value FIO and the port ID value PID. Therefore, when the verification result is a match, the estimated faulty portion can be easily identified or narrowed down, and thus the faulty portion can be identified or narrowed down. In other words, from the perspective of memory failure analysis, the estimated faulty portion causing the I / O module failure can be narrowed down around the memory connection port MCP. In addition, from the perspective of logical failure analysis, the accuracy of the memory connection port MCP being the faulty portion can be increased.

[0058] Figure 4A is a diagram illustrating an exemplary process, wherein Figure 2 The estimated fault portion limiting unit 337 in limits the estimated fault portion. Figure 4B yes Figure 4A 0 is a specific example of the process details shown in , and is a diagram showing an example of a schematic layout around an estimated faulty portion.

[0059] exist Figure 4A In the embodiment, when the failure mode FMD of the failure bit is an I / O module failure, the estimated failure part limiting unit 337 determines the match / mismatch between the failure I / O value FIO and the port ID value PID. Then, when the failure I / O value FIO matches the port ID value PID, the estimated failure part limiting unit 337 limits the estimated failure part to the relevant part of the memory connection port MCP in the logic circuit area AR1 or in the peripheral circuit area AR2.

[0060] Specifically, Figure 4B As shown in FIG. 1 , the semiconductor device is provided with a logic circuit area AR1 and a memory circuit area AR4. The memory circuit area AR4 has a peripheral circuit area AR2 connected to the logic circuit area AR1 and a memory array area AR3 connected to the logic circuit area AR1 via the peripheral circuit area AR2. The memory array area AR3 includes a plurality of memory cells arranged in a matrix-like manner and word lines and bit lines connected to the plurality of memory cells. The peripheral circuit area AR2 includes a driver for driving the word lines and the bit lines and an amplifier for amplifying the bit line signals.

[0061] The logic circuit area AR1 includes a memory connection port MCP as an estimated faulty portion. In this example, the memory connection port MCP is an output port to the memory circuit device and has "46" as a port ID value PID. In addition, the memory array area AR3 includes a large number of faulty bits that are classified as a faulty I / O module at an I / O port of "46" as a faulty I / O value FIO.

[0062] In this way, when the faulty I / O value FIO matches the port ID value PID, the estimated faulty portion limiting unit 337 limits the estimated faulty portion to the signal transmission path SP1 of the memory connection port MCP in the logic circuit or the signal transmission path SP2 of the memory connection port MCP in the peripheral circuit in the memory circuit. Then, for example, the estimated faulty portion limiting unit 337 displays the layout screen as an emphasis on the display device 350 through the display control unit 338. Figure 4B The signal transmission path SP1 in.

[0063] In addition, Figure 4A In the embodiment, when the failure mode FMD is an I / O module failure mode and when the failure I / O value FIO does not match the port ID value PID, the estimated failure portion limiting unit 337 determines the estimated failure portion in the entire area of ​​the peripheral circuit area AR2. In this case, for example, it is necessary to identify or narrow down the failure portion by using light emission analysis alone or the like.

[0064] On the other hand, when the failure mode FMD is not the I / O module failure mode, that is, is the bit failure mode or the line failure mode, the estimated failure portion limiting unit 337 determines the estimated failure portion in the target portion at or around the memory array area AR3. Specifically, when the bit failure mode is selected, the estimated failure portion is defined in the corresponding memory cell, and when the line failure mode is selected, the estimated failure portion is defined in the corresponding bit line or word line, or the corresponding driver or sense amplifier.

[0065] (Failure Analysis Method)

[0066] Figure 5is a diagram showing the use of a fault analysis method according to a first embodiment Figure 1 and Figure 2 A flowchart of an example of the processing content of the failure analysis system is shown in FIG. Figure 6 It is shown Figure 5 A flowchart showing an example of the processing contents that follow. Figure 5 In the present invention, first, the LSI tester 100 performs a logic circuit test on a logic circuit in a semiconductor device (step S101). Then, the LSI tester 100 performs a logic circuit test on a logic circuit in a semiconductor device (step S101). Figure 2 The fault analysis device 400 shown in Figure 1 The processor 310 specifically shown in the figure executes the multiple processes included in step S102, that is, the processes of step S201 to step S214.

[0067] In step S102, first, the logic fault diagnosis unit 335 performs fault diagnosis on the logic fault data 325 as a result of the logic circuit test (step S201). Subsequently, the fault analysis device 400, based on the result of the fault diagnosis, determines whether there is a logic fault (step S202). If there is no logic fault (step S202: No), the process advances to the subsequent test process (step S203). On the other hand, when there is a logic fault (step S202: Yes), the memory connection port extraction unit 336 determines whether the memory connection port MCP is included in the estimated fault part of the logic circuit device, that is, in the fault diagnosis data 326 (step S204).

[0068] When the fault diagnosis data 326 does not include the memory connection port MCP (step S204: No), the memory connection port extraction unit 336 notifies the estimated fault part restriction unit 337 of this fact. In response to this, the estimated fault part restriction unit 337 determines the estimated fault part in the logic circuit area AR1, in particular, the logic line and logic element described in the fault diagnosis data 326 (step S205). In this example, physical analysis and the like are then performed on the estimated fault part (step S103).

[0069] On the other hand, when the memory connection port MCP is included in the fault diagnosis data 326 (step S204: Yes), the memory connection port extraction unit 336 extracts the data 327 of the memory connection port (step S206). Subsequently, the failure analysis device 400 causes the LSI tester 100 to perform a memory circuit test on the memory circuit in the semiconductor device (step S207). In response to this, the LSI tester 100 performs a memory circuit test using, for example, a memory BIST circuit or the like included in the logic circuit in the semiconductor device, and notifies the failure analysis device 400 of the test result.

[0070] The failure analysis device 400 receives the test result from the LSI tester 100 and determines the presence or absence of a failure bit (step S208). If there is no failure bit (step S208: No), the failure analysis device 400 proceeds to step S205. On the other hand, when there is a failure bit (step S208: Yes), the failure analysis device 400 analyzes the failure bit (step S209).

[0071] In step S209, specifically, conversion to the fault physical address PADR by the physical address conversion unit 331, extraction of the fault I / O value FIO by the fault I / O extraction unit 332, and classification of the fault mode FMD by the fault mode classification unit 333 are performed. In addition, based on the processing result, creation of the memory fault data 324 by the memory fault data generation unit 334 is performed.

[0072] Then, if Figure 6 As shown in FIG. 2 , the estimated fault portion limiting unit 337 determines whether the fault mode FMD is an I / O module fault mode based on the classification of the fault mode FMD (step S210). When the fault mode FMD is not an I / O module fault mode (step S210: No), the estimated fault portion limiting unit 337 determines that the estimated fault portion is a target portion at or near the memory array area AR3 or AR3, such as Figure 4A and Figure 4B Then, a physical analysis of the estimated faulty part etc. may be performed thereafter (step S104).

[0073] On the other hand, when the failure mode FMD is the I / O module failure mode (step S210: Yes), the estimated failure portion restriction unit 337 determines the match / mismatch between the port ID value PID and the failure I / O value FIO, such as Figure 3 Here, when the port ID value PID and the faulty I / O value FIO do not match (step S212: No), the estimated faulty portion limiting unit 337 determines the estimated faulty portion in the entire area of ​​the peripheral circuit area AR2, as described in 4A and 4B of the accompanying drawings (step S213). In this case, thereafter, it is required to perform light emission analysis or the like to identify or narrow down the faulty generating unit (step S105).

[0074] On the other hand, when the port ID value PID and the faulty I / O value FIO match (step S212: Yes), the estimated faulty portion limiting unit 337 limits the estimated faulty portion to a relevant portion of the memory connection port MCP in the logic circuit area AR1 or the peripheral circuit area AR2, such as Figure 4A That is, the estimated fault part limiting unit 337, for example, Figure 4BAs shown in FIG. 1 , the estimated faulty portion is limited to the signal transmission path SP1 of the memory connection port MCP in the logic circuit or the signal transmission path SP2 of the memory connection port MCP in the peripheral circuit. Then, subsequently, without passing through emission analysis or the like, physical analysis or the like may be performed on the estimated faulty portion (step S106).

[0075] As described above, in the system of the first embodiment, when the memory connection port is included in the estimated fault part of the logic circuit and the fault bit occurs in the memory circuit, the port ID of the memory connection port is checked according to the faulty I / O of the fault bit. Therefore, it can be determined whether there is a connection before the logic fault and the memory fault. In this case, specifically, when the verification result matches and the fault bit is classified as an I / O module fault, the estimated fault part can be identified or narrowed down by judging the relationship.

[0076] This makes it possible to increase the efficiency of failure analysis. Specifically, the time required for analysis can be reduced because an estimated failure portion can be identified or narrowed down without performing emission analysis or detailed investigation of layout and circuit diagrams. In addition, as a result, the yield of semiconductor devices can be increased at an early stage.

[0077] (Second embodiment)

[0078] (Configuration of the fault analysis system)

[0079] Figure 7 is a schematic diagram showing a configuration example of a failure analysis system according to the second embodiment. Figure 7 The fault analysis system shown in Figure 1 Compared to the configuration example shown in FIG. 1 , the data stored in the memory device 320 in the computer 300 is different. That is, in addition to Figure 1 In addition to the various data shown in Figure 7 The memory device 320 shown in FIG. 1 also stores EDA data 340 and fault scan trigger data 341 .

[0080] Figure 8 is shown by using Figure 7 A functional block diagram of a configuration example of a main part of a failure analysis device implemented by the configuration. Figure 8 The fault analysis device 400a shown in FIG. 4 also includes a Figure 2 The fault scan trigger data obtaining unit 342 of the configuration shown in FIG. In addition, the fault analysis device 400a stores Figure 7 The EDA data 340 and the fault scan trigger data 341 shown in FIG. Figure 2Unlike the case of FIG. 1 , the estimated fault portion limiting portion 337 uses the fault scan trigger data 341 to limit the estimated fault portion in addition to the memory fault data 324 and the memory connection port data 327 .

[0081] The fault scan trigger data acquisition unit 342 also obtains Figure 7 The processor 310 shown in FIG. 3 executes the fault analysis tool 329 in the memory device 320. The fault scan trigger data obtaining unit 342 obtains data corresponding to the memory connection port CMP from the EDA data 340 as the fault scan trigger data 341 based on the information of the memory connection port CMP extracted by the memory connection port extraction unit 336.

[0082] (Details of the fault scan trigger data acquisition unit)

[0083] Fig. 9 Shows Figure 7 and Figure 8 An example of EDA data 340 . Fig. 9 The EDA data 340 shown in FIG. 3 includes scan chain data 345 . The scan chain data 345 is provided by a number of scan chains installed in a semiconductor device, and specifically in a logic circuit device. Each scan chain is distinguished by a scan chain name 370 .

[0084] In addition to the scan chain name 370, each scan chain data 345 includes a scan input port name 371, a scan output port name 372, and detailed information for a plurality of scan flip-flops constituting the scan chain. The detailed information includes identification information 373, such as a number for each of the plurality of scan flip-flops, an instance name 374, a logic element name 375, and layout placement information 376, such as layout coordinates.

[0085] The fault scan trigger data obtaining unit 342 obtains data corresponding to the memory connection port MCP from these scan chain data 345 as the fault scan trigger data 341. Specifically, the fault scan trigger data obtaining unit 342 receives information of the memory connection port MCP including the instance name from the memory connection port extraction unit 336 and searches for the instance name 374 matching the instance name from the scan chain data 345.

[0086] Then, the fault scan trigger data obtaining unit 342 obtains the data of the hit scan trigger by searching as the fault scan trigger data 341. In this example, the fault scan trigger data obtaining unit 342 receives the instance name of "Q

[46] " including the information of the memory connection port MCP, and obtains the data of the scan trigger corresponding to the instance name as the fault scan trigger data 341.

[0087] (Details of estimated faulty part limiting unit)

[0088] Fig. 10A is a diagram illustrating an exemplary process, wherein Figure 8 The estimated fault portion limiting section 337 in limits the estimated fault portion. Fig. 10B yes Fig. 10A 0 is a specific example of the process details shown in , and is a diagram showing an example of a schematic layout around an estimated faulty portion. Fig. 10A Different from the above Figure 4A The place is to estimate the fault location when an I / O module failure occurs.

[0089] The estimated faulty portion limiting unit 337, when an I / O module fault occurs, when the faulty I / O value FIO matches the port ID value PID, the estimated faulty portion is limited to the relevant portion of the memory connection port MCP in the logic circuit area AR1 or in the connection circuit area AR2a. On the other hand, when an I / O module fault occurs and when the faulty I / O value FIO and the port ID value PID do not match each other, the estimated faulty portion limiting unit 337 generally determines the estimated faulty portion in the array control circuit area AR2b.

[0090] Specifically, Figure 4B The peripheral circuit area AR2 in the memory circuit shown in FIG. 1 can be divided into Fig. 10B 1 and 2. The connection circuit area AR2a and the array control circuit area AR2b are shown in FIG. The array control circuit area AR2b is connected to the memory array area AR3 and is mainly a circuit area including analog circuits such as drivers and sense amplifiers. The connection circuit area AR2a is a circuit area responsible for connecting the logic circuit area AR1 and the array control circuit area AR2b, and is a circuit area including digital circuits.

[0091] The connection circuit area AR2a and the array control circuit area AR2b are Fig. 10B Each scan flip-flop SFF included in the scan chain SC is, for example, responsible for holding incoming data or outgoing data of the memory circuit device. Fig. 10B In the example embodiment shown in FIG. 1 , the memory connection port MCP as the estimated fault part has a scan trigger SFF

[46] , where the port ID value PID is "46". In addition, the position of the scan trigger SFF

[46] is determined by the Fig. 9 The layout placement information 376 in the fault scan trigger data 341 shown in FIG.

[0092] Therefore, the estimated faulty portion limiting unit 337 determines the boundary of the estimated faulty portion based on the layout arrangement information 376. Then, when the faulty I / O value FIO matches the port ID value PID, the estimated faulty portion limiting unit 337 limits the estimated faulty portion to the signal transmission path SP3 of the memory connection port MCP, which is located on the logic circuit side instead of the defined boundary, as shown in FIG. Fig. 10B Therefore, compared to Figure 4B The estimated fault portion can be further narrowed down.

[0093] On the other hand, when the failed I / O value FIO does not match the port ID value PID, the estimated failed portion limiting unit 337 determines the estimated failed portion in the array control circuit area AR2b located on the memory circuit side with the scan chain SC as a boundary. Figure 4A and Figure 4B Compared with the case of , the estimated fault part can be slightly reduced.

[0094] (Failure Analysis Method)

[0095] Fig.11 is a diagram showing a fault analysis method according to the second embodiment. Figure 5 A flowchart showing an example of the processing contents that follow. Fig.11 In the process shown in Figure 6 Compared with the process shown in , step S301 is added between step S210 and step S212, and step S213 and step S214 are replaced by step S302 and step S303 respectively.

[0096] In step S301, when the failure mode FMD is the I / O module failure mode (step S210: Yes), the estimated failure portion restriction unit 337 is Fig. 9 The data corresponding to the memory connection port MCP is obtained from the scan chain data 345 shown in FIG. 3 as the fault scan trigger data 341. Then, the estimated faulty part limiting unit 337 determines the boundary of the estimated faulty part based on the layout arrangement information 376 included in the fault scan trigger data 341 and advances to step S212.

[0097] Furthermore, in step S302, when the faulty I / O value FIO does not match the port ID value PID (step S212: No), the estimated faulty portion limiting unit 337 is as follows: Fig. 10A and Fig. 10B The estimated faulty portion is determined in the array control circuit area AR2b described in . In this example, since the area is still wide, emission analysis and the like must be performed later (step S105).

[0098] On the other hand, in step S303, when the faulty I / O value FIO matches the port ID value PID (step S212: ), the estimated faulty portion limiting unit 337 limits the estimated faulty portion to the associated portion of the memory connection port MCP in the logic circuit area AR1 or in the connection circuit area AR2a, such as Fig. 10A That is, the estimated fault part limiting unit 337, as shown in Fig. 10B As shown in FIG. 1 , the estimated faulty portion is limited to the signal transmission path SP3 of the memory connection port MCP located on the logic circuit side of the defined boundary. In this case, then, Figure 6 Compared with the case where physical analysis or the like is performed on the estimated faulty part more efficiently (step S106).

[0099] (Key Effect of the Second Embodiment)

[0100] As described above, by using the scheme of the second embodiment, the same effects as those described in the first embodiment can also be obtained. In addition, by using the data of the scan flip-flop SFF, the estimated fault part can be further narrowed, thereby further increasing the efficiency of fault analysis compared with the case of the first embodiment.

[0101] Although the invention made by the present inventors has been described in detail based on the embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

[0102] For example, in Figure 2 or Figure 8 In the fault analysis device 400, 400a shown in FIG. 1 , some or all components are not limited to being programmed by a processor and can be implemented in other ways. Specifically, for example, Figure 8 Some or all of the components (331-338, 342) may be implemented in hardware, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit), or may be implemented in a combination of software and hardware.

[0103] The program described above can also be provided to a computer on a non-transitory tangible computer-readable recording medium, such as a magnetic recording medium represented by a hard disk drive, an optical recording medium represented by a DVD (Digital Versatile Disc) or a Blu-ray disk, or a semiconductor-based memory represented by a flash memory or an SSD.

Claims

1. A failure analysis device for analyzing failure of a semiconductor having a logic circuit and a memory circuit, comprising: a storage device for storing fault bit data obtained by testing the memory circuit and fault diagnosis data obtained by performing fault diagnosis on the test results of the logic circuit, and processor, The processor extracts a faulty I / O from the fault bit data and extracts data of a memory connection port from an estimated fault portion included in the fault diagnostic data, the memory connection port being a connection port to the memory circuit, and determines whether the faulty I / O matches a port ID included in the data of the memory connection port.

2. The failure analysis device according to claim 1, wherein the processor converts a faulty logical address and the faulty I / O included in the faulty bit data into a faulty physical address, and classifies the faulty bit data into any one of a plurality of fault modes based on the faulty physical address and the faulty I / O, the plurality of fault modes including a line fault mode and an I / O module fault mode, and determines a match / mismatch between the faulty I / O value and the port ID value when the classified result of the fault mode is the I / O module fault mode.

3. The failure analysis device according to claim 2, When the faulty I / O matches the port ID, the processor limits the estimated faulty portion to a signal transmission path of the memory connection port in the logic circuit or to a signal transmission path of the memory connection port in a peripheral circuit in the memory circuit.

4. The failure analysis device according to claim 2, The storage device further stores scan chain data, the scan chain data including identification information and layout information, the identification information is used for each scan trigger of a plurality of scan triggers constituting the scan chain, and the layout information is used for each scan trigger of the plurality of scan triggers, The processor obtains the data corresponding to the memory connection port from the scan chain data as fault scan trigger data, and defines a boundary of the estimated faulty portion based on the layout arrangement information included in the fault scan trigger data.

5. The failure analysis device according to claim 4, Wherein when the faulty I / O matches the port ID, the processor limits the estimated faulty portion to the signal transmission path of the memory connection port located at the logic circuit side instead of the boundary.

6. A method for analyzing a failure of a semiconductor device having a logic circuit and a memory circuit: obtaining fault bit data by testing the memory circuit, and obtaining fault diagnosis data by performing fault diagnosis on the test results of the logic circuit stored in the memory device, Extracting the fault I / O from the fault bit data, extracting data of a memory connection port, which is a connection port to the memory circuit, from the estimated fault portion included in the fault diagnosis data, It is determined whether the failed I / O matches a port ID included in the data of the memory connection port.

7. The fault analysis method according to claim 6, converting a failed logical address and the failed I / O included in the failed bit data into a failed physical address, classifying the failed bit data into any one of a plurality of failure modes based on the failed physical address and the failed I / O, the plurality of failure modes comprising a bit failure mode, a line failure mode, and an I / O module failure mode, A match / mismatch between the faulty I / O and the port ID is determined when the classified result of the fault mode is the I / O module fault mode.

8. The fault analysis method according to claim 7, When the faulty I / O matches the port ID, the estimated faulty portion is limited to a signal transmission path of the memory connection port in the logic circuit or to a signal transmission path of the memory connection port in a peripheral circuit in the memory circuit.

9. The fault analysis method according to claim 7, scan chain data is also stored in the storage device, the scan chain data including identification information and layout information, the identification information is used for each scan trigger of a plurality of scan triggers constituting the scan chain, and the layout information is used for each scan trigger of the plurality of scan triggers, Obtain the data corresponding to the memory connection port from the scan chain data as fault scan trigger data, The boundary of the estimated faulty portion is defined based on the layout arrangement information included in the faulty scan flip-flop data.

10. The fault analysis method according to claim 9, When the faulty I / O matches the port ID, the estimated faulty portion is limited to the signal transmission path of the memory connection port located on the logic circuit side instead of the boundary.

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