A method for double-sided overlay accuracy alignment and risk control of protecting the back hole from over-etching

Abstract

The present invention discloses a method for controlling the risk of over-etching of the back hole during double-sided overlay accuracy alignment and protection, and the present invention relates to the technical field of lithography overlay. The method includes the following steps: First, form the first layer of overlay pattern and alignment marks on the front side of the wafer, and establish a front-side coordinate system; calculate the local and global offset errors by overlaying the coordinate information of the two layers of front-side overlay patterns, determine the comprehensive front-side overlay error, and correct the front-side alignment system. Subsequently, flip the wafer, process the back-side overlay pattern in the same way as the front-side alignment, correct the back-side alignment system, and complete the double-sided error correction. Finally, by extracting surface characteristic parameters including the photoresist thickness distribution factor and the edge roughness factor, correct the lithography depth to obtain an accurate value, realize the precise control of the lithography depth, reduce the risk of over-etching of the back hole of the wafer, and significantly improve the yield of the equipment and the performance stability of the product.

Description

Technical Field

[0001] The present invention relates to the technical field of lithography overlay technology, and specifically to a method for double-sided overlay accuracy alignment and protection against the risk of over-etching of back holes. Background Art

[0002] With the development of the semiconductor industry, in the process of semiconductor processing and manufacturing, double-sided lithography technology has been applied to the fields of micro-electro-mechanical systems (MEMS, also known as micro-electromechanical systems), radio frequency device manufacturing, and advanced packaging technology. In the process of radio frequency device manufacturing, double-sided lithography technology can reduce signal attenuation caused by thick metal deposition and protect the front side of the wafer from the risk of over-etching. The double-sided lithography overlay technology directly determines the quality and performance of the product. For example, in the manufacturing process of a pressure sensor, the quality and performance of the sensor depend on the alignment accuracy between the front side of the wafer and the process layer on the back side of the wafer; in advanced packaging devices, the internal connection pipes need to be arranged arbitrarily, which also puts forward high-precision requirements for the overlay alignment between the front side and the back side of the wafer. For opaque wafers, neither the alignment system nor the contact lithography machine can measure the marked positions on both the front and back sides of the wafer simultaneously. The application of double-sided alignment technology in lithography equipment has derived a new double-sided alignment ( "double-sided alignment" means "double-sided overlay error calibration") measurement direction. The double-sided overlay accuracy is defined as the alignment error between the front side of the wafer and the process layer on the back side of the wafer. The double-sided alignment measurement tool needs to have a large measurement range, cover as large an area as possible on the wafer surface, and the measurement objects cover various materials and wafers or thin film layers with different thicknesses. Currently, through the mutual feedback calibration of the front-side alignment system and the back-side alignment system of the wafer, the overlay accuracy of the positioning coordinates of the TSA layer and the BSA layer patterns is corrected in a timely manner, ensuring the deviation of the overlay accuracy between the front-side alignment and the back-side alignment of the wafer, providing protection against being etched through during the subsequent metal layer etching, and improving the quality and yield of the wafer products.

[0003] Although the prior art has proposed methods for error correction through single-sided alignment systems, these technologies have limitations in complex applications of double-sided processing. For example, the alignment marks on the front and back sides cannot be completely unified, resulting in difficulty in controlling the alignment accuracy between the front and back sides at the micron level; at the same time, there is a lack of effective control and compensation mechanisms for the risk of over-etching during the back-side etching process. Therefore, a more precise and comprehensive method is needed to solve the problems of error correction and over-etching risk in the double-sided overlay process.

[0004] In the prior art, the published number CN103926797B discloses a double-sided overlay system and method for a lithography apparatus, including: Step 1: forming a back pattern on the back of a substrate through a previous process; Step 2: loading the substrate onto a substrate stage, performing a first exposure on the substrate to obtain a front alignment mark and a front overlay pattern; Step 3: downloading the substrate and developing the substrate; Step 4: obtaining the relative position error between the overlay pattern and the back pattern; Step 5: loading the substrate again and performing front alignment based on the front alignment mark; Step 6: compensating for the relative position error and performing a second exposure on the substrate. However, in this solution, the compensation of the overlay error is only completed through the front alignment mark, ignoring the help of the back alignment mark, and it is easy to have inaccurate compensation, especially in the case of complex deformation or wafer warping between the front and back patterns. Since there is no direct mathematical relationship established between the spatial positions of the front alignment mark and the back pattern, the error compensation accuracy between the front and the back is limited. At the same time, there is no mention of the control of the over-etching risk. Therefore, it may lead to the interference or damage between the back pattern and the front key structure, and also reduce the accuracy and effectiveness of the alignment result.

[0005] The above information disclosed in the background art section is only used to strengthen the understanding of the background of the present disclosure, and thus it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present invention is to provide a double-sided overlay accuracy alignment and method for controlling the risk of over-etching of back holes to solve the problems raised in the above background art.

[0007] To achieve the above purpose, the present invention provides the following technical solutions:

[0008] A double-sided overlay accuracy alignment and method for controlling the risk of over-etching of back holes, the specific steps include:

[0009] Forming a first-layer front overlay pattern and an alignment mark pattern on the front of a sample wafer, the pattern of the alignment mark includes a plurality of front alignment marks and a plurality of back alignment marks, determining the position information of the front alignment marks based on the wafer front alignment system in the lithography apparatus, and establishing a wafer front coordinate system with the obtained position information of the front alignment marks;

[0010] Based on the established wafer front coordinate system, determining the coordinate information of the first-layer front overlay pattern, and forming a second-layer front overlay pattern on the front of the sample wafer according to the obtained coordinate information of the first-layer front overlay pattern, and extracting the coordinate information of the second-layer front overlay pattern in the wafer front coordinate system;

[0011] Based on the coordinate information of the second-layer front-side overlay pattern in the front-side coordinate system of the wafer and the coordinate information of the first-layer front-side overlay pattern, several corresponding feature points in the two layers of front-side overlay patterns are selected and the coordinates of the feature points are recorded. Based on the obtained feature point coordinates, the local offset error coefficient and the global error coefficient of the two layers of front-side overlay patterns are calculated, and the comprehensive front-side overlay error is determined according to the local offset error coefficient and the global error coefficient;

[0012] Based on the comprehensive front-side overlay error, error correction is performed on the front-side wafer alignment system in the lithography apparatus. The sample wafer is flipped, and the first-layer back-side overlay pattern is etched on the back side of the sample wafer. Using the same processing method as the front-side alignment system, the back-side overlay error is obtained. Based on the back-side overlay error, error correction is performed on the back-side wafer alignment system in the lithography apparatus. Finally, according to the double-sided error between the first-layer back-side overlay pattern and the first-layer front-side overlay pattern, double-sided overlay error correction is completed;

[0013] The surface feature parameters of the overlay pattern after error correction are obtained. Based on the obtained surface feature parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated. According to the photoresist thickness distribution factor and the photoresist edge roughness factor, the lithography depth is corrected to obtain the accurate depth value of each point of lithography, and over-etching risk control is completed. The surface feature parameters include the lithography edge roughness and the average thickness of the photoresist.

[0014] Further, based on the wafer front-side alignment system in the lithography apparatus, the position information of the front-side alignment mark is determined. The specific steps to establish the front-side coordinate system of the wafer with the obtained position information of the front-side alignment mark are as follows: The wafer is loaded onto the alignment platform of the lithography machine through a robotic arm or other transfer device, and the wafer is fixed on the alignment table by using the vacuum adsorption or clamping mechanism of the lithography apparatus. The front-side alignment system in the lithography apparatus will detect the front-side alignment mark on the wafer through software configuration. By performing image processing on the detected mark, the geometric features of the mark are extracted. The geometric features include the center position and the edge point coordinates. The reference line between the marks is defined as the X-axis of the front-side coordinate system of the wafer, the center position of the mark is defined as the coordinate origin, and the direction perpendicular to the X-axis is the Y-axis, thus establishing the front-side coordinate system of the wafer.

[0015] Further, based on the coordinate information of the second-layer front-side overlay pattern in the front-side coordinate system of the wafer and the coordinate information of the first-layer front-side overlay pattern, the coordinates of several corresponding feature points in the two layers of front-side overlay patterns are selected. The logic for selecting the coordinates of several corresponding feature points in the two layers of front-side overlay patterns is as follows: Randomly select feature points on the first-layer front-side overlay pattern, record the coordinate information of each feature point, denoted as , and then determine the corresponding A number of feature points are recorded, and the coordinate information of each feature point is denoted as , where is the index of the feature point, and .

[0016] Furthermore, based on the obtained corresponding feature point coordinates, the local offset error coefficients and the global error coefficients of the two-layer front-side overlay patterns are calculated. The formula for calculating the local offset error coefficients of the two-layer front-side overlay patterns is:

[0017]

[0018] In the formula, represents the local offset error coefficient of the i-th group of corresponding feature points, is the radial distance from the i-th group of feature points to the center of the wafer;

[0019] The formula for calculating the global error coefficient of the two-layer front-side overlay patterns is:

[0020]

[0021] In the formula, is the global error coefficient of the two-layer front-side overlay patterns, is the scaling factor of the sample wafer, is the rotation angle of the sample wafer.

[0022] Furthermore, the rotation angle of the sample wafer is calculated according to the formula:

[0023]

[0024] In the formula, and are the corresponding feature points of the two-layer front-side overlay patterns, respectively, on the axis and axis of the average offset error;

[0025] Among them and The calculation formulas are respectively:

[0026]

[0027]

[0028] Among them, the scaling factor of the sample wafer is corrected by the ambient temperature and the clamping stress applied to the sample wafer. The specific calculation formula is:

[0029]

[0030] In the formula, is the initial scaling factor of the sample wafer, is the average environmental temperature during the overlay process, is the reference temperature, is the clamping stress applied to the sample wafer, is the Young's modulus of the sample wafer, is the Poisson's ratio of the sample wafer.

[0031] Furthermore, the comprehensive front-side overlay error is determined based on the local offset error coefficient and the global error coefficient. The formula for calculating the comprehensive front-side overlay error is:

[0032]

[0033] In the formula, is the comprehensive front-side overlay error of the i-th feature point, and are the weight coefficients of the local offset error coefficient and the global error coefficient respectively, where and and are both greater than 0;

[0034] The back-side overlay error and the double-sided error are calculated in the same way as the comprehensive front-side overlay error.

[0035] Furthermore, based on the obtained surface feature parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated. The formula for calculating the photoresist thickness distribution factor is:

[0036]

[0037] In the formula, is the photoresist thickness distribution factor of the i-th feature point, is the local photoresist thickness of the i-th feature point, is the average thickness of the photoresist on the surface of the sample wafer, is the amplitude constant of the thickness distribution, is the maximum radius of the sample wafer;

[0038] The formula for calculating the photoresist edge roughness factor is:

[0039]

[0040] In the formula, is the photoresist edge roughness factor of the i-th feature point, is the photoresist edge roughness of the i-th feature point, is the ideal edge roughness value.

[0041] Furthermore, the lithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the accurate depth value of each point in lithography. The formula based on which the accurate depth value of each point in lithography is calculated is:

[0042]

[0043] In the formula, is the accurate depth value of the i-th feature point, is the initial overlay depth value of the i-th feature point.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] First of all, in this solution, alignment marks are formed on the front side and the front alignment system of the lithography device is used to establish the wafer front coordinate system, further unifying the coordinate information on the front and back sides, and realizing the accurate overlay between multiple layers of patterns. Especially during the alignment process between the front and back sides, an interactive correction method for the front and back alignment marks is adopted, significantly reducing the local offset error and global error caused by the non-uniform coordinate system in the traditional method, so as to meet the manufacturing requirements of high-precision devices. Secondly, aiming at the over-etching risk during the backside lithography process, an etching depth correction method based on the surface characteristic parameters of the photoresist is proposed. By extracting the photoresist thickness distribution factor, the depth distribution of each point in lithography can be calculated more accurately, and the possible etching abnormal areas can be predicted through the analysis of the edge roughness factor, and finally the accurate control of the lithography depth is realized. The over-etching problem caused by the uneven photoresist thickness or insufficient edge roughness control in the traditional etching process is solved, and the accuracy and stability of the etching process are significantly improved. Finally, through the comprehensive error correction of the front and back sides, not only the overall accuracy of the double-sided overlay is improved, but also the control process of the lithography depth is optimized, thus effectively reducing the risk of over-etching of the wafer back holes. The yield of the equipment and the performance stability of the product are significantly improved. Description of the Drawings

[0046] Figure 1 is the schematic diagram of the overall method flow of the present invention;

[0047] Figure 2 is the schematic diagram of the specific shape of the wafer overlay mark;

[0048] Figure 3 is the schematic diagram of forming the first layer of front overlay pattern on the wafer front side;

[0049] Figure 4 is the schematic diagram of determining the position of the front alignment mark and establishing the wafer front coordinate;

[0050] Figure 5 Schematic diagram for forming the second front-side overlay pattern on the front side of the wafer;

[0051] Figure 6 Schematic diagram for determining the overlay error on the front side and the overlay error on the back side of the wafer;

[0052] Figure 7 Schematic diagram for calibrating the wafer overlay error. Detailed implementation manners

[0053] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with specific embodiments.

[0054] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the present invention should have the ordinary meanings understood by those of ordinary skill in the field to which the present invention belongs. The "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0055] Embodiment:

[0056] Please refer to Figures 1-7 , the present invention provides a technical solution:

[0057] A method for double-sided overlay accuracy alignment and protection against the risk of over-etching of back holes, the specific steps include:

[0058] Step 1: Form a first front-side overlay pattern and alignment mark patterns on the front side of the sample wafer. The patterns of the alignment marks include a plurality of front-side alignment marks and a plurality of back-side alignment marks. Based on the wafer front-side alignment system in the lithography apparatus, determine the position information of the front-side alignment marks, and establish a wafer front-side coordinate system with the obtained position information of the front-side alignment marks.

[0059] Based on the travel ranges of TSA (front side of the wafer) and BSA (back side of the wafer), two cross-shaped solid bar marks are made on the first set of etched marks on the first pattern layer on the front side of the wafer, with a pattern having alignment marks. Two cross-shaped hollow bar marks are made on the first set of etched marks on the first pattern layer on the back side of the wafer. It is selected that the cross-shaped hollow bar mark on the back side is about 10 um larger than the cross-shaped solid bar mark on the front side. The etched marks in the shape of a cross are the same as the shape of the actual pattern. Among them, alignment is carried out through a photomask.

[0060] Based on the wafer front alignment system in the lithography apparatus, determine the position information of the front alignment marks. The specific steps to establish the wafer front coordinate system with the obtained position information of the front alignment marks are as follows: Load the wafer onto the alignment platform of the lithography machine through a robotic arm or other transfer device, and use the vacuum adsorption or clamping mechanism of the lithography apparatus to fix the wafer on the alignment table. The front alignment system in the lithography apparatus will detect the front alignment marks on the wafer through software configuration. By performing image processing on the detected marks, extract the geometric features of the marks. The geometric features include the center position and the coordinates of the edge points. The reference line between the marks is defined as the X-axis of the wafer front coordinate system, the center position of the mark is defined as the coordinate origin, and the direction perpendicular to the X-axis is the Y-axis. In this way, the wafer front coordinate system is established.

[0061] Step 2: Based on the established wafer front coordinate system, determine the coordinate information of the first layer of front alignment patterns. According to the obtained coordinate information of the first layer of front alignment patterns, form the second layer of front alignment patterns on the front side of the sample wafer, and extract the coordinate information of the second layer of front alignment patterns in the wafer front coordinate system.

[0062] Based on the coordinate information of the second layer of front alignment patterns in the wafer front coordinate system and the coordinate information of the first layer of front alignment patterns, select the coordinates of several corresponding feature points in the two layers of front alignment patterns. The logic for selecting the coordinates of several corresponding feature points in the two layers of front alignment patterns is as follows: Randomly select feature points on the first layer of front alignment patterns, record the coordinate information of each feature point, denoted as , and then determine the corresponding feature points on the second layer of front alignment patterns, record the coordinate information of each feature point, denoted as , where is the index of the feature point, and .

[0063] Step 3: Based on the coordinate information of the second-layer front-side alignment pattern in the front-side coordinate system of the wafer and the coordinate information of the first-layer front-side alignment pattern, select several corresponding feature points from the two layers of front-side alignment patterns and record the coordinates of the feature points. Based on the obtained feature point coordinates, calculate the local offset error coefficient and the global error coefficient of the two layers of front-side alignment patterns, and determine the comprehensive front-side alignment error according to the local offset error coefficient and the global error coefficient.

[0064] Based on the obtained corresponding feature point coordinates, calculate the local offset error coefficient and the global error coefficient of the two layers of front-side alignment patterns. The formula for calculating the local offset error coefficient of the two layers of front-side alignment patterns is as follows:

[0065]

[0066] In the formula, represents the local offset error coefficient of the i-th group of corresponding feature points, is the radial distance from the i-th group of feature points to the center of the wafer;

[0067] It should be noted that the local offset error coefficient of the i-th group of corresponding feature points combines geometric deviation and structural deviation and is used to characterize the local offset error of each feature point. Among them, the larger the value of the local offset error coefficient , the more offset and the greater the error.

[0068] The radial distance from the i-th group of feature points to the center of the wafer , in lithography and alignment, environmental factors in the local area (such as mechanical vibration, temperature gradient, or equipment accuracy) may cause additional offsets. By including the local offset, the actual error of the i-th point can be more accurately quantified without simply relying on geometric offset. The error distribution on the wafer is usually not uniform. The error in the central area may be small, while the error in the edge area may be amplified due to equipment optical distortion, mechanical error, etc. Therefore, the radial distance from the i-th group of feature points to the center of the wafer is proportional to the local offset error coefficient of the i-th group of corresponding feature points. It is represented by the logarithmic function indicating that after reaching the central area of the wafer, the influence of the radial distance from the i-th feature point to the center of the wafer on the local offset error coefficient gradually decreases. The radial distance from the i-th group of feature points to the center of the wafer is the average distance from the corresponding feature points of the first-layer and second-layer alignment patterns to the center of the wafer. Among them, the radial distance The acquisition method is as follows: Use high-precision measuring equipment (such as laser rangefinders, coordinate measuring machines, or optical microscopes) to directly measure the positions of feature points on the wafer. Based on the coordinate positions of the feature points and the coordinates of the wafer center, calculate the Euclidean distance between the first-layer overlay pattern and the second-layer overlay pattern, and use the average value of this data as the radial distance from the i-th group of feature points to the wafer center 。

[0069] The formula for calculating the global error coefficient of the two-layer front-side overlay patterns is as follows:

[0070]

[0071] In the formula, is the global error coefficient of the two-layer front-side overlay patterns, is the scaling factor of the sample wafer, is the rotation angle of the sample wafer.

[0072] Among them, the global error coefficient of the two-layer front-side overlay patterns is used to describe the influence of the global deformation of the wafer during the lithography process on the overlay error by comprehensively considering the scaling factor of the sample wafer and the rotation angle of the sample wafer. The larger the value of the global error coefficient of the two-layer front-side overlay patterns, the greater the overlay error.

[0073] Among them, the scaling factor of the sample wafer represents the dimensional changes that occur to the wafer during the lithography process due to environmental factors (such as temperature) or material properties. During the lithography process, the wafer may undergo global deformation due to the following factors: The wafer expands or contracts due to the influence of the processing equipment temperature; mechanical stress: For example, tensile or compressive stress may be introduced during loading, clamping, or alignment. Therefore, the larger the scaling factor of the sample wafer, the greater the interference on the wafer, and the overlay error also increases accordingly. Therefore, the scaling factor of the sample wafer is proportional to the global error coefficient of the two-layer front-side overlay patterns.

[0074] The rotation angle of the sample wafer, the deformation of the wafer is usually two-dimensional. The rotation angle of the wafer describes the overall rotation that occurs to the wafer during the lithography process. Therefore, the larger the rotation angle of the wafer, the greater the offset that occurs during the lithography process. Therefore, the rotation angle of the sample wafer is proportional to the global error coefficient of the two-layer front-side overlay patterns.

[0075] The formula for calculating the rotation angle of the sample wafer is as follows:

[0076]

[0077] Wherein, and are the corresponding feature points of the two-layer front-side overlay patterns, respectively, and are the average offset errors on the axis and the axis;

[0078] Among them and The formulas based on which the calculations are performed are respectively:

[0079]

[0080]

[0081] Among them, the scaling factor of the sample wafer is corrected by the ambient temperature and the clamping stress applied to the sample wafer. The specific formula based on which the calculation is performed is:

[0082]

[0083] Wherein, is the initial scaling factor of the sample wafer, is the average ambient temperature during the overlay process, is the reference temperature, is the clamping stress applied to the sample wafer, is the Young's modulus of the sample wafer, is the Poisson's ratio of the sample wafer.

[0084] Among them, the scaling factor of the sample wafer is obtained by dynamically correcting the initial scaling factor of the sample wafer through material characteristics and ambient temperature.

[0085] Among them, the thermal expansion of the wafer is mainly caused by the temperature gradient, that is, the temperature difference in different regions of the wafer will cause non-uniform expansion and contraction. Therefore, in the actual lithography process, it is necessary to combine the temperature distribution of the wafer to characterize the scaling factor. The greater the difference between the ambient temperature and the reference temperature during the overlay process, the more likely it is to cause thermal expansion of the wafer. Therefore, the difference between the ambient temperature and the reference temperature during the overlay process is proportional to the scaling factor of the sample wafer.

[0086] The greater the clamping stress applied to the sample wafer, the greater the mechanical force on the wafer, and the mechanical force will cause the wafer to deform. Therefore, the clamping stress applied to the sample wafer is proportional to the scaling factor

[0087] The Young's modulus and Poisson's ratio of the sample wafer. Since the larger the Young's modulus of the material, it indicates that when the material is subjected to the same stress, the strain (deformation) generated is smaller, and the material is less likely to deform; for the Poisson's ratio, the larger the Poisson's ratio of the material, the more obvious the contraction in the transverse direction. Therefore, the scaling factor of the sample wafer is inversely proportional to the Young's modulus of the sample wafer, and the inverse relationship is represented by a fraction; it is directly proportional to the Poisson's ratio of the sample wafer. Among them, the reference temperature is generally taken as 25 .

[0088] Determine the comprehensive front-side overlay error according to the local offset error coefficient and the global error coefficient. The formula based on which the comprehensive front-side overlay error is calculated is:

[0089]

[0090] In the formula, is the comprehensive front-side overlay error of the i-th feature point, and are the weight coefficients of the local offset error coefficient and the global error coefficient respectively. Among them, and and are all greater than 0.

[0091] Among them, since the larger the local offset error coefficient and the global error coefficient, both indicate the larger the offset error, so both are proportional to the comprehensive front-side overlay error of the i-th feature point in a proportional relationship, and the influence of the global error coefficient on the comprehensive front-side overlay error is reduced in the form of a square root .

[0092] And because the local offset error coefficient is for specific feature points, while the global error coefficient is a precision correction based on the local offset error, so set and and are all greater than 0.

[0093] Step 4: Perform error correction on the wafer front-side alignment system in the lithography apparatus based on the comprehensive front-side overlay error. Flip the sample wafer, etch the first layer of back-side etched pattern on the back of the sample wafer, and use the same processing method as the front-side alignment system to obtain the back-side overlay error. Perform error correction on the wafer back-side alignment system in the lithography apparatus based on the back-side overlay error, and finally complete the double-sided overlay error correction according to the double-sided error between the first layer of back-side etched pattern and the first layer of front-side etched pattern.

[0094] The comprehensive front-side overlay error refers to the offset error between the front-side pattern of the wafer (the current lithography layer) and the fabricated pattern (the underlying layer). It is the result of the superposition of multiple errors, including position offset, rotation error, scaling error, etc. The wafer front-side alignment system in the lithography apparatus is corrected for errors according to the comprehensive front-side overlay error, and the error correction can be achieved through the high-precision stepping motors and feedback control systems equipped in modern lithography machines. The error determination is all detected through the wafer chucking device.

[0095] By using the front-side alignment system to determine the position of the front-side alignment mark, the front-side coordinates of the substrate are established; based on the front-side coordinates of the substrate, a second-layer front-side overlay pattern is formed on the front side of the substrate; the position error between the first-layer front-side overlay pattern and the second-layer front-side overlay pattern is measured; according to the position error between the first-layer front-side overlay pattern and the second-layer front-side overlay pattern, the first overlay error calibration is performed, that is, the overlay error of the front side of the substrate is calibrated; then the substrate is flipped, and the back-side alignment system is used to determine the position of the back-side alignment mark, and the back-side coordinates of the substrate are established; based on the back-side coordinates of the substrate, a first-layer back-side overlay pattern and a second-layer back-side overlay pattern are formed on the back side of the substrate; the position error between the first-layer back-side overlay pattern and the second-layer back-side overlay pattern is measured; according to the position error between the first-layer back-side overlay pattern and the second-layer back-side overlay pattern, the second overlay error calibration is performed, that is, the overlay error of the back side of the substrate is calibrated. Thus, by flipping the substrate once, the overlay error of the front side and the overlay error of the back side of the substrate can be calibrated, that is, by flipping the substrate once, the double-sided overlay error calibration of the substrate can be achieved, with high calibration efficiency, high overlay accuracy, good pattern protection, and the risk of over-etching the BSA layer can be effectively reduced.

[0096] The calculation methods of the back-side overlay error and the double-sided error are the same as that of the comprehensive front-side overlay error. In the calculation of the double-sided error, the radial distance from the feature point to the center of the wafer uses the radial distance data in the front-side overlay. This will not be elaborated here.

[0097] Step 5: Obtain the surface characteristic parameters of the overlay pattern after error correction. Based on the obtained surface characteristic parameters, calculate the photoresist thickness distribution factor and the photoresist edge roughness factor, and correct the lithography depth according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the accurate depth value of each point of the lithography, and complete the over-etching risk control. The surface characteristic parameters include the lithography edge roughness and the average thickness of the photoresist.

[0098] Based on the obtained surface characteristic parameters, calculate the photoresist thickness distribution factor and the photoresist edge roughness factor. The formula based on which the photoresist thickness distribution factor is calculated is:

[0099]

[0100] In the formula, is the resist thickness distribution factor of the i-th feature point, is the local resist thickness of the i-th feature point, is the average resist thickness on the surface of the sample wafer, is the amplitude constant of the thickness distribution, is the maximum radius of the sample wafer;

[0101] Among them, the resist thickness distribution factor of the i-th feature point is used to characterize the influence of the resist thickness on the overlay depth. Among them, the resist thickness distribution factor of the i-th feature point The larger it is, the thicker the resist thickness of this feature point. During overlay, the overlay depth can be increased to meet the actual requirements.

[0102] Among them, the local resist thickness of the i-th feature point directly characterizes the local resist thickness. Therefore, the local resist thickness of the i-th feature point is proportional to the resist thickness distribution factor of the i-th feature point, and the proportional relationship is characterized by the ratio to the average resist thickness.

[0103] is used to describe the periodic distribution of the radial thickness, especially applicable to the non-uniformity of the wafer edge and center regions. During wafer manufacturing, the wafer edge is usually thinned and chamfered to avoid being too sharp (which may cause the wafer to be fragile during handling and processing). This treatment makes the thickness of the edge region slightly smaller than that of the center. Therefore, in the edge region, due to the slightly smaller thickness, the overlay depth should be increased to reach the actual required depth.

[0104] Among them, the formula for calculating the resist edge roughness factor is:

[0105]

[0106] In the formula, is the resist edge roughness factor of the i-th feature point, is the resist edge roughness of the i-th feature point, is the ideal edge roughness value.

[0107] Among them, the larger the resist edge roughness factor, the rougher the resist edge, resulting in a reduction in the mask protection effect, an increase in the exposed substrate area, and a deeper etching reaction. Therefore, the larger the resist edge roughness factor, the overlay depth should be reduced to avoid the risk of over-etching.

[0108] The methods for obtaining the local thickness and the average thickness of the photoresist include: Ellipsometer: determining the thickness of the photoresist by measuring the phase change of polarized light; Optical Interferometer: performing interference measurement using a multi-wavelength light source to achieve the analysis of the local thickness distribution.

[0109] The method for obtaining the maximum radius of the sample wafer is as follows: During the wafer manufacturing and processing, the size parameters of the wafer (including the maximum radius) are usually provided by the production equipment.

[0110] The lithography edge roughness and the ideal edge roughness value can be obtained by scanning the edge of the lithography pattern with an electron beam to obtain a high-resolution edge topography image, extracting the edge contour through an image processing algorithm, comparing the actual edge with the ideal edge, and calculating the edge roughness according to the deviation degree of the edge contour. In semiconductor manufacturing, different lithography processes and equipment usually have specific ideal edge roughness reference values, which are often provided by equipment suppliers or research institutions.

[0111] Among them, the amplitude constant of the thickness distribution is experimentally determined by ellipsometric spectroscopy and is usually between 0.01 - 0.05.

[0112] The lithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the accurate depth value of each point of the lithography. The formula based on which the accurate depth value of each point of the lithography is calculated is as follows:

[0113]

[0114] In the formula, is the accurate depth value of the i-th feature point, is the initial overlay depth value of the i-th feature point.

[0115] Since the above explains the correlation between the photoresist thickness distribution factor and the photoresist edge roughness factor and the overlay depth, that is, the accurate depth value of the i-th feature point is directly proportional to the photoresist thickness distribution factor and inversely proportional to the photoresist edge roughness factor, and the square root and the logarithmic function are used to avoid overcorrection.

[0116] The above formulas are all dimensionless and take their numerical values for calculation. The formula is obtained by collecting a large amount of data for software simulation to get a formula closest to the actual situation. The preset parameters in the formula are set by those skilled in the art according to the actual situation.

[0117] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. Those skilled in the art will appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0118] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. They may be located in one place or distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the objectives of the solution of this embodiment.

[0119] As described above, the specific implementation manners of the present application are only described, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all of them should be covered by the protection scope of the present application.

Claims

1. A method for double-sided overlay accuracy alignment and protection of the risk control of back hole over-etching, characterized in that, The specific steps include: Form a first-layer front-side overlay pattern and alignment mark pattern on the front side of the sample wafer. The alignment mark pattern includes several front-side alignment marks and several back-side alignment marks. Based on the wafer front-side alignment system in the lithography apparatus, determine the position information of the front-side alignment marks, and establish a wafer front-side coordinate system with the obtained position information of the front-side alignment marks; Based on the established wafer front-side coordinate system, determine the coordinate information of the first-layer front-side overlay pattern. According to the obtained coordinate information of the first-layer front-side overlay pattern, form a second-layer front-side overlay pattern on the front side of the sample wafer, and extract the coordinate information of the second-layer front-side overlay pattern in the wafer front-side coordinate system; Based on the coordinate information of the second-layer front-side overlay pattern in the front-side coordinate system of the wafer and the coordinate information of the first-layer front-side overlay pattern, the coordinates of several corresponding feature points in the two layers of front-side overlay patterns are selected. The logic for selecting the coordinates of several corresponding feature points in the two layers of front-side overlay patterns is as follows: Randomly select feature points on the first-layer front-side overlay pattern, record the coordinate information of each feature point, denoted as , and then determine the corresponding feature points on the second-layer front-side overlay pattern, record the coordinate information of each feature point, denoted as , where is the index of the feature point, and ; Based on the coordinate information of the second-layer front-side overlay pattern in the wafer front-side coordinate system and the coordinate information of the first-layer front-side overlay pattern, select several corresponding feature points in the two layers of front-side overlay patterns and record the feature point coordinates. Based on the obtained feature point coordinates, calculate the local offset error coefficient and global error coefficient of the two layers of front-side overlay patterns, and determine the comprehensive front-side overlay error according to the local offset error coefficient and global error coefficient; Among them, the formula for calculating the local offset error coefficient of the two layers of front-side overlay patterns is: In the formula, represents the local offset error coefficient corresponding to the i-th group of feature points, is the radial distance from the i-th group of feature points to the center of the wafer; Among them, the formula for calculating the global error coefficient of the two layers of front-side overlay patterns is: In the formula, is the global error coefficient of the two-layer front-side overlay pattern, is the scaling factor of the sample wafer, is the rotation angle of the sample wafer; the comprehensive front-side overlay error is determined according to the local offset error coefficient and the global error coefficient, and the back-side overlay error and the double-sided error have the same calculation method as the comprehensive front-side overlay error; Based on the comprehensive front-side overlay error, perform error correction on the wafer front-side alignment system in the lithography apparatus. Flip the sample wafer, and perform back-side overlay of the first-layer back-side overlay pattern on the back side of the sample wafer. Use the same processing method as the front-side alignment system to obtain the back-side overlay error. Based on the back-side overlay error, perform error correction on the wafer back-side alignment system in the lithography apparatus. Finally, complete the double-sided overlay error correction according to the double-sided error between the first-layer back-side overlay pattern and the first-layer front-side overlay pattern; Obtain the surface characteristic parameters of the overlay pattern after error correction. Based on the obtained surface characteristic parameters, calculate the photoresist thickness distribution factor and photoresist edge roughness factor, and correct the lithography depth according to the photoresist thickness distribution factor and photoresist edge roughness factor to obtain the accurate depth value of each point of lithography, and complete the over-etching risk control. The surface characteristic parameters include the lithography edge roughness and the average thickness of the photoresist; Among them, the formula for calculating the photoresist thickness distribution factor is: In the formula, The photoresist thickness distribution factor of the i-th feature point, Is the local thickness of the photoresist at the i-th feature point, Is the average thickness of the photoresist on the surface of the sample wafer, Is the amplitude constant of the thickness distribution, Is the maximum radius of the sample wafer; Among them, the formula for calculating the photoresist edge roughness factor is: Wherein, is the photoresist edge roughness factor of the i-th feature point, is the lithography edge roughness of the i-th feature point, is the ideal edge roughness value.

2. A method for controlling the risk of over-etching of the back hole while achieving double-sided overlay accuracy alignment and protection, according to claim 1, characterized in that: Based on the wafer front alignment system in the lithography apparatus to determine the position information of the front alignment marks, and to establish the wafer front coordinate system with the obtained position information of the front alignment marks, the specific steps are as follows: Load the wafer onto the alignment platform of the lithography machine through a robotic arm or other transfer device, and use the vacuum adsorption or clamping mechanism of the lithography apparatus to fix the wafer on the alignment table. The front alignment system in the lithography apparatus will detect the front alignment marks on the wafer through software configuration, perform image processing on the detected marks, and extract the geometric features of the marks. The geometric features include the center position and the edge point coordinates. The reference line between the marks is defined as the X-axis of the wafer front coordinate system, the center position of the mark is defined as the coordinate origin, and the direction perpendicular to the X-axis is the Y-axis, thereby establishing the wafer front coordinate system.

3. A method for double-sided overlay accuracy alignment and protection against the risk of over-etching of back holes according to claim 1, characterized in that: The rotation angle of the sample wafer The formula based on the calculation is as follows: In the formula, and are the characteristic points corresponding to the two-layer front-side overlay patterns, respectively, and are the average offset errors in the axis and the axis; Among them and The formulas based on the calculations are respectively as follows: Among them, the scaling factor of the sample wafer is corrected by the ambient temperature and the clamping stress applied to the sample wafer. The specific calculation is based on the formula: Wherein, is the initial scaling factor of the sample wafer, is the average ambient temperature during the lithography process, is the reference temperature, is the clamping stress applied to the sample wafer, is the Young's modulus of the sample wafer, is the Poisson's ratio of the sample wafer; Among them, the formula for calculating the comprehensive front overlay error is: Wherein, is the comprehensive front alignment error of the i-th feature point, and are the weight coefficients of the local offset error coefficient and the global error coefficient respectively, where and and are both greater than 0.

4. A method for double-sided overlay accuracy alignment and protection of the risk control of over-etching of the back hole according to claim 1, characterized in that: According to the photoresist thickness distribution factor and the photoresist edge roughness factor, correct the lithography depth to obtain the accurate depth value of each point of lithography. The formula for calculating the accurate depth value of each point of lithography is: wherein, is the depth accurate value of the i-th feature point, is the initial overlay depth value of the i-th feature point.

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