Reference voltage circuit

Abstract

The invention provides a reference voltage circuit including a differential amplifier circuit capable of stably performing a constant voltage operation even if a collector voltage of an NPN transistor is input due to a temperature change. A voltage adjustment circuit (30) is provided between a source and a back gate of a common connection of a first PMOS transistor (1) and a second PMOS transistor (2), which are input units of a differential amplifier circuit (10). The collector voltage of an NPN transistor input to one of the input units of the differential amplifier circuit (10) is changed in accordance with a voltage drop due to a temperature rise, so that the voltage generated in the voltage adjustment circuit (30) is adjusted such that the source-back gate voltage between the first PMOS transistor (1) and the second PMOS transistor (2) rises.

Description

Technical Field

[0001] The invention relates to a reference voltage circuit. Background Art

[0002] There is known a reference voltage circuit that performs differential amplification on two input voltages to output a reference voltage. In the reference voltage circuit including the differential amplifier circuit, the voltage input to the input terminal of the differential amplifier circuit is, for example, a voltage based on the voltage of a PN junction element having a PN junction surface such as a diode. In the reference voltage circuit including the differential amplifier circuit, in order to stably perform constant voltage operation, each transistor constituting the differential amplifier circuit is generally operated in a saturation region also called a pentode region. A bandgap reference voltage circuit (hereinafter referred to as a "reference voltage circuit") using an NPN bipolar transistor (hereinafter referred to as an "NPN transistor") at the input of the differential amplifier circuit is proposed (for example, refer to Patent Document 1).

[0003] As an example of a conventional differential amplifier circuit included in a reference voltage circuit, there is, for example, Figure 6 The differential amplifier circuit (3) shown. In the differential amplifier circuit (3) illustrated in Patent Document 2, a P-channel metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) transistor (hereinafter referred to as "PMOS transistor") (P32) as an example of a P-channel field effect transistor (Field Effect Transistor, FET) is turned on, and an N-channel metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) transistor (hereinafter referred to as "NMOS transistor") (N31) as an example of an N-channel FET connected to the drain of the PMOS transistor (P32) is turned on, thereby a first current flows through the PMOS transistor (P32) and the NMOS transistor (N31). In addition, the PMOS transistor (P33) is turned on, and the NMOS transistor (N32) connected to the drain of the PMOS transistor (P33) is turned on, thereby a second current flows through the NMOS transistor (N32) and the PMOS transistor (P33). The differential amplifier circuit (3) compares the first current and the second current, performs differential amplification, and outputs an output voltage from an output terminal (at least one of O1 and O2).

[0004] An existing reference voltage circuit including a differential amplifier circuit, for example, as shown in FIG. 14 of Patent Document 1, generates two voltages (VA, VB) based on the output voltage of the differential amplifier circuit, and inputs the two voltages as the first input voltage and the second input voltage of the differential amplifier circuit, respectively, thereby performing negative feedback control to obtain a reference voltage (Reference Voltage, VREF) that has no temperature dependence.

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 10-303658

[0008] [Patent Document 2] Japanese Patent Application Publication No. 2005-136473 Summary of the invention

[0009] [Problems to be solved by the invention]

[0010] However, in the conventional reference voltage circuit including a differential amplifier circuit composed of two PMOS transistors and two NMOS transistors as described in Patent Document 1, it is difficult to perform a constant voltage operation at a low power supply voltage of, for example, 2 V (volts) or less. To be more specific, in the conventional reference voltage circuit, the voltage supplied to the input terminal of the differential amplifier circuit may drop excessively as the external temperature changes.

[0011] When the reference voltage circuit is operated at a constant voltage, in order to obtain a stable operation, each metal oxide semiconductor (MOS) transistor constituting the differential amplifier circuit included in the reference voltage circuit needs to be operated at a saturation. Here, the following case is used as an example for explanation: the conventional differential amplifier circuit is set to the differential amplifier circuit (3) described in Patent Document 2, and the collector voltage of an NPN transistor whose collector and base are connected (so-called diode connection) is used as the input voltage of the differential amplifier circuit (3).

[0012] In the differential amplifier circuit (3), when the voltage applied to the gate of the PMOS transistor (P32) decreases due to external factors such as temperature changes, the source voltage of the PMOS transistor (P32) decreases. The decrease in the source voltage of the PMOS transistor (P32) causes the drain-source voltage of the PMOS transistor (P32) to decrease, so the PMOS transistor (P32) may not be able to perform saturation operation. In other words, the PMOS transistor (P32) may perform unsaturated operation. On the other hand, when the voltage applied to the gate of the PMOS transistor (P32) increases, the source voltage of the PMOS transistor (P32) increases, and the drain-source voltage of the PMOS transistor (P31) operating as a current source decreases, which may cause unsaturated operation. When the PMOS transistor (P31) is in unsaturated operation, the PMOS transistor (P31) may not be able to flow a predetermined constant current. Thus, in the conventional circuit structure, there is a restriction on the source voltage of the PMOS transistor (P32) (the voltage range in which saturation operation can be performed is narrow), and it is difficult to suppress the minimum operating voltage that can be input as the power supply voltage (VDD) while making each MOS transistor perform saturation operation.

[0013] In view of the above situation, an object of the present invention is to provide a reference voltage circuit including a differential amplifier circuit, which can stably perform a constant voltage operation while suppressing the minimum operating voltage to be lower than before, even if the voltage of a PN junction element included in the reference voltage circuit, such as the collector voltage of a diode-connected NPN transistor, changes due to external temperature changes and is input to the differential amplifier circuit.

[0014] [Technical means to solve the problem]

[0015] A reference voltage circuit according to an embodiment of the present invention includes a differential amplifier circuit, wherein the gates of a first PMOS transistor and a second PMOS transistor are respectively used as inputs, the drains of the first PMOS transistor and the second PMOS transistor are respectively connected to the drains of the first NMOS transistor and the second NMOS transistor, the sources and back gates of the first NMOS transistor and the second NMOS transistor are connected to a ground terminal, the differential amplifier circuit includes a voltage adjustment circuit, the voltage adjustment circuit includes a first end, a second end, and a power supply end, and is capable of adjusting a voltage between the first end and the second end, the first end is connected to a source commonly connected to the first PMOS transistor and the second PMOS transistor, the second end is connected to a back gate commonly connected to the first PMOS transistor and the second PMOS transistor, the power supply end is connected to a power supply terminal, and the voltage adjustment circuit is configured such that a voltage generated between the first end and the second end increases or decreases according to a change in an input voltage of the differential amplifier circuit.

[0016] In one embodiment of the present invention, the voltage adjustment circuit comprises: a current source connected between the power supply terminal and the second terminal; and a resistor connected between the first terminal and the second terminal, wherein the resistor comprises a variable resistor having a temperature coefficient of opposite polarity to the temperature coefficient of the voltage input to the gate of the first P-channel metal oxide semiconductor transistor and capable of adjusting the resistance value.

[0017] In one embodiment of the present invention, the voltage adjustment circuit comprises: a current source connected between the power supply terminal and the second terminal; and a resistor connected between the first terminal and the second terminal, wherein the current source is a variable current source, and the variable current source can adjust the current value in such a way that the voltage generated at both ends of the resistor increases or decreases according to the change of the input voltage of the differential amplifier circuit.

[0018] In one embodiment of the present invention, the voltage adjustment circuit is configured to generate a voltage that is lower than the gate voltage or threshold voltage of the first P-channel metal oxide semiconductor transistor and the second P-channel metal oxide semiconductor transistor within a specified temperature range, and is a voltage having a temperature coefficient with a polarity opposite to the polarity of the temperature coefficient of the voltage input to the gate of the first P-channel metal oxide semiconductor transistor.

[0019] In one embodiment of the present invention, the generated voltage is greater than or equal to 0.10 V and less than or equal to 0.35 V within the predetermined temperature range.

[0020] [Effects of the Invention]

[0021] According to the present invention, even if the minimum operating voltage of the differential amplifier circuit in the reference voltage circuit is suppressed to a low level, the saturation operation of each MOS transistor constituting the differential amplifier circuit can be stabilized under the condition that the voltage input to the differential amplifier circuit changes due to external temperature changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 : is a circuit diagram showing a configuration example of a reference voltage circuit according to an embodiment of the present invention.

[0023] Figure 2 : is a circuit diagram showing a configuration example of a differential amplifier circuit in the reference voltage circuit of the present embodiment.

[0024] Figure 3 : is a circuit diagram showing a first configuration example of a voltage adjustment circuit of a differential amplifier circuit in the reference voltage circuit of the present embodiment.

[0025] Figure 4 : is a circuit diagram showing a configuration example of a differential amplifier circuit in a reference voltage circuit of a first comparative example.

[0026] Figure 5 : is a circuit diagram showing a configuration example of a differential amplifier circuit in a reference voltage circuit of a second comparative example.

[0027] Figure 6 This is a circuit diagram showing a modified example (second configuration example) of the voltage adjustment circuit of the differential amplifier circuit in the reference voltage circuit of the present embodiment.

[0028] [Explanation of Symbols]

[0029] 1: PMOS transistor / first PMOS transistor

[0030] 2: PMOS transistor / second PMOS transistor

[0031] 3, 4, 93, 94, 95: NMOS transistors

[0032] 5.6: Transistor

[0033] 7a: Variable resistor

[0034] 7b: Fixed resistor

[0035] 8a: Variable Current Source

[0036] 8b: Constant current source

[0037] 10: Differential amplifier circuit

[0038] 11: VDD terminal

[0039] 12: GND terminal

[0040] 15, 16: Reference voltage source

[0041] 20: Buffer

[0042] 21, 22, 23: Resistance

[0043] 25, 26: Output terminal

[0044] 30, 30A: Voltage regulation circuit

[0045] 30a: First end

[0046] 30b: Second end

[0047] 30c: Power supply end

[0048] 50: VREF output terminal

[0049] 90, 91, 92: PMOS transistors

[0050] 100: Reference voltage circuit

[0051] 210, 310: Differential amplifier circuit

[0052] GND: Ground voltage

[0053] INN: Inverting input

[0054] INP: non-inverting input

[0055] N1, N2, N3: connection points

[0056] To: Output

[0057] Vbias: bias voltage

[0058] VDD: power supply voltage / voltage DETAILED DESCRIPTION

[0059] Hereinafter, a reference voltage circuit according to an embodiment of the present invention will be described with reference to the drawings.

[0060] [Overall reference voltage circuit]

[0061] Figure 1 : is a circuit diagram showing the overall configuration of a reference voltage circuit 100 as an example of a reference voltage circuit according to an embodiment of the present invention.

[0062] The reference voltage circuit 100 includes: a VDD terminal 11 for supplying a voltage VDD as an example of a power supply voltage, a GND terminal 12 for supplying a ground voltage GND different from the voltage VDD, a VREF output terminal 50 for outputting a reference voltage VREF, a differential amplifier circuit 10, a buffer 20, a reference voltage source 15, a reference voltage source 16, a resistor 21, and a resistor 22.

[0063] The reference voltage source 15 comprises an output terminal 25 and a transistor 5 which is a first NPN transistor.

[0064] The reference voltage source 16 includes an output terminal 26 , a resistor 23 , and a transistor 6 which is a second NPN transistor.

[0065] The differential amplifier circuit 10 includes: a power supply terminal, a ground terminal, an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal To. The power supply terminal of the differential amplifier circuit 10 is connected to the VDD terminal 11. The ground terminal of the differential amplifier circuit 10 is connected to the GND terminal 12. The non-inverting input terminal (+) is connected to the output terminal 25. The inverting input terminal (-) is connected to the output terminal 26. The output terminal To is connected to the VREF output terminal 50 via the buffer 20. The resistor 21 and the resistor 22 are connected to the connection point N1 between the buffer 20 and the VREF output terminal 50.

[0066] Here, of the two ends of the resistor 21, one end connected to the connection point N1 is called a first end, and the other end is called a second end. The first end and the second end of the resistor 22 are also called the same as the first end and the second end of the resistor 21.

[0067] The emitter of the transistor 5 is connected to the GND terminal 12. The base and collector of the transistor 5 are directly connected to the output terminal 25 of the reference voltage source 15 and the second end of the resistor 21.

[0068] The emitter of transistor 6 is connected to GND terminal 12. The base and collector of transistor 6 are directly connected to the first end of resistor 23. The second end of resistor 23 is connected to output end 26 of reference voltage source 16 and the second end of resistor 22.

[0069] The operation of the reference voltage circuit 100 will be described. In the above description, it is assumed that the distribution of the sizes of the resistors 21, 22, 23, transistors 5, and transistors 6 is appropriately selected in advance. If the output terminal of the buffer 20 is separated from the connection point N1 and the voltage of the connection point N1 is gradually increased from 0, the voltage of the output terminal 25 of the reference voltage source 15 hardly increases from a certain specific value. On the other hand, the voltage of the output terminal 26 of the reference voltage source 16 is lower than the voltage of the output terminal 25 near zero in the case of the same increase pattern of the voltage of the connection point N1, but after reaching a certain specific value, it also slowly continues to increase and becomes higher than the voltage of the output terminal 25. That is, the high-low relationship between the voltage of the output terminal 25 and the voltage of the output terminal 26 is reversed from the middle.

[0070] Here, if the voltage at the connection point N1 is added or subtracted so that the voltage at the output terminal 25 of the reference voltage source 15 and the voltage at the output terminal 26 of the reference voltage source 16 become equal, the voltage at the connection point N1 becomes a constant voltage regardless of temperature or the like.

[0071] If the voltage of the output terminal 25 of the reference voltage source 15 is input to the non-inverting input terminal (+) of the differential amplifier circuit 10, the voltage of the output terminal 26 of the reference voltage source 16 is input to the inverting input terminal (-), the signal from the output terminal To is input to the buffer 20, and a current is supplied from the output terminal of the buffer 20 to the resistor 21 and the resistor 22 via the connection point N1, then the certain reference voltage VREF that is independent of temperature, etc. appears at the VREF output terminal 50 connected to the connection point N1.

[0072] [Differential amplifier circuit]

[0073] Figure 2 : is a circuit diagram showing a configuration example of a differential amplifier circuit 10 as an example of a differential amplifier circuit included in the reference voltage circuit of the present embodiment.

[0074] The differential amplifier circuit 10 includes a PMOS transistor 1, a PMOS transistor 2, an NMOS transistor 3, and an NMOS transistor 4 constituting a differential pair, and a voltage adjustment circuit 30 including a first terminal 30a, a second terminal 30b, and a power supply terminal 30c. Here, the non-inverting input terminal (+) and the inverting input terminal (-) of the differential amplifier circuit 10 correspond to the gate of the PMOS transistor 1 and the gate of the PMOS transistor 2, respectively. The power supply terminal of the differential amplifier circuit 10 corresponds to the power supply terminal 30c in the voltage adjustment circuit 30. In addition, the ground terminal of the differential amplifier circuit 10 corresponds to the back gate and source of the NMOS transistor 3 and the NMOS transistor 4. The output terminal To is connected to the connection point of the drain of the PMOS transistor 2 and the drain of the NMOS transistor 4.

[0075] The drains of the PMOS transistor 1 and the PMOS transistor 2 are connected to the drains of the NMOS transistor 3 and the NMOS transistor 4. The sources of the NMOS transistor 3 and the NMOS transistor 4 are connected to the GND terminal 12. The PMOS transistor 1 and the PMOS transistor 2 have a common source at a connection point N2 at which the sources are connected to each other, and a common back gate at a connection point N3 at which the back gates are connected to each other.

[0076] The voltage regulating circuit 30 is a circuit having a function of regulating the voltage applied between the first end 30a and the second end 30b. In the voltage regulating circuit 30, the first end 30a is connected to the connection point N2, and the second end 30b is connected to the connection point N3. In addition, the power supply terminal 30c is connected to the VDD terminal 11. From the perspective of reducing the influence of the negative temperature coefficient T1 (<0) of the voltage input to the differential amplifier circuit 10, that is, the voltage of the PN junction element, the voltage applied between the first end 30a and the second end 30b is configured to have a positive temperature coefficient T2 (>0) smaller than the absolute value of the temperature coefficient T1. Here, the temperature coefficient T1 is known to be -2mV / ℃, so the temperature coefficient T2 is set to [X1]mV / ℃ which is greater than 0. The temperature coefficient T2 is more preferably set to [1mV / ℃≦T2≦2mV / ℃], and is further preferably set to [2mV / ℃].

[0077] Figure 3 : is a circuit diagram showing a configuration example of a voltage regulating circuit 30 which is an example (first configuration example) of a voltage regulating circuit in a differential amplifier circuit included in the reference voltage circuit of the present embodiment.

[0078] The voltage regulating circuit 30 includes: a resistor including a variable resistor 7a having a resistance value with a positive temperature coefficient and configured to be able to adjust the resistance value; and a constant current source 8b for supplying a predetermined constant current. The first end and the second end of the variable resistor 7a are connected to the first end 30a and the second end 30b of the voltage regulating circuit 30, respectively. The first end and the second end of the constant current source 8b are connected to the power supply end 30c and the second end 30b of the voltage regulating circuit 30, respectively. The voltage regulating circuit 30 is configured to be able to adjust the voltage value of the voltage having a positive temperature coefficient applied between the first end 30a and the second end 30b by adjusting the resistance value of the variable resistor 7a.

[0079] Next, the reference voltage circuit including the differential amplifier circuit 10 (the first embodiment to the third embodiment: Figure 1 ) is centered on the differential amplifier circuit 10, which has a significant difference, and includes a differential amplifier circuit 210 (see the following Figure 4 ) of the reference voltage circuit (first comparative example) and a differential amplifier circuit 310 (see the following description) Figure 5 ) is compared with a reference voltage circuit (second comparative example) of FIG. 1. In order to make the conditions consistent with those of the differential amplifier circuit 10, the voltage input to the gate of the PMOS transistor 91 and the PMOS transistor 92 is assumed to be the same as the voltage input to the gate of the PMOS transistor 1 and the PMOS transistor 2, that is, the voltage output from the reference voltage source 15 and the reference voltage source 16.

[0080] (First Comparative Example)

[0081] Figure 4 : is a circuit diagram showing a configuration example of a differential amplifier circuit 210 of a reference voltage circuit according to a first comparative example.

[0082] The differential amplifier circuit 210 includes a PMOS transistor 90 receiving a bias voltage Vbias at its gate, a PMOS transistor 91, a PMOS transistor 92, and an NMOS transistor 93 and an NMOS transistor 94 constituting a differential pair, and is substantially equivalent to the differential amplifier circuit of Patent Document 2. Figure 6 The differential amplifier circuit (3) shown.

[0083] The operation of the differential amplifier circuit 210 will be briefly described. The differential amplifier circuit 210 inputs voltages to the gate of the PMOS transistor 91 corresponding to the non-inverting input terminal INP and the gate of the PMOS transistor 92 corresponding to the inverting input terminal INN. In addition, it is assumed that the voltages input to the gates of the PMOS transistors 91 and 92 in a manner comparable to the differential amplifier circuit 10 are voltages based on the voltage of the PN junction element.

[0084] The voltage at the source of PMOS transistor 91 and PMOS transistor 92 automatically increases from the voltage at the midpoint between the voltage at the gate of PMOS transistor 91 and the voltage at the gate of PMOS transistor 92 (hereinafter referred to as the "common-phase input voltage") to a voltage that is higher than the absolute value of the gate threshold voltage of PMOS transistor 91 and PMOS transistor 92.

[0085] Therefore, the voltage of the difference between the gate voltage of the PMOS transistor 91 and the gate voltage of the PMOS transistor 92 ideally appears in proportion to the difference between the drain current of the PMOS transistor 91 and the drain current of the PMOS transistor 92, regardless of the non-inverting input voltage. The current mirror circuit composed of the NMOS transistor 93 and the NMOS transistor 94 converts the change of the difference between the drain current of the PMOS transistor 91 and the drain current of the PMOS transistor 92 into a change of voltage, and outputs it to the output terminal To of the differential amplifier circuit 210.

[0086] Here, the drain-source voltage of the PMOS transistor 91 and the PMOS transistor 92 is described. The source voltage of the PMOS transistor 91 and the PMOS transistor 92 is higher than the gate voltage of the PMOS transistor 91 and the PMOS transistor 92 by an amount corresponding to the absolute value of the gate threshold voltage of the PMOS transistor 91 and the PMOS transistor 92. Since the drain and the gate of the NMOS transistor 93 are directly connected, the drain voltage of the PMOS transistor 91 becomes the drain and gate voltage of the NMOS transistor 93.

[0087] Therefore, the absolute value of the drain-source voltage of the PMOS transistor 91 is obtained by adding the absolute values ​​of the gate threshold voltages of the PMOS transistors 91 and 92 to the gate voltages of the PMOS transistors 91 and 92 and subtracting the gate threshold voltage of the NMOS transistor 93 .

[0088] If the temperature of the differential amplifier circuit 210 and its surroundings rises, then around the PMOS transistor 91, (I) the voltage input to the gate of the PMOS transistor 91 decreases, (II) the absolute value of the gate threshold voltage of the PMOS transistor 91 decreases, and (III) the gate threshold voltage of the NMOS transistor 93 decreases. Since the drain of the PMOS transistor 91 and the drain and gate of the NMOS transistor 93 form the same node, the changes caused by (II) and (III) respectively decrease the source voltage and drain voltage of the PMOS transistor 91, and thus the changes are offset from the drain-source voltage of the PMOS transistor 91. As a result, among (I) to (III), the decrease in the voltage input to the gate of the PMOS transistor 91 (I) affects the change in the absolute value of the drain-source voltage of the PMOS transistor 91.

[0089] If the temperature rises in the reference voltage circuit including the differential amplifier circuit 210 and the reference voltage sources 15 and 16, the absolute value of the drain-source voltage of the PMOS transistor 91 decreases. Therefore, if the temperature rise exceeds the specified value, the absolute value of the drain-source voltage of the PMOS transistor 91 becomes lower than the lower limit value that can maintain the operation in the saturation region, and the operation in the saturation region cannot be ensured.

[0090] (Second Comparative Example)

[0091] Figure 5 : is a circuit diagram showing a configuration example of a differential amplifier circuit 310 of a reference voltage circuit according to a second comparative example.

[0092] The difference between the differential amplifier circuit 310 and the differential amplifier circuit 210 is that the differential amplifier circuit 310 further includes an NMOS transistor 95, but is substantially the same in other aspects. Therefore, when describing the differential amplifier circuit 310, components that are substantially the same as those of the differential amplifier circuit 210 are denoted by the same reference numerals and repeated descriptions are omitted.

[0093] The drain and gate of the NMOS transistor 95 and the source of the PMOS transistor 90 are connected to the common back gate of the PMOS transistors 91 and 92, that is, the connection point N3. The source of the NMOS transistor 95 is connected to the common source of the PMOS transistors 91 and 92, that is, the connection point N2. The back gate of the NMOS transistor 95 is connected to the GND terminal 12.

[0094] In the differential amplifier circuit 310 configured in this manner, the substrate bias voltage V is the voltage between the substrate (back gate) and the source of the PMOS transistor 91 and the PMOS transistor 92. BS becomes a voltage based on the PN junction in the NMOS transistor 95. However, due to the substrate bias voltage V BS The temperature characteristic of becomes a negative temperature characteristic. Therefore, if the temperature rises in the reference voltage circuit including the differential amplifier circuit 310 and the reference voltage sources 15 and 16, the substrate bias voltage V in the differential amplifier circuit 310 BS The voltage also drops in the same manner as the voltage input to the gate of the PMOS transistor 91 .

[0095] (First to Third Embodiments)

[0096] On the other hand, in the differential amplifier circuit 10 including the voltage adjustment circuit 30, the voltage of the common back gate of the PMOS transistor 1 and the PMOS transistor 2, that is, the connection point N3 is increased by the potential difference generated at both ends (the first end 30a and the second end 30b) of the voltage adjustment circuit 30. By adopting a structure in which the voltage of the connection point N3 is increased, the absolute values ​​of the substantial gate threshold voltages of the PMOS transistor 1 and the PMOS transistor 2 are increased relative to the absolute values ​​of the gate threshold voltages of the PMOS transistor 91 and the PMOS transistor 92.

[0097] Compared to the differential amplifier circuit 210, in the differential amplifier circuit 10, the PMOS transistors 1 and 2 have substantially greater absolute values ​​of drain-source voltages than the absolute values ​​of drain-source voltages of the PMOS transistors 91 and 92, and thus can ensure operation in the saturation region with respect to a wider range of temperature rise. That is, compared to the differential amplifier circuit 210, the temperature band in which the differential pair can operate correctly can be expanded. In addition, as described in the subject, it is also important that the voltage difference generated in the voltage adjustment circuit 30 is correspondingly small in accordance with the small voltage generated by the temperature change of the gate voltages of the PMOS transistors 1 and 2 corresponding to the input voltage of the differential amplifier circuit.

[0098] The voltage regulator circuit 30 adjusts the voltage at both ends in a manner that increases or decreases according to the change of the input voltage of the differential amplifier circuit 10, so that the PMOS transistor 1 and the PMOS transistor 2 produce a substrate bias effect. The voltage between the source and the substrate (back gate) of the PMOS transistor 1 and the PMOS transistor 2 is called the substrate bias voltage V BS . Using substrate bias voltage V BS , the threshold voltage Vth of PMOS transistor 1 and PMOS transistor 2 is expressed by the following formula (1).

[0099] [Number 1]

[0100]

[0101] Here, V FB is the flat band voltage, 2φ F To achieve the surface potential in the inversion state, C OX is the gate oxide film capacitance, ε is the dielectric constant, q is the pixel charge, N D is the donor density.

[0102] According to formula (1), the absolute value of the substrate bias voltage |V BS | The larger the value, the larger the threshold voltage Vth of PMOS transistor 1 and PMOS transistor 2. If a positive substrate bias voltage V is applied so that the voltage of the back gate becomes higher than the voltage of the source, BS , a reverse bias is applied to the PN junction between the P-type channel and the N-type well formed by inversion on the channel surface of PMOS transistor 1 and PMOS transistor 2 (hereinafter referred to as "reverse bias applied state"). In the reverse bias applied state, the depletion layer expands and the positive charge in the depletion layer increases compared to the state where the reverse bias is not applied. The increase in positive charge in the depletion layer increases the gate voltage used to form the channel, so a larger gate voltage is required, thereby increasing the threshold voltage |Vth| of PMOS transistor 1 and PMOS transistor 2.

[0103] In order to suppress the lowest operating voltage that can be used as the voltage VDD, it is sufficient to reduce the drain-source voltage Vds for the saturation operation of the PMOS transistor 1 and the PMOS transistor 2. The drain-source voltage Vds required for the saturation operation of the PMOS transistor 1 and the PMOS transistor 2 is obtained by using the gate-source voltage Vgs and the threshold voltage Vth.

[0104] Vds≧Vgs-Vth···(2)

[0105] Therefore, in order to reduce the drain-source voltage Vds at which the PMOS transistor 1 and the PMOS transistor 2 perform saturation operation, it is sufficient to reduce Vgs-Vth (=Vov).

[0106] In the differential amplifier circuit 10 including the voltage regulator circuit 30, the voltage difference between the two ends (the first end 30a and the second end 30b) of the voltage regulator circuit 30 is adjusted in a manner satisfying the above-mentioned equation (2) within the assumed operating temperature range. Here, if the operation is performed under a constant voltage of 2V as an example of a low voltage, the absolute value of the substrate bias voltage |V BS Since the upper limit satisfying the formula (2) is about 0.36 V, the voltage is adjusted to a positive voltage of 0.36 V or less.

[0107] However, if the absolute value of the substrate bias voltage |V BS | is too low to fully obtain the threshold voltage raising effect caused by the back gate effect, so it is preferably adjusted to 0.07V or more and 0.36V or less, and more preferably adjusted to a predetermined range of more than 0.1V and less than 0.3V including 0.2V, that is, around 0.2V. In this embodiment, the absolute value of the substrate bias voltage |V is prepared. BS |In the positive voltage range of 0.36V or less, and the values ​​are different in three embodiments. The absolute value of the substrate bias voltage|V BS |They are called the first embodiment, the second embodiment and the third embodiment in order from the lowest (see Table 1 described later for details).

[0108] In addition, by adjusting the substrate bias voltage V BS The temperature characteristic of is set to be positive. When a temperature change occurs in the reference voltage circuit 100, the substrate bias voltage V is set to be positive in accordance with the change in the voltage input to the gate of the PMOS transistor 1. BS That is, when the temperature rises in the reference voltage circuit 100, the voltage input to the gate of the PMOS transistor 1 decreases, but the substrate bias voltage V of the PMOS transistor 1 and the PMOS transistor 2 increases. BSChanges in the opposite upward direction.

[0109] Next, for the first to third embodiments, the first comparative example, and the second comparative example, specific numerical examples are described by listing Tables 1 and 2. Here, Examples (1) to (5) in Tables 1 and 2 correspond to the first comparative example, the first embodiment, the second embodiment, the third embodiment, and the second comparative example, respectively.

[0110] VDD1 recorded in Table 1 is the voltage VDD required for the saturation operation of the PMOS transistor 1 or the PMOS transistor 91, VDD2 is the voltage VDD required for the saturation operation of the NMOS transistor 3 or the NMOS transistor 93, Vf is the collector voltage of the transistor 5, Vgsp is the gate-source voltage of the PMOS transistor 1 or the PMOS transistor 91, Vdsp is the drain-source voltage of the PMOS transistor 1 or the PMOS transistor 91, and Vgsn is the gate-source voltage of the NMOS transistor 3 or the NMOS transistor 93, which is the same as the drain-source voltage Vdsn of the NMOS transistor 3 or the NMOS transistor 93. I8 is the voltage between the terminals of the constant current source 8b, V R7 is the voltage between the terminals of the variable resistor 7a.

[0111] In addition, the threshold voltage Vthp of the PMOS transistor 1 or the PMOS transistor 91 can be obtained by replacing V R7 Substituting the absolute value of the substrate bias voltage |V BS The threshold voltage Vthn of the NMOS transistor 3 or the NMOS transistor 93 is the absolute value of the substrate bias voltage |V in equation (1): BS |=value when 0V.

[0112] Furthermore, the judgment column of Table 1 shows the result of the judgment based on Formula (2), and the presence or absence of a mark "○" indicates whether the following Formulas (3) and (4) are satisfied for the PMOS transistor 1 or the PMOS transistor 91 and the NMOS transistor 3 or the NMOS transistor 93. When Formula (3) is satisfied, a mark "○" is marked in the column of Formula (3) (mark "○" is present), and when Formula (4) is satisfied, a mark "○" is marked in the column of Formula (4).

[0113] Vdsp≧Vgsp-Vthp···(3)

[0114] Vdsn≧Vgsn-Vthn···(4)

[0115] [Table 1]

[0116]

[0117] Table 1 shows whether each of the examples (1) to (5) satisfies the above formula (3) and formula (4) at a representative value of the low temperature side temperature of -40°C and a representative value of the high temperature side temperature of at least a continuous temperature range of -40°C to 125°C. Here, the threshold voltage Vthp of the PMOS transistor 1 or the PMOS transistor 91 can be obtained by replacing V in the formula (1) with R7 Substituting the absolute value of the substrate bias voltage |V BS The threshold voltage Vthn of the NMOS transistor 3 or the NMOS transistor 93 is the absolute value of the substrate bias voltage |V in equation (1): BS |=value when 0V.

[0118] In Example (1) (Comparative Example 1), although V R7 =|V BS | is a fixed value of 0V and cannot be adjusted, but at -40°C and 125°C, there are VDD1 and VDD2 that satisfy the above equations (3) and (4). Example (5) (Second Comparative Example) is to connect NMOS transistor 95 to V R7 =|V BS | is an example of configuring the differential amplifier circuit 310 so as to obtain 0.4V at -40°C and 0.5V at 125°C. In Example (5) (the second comparative example), there are VDD1 and VDD2 that satisfy the above equations (3) and (4). In Example (5), in order to change V R7 =|V BS |, it is necessary to change the characteristics of the NMOS transistor 95 or change the operating conditions, which is difficult compared to adjusting the resistance value of the resistor or the current value flowing in the resistor.

[0119] On the other hand, in Example (2) (first embodiment), Example (3) (second embodiment) and Example (4) (third embodiment), by adjusting the resistance value of the variable resistor 7a, V R7 =|V BS |, so we can search for V that satisfies the above formula (2) R7 The threshold voltage Vthp of the PMOS transistor 1 and the PMOS transistor 2 is changed by adjusting the value of Vthp. The differential amplifier circuit 10 has the same structure simplicity as the differential amplifier circuit 310 without increasing the number of components. R7 =|V BS |The adjustment compared to V R7 =|V BS In the examples (2), (3) and (4) shown in Table 1, the resistance value of the variable resistor 7a can be adjusted to adjust V R7 =|V BS| VDD1 and VDD2 satisfying the above formula (2) can be obtained by adjusting them to 0.07 V, 0.20 V and 0.30 V at -40°C and 0.10 V, 0.23 V and 0.36 V at 125°C.

[0120] [Table 2]

[0121]

[0122] Table 2 shows the calculation results of VDD1 and VDD2 shown in Table 1. Differential amplifier circuit 10, differential amplifier circuit 210, differential amplifier circuit 310 ( Figure 2 , Figure 4 , Figure 5 ) is the VDDmax listed in Table 2. VDDmax is the higher of VDD1 and VDD2. The mark "○" in the judgment column indicates that VDDmax is less than 2V, and the mark "×" indicates that VDDmax is not less than 2V, that is, VDDmax is greater than 2V.

[0123] As shown in Table 2, in Example (1) and Example (5), that is, in the differential amplifier circuit 210 and the differential amplifier circuit 310, the minimum operating voltage VDDmax exceeds 2.0V. R7 =|V BS |In the voltage band less than 0.07V (Example (1)) or the voltage band greater than 0.4V (Example (5)), even if PMOS transistor 91, PMOS transistor 92 and NMOS transistor 93, NMOS transistor 94 can be used in the saturation region, VDDmax, which is the minimum operating voltage, cannot be suppressed to less than 2.0V.

[0124] On the other hand, in the differential amplifier circuit 10 of examples (2), (3) and (4), the minimum operating voltage VDDmax is lower than 2.0 V. Thus, it can be seen that in the reference voltage circuit 100 including the differential amplifier circuit 10, V R7 =|V BS |VDDmax is set to a positive voltage of about 0.36V or less, which is less than 2.0V and enables the use of PMOS transistor 1, PMOS transistor 2, NMOS transistor 3, and NMOS transistor 4 in the saturation region, preferably within a range of 0.07V to 0.36V (roughly 0.10V to 0.35V), and more preferably within a range of about 0.2V, thereby allowing the use of PMOS transistor 1, PMOS transistor 2, NMOS transistor 3, and NMOS transistor 4 in the saturation region while suppressing VDDmax, which is the minimum operating voltage, to a low voltage of less than 2.0V.

[0125] As described above, the reference voltage circuit 100 includes the differential amplifier circuit 10, and the differential amplifier circuit 10 includes a substrate bias voltage V BS The voltage adjustment circuit 30 that can be easily adjusted. The reference voltage circuit 100 includes the differential amplifier circuit 10, and can adjust the voltage and apply it between the common source and the common back gate of the PMOS transistor 1 and the PMOS transistor 2 so that the potential of the common back gate is higher than the potential of the common source. Since the potential difference between the common source and the common back gate of the PMOS transistor 1 and the PMOS transistor 2 can be adjusted, the magnitude of the back gate effect given to the PMOS transistor 1 and the PMOS transistor 2 can be adjusted.

[0126] The reference voltage circuit 100 includes a differential amplifier circuit 10 configured to be able to adjust the magnitude of the back gate effect applied to the PMOS transistor 1 and the PMOS transistor 2. Therefore, even if the drain-source voltage of the PMOS transistor 1 and the PMOS transistor 2 is configured to be small in a state where no substrate bias effect is applied, in an environment where the input voltage fluctuates due to temperature changes, stable operation of the PMOS transistor 1 and the PMOS transistor 2 and the NMOS transistor 3 and the NMOS transistor 4 in the saturation region can be ensured.

[0127] In other words, when the operable range in the saturation region of the differential amplifier circuit 10 is designed to be equal to the operable range in the saturation region of the differential amplifier circuit 210, the absolute value of the drain-source voltage in a state where the substrate bias effect is not applied to the PMOS transistors 1 and 2 can be designed to be smaller than the absolute value of the drain-source voltage of the PMOS transistors 91 and 92. In other words, the voltage VDD supplied to the differential amplifier circuit 10 can be made lower than the voltage VDD supplied to the differential amplifier circuit 210.

[0128] According to the reference voltage circuit 100, the voltage adjusted by the voltage adjustment circuit 30, that is, the substrate bias voltage V BS The reference voltage circuit 100 has a positive temperature coefficient of opposite polarity to the temperature coefficient of the gate voltage of the PMOS transistor 1 input to the differential amplifier circuit 10. Therefore, according to the reference voltage circuit 100, the substrate bias voltage V BS According to the change in the voltage input to the gate of the PMOS transistor 1 , the voltage changes in the direction opposite to the change.

[0129] In addition, the reference voltage circuit 100 includes the differential amplifier circuit 10, and thus the magnitude of the substrate bias effect can be easily adjusted and given, so that the substrate bias voltage V can be adjusted to achieve both a lower minimum operating voltage and ensuring stable operation of the PMOS transistors 1 and 2 and the NMOS transistors 3 and 4 in the saturation region. BS . More specifically, within a predetermined temperature range such as the assumed use temperature range, the inter-terminal voltage between the first end 30a and the second end 30b is designed to be approximately 0.1V to 0.3V. The absolute value of the gate threshold voltage of the PMOS transistor 1 and the PMOS transistor 2 increases by an amount corresponding to the set inter-terminal voltage between the first end 30a and the second end 30b, and thus the source voltage of the PMOS transistor 1 and the PMOS transistor 2 increases accordingly. As a result, the absolute value of the drain-source voltage of the PMOS transistor 1 and the PMOS transistor 2 increases, and the differential amplifier circuit 10 can be operated stably.

[0130] Therefore, according to the reference voltage circuit of this embodiment, even if the minimum operating voltage of the differential amplifier circuit is suppressed to a low level, the saturation operation of each MOS transistor constituting the differential amplifier circuit can be stabilized in a situation where the voltage input to the differential amplifier circuit changes due to external temperature changes. According to the reference voltage circuit of this embodiment, the minimum operating voltage that can be used as the power supply voltage VDD can be suppressed to a low level, so it can contribute to energy saving of a semiconductor integrated circuit such as a linear regulator including the reference voltage circuit of this embodiment.

[0131] In addition, the present invention is not limited to the above-described embodiments, and in the implementation stage, it can be implemented in various ways other than the above-described embodiments, and various omissions, additions, substitutions, or changes can be made without departing from the scope of the invention. For example, Figure 1 The reference voltage circuit 100 shown in FIG. 1 includes the buffer 20, but the buffer 20 may be omitted. That is, the reference voltage circuit of this embodiment may have a configuration that does not include a buffer.

[0132] In addition, the differential amplifier circuit 10 is an example including the voltage adjustment circuit 30, but the differential amplifier circuit 10 may also include a voltage adjustment circuit 30A instead of the voltage adjustment circuit 30 (see Figure 6 ).

[0133] Figure 6 : is a circuit diagram showing a configuration example of a voltage adjustment circuit 30A which is a modified example (second configuration example) of the voltage adjustment circuit of the differential amplifier circuit in the reference voltage circuit of the present embodiment.

[0134] The voltage regulating circuit 30A has a fixed resistor 7b having a predetermined resistance value and a variable current source 8a, and is configured to be able to adjust the voltage between the first end 30a and the second end 30b. The fixed resistor 7b has a predetermined resistance value, and the variable current source 8a is configured to be able to adjust the supplied current value. According to the voltage regulating circuit 30A, the first end and the second end of the fixed resistor 7b are connected to the first end 30a and the second end 30b of the voltage regulating circuit 30A, respectively. The first end and the second end of the variable current source 8a are connected to the power supply end 30c and the second end 30b of the voltage regulating circuit 30A, respectively.

[0135] Thus, the voltage regulating circuit 30A is different from the voltage regulating circuit 30 in that it has a fixed resistor 7b instead of the variable resistor 7a and a variable current source 8a instead of the constant current source 8b, but other aspects are substantially the same as the voltage regulating circuit 30. In the voltage regulating circuit 30A, the voltage between the first end 30a and the second end 30b is adjusted by adjusting the current value of the current supplied by the variable current source 8a.

[0136] These embodiments and modifications thereof are included in the scope and spirit of the inventions and are included in the inventions described in the claims and their equivalents.

Claims

1. A reference voltage circuit, characterized in that: Including differential amplifier circuit, The gates of the first P-channel metal oxide semiconductor transistor and the second P-channel metal oxide semiconductor transistor are used as inputs. The drains of the first P-channel metal oxide semiconductor transistor and the second P-channel metal oxide semiconductor transistor are connected to the drains of the first N-channel metal oxide semiconductor transistor and the second N-channel metal oxide semiconductor transistor, respectively. The first N-channel metal oxide semiconductor transistor is connected to a source and a back gate of the second N-channel metal oxide semiconductor transistor and a ground terminal, The differential amplifier circuit includes a voltage adjustment circuit, the voltage adjustment circuit includes a first end, a second end, and a power supply end, and is capable of adjusting a voltage between the first end and the second end, the first end is connected to a source electrode commonly connected between the first P-channel metal oxide semiconductor transistor and the second P-channel metal oxide semiconductor transistor, the second end is connected to a back gate electrode commonly connected between the first P-channel metal oxide semiconductor transistor and the second P-channel metal oxide semiconductor transistor, and the power supply end is connected to a power supply terminal. The voltage adjustment circuit is configured such that a voltage generated between a first end and a second end increases or decreases according to a change in an input voltage of the differential amplifier circuit.

2. The reference voltage circuit according to claim 1, wherein: The voltage regulating circuit comprises: a current source connected between the power supply terminal and the second terminal; and a resistor connected between the first terminal and the second terminal. The resistor includes a variable resistor having a temperature coefficient of opposite polarity to a temperature coefficient of a voltage input to a gate of the first P-channel metal oxide semiconductor transistor and capable of adjusting a resistance value.

3. The reference voltage circuit according to claim 1, wherein: The voltage regulating circuit comprises: a current source connected between the power supply terminal and the second terminal; and a resistor connected between the first end and the second end, The current source is a variable current source capable of adjusting a current value in such a manner that a voltage generated across the resistor increases or decreases in accordance with a change in an input voltage of the differential amplifier circuit.

4. The reference voltage circuit according to any one of claims 1 to 3, wherein: The voltage adjustment circuit is configured to generate a voltage that is lower than the gate voltage or threshold voltage of the first P-channel metal oxide semiconductor transistor and the second P-channel metal oxide semiconductor transistor within a specified temperature range, and is a voltage having a temperature coefficient with a polarity opposite to the polarity of the temperature coefficient of the voltage input to the gate of the first P-channel metal oxide semiconductor transistor.

5. The reference voltage circuit according to claim 4, wherein: The generated voltage is greater than or equal to 0.10 V and less than or equal to 0.35 V within the predetermined temperature range.

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