Data processing methods, apparatus, systems, computing devices, and storage media

Abstract

A data processing method is provided in which a processor obtains the instruction sequence of an application, identifies the execution order of read and write instructions in the instruction sequence, and executes the read and write instructions in the identified execution order to access the memory in the computing device, so that the processor can execute the application normally.

Description

[0001] This application is a divisional application. The original application has the application number 202210238254.1 and the original application date is March 11, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus, system, computing device, and storage medium. Background Technology

[0003] Applications include read and write instructions that perform read or write operations on memory. When the processor executes an application, it inevitably performs read and write operations on memory by executing these instructions. However, during these memory read and write operations, the processor may fail to execute the application correctly. Summary of the Invention

[0004] This application provides a data processing method, apparatus, system, computing device, and storage medium, enabling the processor to run applications normally. The technical solution is as follows:

[0005] In a first aspect, a data processing method is provided, which is executed by a processor of a computing device. The method includes: acquiring an instruction sequence of an application, identifying the execution order of read and write instructions in the instruction sequence according to the instruction sequence, and executing the read and write instructions according to the identified execution order. The instruction sequence includes multiple instructions, which include read and write instructions for performing read or write operations on the memory of the computing device. The application is deployed in the computing device.

[0006] This method involves the processor acquiring the instruction sequence of the application, identifying the execution order of read and write instructions in the instruction sequence, and executing the read and write instructions in the identified execution order to access the memory in the computing device, thereby enabling the processor to execute the application normally.

[0007] In one possible implementation, identifying the execution order of read and write instructions in the instruction sequence based on the instruction sequence includes: identifying the order in which the read and write instructions are arranged in the instruction sequence as the execution order of the read and write instructions.

[0008] Based on the above possible implementation methods, the order of read and write instructions in the instruction sequence is forcibly identified as the execution order of read and write instructions, so that the order of read and write instructions in the instruction sequence is consistent with the execution order of read and write instructions. Accordingly, when the processor executes read and write instructions according to the execution order of read and write instructions, it can avoid the situation where the memory access order is inconsistent with the order of read and write instructions in the application, thereby avoiding memory consistency problems.

[0009] In another possible implementation, the order of read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions, including: according to the sequential memory access mode, the order of read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions; wherein, the sequential memory access mode requires that the execution order of the read and write instructions is consistent with the order of read and write instructions in the instruction sequence.

[0010] Based on the above possible implementation methods, since the sequential memory access mode requires that the execution order of read and write instructions be consistent with the order in which they are arranged in the instruction sequence, the processor forcibly recognizes the order in which read and write instructions are arranged in the instruction sequence as the execution order of read and write instructions. Accordingly, when the processor executes read and write instructions in the order of their execution, it can avoid the situation where the memory access order is inconsistent with the order in which read and write instructions are arranged in the application, thereby avoiding memory consistency problems.

[0011] In another possible implementation, the read and write instructions include read instructions that perform read operations on memory or write instructions that perform write operations on memory. The read instructions have a first semantic, and the write instructions have a second semantic. The first semantic indicates that the first instruction in the instruction sequence is executed after the read instruction, and the second semantic indicates that the second instruction in the instruction sequence is executed before the write instruction is completed. The first instruction is arranged after the read instruction in the instruction sequence, and the second instruction is arranged before the write instruction in the instruction sequence.

[0012] Based on the above possible implementation methods, since read instructions have a first semantic and write instructions have a second semantic, the processor can be automatically triggered to identify the execution order of read and write instructions according to the instruction sequence. Accordingly, when the processor executes read and write instructions in the order of execution, it can avoid the situation where the order of memory access is inconsistent with the order of read and write instructions in the application.

[0013] In another possible implementation, the read instruction is compiled based on the extended memory read instruction, which has a first semantic and is an instruction added to the processor's instruction set to indicate reading memory data; the write instruction is compiled based on the extended memory write instruction, which has a second semantic and is an instruction added to the processor's instruction set to indicate writing memory data.

[0014] Based on the above possible implementations, since the extended memory read instruction has a first semantic, the read instruction compiled from the extended memory read instruction also has a first semantic, enabling the processor to execute the read instructions in the instruction sequence in order. Furthermore, since the extended memory write instruction has a second semantic, the write instruction compiled from the extended memory write instruction also has a second semantic, enabling the processor to execute the write instructions in the instruction sequence in order.

[0015] In another possible implementation, the extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; wherein, the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not include non-scaling immediate addressing mode, while the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction all support non-scaling immediate addressing mode; the first extended memory read instruction is used to instruct the determination of a memory address based on the supported addressing mode, and read the first byte of data from the determined memory address into a first destination register; the second extended memory read instruction is used to instruct the determination of a memory address based on the supported addressing mode, and read the second byte of data from the determined memory address into a first destination register; The data is read into the second destination register, and the sign bit of the read data is used to fill the remaining bits of the second destination register; the third extended memory read instruction is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and the first byte of data at the determined memory address is read into the third destination register; the fourth extended memory read instruction is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and the second byte of data at the determined memory address is read into the fourth destination register, and the sign bit of the read data is used to fill the remaining bits of the fourth destination register; the first extended memory write instruction is used to instruct the memory address to be determined based on the supported addressing mode, and the third byte of data in the first source register is written into the determined memory address; the second extended memory write instruction is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and the third byte of data in the second source register is written into the determined memory address.

[0016] Based on the above possible implementation methods, a variety of extended memory read / write instructions are provided to meet the needs of multiple application scenarios for extended memory read / write instructions.

[0017] In another possible implementation, the first byte count includes 1 byte, 2 bytes, 4 bytes, or 8 bytes; the second byte count includes 1 byte, 2 bytes, or 4 bytes; and the third byte count includes 1 byte, 2 bytes, 4 bytes, or 8 bytes. The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction include scaled immediate addressing mode, tag addressing mode, or register addressing mode. When performing address offset in scaled immediate addressing mode, the immediate value used is the scaled operand in the corresponding instruction. When performing address offset in non-scaled immediate addressing mode, the immediate value used is the operand in the corresponding instruction, and the operand's value range is -256 to 256.

[0018] Based on the above possible implementation methods, various first byte counts, second byte counts, and supported addressing modes are provided to meet the needs of different application scenarios for the number of bytes supported by extended memory read / write instructions and addressing modes.

[0019] In another possible implementation, the read instruction is compiled based on the extended memory read instruction, which is the general memory read instruction in the processor's instruction set with the addition of a first semantic; the write operation instruction is compiled based on the extended memory write instruction, which is the general memory write instruction in the instruction set with the addition of a second semantic.

[0020] Based on the above possible implementations, by adding a first semantic to the general memory read instructions in the instruction set, extended memory read instructions can be obtained, thus expanding the functionality of the general memory read instructions and making them applicable to more application scenarios. Similarly, by adding a second semantic to the general memory write instructions in the instruction set, extended memory write instructions can be obtained, further expanding the functionality of the general memory write instructions and making them applicable to more application scenarios.

[0021] In another possible implementation, the read and write instructions include read instructions that perform read operations on memory or write instructions that perform write operations on memory. The read instructions are compiled based on general memory read instructions in the processor's instruction set, and the write instructions are compiled based on general memory write instructions in the processor's instruction set.

[0022] Based on the above possible implementation methods, general memory read instructions and general memory write instructions do not have special semantics (such as first semantics or second semantics). Correspondingly, the read and write instructions compiled from these two general memory instructions also do not have special semantics. The processor still identifies the execution order of read and write instructions according to the instruction sequence. Accordingly, when the processor executes read and write instructions in the order of execution, it can also enable the processor to execute the application normally.

[0023] In a second aspect, a data processing system is provided, which includes a first computing device and a second computing device, wherein the first computing device includes a processor.

[0024] The second computing device is used to compile the application source program to obtain the application program, and then send the application program to the first computing device.

[0025] A processor is used to receive an application and obtain a sequence of instructions from the application. The sequence of instructions includes multiple instructions, including read and write instructions that perform read or write operations on the memory of a first computing device.

[0026] The processor is also used to identify the execution order of read and write instructions based on the instruction sequence, and to execute the read and write instructions in the order of execution.

[0027] In one possible implementation, the processor is also configured to: recognize the order of read and write instructions in the instruction sequence as the execution order of the read and write instructions.

[0028] In another possible implementation, the processor is also used to: recognize the order of read and write instructions in the instruction sequence as the execution order of read and write instructions according to the sequential memory access mode, wherein the sequential memory access mode requires that the execution order of read and write instructions be consistent with the order of read and write instructions in the instruction sequence.

[0029] In another possible implementation, the read and write instructions include read instructions that perform read operations on memory or write instructions that perform write operations on memory. The read instructions have a first semantic, and the write instructions have a second semantic. The first semantic indicates that the first instruction in the instruction sequence is executed after the read instruction, and the second semantic indicates that the second instruction in the instruction sequence is executed before the write instruction is completed. The first instruction is arranged after the read instruction in the instruction sequence, and the second instruction is arranged before the write instruction in the instruction sequence.

[0030] In another possible implementation, the read instruction is compiled based on the extended memory read instruction, which has a first semantic and is an instruction added to the processor's instruction set to indicate reading memory data; the write instruction is compiled based on the extended memory write instruction, which has a second semantic and is an instruction added to the processor's instruction set to indicate writing memory data.

[0031] In another possible implementation, the extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; wherein, the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not include non-scaling immediate addressing mode, while the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction all support non-scaling immediate addressing mode; the first extended memory read instruction is used to instruct the determination of a memory address based on the supported addressing mode, and read the first byte of data from the determined memory address into a first destination register; the second extended memory read instruction is used to instruct the determination of a memory address based on the supported addressing mode, and read the second byte of data from the determined memory address into a first destination register. Data is read into the second destination register, and the sign bit of the read data is used to fill the remaining bits of the second destination register; the third extended memory read instruction is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and reads the first byte of data at the determined memory address into the third destination register; the fourth extended memory read instruction is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and reads the second byte of data at the determined memory address into the fourth destination register, and fills the remaining bits of the fourth destination register with the sign bit of the read data; the first extended memory write instruction is used to instruct the memory address to be determined based on the supported addressing mode, and writes the third byte of data from the first source register into the determined memory address; the second extended memory write instruction is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and writes the third byte of data from the second source register into the determined memory address.

[0032] In another possible implementation, the first byte count includes 1 byte, 2 bytes, 4 bytes, or 8 bytes; the second byte count includes 1 byte, 2 bytes, or 4 bytes; and the third byte count includes 1 byte, 2 bytes, 4 bytes, or 8 bytes. The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction include scaled immediate addressing mode, tag addressing mode, or register addressing mode. When performing address offset in scaled immediate addressing mode, the immediate value used is the scaled operand in the corresponding instruction. When performing address offset in non-scaled immediate addressing mode, the immediate value used is the operand in the corresponding instruction, and the operand's value range is -256 to 256.

[0033] In another possible implementation, the read instruction is compiled based on the extended memory read instruction, which is the general memory read instruction in the processor's instruction set with the addition of a first semantic; the write operation instruction is compiled based on the extended memory write instruction, which is the general memory write instruction in the instruction set with the addition of a second semantic.

[0034] In another possible implementation, the read and write instructions include read instructions that perform read operations on memory or write instructions that perform write operations on memory. The read instructions are compiled based on general memory read instructions in the processor's instruction set, and the write instructions are compiled based on general memory write instructions in the processor's instruction set.

[0035] Thirdly, a data processing apparatus is provided for performing the aforementioned data processing method. Specifically, the data processing apparatus includes a functional module for performing the data processing method provided in the first aspect or any alternative embodiment of the first aspect.

[0036] Fourthly, a computing device is provided, the computing device including a processor for performing the method provided as described in the first aspect or any alternative method of the first aspect.

[0037] Fifthly, a computer-readable storage medium is provided, the storage medium storing at least one piece of program code, the program code being read by a processor in a computing device to cause the processor to perform the method provided as described in the first aspect or any alternative method of the first aspect.

[0038] In a sixth aspect, a computer program product is provided, comprising at least one piece of program code stored in a computer-readable storage medium, the at least one piece of program code being read by a processor in a computing device to cause the processor to execute the methods provided in the first aspect or various alternative implementations of the first aspect.

[0039] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a data processing system 100 provided in an embodiment of this application;

[0041] Figure 2 This is a flowchart of a data processing method provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of a data processing process of a processor provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0045] For ease of understanding, the following explanations are provided for some of the terms used in the embodiments of this application:

[0046] Application: refers to a sequence of instructions developed and executed on an operating system to accomplish at least one specific task.

[0047] Instruction sequence: This includes multiple instructions. Optionally, these multiple instructions are arranged in sequence to form the instruction sequence, with each instruction corresponding to a specific order within the sequence.

[0048] The instruction sequence includes either read or write instructions. If the sequence includes read instructions, there is at least one read instruction. If the sequence includes write instructions, there is at least one write instruction. Read instructions instruct the execution of a read operation on main memory, where a read operation is the act of retrieving data from memory. Write instructions instruct the execution of a write operation on memory, where a write operation is the act of writing data to memory. For ease of description, read and write instructions can be collectively referred to as read-write instructions.

[0049] First semantics: Indicates that the first instruction in an instruction sequence is executed after the read instruction. For a read instruction in the instruction sequence, the first instruction is the instruction that follows the read instruction. For example, if the instruction sequence includes 100 instructions, and the second instruction is a read instruction, then for that read instruction, the third through the 100th instructions are all the first instructions. Because the first semantics indicates that the first instruction in the instruction sequence is executed after the read instruction, it prevents instructions that are ordered after the read instruction from being executed before it. In some embodiments, this first semantics is also called acquiresemantic.

[0050] Second semantics: This indicates that the second instruction in an instruction sequence is executed before the write instruction completes. For a write instruction in the instruction sequence, the second instruction is the instruction that precedes it. For example, if the instruction sequence includes 100 instructions, and the third instruction is a write instruction, then for that write instruction, the first and second instructions out of the 100 instructions are both second instructions. Because the second semantics indicates that the second instruction in the instruction sequence is executed before the write instruction completes, it prevents instructions that precede the write instruction from being executed after it. In some embodiments, this second semantics is also called release semantics.

[0051] Sequential memory access mode: requires that the execution order of read and write instructions in the instruction sequence be consistent with the order in which the read and write instructions are arranged in the instruction sequence.

[0052] Memory model: Defines how the processor executes read and write instructions. This memory model includes the weakly-ordered memory model.

[0053] Weak memory model: When the processor executes an application, it can swap the execution order of read and write instructions within that application without changing the application's behavior.

[0054] This application proposes that, when executing an application, the execution order of read and write instructions in the application is identified based on the instruction sequence in the application. The read and write instructions in the application are executed according to the execution order of the read and write instructions, so that the processor can execute the application normally. Accordingly, the occurrence of adverse situations such as random crashes, restarts or erroneous running results in the application is reduced, and the reliability of processors supporting weak memory models is increased, so as to further improve the reputation and market sales of processors supporting weak memory models.

[0055] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0056] Figure 1 This is a schematic diagram of the structure of a data processing system 100 provided in an embodiment of this application. The data processing system 100 includes a first computing device 101 and a second computing device 102. The first computing device 101 and the second computing device 102 are directly or indirectly connected through wired or wireless communication. The user using the first computing device 101 is referred to as the first user, and the user using the second computing device 102 is referred to as the second user.

[0057] The second computing device 102 is equipped with compiler software that provides the function of compiling application source programs. The second computing device 102 uses the compiler software to compile the application source programs to obtain compiled application programs. Both the application source programs and the compiled application programs are used to implement customized functions. The application source programs are source code written in a high-level language to implement these customized functions. Compiling the application source programs yields a sequence of instructions that the processor can recognize. This sequence of instructions is called the application program, and it can be, for example, a sequence of instructions composed of binary data.

[0058] The first computing device 101 obtains the compiled application from the second computing device 102. The first computing device 101 deploys the obtained application, for example, by installing the application. The first user issues an execution instruction to the first computing device 101 to execute the application. In response to the execution instruction, the first computing device executes the application (i.e., runs the application).

[0059] The first computing device 101 includes a processor 11 and memory 12. When the first computing device 101 executes the application, each instruction in the application is executed by the processor 11 in the first computing device 101. Temporary data during the execution of the application is stored in memory 12. Therefore, the processor 11 performs read and write operations on memory 12 during instruction execution to read data from memory and write data to memory. In order to enable the processor 11 to interact better with memory 12, an execution mode for read and write instructions (e.g., a memory model) is defined for the processor 11. Accordingly, the read and write operations of the processor 11 on memory 12 need to follow the defined memory model; otherwise, memory access errors will occur.

[0060] Accordingly, in order to enable a certain processor to run an application normally, developers will consider the requirements of the memory model supported by the processor for the execution order of read and write instructions when developing applications for that processor. Consequently, applications developed for that processor will also support the memory model supported by that processor, and the order of read and write instructions in the application will meet the requirements of the memory model for the execution order of read and write instructions.

[0061] Processors with different architectures may support the same memory model. For example, processors with advanced RISC machines (ARM) architecture and processors with performance optimization with enhanced RISC (POWER) architecture both support weak memory models. Applications developed based on ARM architecture processors and applications developed based on POWER architecture processors also support weak memory models.

[0062] In this embodiment of the application, the instruction set supported by the processor of the first computing device includes at least one of a general instruction set, an extended instruction set 1, and an extended instruction set 2, as shown in Table 1 below. Referring again to Table 1, the instructions for accessing memory in the general instruction set include general memory read instructions and general memory write instructions, wherein the general memory read instructions include at least one of general memory read instructions 1-4, and the general memory write instructions include at least one of general memory write instructions 1-2. The instructions for accessing memory in extended instruction set 1 include extended memory read instruction 1 and extended memory write instruction 1, wherein extended memory read instruction 1 includes at least one of extended memory read instructions 11-14, and extended memory write instruction 1 includes at least one of extended memory write instructions 11-12. The instructions for accessing memory in extended instruction set 2 include extended memory read instruction 2 and extended memory write instruction 2, wherein extended memory read instruction 2 includes at least one of extended memory read instructions 21-12, and extended memory write instruction 2 includes at least one of extended memory write instructions 21-22.

[0063] Table 1

[0064]

[0065]

[0066] The following is a description of the various instruction sets supported by the processor of the first computing device, in conjunction with Table 1:

[0067] The first type of instruction set: General instruction set

[0068] The general instruction set refers to the instruction set originally supported by the processor. Taking an ARM64 architecture processor as an example, the general instruction set is the ARM64 instruction set. The general memory (i.e., memory) read instruction in the general instruction set is used to determine the memory address to be read based on the supported addressing mode, and read a specific number of bytes of data from that memory address into the destination register. The specific number of bytes is the bit width of the data to be read indicated by the general memory read instruction.

[0069] The general-purpose memory read instruction supports at least one of the following modes: immediate addressing, tag addressing, and register addressing. There are two types of immediate addressing: scaled immediate addressing and unscaled (U) immediate addressing.

[0070] In this context, the scaled immediate addressing mode is used to indicate the scaling of the operands in the corresponding instruction, using the scaled operands for addressing. The scaling factor of the operands can be set according to the scenario requirements, such as 1, 4, or 8. When the scaling factor is 1, the operands before and after scaling remain unchanged. Here, this application embodiment does not limit the scaling factor of the operands. For example, for a general memory read instruction that supports scaled immediate addressing mode, when the processor executes the general memory read instruction, it scales the operands in the general memory read instruction, using the scaled operands to offset the address stored in the base address register, thereby determining the memory address to be read.

[0071] Unscaled immediate addressing mode indicates that addressing is performed using operands in the corresponding instruction whose values ​​range from -256 to 256, without scaling the operands. For example, for a general-purpose memory read instruction that supports unscaled immediate addressing mode, the operands in this general-purpose memory read instruction range from -256 to 256. When the processor executes this general-purpose memory read instruction, it sums the operands in the general-purpose memory read instruction with the address stored in the base address register to obtain the memory address to be read. For immediate addressing mode, the operands used for address offset are collectively referred to as immediate values.

[0072] As shown in Table 2 below, the specific number of bytes includes either the first number of bytes or the second number of bytes. Depending on the supported addressing mode and the specific number of bytes, the general memory read instruction includes at least one of the general memory read instructions 1-4.

[0073] Table 2

[0074]

[0075] In Table 2, " / " represents none.

[0076] The following explains in detail how each instruction in Table 2 is processed:

[0077] General memory read instruction 1 is used to instruct the determination of the memory address based on the supported addressing mode, and to read the first byte of data at the determined memory address into the first destination register.

[0078] In one possible implementation, the number of the first byte includes 1 byte, 2 bytes, 4 bytes, or 8 bytes. As shown in Table 2, depending on the different values ​​of the first byte, the general memory read instruction 1 includes at least one of the general memory read instructions 11-13. For general memory read instruction 13, when the length of the first destination register is greater than or equal to 4 bytes and less than 8 bytes, the number of the first byte is 4 bytes. When the length of the first destination register is greater than or equal to 8 bytes, the number of the first byte is 8 bytes.

[0079] The encoding format and reference method of different general-purpose memory read instructions 1 are different. In one possible implementation, byte load (Load Register Byte, LDRB), half-word load (Load Register Halfword, LDRH), and word or double-word load (Load Register, LDR) are used to refer to general-purpose memory read instructions 11-13, respectively. Alternatively, UR11, UR12, and UR13 are used to refer to general-purpose memory read instructions 11-13, respectively, to distinguish different general-purpose memory read instructions 1.

[0080] General memory read instruction 2 is used to instruct the determination of the memory address based on the supported addressing mode, read the second byte of data at the determined memory address into the second destination register, and fill the remaining bits of the second destination register with the sign bit of the read data.

[0081] The second destination register is longer than the second byte, and the data read includes the sign bit (S) and the value bits. In one possible implementation, the general-purpose memory instruction 2 is also used to support filling the read data sequentially from the least significant bit to the most significant bit in the second destination register. Accordingly, the remaining bits in the second destination register are the remaining high-order bits of the second destination register, which are filled with the sign bit of the read data.

[0082] In one possible implementation, the second byte may be 1 byte, 2 bytes, or 4 bytes. As shown in Table 2, depending on the value of the second byte data, the general memory read instruction 2 includes at least one of general memory read instructions 21-23. The encoding formats and referencing methods of different general memory read instructions 2 are different. In one possible implementation, the general memory read instructions 21-23 are referred to as Load Register Signed Byte (LDRSB), Load Register Signed Halfword (LDRSH), and Load Register Signed Word (LDRSW), respectively. Alternatively, UR21, UR22, and UR23 are used to refer to general memory read instructions 21-23, to distinguish between different general memory read instructions 2.

[0083] General memory read instruction 3 is used to instruct the determination of the memory address based on the non-scaling immediate addressing mode, and to read the first byte of data at the determined memory address into the third destination register.

[0084] As shown in Table 2, depending on the different values ​​of the first byte number, the general memory read instruction 3 includes at least one of the general memory read instructions 31-33. For general memory read instruction 33, when the length of the third destination register is greater than or equal to 4 bytes and less than 8 bytes, the first byte number is 4 bytes. When the length of the third destination register is greater than or equal to 8 bytes, the first byte number is 8 bytes.

[0085] The encoding formats and referencing methods of different general-purpose memory read instructions 3 are all different. In one possible implementation, the general-purpose memory read instructions 31-33 are referred to as Load Register Byte Unscaled (LDURB), Load Register Halfword Unscaled (LDURH), and Load Register Unscaled (LDUR), respectively. Alternatively, UR31, UR32, and UR33 are used to refer to the general-purpose memory read instructions 31-33, respectively, to distinguish the different general-purpose memory read instructions 3.

[0086] The general memory read instruction 4 is used to instruct the determination of the memory address based on the non-scaling immediate addressing mode, read the second byte of data from the determined memory address into the fourth destination register, and fill the remaining bits of the fourth destination register with the sign bit of the read data.

[0087] The fourth destination register is longer than the second byte, and the data read includes the sign bit and the value bit. In one possible implementation, this general-purpose memory instruction 4 is also used to support filling the read data sequentially from the least significant bit to the most significant bit in the fourth destination register. Accordingly, the remaining bits in the fourth destination register are the remaining high-order bits of the fourth destination register, which are filled with the sign bit of the read data.

[0088] As shown in Table 2, depending on the different values ​​of the second byte, the general memory read instruction 4 includes general memory read instructions 41-43.

[0089] The encoding format and referencing methods of different general-purpose memory read instructions 4 are different. In one possible implementation, Load Register Signed Byte Unscaled (LDURSB), Load Register Signed Halfword Unscaled (LDURSH), and Load Register Signed Word Unscaled (LDURSW) are used to refer to general-purpose memory read instructions 41-43, respectively. Alternatively, UR41, UR42, and UR43 are used to refer to general-purpose memory read instructions 41-43, to distinguish the different general-purpose memory read instructions 4.

[0090] The general memory write instruction in this general instruction set is used to instruct the user to determine the memory address to be written based on the supported addressing modes, and to write the third byte of data from the source register to the determined memory address, where the third byte is the bit width of the data to be written as indicated by the general memory write instruction. The general memory write instruction supports at least one of immediate addressing mode, tag addressing mode, and register addressing mode.

[0091] As shown in Table 3 below, based on the different supported addressing modes, the general memory write instructions include at least one of general memory write instructions 1-2.

[0092] Table 3

[0093]

[0094]

[0095] The processing procedure for each instruction in Table 3 is described in detail below:

[0096] General memory write instruction 1 is used to instruct the third byte of data in the first source register to be written to the determined memory address based on the supported addressing mode.

[0097] In one possible implementation, the third byte can be 1 byte, 2 bytes, 4 bytes, or 8 bytes. As shown in Table 3, the general memory write instruction 1 includes general memory write instructions 11-13 depending on the value of the third byte. For general memory write instruction 13, when the length of the first source register is greater than or equal to 4 bytes and less than 8 bytes, the third byte is 4 bytes. When the length of the first source register is greater than or equal to 8 bytes, the third byte is 8 bytes.

[0098] The encoding format and reference method of different general-purpose memory write instructions 1 are different. In one possible implementation, byte storage (Store Register Byte, STRB), half-word storage (Store Register Halfword, STRH), and word or double-word storage (Store Register, STR) are used to refer to general-purpose memory write instructions 11-13, respectively. Alternatively, UW11, UW12, and UW13 are used to refer to general-purpose memory write instructions 11-13, in order to distinguish different general-purpose memory write instructions 11-13.

[0099] General memory write instruction 2 is used to instruct the memory address to be determined based on the non-scaling immediate addressing mode, and to write the third byte of data in the second source register to the determined memory address.

[0100] As shown in Table 3, the general memory write instruction 2 includes general memory write instructions 21-23, depending on the different values ​​of the third byte. For general memory write instruction 23, when the length of the second source register is greater than or equal to 4 bytes and less than 8 bytes, the third byte is 4 bytes. When the length of the second source register is greater than or equal to 8 bytes, the third byte is 8 bytes.

[0101] The encoding formats and referencing methods of different general-purpose memory write instructions 2 are all different. In one possible implementation, Store Register Byte Unscaled (STURB), Store Register Halfword Unscaled (STURH), and Store Register Unscaled Word or Double Word (STUR) are used to refer to general-purpose memory write instructions 21-23, respectively. Alternatively, UW21, UW22, and UW23 are used to refer to general-purpose memory write instructions 21-23, to distinguish between different general-purpose memory write instructions 21-23.

[0102] In one possible implementation, the general instruction set also includes at least one other function instruction, which is used to implement functions other than accessing memory. Here, the embodiments of this application do not limit the at least one other function instruction.

[0103] The second instruction set: Extended Instruction Set 1

[0104] Extended Instruction Set 1 is an instruction set extended for the processor of the first computing device. The Extended Memory Read Instruction 1 and Extended Memory Write Instruction 1 in Extended Instruction Set 1 are instructions added to the processor's general instruction set to perform read and write operations on memory. For example, replacing the general memory read instruction in the general instruction set with the Extended Memory Read Instruction 1, and replacing the general memory write instruction in the general instruction set with the Extended Memory Write Instruction 1, yields Extended Instruction Set 1.

[0105] The extended memory read instruction 1 and extended memory write instruction 1 are described below. Here, we will first introduce the extended memory read instruction 1:

[0106] Extended memory read instruction 1 is used to instruct the determination of the memory address to be read based on the supported addressing mode, and to read a specific number of bytes of data from that memory address into the destination register. Extended memory read instruction 1 also has a first semantic.

[0107] The extended memory read instruction 1 supports at least one of immediate addressing mode, tag addressing mode, and register addressing mode. For example, as shown in Table 4 below, based on the supported addressing modes and the specific number of bytes, the extended memory read instruction 1 includes at least one of the extended memory read instructions 11-14.

[0108] Table 4

[0109]

[0110]

[0111] In Table 4, " / " represents none.

[0112] The processing procedure for each instruction in Table 4 is described in detail below:

[0113] Extended memory read instruction 11 is used to instruct the determination of the memory address based on the supported addressing mode, and to read the first byte of data in the determined memory address into the first destination register. Extended memory read instruction 11 also has a first semantic.

[0114] Among them, the extended memory read instruction 11 is a memory read instruction that extends the functionality of the general memory read instruction 1. The extended memory read instruction 11 has the functionality of the general memory read instruction 1 and also has the first semantics. The instruction format of the extended memory read instruction 11 and the general memory read instruction 1 can be the same or different, but the encoding format of the extended memory read instruction 1 is different.

[0115] As shown in Table 4, depending on the different values ​​of the first byte number, the extended memory read instruction 11 includes at least one of the extended memory read instructions 111-113. The extended memory read instructions 111-113 are memory read instructions newly added based on the general memory read instructions 11-13. Compared with the general memory read instructions 111-113, the extended memory read instructions 111-113 each have the functions of the general memory read instructions 11-13, and all of the extended memory read instructions 111-113 have the first semantic, while none of the general memory read instructions 11-13 have the first semantic.

[0116] The encoding format and reference method of different extended memory read instructions 11 are different. In one possible implementation, LDRBE1, LDRHE1, and LDRE1 are used to refer to extended memory read instructions 111-113 respectively, where "E1" refers to the first extended form of the general extended memory read instruction. Alternatively, ER111, ER112, and ER113 are used to refer to extended memory read instructions 111-113 respectively, to distinguish the different extended memory read instructions 11.

[0117] Extended memory read instruction 12 is used to instruct the determination of the memory address based on the supported addressing mode, read the second byte of data at the determined memory address into the second destination register, fill the remaining bits of the second destination register with the sign bit of the read data, and extended memory read instruction 12 also has a first semantic.

[0118] Among them, the extended memory read instruction 12 is a memory read instruction that extends the functionality of the general memory read instruction 2. The extended memory read instruction 12 has the functionality of the general memory read instruction 2, and also has the first semantics. The instruction format of the extended memory read instruction 12 and the general memory read instruction 2 can be the same or different, but the encoding format of the extended memory read instruction 12 is different.

[0119] As shown in Table 4, depending on the different values ​​of the second byte number, the extended memory read instruction 12 includes at least one of extended memory read instructions 121-123. Specifically, extended memory read instructions 121-123 are memory read instructions newly added based on general memory read instructions 21-23. Compared to general memory read instructions 21-23, extended memory read instructions 121-123 each have the functions of general memory read instructions 21-23, and all extended memory read instructions 121-123 have the first semantic, while none of the general memory read instructions 21-23 have the first semantic.

[0120] The encoding format and referencing method of different extended memory read instructions 11 are different. In one possible implementation, LDRSBE1, LDRSHE1, and LDRSWE1 are used to refer to extended memory read instructions 121-123 respectively. Alternatively, ER121, ER122, and ER123 are used to refer to extended memory read instructions 121-123 respectively, to distinguish different extended memory read instructions 12.

[0121] Extended memory read instruction 13 is used to instruct the determination of the memory address based on non-scaling immediate addressing mode, and to read the first byte of data in the determined memory address into the third destination register. Extended memory read instruction 13 also has a first semantic.

[0122] Among them, the extended memory read instruction 13 is a memory read instruction extended from the general memory read instruction 3. The extended memory read instruction 13 has the function of the general memory read instruction 3, and also has the first semantics. The instruction format of the extended memory read instruction 13 and the general memory read instruction 3 can be the same or different, but the encoding format of the extended memory read instruction 13 is different from that of the general memory read instruction 3.

[0123] As shown in Table 4, depending on the different values ​​of the first byte number, the extended memory read instruction 13 includes at least one of the extended memory read instructions 131-133. Specifically, the extended memory read instructions 131-133 are memory read instructions newly added based on the general memory read instructions 31-33. Compared to the general memory read instructions 31-33, the extended memory read instructions 131-133 each have the functions of the general memory read instructions 31-33. All of the extended memory read instructions 131-133 have the first semantic, while none of the general memory read instructions 31-33 have the first semantic.

[0124] The encoding format and referencing method of different extended memory read instructions 13 are different. In one possible implementation, LDURBE1, LDURHE1, and LDURE1 are used to refer to extended memory read instructions 131-133 respectively. Alternatively, ER131, ER132, and ER133 are used to refer to extended memory read instructions 131-133 respectively, in order to distinguish the different extended memory read instructions 13.

[0125] Extended memory read instruction 14 is used to instruct the determination of the memory address based on non-scaling immediate addressing mode, read the second byte of data in the determined memory address into the fourth destination register, fill the remaining bits of the fourth destination register with the sign bit of the read data, and extended memory read instruction 14 also has the first semantics.

[0126] Among them, the extended memory read instruction 14 is a memory read instruction that extends the functionality of the general memory read instruction 4. The extended memory read instruction 14 has the functionality of the general memory read instruction 4, and also has the first semantics. The instruction format of the extended memory read instruction 14 and the general memory read instruction 4 can be the same or different, but the encoding format of the extended memory read instruction 14 is different.

[0127] As shown in Table 4 above, depending on the different values ​​of the second byte number, the extended memory read instruction 14 includes at least one of the extended memory read instructions 141-143. Specifically, the extended memory read instructions 141-143 are memory read instructions newly added based on the general memory read instructions 31-33. Compared with the general memory read instructions 31-33, the extended memory read instructions 141-143 each have the functions of the general memory read instructions 31-33, and all of the extended memory read instructions 141-143 have the first semantic, while none of the extended memory read instructions 31-33 have the first semantic.

[0128] The encoding format and referencing method of different extended memory read instructions 14 are different. In one possible implementation, LDURSBE1, LDURSHE1, and LDURSWE1 are used to refer to extended memory read instructions 141-143 respectively. Alternatively, ER141, ER142, and ER143 are used to refer to extended memory read instructions 141-143 respectively, in order to distinguish the different extended memory read instructions 14.

[0129] It should be noted that for each extended memory read instruction 1 and its corresponding general memory read instruction, each extended memory read instruction 1 is a newly added memory read instruction compared to the corresponding general memory read instruction, and it also has a first semantic. Accordingly, the encoding formats corresponding to each extended memory read instruction 1 and the corresponding general memory read instruction are different. For example, the encoding format corresponding to an extended memory read instruction 1 may have a semantic bit, and the value of the semantic bit is used to identify the first semantic, while the encoding format corresponding to the general memory read instruction may or may not have a semantic bit. If the encoding format corresponding to the general memory read instruction has a semantic bit, but the value of the semantic bit is different from the value of the semantic bit in the encoding format corresponding to the extended memory read instruction 1, and it is not used to identify the first semantic.

[0130] The extended memory write instruction 1 in extended instruction set 1 is described below:

[0131] Extended memory write instruction 1 is used to instruct the memory address to be written to be determined based on the supported addressing mode, and write the data of the third byte in the source register to the determined memory address. Extended memory write instruction 1 also has a second semantic.

[0132] Specifically, the extended memory write instruction 1 supports at least one of the following: immediate addressing mode, tag addressing mode, and register addressing mode. For example, as shown in Table 5 below, based on the different supported addressing modes, the extended memory write instruction 1 includes at least one of the extended memory write instructions 11-12.

[0133] Table 5

[0134]

[0135] The processing procedure for each instruction in Table 5 is described in detail below:

[0136] Extended memory write instruction 11 is used to instruct the storage address in memory to be determined based on the supported addressing mode, and to write the data of the third byte in the first source register to the determined storage address, and extended memory write instruction 11 has a second semantic.

[0137] Among them, the extended memory write instruction 11 is a memory write instruction that extends the functionality of the general memory write instruction 1. The extended memory read instruction 11 has the functionality of the general memory write instruction 1 and also has a second semantic. The instruction format of the extended memory write instruction 11 and the general memory write instruction 1 can be the same or different, but the encoding format of the extended memory write instruction 1 is different.

[0138] As shown in Table 5, depending on the different values ​​of the third byte, the extended memory write instruction 11 includes at least one of the extended memory write instructions 111-113. The extended memory write instructions 111-113 are memory write instructions newly added based on the general memory write instructions 11-13. Compared with the general memory write instructions 111-113, the extended memory write instructions 111-113 each have the functions of the general memory write instructions 11-13, and the extended memory write instructions 111-113 also all have a second semantic, while the general memory write instructions 11-13 do not have a second semantic.

[0139] The encoding format and referencing method of different extended memory write instructions 11 are different. In one possible implementation, STRBE1, STRHE1, and STRE1 are used to refer to extended memory write instructions 111-113 respectively. Alternatively, EW111, EW112, and EW113 are used to refer to extended memory write instructions 111-113 respectively, in order to distinguish the different extended memory write instructions 11.

[0140] Extended memory write instruction 12 is used to instruct the storage address in memory to be determined based on the non-scaling immediate addressing mode, and to write the data of the third byte in the second source register to the determined storage address. Extended memory write instruction 12 has a second semantic.

[0141] Among them, the extended memory write instruction 12 is a memory write instruction that extends the functionality of the general memory write instruction 2. The extended memory read instruction 12 has the functionality of the general memory write instruction 2, and also has a second semantic. The instruction format of the extended memory write instruction 12 and the general memory write instruction 2 can be the same or different, but the encoding format of the extended memory write instruction 12 is different from that of the general memory write instruction 2.

[0142] As shown in Table 5, depending on the different values ​​of the third byte number, the extended memory write instruction 12 includes at least one of the extended memory write instructions 121-123. The extended memory write instructions 121-123 are memory write instructions added based on the general memory write instructions 21-23. Compared with the general memory write instructions 21-23, the extended memory write instructions 121-123 each have the functions of the general memory write instructions 21-23, and all of them also have a second semantic, while the general memory write instructions 21-23 do not have a second semantic.

[0143] The encoding format and referencing method of different extended memory write instructions 12 are different. In one possible implementation, STURBE1, STURHE1, and STURE1 are used to refer to extended memory write instructions 121-123 respectively. Alternatively, EW121, EW122, and EW123 are used to refer to extended memory write instructions 121-123 respectively, in order to distinguish the different extended memory write instructions 12.

[0144] It should be noted that for each extended memory write instruction 1 and its corresponding general memory write instruction, each extended memory write instruction 1 is a newly added memory write instruction compared to the corresponding general memory write instruction, and it also has a second semantic. Accordingly, the encoding formats corresponding to each extended memory write instruction 1 and the corresponding general memory write instruction are different. For example, the encoding format corresponding to an extended memory write instruction 1 may have a semantic bit, and the value of the semantic bit is used to identify the second semantic, while the encoding format corresponding to the general memory write instruction may or may not have a semantic bit. If the encoding format corresponding to the general memory write instruction has a semantic bit, but the value of the semantic bit is different from the value of the semantic bit in the encoding format corresponding to the extended memory write instruction 1, and it is not used to identify the second semantic.

[0145] In one possible implementation, the extended instruction set 1 further includes at least one other function instruction, which is used to implement functions other than accessing memory. Here, the embodiments of this application do not limit the at least one other function instruction.

[0146] The third instruction set: Extended Instruction Set 2

[0147] Extended Instruction Set 2 (EIS2) is another instruction set extended for this processor. Compared to EIS1, EIS2 is an instruction set obtained by adding special semantics (first semantics or second semantics) to the general memory read / write instructions (i.e., general memory read instructions or general memory write instructions) in the general instruction set. EIS1, on the other hand, is a new instruction set developed based on the functionality of the general memory read / write instructions in the general instruction set. To distinguish between EIS1 and EIS2, the encoding formats of the instructions in EIS1 and EIS2 are different.

[0148] As shown in Table 1, the extended memory read instruction 2 in extended instruction set 2 has a first semantic. Extended memory read instruction 2 is obtained by adding the first semantic to the general memory read instruction in the processor's general instruction set. Extended memory write instruction 2 in extended instruction set 2 is obtained by adding the second semantic to the general memory write instruction in the general instruction set. For example, adding the first semantic to the general memory read instruction in the general instruction set yields the extended memory read instruction 2; adding the second semantic to the general memory write instruction in the general instruction set yields the extended memory write instruction 2; replacing the general memory read instruction in the general instruction set with the extended memory read instruction 2, and replacing the general memory write instruction in the general instruction set with the extended memory write instruction 2, yields extended instruction set 2.

[0149] The extended memory read instruction 2 and extended memory write instruction 2 are described below. Here, we will first introduce the extended memory read instruction 2:

[0150] Extended memory read instruction 2 is used to instruct the determination of the memory address to be read based on the supported addressing mode, and to read a specific number of bytes of data from that memory address into the destination register. Extended memory read instruction 2 also has a first semantic.

[0151] Specifically, Extended Memory Read Instruction 2 supports at least one of immediate addressing mode, tag addressing mode, and register addressing mode. For example, as shown in Table 6 below, based on the supported addressing modes and the specific number of bytes, Extended Memory Read Instruction 2 includes at least one of Extended Memory Read Instructions 22-24.

[0152] Table 6

[0153]

[0154]

[0155] In Table 6, " / " represents none.

[0156] The processing procedure for each instruction in Table 6 is described in detail below.

[0157] Extended memory read instruction 21 is used to instruct the determination of the memory address based on the supported addressing mode, and to read the first byte of data at the determined memory address into the first destination register. Extended memory read instruction 21 also has a first semantic.

[0158] The extended memory read instruction 21 is an instruction obtained by adding a first semantic to the general memory read instruction 1. The extended memory read instruction 21 has the same instruction format as the general memory read instruction 1, but the encoding format is different from that of the general memory read instruction 1.

[0159] As shown in Table 6, depending on the different values ​​of the first byte number, the extended memory read instruction 21 includes at least one of extended memory read instructions 211-213. Specifically, extended memory read instructions 211-213 are memory read instructions obtained by adding a first semantic to general memory read instructions 11-13. Compared to general memory read instructions 11-13, extended memory read instructions 211-213 each have the functions of general memory read instructions 11-13, and all extended memory read instructions 211-213 have the first semantic, while all general memory read instructions 11-13 do not have the first semantic.

[0160] The encoding format and reference method of different extended memory read instructions 21 are different. In one possible implementation, LDRBE2, LDRHE2, and LDRE2 are used to refer to extended memory read instructions 211-213 respectively. Here, "E2" refers to an extended form of the general extended memory read instruction. Alternatively, ER211, ER212, and ER213 are used to refer to extended memory read instructions 211-213 respectively, to distinguish different extended memory read instructions 21.

[0161] Extended memory read instruction 22 is used to instruct the determination of the memory address based on the supported addressing mode, read the second byte of data in the determined memory address into the second destination register, fill the remaining bits of the second destination register with the sign bit of the read data, and extended memory read instruction 22 also has the first semantics.

[0162] Specifically, the extended memory read instruction 22 is an instruction obtained by adding a first semantic to the general memory read instruction 2. The extended memory read instruction 22 has the same instruction format as the general memory read instruction 2, but the encoding format is different from that of the general memory read instruction 2.

[0163] As shown in Table 6, depending on the different values ​​of the second byte number, the extended memory read instruction 22 includes at least one of extended memory read instructions 221-223. Specifically, extended memory read instructions 221-223 are instructions obtained by adding a first semantic to general memory read instructions 21-23. Compared to general memory read instructions 21-23, extended memory read instructions 221-223 each have the functions of general memory read instructions 21-23, and all extended memory read instructions 221-223 have the first semantic, while none of the general memory read instructions 21-23 have the first semantic.

[0164] The encoding format and referencing method of different extended memory read instructions 22 are different. In one possible implementation, LDRSBE2, LDRSHE2, and LDRSWE2 are used to refer to extended memory read instructions 221-223 respectively. Alternatively, ER221, ER222, and ER223 are used to refer to extended memory read instructions 221-223 respectively, in order to distinguish different extended memory read instructions 22.

[0165] Extended memory read instruction 23 is used to instruct the determination of the memory address based on non-scaling immediate addressing mode, and to read the first byte of data in the determined memory address into the third destination register. Extended memory read instruction 23 also has the first semantics.

[0166] Among them, the extended memory read instruction 23 is an instruction obtained by adding a first semantic to the general memory read instruction 3. The extended memory read instruction 23 has the same instruction format as the general memory read instruction 3, but the encoding format is different from that of the general memory read instruction 3.

[0167] As shown in Table 6, depending on the different values ​​of the first byte number, the extended memory read instruction 23 includes at least one of extended memory read instructions 231-233. Specifically, extended memory read instructions 231-233 are instructions obtained by adding a first semantic to general memory read instructions 31-33. Compared to general memory read instructions 31-33, extended memory read instructions 231-233 each have the functions of general memory read instructions 31-33, and all extended memory read instructions 231-233 have the first semantic, while none of the general memory read instructions 31-33 have the first semantic.

[0168] The encoding format and referencing method of different extended memory read instructions 23 are different. In one possible implementation, LDURBE2, LDURHE2, and LDURE2 are used to refer to extended memory read instructions 231-233 respectively. Alternatively, ER231, ER132, and ER233 are used to refer to extended memory read instructions 231-233 respectively, in order to distinguish the different extended memory read instructions 23.

[0169] Extended memory read instruction 24 is used to instruct the determination of the memory address based on non-scaling immediate addressing mode, read the second byte of data in the determined memory address into the fourth destination register, fill the remaining bits of the fourth destination register with the sign bit of the read data, and extended memory read instruction 24 also has the first semantics.

[0170] The extended memory read instruction 24 is an instruction obtained by adding a first semantic to the general memory read instruction 4. The extended memory read instruction 24 has the same instruction format as the general memory read instruction 4, but its encoding format is different.

[0171] As shown in Table 6, depending on the different values ​​of the second byte number, the extended memory read instruction 24 includes at least one of extended memory read instructions 241-243. Specifically, extended memory read instructions 241-243 are instructions obtained by adding a first semantic to general memory read instructions 41-43. Compared to general memory read instructions 41-43, extended memory read instructions 241-243 each have the functions of general memory read instructions 41-43, and all extended memory read instructions 241-243 have the first semantic, while none of the general memory read instructions 41-43 have the first semantic.

[0172] The encoding format and referencing method of different extended memory read instructions 24 are different. In one possible implementation, LDURSBE2, LDURSHE2, and LDURSWE2 are used to refer to extended memory read instructions 241-243 respectively. Alternatively, ER241, ER242, and ER243 are used to refer to extended memory read instructions 241-243 respectively, in order to distinguish the different extended memory read instructions 24.

[0173] The extended memory write instruction 2 in extended instruction set 2 is described below:

[0174] Extended memory write instruction 2 determines the memory address to be written based on the supported addressing modes, writes the third byte of data in the source register to the determined memory address, and also has a second semantic.

[0175] Specifically, the extended memory write instruction 2 supports at least one of immediate addressing mode, tag addressing mode, and register addressing mode. For example, as shown in Table 7 below, based on the different supported addressing modes, the extended memory write instruction 2 includes at least one of extended memory write instructions 21-22.

[0176] Table 7

[0177]

[0178] The processing procedure for each instruction in Table 7 is described in detail below.

[0179] Extended memory write instruction 21 is used to instruct the memory address to be determined based on the supported addressing mode, and to write the number of bytes of data in the first source register to the determined memory address. Extended memory write instruction 21 also has a second semantic.

[0180] Among them, the extended memory write instruction 21 is an instruction obtained by adding a second semantic to the general memory write instruction 1. The extended memory write instruction 21 has the same instruction format as the general memory write instruction 1, but the encoding format is different from that of the general memory write instruction 1.

[0181] As shown in Table 7, depending on the different values ​​of the third byte number, the extended memory write instruction 21 includes at least one of extended memory write instructions 211-213. Specifically, extended memory write instructions 211-213 are instructions obtained by adding a second semantic to general memory write instructions 11-13. Compared to general memory write instructions 11-13, extended memory write instructions 211-213 each have the functionality of general memory write instructions 11-13, and all extended memory write instructions 211-213 have a second semantic, while all general memory write instructions 11-13 do not have a second semantic.

[0182] The encoding format and referencing method of different extended memory write instructions 21 are different. In one possible implementation, STRBE2, STRHE2, and STRE2 are used to refer to extended memory write instructions 211-213 respectively. Alternatively, EW211, EW212, and EW213 are used to refer to extended memory write instructions 211-213 respectively, in order to distinguish the different extended memory write instructions 21.

[0183] Extended memory write instruction 22 is used to instruct the storage address in memory to be determined based on the non-scaling immediate addressing mode, and to write the data of the third byte in the second source register to the determined storage address. Extended memory write instruction 22 has a second semantic.

[0184] Among them, the extended memory write instruction 22 is an instruction obtained by adding a second semantic to the general memory write instruction 2. The extended memory write instruction 22 has the same instruction format as the general memory write instruction 2, but the encoding format is different from that of the general memory write instruction 2.

[0185] As shown in Table 7, depending on the different values ​​of the third byte number, the extended memory write instruction 22 includes at least one of the extended memory write instructions 221-223. Specifically, the extended memory write instructions 221-223 are instructions obtained by adding a second semantic to the general memory write instructions 21-23. Compared to the general memory write instructions 21-23, the extended memory write instructions 221-223 each have the functions of the general memory write instructions 21-23, and all of the extended memory write instructions 221-223 have the second semantic, while none of the general memory write instructions 21-23 have the second semantic.

[0186] The encoding format and referencing method of different extended memory write instructions 22 are different. In one possible implementation, STURBE2, STURHE2, and STURE2 are used to refer to extended memory write instructions 221-223 respectively. Alternatively, EW221, EW222, and EW223 are used to refer to extended memory write instructions 2221-223 respectively, in order to distinguish the different extended memory write instructions 22.

[0187] In one possible implementation, the extended instruction set 2 further includes at least one other function instruction, which is used to implement functions other than accessing memory. Here, the embodiments of this application do not limit the at least one other function instruction.

[0188] It should be noted that processors with different architectures support different general instruction sets, extended instruction set 1, and extended instruction set 2. Accordingly, the encoding format and reference method of memory read and write instructions (i.e., general memory read instructions, general memory write instructions, extended memory read instructions, or extended memory write instructions) in different instruction sets are different. Here, this application embodiment does not limit the encoding format and reference method of each memory read and write instruction in various instruction sets supported by the processor of the first computing device.

[0189] The aforementioned general instruction set, extended instruction set 1, and extended instruction set 2 are all instruction sets supported by the processor of the first computing device. The second computing device can use the general instruction set, extended instruction set 1, or extended instruction set 2 to compile the application source program into an application program, enabling the processor of the first computing device to recognize and execute the application program. To further illustrate the process of the second computing device using the instruction set supported by the processor of the first computing device to compile the application source program, and the process of the first computing device executing the application program, see [link to documentation]. Figure 2The flowchart shown is a data processing method provided in an embodiment of this application.

[0190] 201. The second computing device displays a compilation interface, which provides compilation functionality for the target type of processor.

[0191] The target type of processor includes the processor in the first computing device. The compilation function includes compiling an application that the processor can recognize and execute. The target type of processor supports memory access order during application execution that is inconsistent with the order of read and write instructions in the application; alternatively, it can be understood that the target type of processor supports a weak memory model, such as an ARM64 architecture processor or a Power architecture processor.

[0192] The compilation interface is provided by compilation software deployed in the second computing device, which displays the interface by running the compilation software. For example, the second computing device runs the compilation software and displays its main interface, which includes a processor selection box that provides at least one processor option, each corresponding to a processor type. The second user selects the processor option corresponding to the target processor type in the processor selection box, and the second computing device displays the compilation interface in response to this selection.

[0193] 202. The second computing device, in response to a compilation operation on the application source program in the compilation interface, compiles the application source program to obtain an application program, the application program including a sequence of instructions, the sequence of instructions including read and write instructions for performing read or write operations on memory.

[0194] Here, the memory refers to the memory of the computing device executing the application. For example, if the application is executed by a first computing device other than the second computing device, then the memory is the memory of the first computing device. The application source code is any source code that implements customized functions, the application program is the compiled result of the application source code, and the processor of the target type can recognize and run it.

[0195] In one possible implementation, the application source code is an application source code developed for a processor that supports a non-weak memory model, wherein the non-weak memory model includes a model that supports total store ordering (TSO), and all cores in a processor that supports the TSO model have one and only one global order in which they perform read and write operations on memory.

[0196] The compilation interface includes compilation options that provide the functionality to compile application source code. A second user selects these compilation options to compile the application source code. In response to the compilation operation in the compilation interface, the second computing device uses the instruction set provided for the processor to compile the application source code, resulting in the application program.

[0197] The compiler software in the second computing device provides the processor with an instruction set including at least one of a general instruction set, a first extended instruction set, and a second extended instruction set, wherein the first extended instruction set is the aforementioned extended instruction set 1, and the second extended instruction set is the aforementioned extended instruction set 2.

[0198] When the instruction set provided for the processor includes one of the general instruction set, the first extended instruction set, and the second extended instruction set, the second computing device, in response to the compilation operation of the application source program, uses one of the instruction sets provided for the processor to compile the application source program to obtain the application program.

[0199] For example, when the compiler provides a general instruction set to the processor, the second computing device, in response to the compilation operation of the application source program, uses this general instruction set to compile the application source program to obtain the application program. In this case, the read instructions in the application program are compiled from the general memory read instructions in the general instruction set, and the write instructions in the application program are compiled from the general memory write instructions in the general instruction set.

[0200] For example, when the compiler software provides an extended instruction set (a first extended instruction set or a second extended instruction set) for the processor, the second computing device, in response to the compilation operation of the application source program, uses the extended instruction set to compile the application source program to obtain the application program. In this case, the read instructions in the application program are compiled from the extended memory read instructions in the extended instruction set, and the write instructions in the application program are compiled from the extended memory write instructions in the extended instruction set.

[0201] When the instruction set provided to the processor includes multiple instruction sets from the general instruction set, the first extended instruction set, and the second extended instruction set, the second user selects the instruction set. In response to the compilation operation of the application source program, the second computing device uses the instruction set selected by the second user to compile the application source program, thus obtaining the application program. For example, the following three cases:

[0202] In the first scenario, when the instruction set provided for the processor includes a general instruction set and an extended instruction set, the compilation interface also includes an instruction set option for providing the extended instruction set.

[0203] If the second user selects both the instruction option and the compilation option, the second computing device, in response to these selections, uses the extended instruction set to compile the application source program, thus obtaining the application program. Specifically, if the extended instruction set is a first extended instruction set, the read instructions in the application program are compiled from the extended memory read instructions in the first extended instruction set, and the write instructions in the application program are compiled from the extended memory write instructions in the first extended instruction set. If the extended instruction set is a second extended instruction set, the read instructions in the application program are compiled from the extended memory read instructions in the second extended instruction set, and the write instructions in the application program are compiled from the second extended memory write instructions in the second extended instruction set.

[0204] Alternatively, the instruction set options in the compilation interface may include a first instruction set option and a second instruction set option, wherein the first instruction set option provides a first extended instruction set, and the second instruction set option provides a second extended instruction set. If the second user selects both the first instruction set option and the compilation option, the second computing device, in response to both selections, uses the first extended instruction set to compile the application source program, resulting in the application program. If the second user selects both the second instruction set option and the compilation option, the second computing device, in response to both selections, uses the second extended instruction set to compile the application source program, resulting in the application program.

[0205] In the second scenario, when the instruction set provided for the processor includes a first extended instruction set and a second extended instruction set, the compilation interface also includes the first instruction set option but does not include the second instruction set option.

[0206] If the second user selects the first instruction set option and the compilation option, the second computing device, in response to the selection of the first instruction set option and the compilation option, uses the first extended instruction set to compile the application source program to obtain the application program.

[0207] If the second user does not select the first instruction set option but selects the compilation option, the second computing device, in response to the selection of the compilation option, uses the second extended instruction set to compile the application source program to obtain the application program.

[0208] In the third scenario, when the instruction set provided for the processor includes a first extended instruction set and a second extended instruction set, the instruction set options in the compilation interface include a first instruction set option and a second instruction set option.

[0209] If the second user selects the first instruction set option and the compilation option, the second computing device, in response to the selection of the first instruction set option and the compilation option, uses the first extended instruction set to compile the application source program to obtain the application program.

[0210] If the second user selects both the second instruction set option and the compilation option, the second computing device, in response to the selection of both the second instruction set option and the compilation option, uses the second extended instruction set to compile the application source program to obtain the application program.

[0211] 203. The second computing device sends the application to the first computing device.

[0212] It should be noted that the second computing device only needs to send the application to the first computing device once; there is no need to send it multiple times.

[0213] 204. The first computing device receives the application.

[0214] After receiving the application, the first computing device stores the application, for example, by storing it on a computer-readable storage medium of the first computing device. If the first user issues a deployment command to the first computing device for the application, the first computing device responds to the deployment command by deploying the application, which can also be understood as installing the application.

[0215] 205. The processor of the first computing device acquires the instruction sequence of the application.

[0216] The instruction sequence can be either a sequence of instructions within the application or the application itself.

[0217] In one possible implementation, if a first user issues an execution command to a first computing device for the instruction sequence within the application, the first computing device, in response to the execution command, acquires the instruction sequence within the application.

[0218] Wherein, if the instruction sequence is a segment of the application, and the instruction sequence is used to implement at least one function of the application, the operation of the first user to open the at least one function on the first computing device is also an execution command issued to the first computing device. If the instruction sequence is the entire application, the operation of the first user to open the application on the first computing device is also an execution command issued to the first computing device.

[0219] The instruction sequence consists of multiple instructions arranged in sequence. For example, the instruction sequence consists of 100 instructions, which are ordered from 1 to 100.

[0220] Correspondingly, the first computing device also acquires the instruction sequence sequentially. Taking an instruction sequence consisting of 100 instructions as an example, the first computing device first acquires the first instruction among the 100 instructions, then acquires the second instruction among the 100 instructions, and so on, until it acquires the last instruction among the 100 instructions.

[0221] Alternatively, it can be understood as the processor sequentially reading each instruction in the instruction sequence to obtain the read instruction sequence. Taking an instruction sequence containing 100 instructions as an example, the first computing device first reads the first instruction of these 100 instructions, then reads the second instruction of these 100 instructions, and so on, until the last instruction of these 100 instructions is read. The read 100 instructions form the instruction sequence.

[0222] 206. The processor identifies the execution order of read and write instructions based on the instruction sequence.

[0223] After the processor acquires the instruction sequence, it sequentially identifies multiple instructions within the sequence. For ease of description, taking the identification of one instruction as an example, step 206 is described as follows:

[0224] Each memory read / write instruction in each instruction set of this processor corresponds to a specific encoding format. A read / write instruction within an application is encoded using the encoding format corresponding to a memory read / write instruction in that instruction set.

[0225] When identifying whether a certain instruction among multiple instructions is a read / write instruction, the processor determines whether the order of the characters in the instruction matches the encoding format corresponding to the read / write instruction. If it matches, the instruction is identified as a read / write instruction; otherwise, it is not identified as a read / write instruction.

[0226] When the instruction is identified as a read instruction in a read / write instruction, the processor parses the instruction according to the encoding format corresponding to the read instruction to extract the operands. Based on the extracted operands, the processor determines the address of the destination register and the source memory address. At this time, the destination register is the register used to store the data to be read, and the source memory address is the address in memory where the data to be read is stored.

[0227] When the instruction is identified as a write instruction in a read / write instruction, the processor parses the instruction according to the encoding format corresponding to the write instruction to extract the operands. Based on the extracted operands, the processor determines the address of the source register and the destination memory address. At this time, the source register is the register used to store the data to be written, and the destination memory address is the memory address where the data to be written is stored.

[0228] After recognizing any read or write instruction, the processor determines its execution order based on the order in which the read or write instructions are arranged in the instruction sequence. In one possible implementation, the processor operates in sequential memory access mode, also known as "ordered" mode, which is a processor memory access mode. Sequential memory access mode requires that the execution order of read and write instructions match their order in the instruction sequence. Therefore, after recognizing a read or write instruction, the processor determines its execution order based on the order in which the read or write instructions are arranged in the instruction sequence, according to the sequential memory access mode.

[0229] The processor starts from the first instruction in the instruction sequence and identifies and parses each instruction in the instruction sequence in turn. Therefore, the identification order and decoding order of each instruction in the instruction sequence are the order in which the corresponding instructions are arranged in the instruction sequence. So when the processor identifies the execution order of each read and write instruction according to the instruction sequence, it identifies the identification order or decoding order of each read and write instruction as the execution order of the corresponding read and write instruction.

[0230] In one possible implementation, after the processor recognizes any read or write instruction, it also allocates a register for that read or write instruction so that when the read or write instruction is executed subsequently, it can perform read and write operations on memory based on the allocated register.

[0231] For example, when the processor recognizes a read instruction that performs a read operation on memory, it checks whether the destination register is in an idle state based on the parsed address of the destination register. If the destination register is in an idle state, the processor allocates the destination register to the read operation corresponding to the read instruction. If the destination register is not in an idle state, the processor allocates other idle registers as destination registers to the read operation corresponding to the read instruction.

[0232] For example, when the processor recognizes a write instruction for memory, it checks whether the source register is free based on the parsed address of the source register. If the source register is free, the processor allocates it to the write operation corresponding to the write instruction. If the source register is not free, the processor uses other free registers as source registers and allocates them to the write operation corresponding to the write instruction.

[0233] 207. The processor executes read and write instructions in the order they are executed.

[0234] Since the execution order of read and write instructions is the order in which they are arranged in the instruction sequence, when the processor executes read and write instructions in the order of execution, it first executes the instructions that are in the instruction sequence before the read and write instruction, then executes the read and write instruction, and then executes the instructions that are in the instruction sequence after the read and write instruction. This ensures that the read and write instructions in the instruction sequence are executed in order, thus guaranteeing the consistency of the processor's access to memory.

[0235] If the application's source code is developed for a processor supporting a non-weak memory model, then the arrangement of read and write instructions in the application satisfies the execution order requirements of the non-weak memory model. When the application is executed by a processor supporting a non-weak memory model, the execution order of read and write instructions in the application is not swapped, thus maintaining memory consistency for memory read and write operations. Therefore, for the application to function correctly, memory consistency must be maintained for memory read and write operations. However, the processor of the first computing device supports a memory access order that is inconsistent with the order of read and write instructions in the application. In related technologies, the processor of the first computing device may swap the execution order of read and write instructions in the application, resulting in memory consistency problems and causing the application to malfunction. In this embodiment, the processor of the first computing device identifies the order of read and write instructions in the instruction sequence as the execution order of the read and write instructions, and executes the read and write instructions in the instruction sequence in order, thereby avoiding memory consistency problems and enabling the application to function correctly.

[0236] When a processor executes a recognized read instruction, it performs a read operation on memory based on the destination register allocated for the corresponding read operation. For example, the processor reads data from the source memory address based on the address of the destination register allocated for the corresponding read operation and the source memory address parsed from the read instruction, and stores the read data in the destination register to perform a read operation on the source memory address.

[0237] When the processor executes any identified write instruction, it performs a write operation on memory based on the source register allocated for the corresponding write operation. For example, the processor retrieves data from the source register based on the address of the source register allocated for the corresponding write operation and the destination memory address in memory parsed from the write instruction, and stores the retrieved data at the destination memory address to perform a write operation on the destination memory address.

[0238] The method provided in this application embodiment obtains the instruction sequence of an application through a processor, identifies the execution order of read and write instructions in the instruction sequence, and executes the read and write instructions according to the identified execution order to access the memory in the computing device. This enables the processor to execute the application normally, thereby reducing the occurrence of adverse situations such as random crashes, restarts, or erroneous execution results in the application, increasing the reliability of the processor, and further improving the processor's reputation and market sales.

[0239] To further illustrate the process shown in steps 204-207 above, see [link to documentation]. Figure 3 The diagram shown is a schematic representation of a data processing procedure for a processor according to an embodiment of this application. This procedure includes the following steps 301-306.

[0240] 301. The second computing device uses compilation software to compile the application source program to obtain the application program that can be executed by the processor of the first computing device.

[0241] 302. After the first computing device acquires the application, the processor of the first computing device fetches instructions from the application.

[0242] For example, the processor reads multiple instructions in the application sequentially according to the order in which the instructions are arranged within the application.

[0243] 303. The processor decodes multiple instructions.

[0244] In one possible implementation, the processor includes a core and a decoder, the core transmitting multiple instructions to the decoder for decoding.

[0245] For example, the decoder identifies read and write instructions among the multiple instructions. The decoder parses the source memory address and destination register address from the read instruction, using these addresses as the parsing result. If the read instruction also includes read micro-operations, the decoder can further parse these micro-operations, including the source memory address, destination register address, and the read micro-operation itself. These read micro-operations are auxiliary operations used to complete the memory read operation, such as data verification.

[0246] The decoder parses the source register address and destination memory address from the write instruction, using these addresses as the parsing result. If the write instruction also includes write micro-operations, the decoder can further parse these micro-operations, using the source register address, destination memory address, and the micro-operation itself as the decoding result. These write micro-operations are auxiliary operations used to complete the memory write operation, such as data verification.

[0247] After the decoder obtains the parsing results of multiple instructions, it sends the parsing results of multiple instructions back to the kernel.

[0248] 304. The processor allocates registers for the corresponding read / write operations based on the parsing results of the read / write instructions.

[0249] When the processor kernel receives the parsed result of a read instruction, it obtains the address of the destination register from the parsed result and checks whether the destination register is in an idle state. If the destination register is in an idle state, the processor allocates the destination register to the read operation corresponding to the read instruction. If the destination register is not in an idle state, the processor uses another idle register as the destination register and allocates it to the read operation corresponding to the read instruction, thus renaming the register.

[0250] When the processor kernel receives the parsing result of a write instruction, it obtains the address of the source register from the parsing result and checks whether the source register is in an idle state. If the source register is in an idle state, the processor allocates the source register to the write operation corresponding to the write instruction. If the source register is not in an idle state, the processor uses another idle register as the source register and allocates it to the write operation corresponding to the write instruction, thereby renaming the register.

[0251] 305. The processor's core dispatches read and write operations to the memory read / write unit.

[0252] In one possible implementation, the processor also includes a load and store unit (LSU) for handling read and write operations on memory. After allocating registers for read and write instructions, the processor kernel sends the read operation indicated by the read instruction and the write operation indicated by the write instruction to the LSU. If the read operation includes a read micro-operation and the write operation includes a write micro-operation, the kernel also sends the read micro-operation from the parsing result of the read instruction and the write operation from the parsing result of the write instruction to the LSU.

[0253] 306. The memory read / write unit uses sequential memory access mode to perform the read and write operations.

[0254] In one possible implementation, the memory read / write unit, when performing read or write operations on memory using sequential memory access mode, does so via a write-back mechanism. Of course, the memory read / write unit can also employ other methods to perform read and write operations on memory.

[0255] The method provided in this application embodiment obtains the instruction sequence of the application through the processor and executes the read and write instructions in the instruction sequence in the sequential memory access mode to access the memory in the computing device. This can avoid memory consistency problems and enable the processor to execute the application normally. Correspondingly, it reduces the occurrence of adverse situations such as random crashes, restarts or erroneous execution results in the application, increases the reliability of the processor, and further improves the reputation and market sales of the processor.

[0256] It should be noted that the above Figure 2 and Figure 3 The data processing procedures shown are illustrated using the example of a second computing device compiling the application source program, and a first computing device executing the application program compiled by the second computing device. In another possible implementation, the application source program does not need to be compiled by the second computing device; instead, it is compiled by the first computing device, and the first computing device executes the compiled application program. In this case, the first computing device performs steps 201-204 and 205-207 as described above.

[0257] The above combination Figures 1 to 3 The data processing method provided in this application has been introduced. Next, we will discuss... Figures 4 to 5 The apparatus and computing device of this application are described using examples.

[0258] See Figure 4 This application provides a schematic diagram of a data processing device, which is configured as a processor of a computing device. The processor supports a memory access order that is inconsistent with the order of read / write instructions in the application when executing an application. The read / write instructions are instructions for reading and writing memory. The data processing device includes:

[0259] The acquisition module 401 is used to acquire the instruction sequence of the application, the instruction sequence including multiple instructions, the multiple instructions including read and write instructions to perform read or write operations on the memory of the computing device, and the application is deployed in the computing device;

[0260] The identification module 402 is used to identify the execution order of the read and write instructions based on the instruction sequence;

[0261] The execution module 403 is used to execute the read and write instructions in the order of execution.

[0262] In one possible implementation, the identification module 402 is used for:

[0263] The order in which the read and write instructions are arranged in the instruction sequence is identified as the execution order of the read and write instructions.

[0264] In another possible implementation, the identification module 402 is used for:

[0265] According to the sequential memory access mode, the order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions. The sequential memory access mode requires that the execution order of the read and write instructions be consistent with the order of the read and write instructions in the instruction sequence.

[0266] In another possible implementation, the read / write instructions include a read instruction that performs a read operation on the memory or a write instruction that performs a write operation on the memory, wherein the read instruction has a first semantic and the write instruction has a second semantic.

[0267] Wherein, the first semantic is used to indicate that the first instruction in the instruction sequence is executed after the read instruction is executed, and the second semantic is used to indicate that the second instruction in the instruction sequence is executed before the write instruction is completed. The first instruction is arranged after the read instruction in the instruction sequence, and the second instruction is arranged before the write instruction in the instruction sequence.

[0268] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, which has the first semantics and is an instruction added to the processor's instruction set to indicate reading memory data.

[0269] The write instruction is compiled based on the extended memory write instruction, which has the second semantics. The extended memory write instruction is an instruction added to the instruction set to indicate the writing of memory data.

[0270] In another possible implementation, the extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; wherein the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not include non-scaling immediate addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction all support the non-scaling immediate addressing mode;

[0271] The first extended memory read instruction is used to instruct the determination of the storage address in the memory based on the supported addressing mode, and to read the first number of bytes of data in the determined storage address into the first destination register;

[0272] The second extended memory read instruction is used to instruct the determination of the storage address in the memory based on the supported addressing mode, read the second byte of data in the determined storage address into the second destination register, and fill the remaining bits of the second destination register with the sign bit of the read data;

[0273] The third extended memory read instruction is used to instruct the determination of the storage address in the memory based on the non-scaling immediate addressing mode, and to read the data of the first byte number in the determined storage address into the third destination register;

[0274] The fourth extended memory read instruction is used to instruct the determination of the storage address in the memory based on the non-scaling immediate addressing mode, read the second byte of data in the determined storage address into the fourth destination register, and fill the remaining bits of the fourth destination register with the sign bit of the read data;

[0275] The first extended memory write instruction is used to instruct the storage address in the memory to be determined based on the supported addressing mode, and to write the data of the third byte in the first source register to the determined storage address;

[0276] The second extended memory write instruction is used to instruct the storage address in the memory to be determined based on the non-scaling immediate addressing mode, and to write the data of the third byte in the second source register to the determined storage address.

[0277] In one possible implementation, the first number of bytes includes 1 byte, 2 bytes, 4 bytes, or 8 bytes; the second number of bytes includes 1 byte, 2 bytes, or 4 bytes; and the third number of bytes includes 1 byte, 2 bytes, 4 bytes, or 8 bytes.

[0278] The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction include scaled immediate addressing mode, tag addressing mode, or register addressing mode. The immediate value used for address offset in the scaled immediate addressing mode is the scaled operand in the corresponding instruction.

[0279] When performing address offset in the non-scaling immediate addressing mode, the immediate value used is the operand in the corresponding instruction, and the operand's value range is -256 to 256.

[0280] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, which is an instruction obtained by adding the first semantic to a general memory read instruction in the processor's instruction set;

[0281] The instructions for the write operation are compiled based on extended memory write instructions, which are instructions obtained by adding the second semantic to the general memory write instructions in the instruction set.

[0282] In another possible implementation, the read / write instructions include read instructions for performing a read operation on the memory or write instructions for performing a write operation on the memory, wherein the read instructions are compiled based on general memory read instructions in the processor's instruction set, and the write instructions are compiled based on general memory write instructions in the processor's instruction set.

[0283] It should be understood that the data processing device corresponds to the processor of the first computing device in the above method embodiments. Each module in the data processing device and the other operations and / or functions described above are for implementing various steps and methods performed by the processor in the method embodiments. Specific details can be found in the above method embodiments, and for simplicity, they will not be repeated here. Furthermore, when the data processing device processes data, the division of the above functional modules is only used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the data processing device can be divided into different functional modules to complete all or part of the functions described above. In addition, the data processing device provided in the above embodiments and the above method embodiments belong to the same concept, and its specific implementation process can be found in the above method embodiments, and will not be repeated here.

[0284] Figure 5 This is a schematic diagram of a computing device provided in an embodiment of this application. It should be understood that the apparatus described below can implement any function of the first computing device in any of the above methods.

[0285] Optionally, Figure 5The computing device shown is configured as the first computing device described above, and the computing device includes at least one processor 501, a communication bus 502, a memory 503, and at least one communication interface 504.

[0286] Processor 501 can be a general-purpose central processing unit (CPU), network processor (NP), microprocessor, microcontroller unit (MCU), digital signal processor (DSP), or artificial intelligence processor, etc., a computing device that runs software. Each computing device may include one or more cores for executing software instructions to perform calculations or processing. The processor may be integrated into a system-on-chip (SoC), or it may be one or more integrated circuits for implementing the scheme of this application, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0287] The communication bus 502 is used to transmit information between the aforementioned components. The communication bus 502 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, it is shown in the figure with only one thick line, but this does not indicate that there is only one bus or one type of bus.

[0288] Memory 503 may include read-only memory and random access memory, and provides instructions and data to processor 501. Memory 503 may also include non-volatile random access memory. For example, memory 503 may also store device type information.

[0289] Memory 503 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0290] The memory 503 can exist independently and be connected to the processor 501 via the communication bus 502. Alternatively, the memory 503 can be integrated with the processor 501.

[0291] Communication interface 504 uses any transceiver-like device for communicating with other devices or communication networks. Communication interface 504 includes a wired communication interface and may also include a wireless communication interface. The wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0292] In a specific implementation, as one example, the processor 501 may include one or more CPUs, such as Figure 5 CPU0 and CPU1 are shown in the diagram.

[0293] In a specific implementation, as one example, the computing device may include multiple processors, such as... Figure 5The processors 501 and 505 are shown. Each of these processors can be a single-core processor or a multi-core processor. A processor here can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0294] In a specific implementation, as one embodiment, the computing device may further include an output device and an input device. The output device communicates with the processor 501 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 501 and can receive user input in various ways. For example, the input device may be a PCIe device, a mouse, a keyboard, a touchscreen device, or a sensing device, etc.

[0295] In some embodiments, the memory 503 is used to store program code 510 for executing the scheme of this application, and the processor 501 can execute the program code 510 stored in the memory 503 to implement the data processing method described above. In other embodiments, based on the hardware structure of the processor 501, the processor 501 is able to implement the data processing method described above.

[0296] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including at least one line of program code, which can be executed by a processor in a computing device to perform the data processing method described above. For example, the computer-readable storage medium is a non-transitory computer-readable storage medium, such as a read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device.

[0297] This application also provides a computer program product, which includes at least one piece of program code stored in a computer-readable storage medium. The processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions to perform the above-described data processing method.

[0298] In this embodiment, the apparatus, device, computer-readable storage medium, and computer program product are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0299] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0300] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions (such as program code). When the computer instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. Semiconductor media can be solid-state disks (SSDs).

[0301] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing method, characterized by, The method comprises: A processor acquires an instruction sequence of an application, the instruction sequence comprising a plurality of instructions, the plurality of instructions comprising a read-write instruction for performing a read operation or a write operation on a memory of a computing device, the application being deployed in the computing device, the computing device comprising the processor; Under a weak memory model, the processor identifies an execution order of the read-write instruction according to an instruction in the instruction sequence; The processor executes the read-write instruction according to the execution order; The read-write instruction comprises a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction having a first semantic, and the write instruction having a second semantic; The first semantic is used to indicate that a first instruction in the instruction sequence is executed after the read instruction, and the second semantic is used to indicate that a second instruction in the instruction sequence is executed before the write instruction is completed, the first instruction being arranged after the read instruction in the instruction sequence, and the second instruction being arranged before the write instruction in the instruction sequence.

2. The method of claim 1, wherein, The execution order of the read-write instruction is identified according to an instruction in the instruction sequence, comprising: The arrangement order of the read-write instruction in the instruction sequence is identified as the execution order of the read-write instruction.

3. The method of claim 2, wherein, The arrangement order of the read-write instruction in the instruction sequence is identified as the execution order of the read-write instruction, comprising: According to a sequential memory access mode, the arrangement order of the read-write instruction in the instruction sequence is identified as the execution order of the read-write instruction, the sequential memory access mode requiring that the execution order of the read-write instruction is consistent with the arrangement order of the read-write instruction in the instruction sequence.

4. The method according to any one of claims 1-3, characterized in that, The read instruction is compiled based on an extended memory read instruction, the extended memory read instruction having the first semantic, and the extended memory read instruction being an instruction for indicating reading memory data added in an instruction set of the processor; The write instruction is compiled based on an extended memory write instruction, the extended memory write instruction having the second semantic, and the extended memory write instruction being an instruction for indicating writing memory data added in the instruction set.

5. The method of claim 4, wherein, The extended memory read instruction comprises at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction comprises at least one of a first extended memory write instruction and a second extended memory write instruction; The first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not support a non-scaled immediate number addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction support the non-scaled immediate number addressing mode; The first extended memory read instruction is used to indicate that a storage address in the memory is determined based on a supported addressing mode, and data of a first number of bytes in the determined storage address is read into a first destination register. The second extended memory read instruction is used for instructing to determine a storage address in the memory based on a supported addressing mode, reading data of a second byte number in the determined storage address into a second destination register, and filling the remaining bits of the second destination register with sign bits of the read data; The third extended memory read instruction is used for instructing to determine a storage address in the memory based on the non-scaled immediate addressing mode, and reading data of a first byte number in the determined storage address into a third destination register; The fourth extended memory read instruction is used for instructing to determine a storage address in the memory based on the non-scaled immediate addressing mode, reading data of a second byte number in the determined storage address into a fourth destination register, and filling the remaining bits of the fourth destination register with sign bits of the read data; The first extended memory write instruction is used for instructing to determine a storage address in the memory based on a supported addressing mode, and writing data of a third byte number in a first source register into the determined storage address; The second extended memory write instruction is used for instructing to determine a storage address in the memory based on the non-scaled immediate addressing mode, and writing data of a third byte number in a second source register into the determined storage address.

6. The method of claim 5, wherein, The first byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes, the second byte number includes 1 byte, 2 bytes or 4 bytes, and the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes; The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction include a scaled immediate addressing mode, a label addressing mode or a register addressing mode, and an immediate number used for address offset in the scaled immediate addressing mode is a scaled operand in a corresponding instruction; An immediate number used for address offset in the non-scaled immediate addressing mode is an operand in a corresponding instruction, and the value range of the operand is -256 to 256.

7. The method according to any one of claims 1-3, characterized in that, The read instruction is compiled based on an extended memory read instruction, and the extended memory read instruction is an instruction obtained by adding the first semantics to a general memory read instruction in an instruction set of the processor; The write instruction is compiled based on an extended memory write instruction, and the extended memory write instruction is an instruction obtained by adding the second semantics to a general memory write instruction in the instruction set.

8. The method of any one of claims 1-3, wherein, The read instruction is compiled based on a general memory read instruction in an instruction set of the processor, and the write instruction is compiled based on a general memory write instruction in the instruction set of the processor.

9. A data processing apparatus, characterized by, The apparatus comprises: An obtaining module is configured to obtain an instruction sequence of an application, the instruction sequence comprising a plurality of instructions, the plurality of instructions comprising read-write instructions for performing read or write operations on a memory of a computing device, and the application being deployed in the computing device; An identifying module is configured to identify, under a weak memory model, an execution order of the read-write instructions according to the instructions in the instruction sequence; An executing module is configured to execute the read-write instructions in the execution order. The device is configured as a processor of a computing device, the read-write instruction includes a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction has a first semantic, and the write instruction has a second semantic; the first semantic is used to indicate that a first instruction in the instruction sequence is executed after execution of the read instruction, the second semantic is used to indicate that a second instruction in the instruction sequence is executed before completion of execution of the write instruction, and the first instruction is arranged after the read instruction in the instruction sequence.

10. The apparatus of claim 9, wherein, The identification module is specifically configured to: arrange the read-write instruction in the instruction sequence in the execution order of the read-write instruction.

11. The apparatus of claim 10, wherein, The identification module is specifically configured to: arrange the read-write instruction in the instruction sequence in the execution order of the read-write instruction in a sequential memory access mode, and the sequential memory access mode requires that the execution order of the read-write instruction is consistent with the arrangement of the read-write instruction in the instruction sequence.

12. The apparatus of any one of claims 9-11, wherein, The read instruction is compiled based on an extended memory read instruction, the extended memory read instruction has the first semantic, and the extended memory read instruction is an instruction for indicating reading of memory data added in an instruction set of the processor; The write instruction is compiled based on an extended memory write instruction, the extended memory write instruction has the second semantic, and the extended memory write instruction is an instruction for indicating writing of memory data added in the instruction set.

13. The apparatus of claim 12, wherein, The extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; The first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not support a non-scaled immediate number addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction support the non-scaled immediate number addressing mode; The first extended memory read instruction is used to indicate determination of a storage address in the memory based on a supported addressing mode, and read data of a first byte number in the determined storage address into a first destination register; The second extended memory read instruction is used to indicate determination of a storage address in the memory based on a supported addressing mode, read data of a second byte number in the determined storage address into a second destination register, and fill the remaining bits of the second destination register with a sign bit of the read data; The third extended memory read instruction is used to indicate determination of a storage address in the memory based on the non-scaled immediate number addressing mode, and read data of a first byte number in the determined storage address into a third destination register; The fourth extended memory read instruction is configured to indicate to determine a storage address in the memory based on the non-scaled immediate number addressing mode, read data of a second byte number from the determined storage address into a fourth destination register, and fill the remaining bits of the fourth destination register with the sign bit of the read data. The first extended memory write instruction is configured to indicate to determine a storage address in the memory based on the supported addressing mode, and write data of a third byte number in a first source register into the determined storage address. The second extended memory write instruction is configured to indicate to determine a storage address in the memory based on the non-scaled immediate number addressing mode, and write data of the third byte number in a second source register into the determined storage address.

14. The apparatus of claim 13, wherein, The first byte number comprises 1 byte, 2 bytes, 4 bytes, or 8 bytes, the second byte number comprises 1 byte, 2 bytes, or 4 bytes, and the third byte number comprises 1 byte, 2 bytes, 4 bytes, or 8 bytes. The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction comprise a scaled immediate number addressing mode, a label addressing mode, or a register addressing mode, and the immediate number used for address offset in the scaled immediate number addressing mode is a scaled operand in the corresponding instruction. The immediate number used for address offset in the non-scaled immediate number addressing mode is an operand in the corresponding instruction, and the value range of the operand is -256 to 256.

15. The apparatus of any one of claims 9-11, wherein, The read instruction is compiled based on an extended memory read instruction, and the extended memory read instruction is an instruction obtained by adding the first semantic to a general memory read instruction in an instruction set of the processor. The write operation instruction is compiled based on an extended memory write instruction, and the extended memory write instruction is an instruction obtained by adding the second semantic to a general memory write instruction in the instruction set.

16. The apparatus of any one of claims 9-11, wherein, The read-write instruction comprises a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction is compiled based on a general memory read instruction in an instruction set of the processor, and the write instruction is compiled based on a general memory write instruction in the instruction set of the processor.

17. A computing device, comprising: The computing device comprises a processor configured to perform the method in any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that, The storage medium stores at least one program code, and the at least one program code is read by a processor in a computing device to cause the processor to perform the method in any one of claims 1 to 8.

Images