Assembly language translation method, device and computing equipment based on deep learning

Abstract

The present invention discloses an assembly language translation method, device and computing equipment based on deep learning, the method comprising: training a pre-training module to obtain a pre-training model; using the pre-training model, converting a first architecture sample assembly code block and a corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector respectively; training a translation module based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector to obtain a translation model; generating an assembly language translation model based on the pre-training model and the translation model; using the assembly language translation model, converting the first architecture actual assembly code block into the corresponding second architecture actual assembly code block. The present invention generates an assembly language translation model through training, and can more intelligently translate between different architecture assembly languages, thereby improving the efficiency of cross-architecture assembly language translation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an assembly language translation method, an assembly language translation device and a computing device based on deep learning. Background Art

[0002] With the rapid development of computer architecture, processor instruction set architecture (ISA) has shown diversified characteristics. ISA defines a series of specifications such as a computer's instruction set, instruction format encoding, register organization, storage access mode, etc., and is the interface between hardware and software. Different ISAs have significant differences in instruction semantics, binary encoding methods, etc., resulting in programs compiled based on one ISA being unable to run directly on processors of another ISA. The current mainstream ISAs include X86, ARM, MIPS, RISC-V, etc.

[0003] The assembly code of a program is a low-level language representation that uses mnemonics and opcodes to represent machine instructions, and is more readable than machine code. Assembly languages ​​of different ISAs differ in instruction semantics, register usage, addressing methods, etc., but compared to binary machine code, assembly code retains more information about program structure and instruction operations, which helps to understand the semantics and control flow of the program.

[0004] Assembly language programs can be assembled into binary machine code by an assembler for direct execution by the processor. The basic unit of a binary program is an instruction, and instructions of different ISAs have different instruction formats and lengths. The binary instruction sequence encodes all the semantic information of the program, but most of these semantics are implicit and lack explicit high-level abstraction, which brings challenges to the semantic understanding and conversion of the program.

[0005] The development of machine translation technology has provided new ideas for cross-language translation tasks. Traditional rule-based translation methods require linguists to define conversion rules between vocabulary and grammar, which is similar to the manual mapping rules in DBT. With the rise of deep learning, neural machine translation (NMT) has gradually become the mainstream translation method. NMT uses an end-to-end neural network model to directly learn translation knowledge from the source language to the target language. The encoder encodes the source language sentence into a semantic vector, and the decoder generates the target language sentence based on the semantic vector. The NMT model can automatically learn translation rules from a large-scale bilingual corpus, reducing the reliance on artificial features and translation rules. The NMT model based on the attention mechanism can automatically learn the alignment relationship between the source language and the target language, capture long-distance dependencies, and generate more fluent and coherent translations. NMT has achieved great success in the field of machine translation, greatly improving translation quality and efficiency.

[0006] With the development of machine translation, researchers have begun to explore the use of deep learning technology for programming language translation. Program translation aims to achieve automatic conversion between different programming languages, such as translation between C++ and Java, translation from high-level language to assembly language, etc. Compared with natural language, programming language has stricter grammatical and semantic specifications. Therefore, program translation has higher requirements on the expressiveness and generalization ability of the model.

[0007] Existing work on program translation mainly focuses on the high-level language level. Researchers have explored a variety of neural network architectures based on sequence-to-sequence models, graph neural networks, pre-trained models, and have made encouraging progress. These works have confirmed the effectiveness of deep learning technology in program language understanding and generation, paving the way for end-to-end program translation.

[0008] However, the application of deep learning in assembly language translation at the instruction set architecture level is still very limited. Compared with high-level languages, assembly languages ​​lack clear program structure information, instruction semantics are highly dependent on context, and assembly codes of different ISAs vary greatly in instruction format and addressing mode, which poses a higher challenge to the modeling ability of neural networks. In addition, due to the lack of large-scale cross-ISA instruction-level parallel corpus, data scarcity has become a bottleneck restricting neural network learning.

[0009] In summary, traditional translation methods face many limitations, and a more automated and intelligent assembly language translation solution is urgently needed. The success of deep learning in the fields of machine translation and program translation has brought new opportunities for intelligent translation of assembly language. However, how to effectively represent and learn instruction-level semantics, solve the differences caused by cross-architecture heterogeneity, and alleviate the lack of training data are huge challenges faced by applying deep learning to assembly language translation.

[0010] Therefore, a deep learning-based assembly language translation method is needed to solve the problems existing in the above technical solutions. Summary of the invention

[0011] To this end, the present invention provides an assembly language translation method and device based on deep learning to solve or at least alleviate the above problems.

[0012] According to one aspect of the present invention, there is provided an assembly language translation method based on deep learning, which is executed in a computing device, and includes: training a pre-training module to obtain a pre-training model; using the pre-training model, converting a first architecture sample assembly code block and a corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively; training a translation module based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector, and the second architecture sample vector to obtain a translation model; generating an assembly language translation model based on the pre-training model and the translation model; and using the assembly language translation model, converting a first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

[0013] Optionally, in the deep learning-based assembly language translation method according to the present invention, the assembly language translation model is used to convert the actual assembly code block of the first architecture into a corresponding actual assembly code block of the second architecture, including: using a pre-trained model of the assembly language translation model to convert the actual assembly code block of the first architecture into a first architecture actual vector; using a translation model of the assembly language translation model to convert the first architecture actual vector into a corresponding second architecture actual assembly code block.

[0014] Optionally, in the assembly language translation method based on deep learning according to the present invention, a pre-training module is trained to obtain a pre-training model, including: obtaining multiple binary programs, the multiple binary programs including a first architecture binary program and a second architecture binary program; disassembling the multiple binary programs to obtain corresponding first architecture original assembly codes and second architecture original assembly codes; performing static analysis on the first architecture original assembly codes and the second architecture original assembly codes to extract data dependency flow and control flow from the first architecture original assembly codes and the second architecture original assembly codes; based on the data dependency flow and control flow, training the pre-training module to obtain a pre-training model.

[0015] Optionally, in the assembly language translation method based on deep learning according to the present invention, the pre-training module is trained based on the data dependency flow and the control flow to obtain a pre-training model, including: based on the data dependency flow and the control flow, a mask language model prediction task and a next sentence prediction task are used to train the pre-training module to obtain a pre-training model.

[0016] Optionally, in the assembly language translation method based on deep learning according to the present invention, the pre-trained model is used to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively, including: compiling and generating corresponding first architecture binary files and second architecture binary files based on the source code file; disassembling the first architecture binary file and the second architecture binary file, respectively, to obtain multiple first architecture sample assembly code blocks and corresponding multiple second architecture sample assembly code blocks in a predetermined format; using the pre-trained model, converting each of the first architecture sample assembly code blocks and the corresponding second architecture sample assembly code blocks into a first architecture sample vector and a second architecture sample vector, respectively.

[0017] Optionally, in the assembly language translation method based on deep learning according to the present invention, the pre-trained model is used to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively, including: embedding and position encoding the first architecture sample assembly and the corresponding second architecture sample assembly code block to obtain a first architecture sample input representation and a second architecture sample input representation; using multiple encoding layers of the pre-trained model to extract the first architecture sample vector and the second architecture sample vector from the first architecture sample input representation and the second architecture sample input representation, respectively.

[0018] Optionally, in the assembly language translation method based on deep learning according to the present invention, a translation module is trained based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector, including: based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector, the translation module is trained using a TeacherForcing training mechanism.

[0019] Optionally, in the assembly language translation method based on deep learning according to the present invention, a translation module is trained based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector to obtain a translation model, including: using the translation module to convert the first architecture sample vector into a corresponding second architecture prediction assembly code block; calculating a target loss value between the second architecture prediction assembly code block and the second architecture sample assembly code block through a hybrid objective function; and training the translation module based on the target loss value to obtain a translation model.

[0020] Optionally, in the deep learning-based assembly language translation method according to the present invention, the assembly language translation model is used to convert the actual assembly code block of the first architecture into the corresponding actual assembly code block of the second architecture, including: using the assembly language translation model and adopting the Beam Search algorithm to convert the actual assembly code block of the first architecture into the corresponding actual assembly code block of the second architecture.

[0021] Optionally, in the assembly language translation method based on deep learning according to the present invention, the assembly language translation model is used to convert the first architecture actual assembly code block into a corresponding second architecture actual assembly code block using a Beam Search algorithm, including: using the assembly language translation model, for the first architecture actual assembly code block, at each time step t, multiple candidate sequences are generated respectively and k optimal candidate sequences are retained; wherein, at each time step, multiple new candidate sequences are generated respectively based on each current optimal candidate sequence in the k current optimal candidate sequences, and the final score of each new candidate sequence is determined based on the basic translation probability score, length penalty item and coverage penalty item of each new candidate sequence, and the k new optimal candidate sequences with the highest scores are selected from all the new candidate sequences according to the final score of each new candidate sequence and retained until k final optimal candidate sequences are obtained, where k is an integer greater than or equal to 2; and the final optimal candidate sequence with the highest score is selected from the k final optimal candidate sequences as the second architecture actual assembly code block and output.

[0022] Optionally, in the deep learning-based assembly language translation method according to the present invention, it also includes: using the assembly language translation model to convert multiple first architecture actual assembly code blocks into corresponding multiple second architecture actual assembly code blocks respectively; and establishing a translation rule set based on the multiple first architecture actual assembly code blocks and the corresponding multiple second architecture actual assembly code blocks.

[0023] Optionally, in the assembly language translation method based on deep learning according to the present invention, a translation rule set is established based on multiple first architecture actual assembly code blocks and corresponding multiple second architecture actual assembly code blocks, including: establishing a mapping relationship between multiple first architecture actual assembly code blocks and multiple second architecture actual assembly code blocks; parameterizing the operands in each of the first architecture actual assembly code blocks and the corresponding second architecture actual assembly code blocks to obtain each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block; and generating a translation rule set based on each of the first architecture parameterized assembly code blocks and the corresponding second architecture parameterized assembly code blocks.

[0024] Optionally, in the assembly language translation method based on deep learning according to the present invention, the first architecture is the x86 architecture, and the second architecture is the ARM architecture.

[0025] Optionally, in the assembly language translation method based on deep learning according to the present invention, the pre-training module is an encoder of a seq2seq model, and the translation module is a decoder of a seq2seq model.

[0026] According to one aspect of the present invention, there is provided an assembly language translation apparatus, which is deployed in a computing device and includes: a first training unit, adapted to train a pre-training module to obtain a pre-training model; a conversion unit, adapted to use the pre-training model to convert a first architecture sample assembly code block and a corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively; a second training unit, adapted to train a translation module based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector to obtain a translation model; a generation unit, adapted to generate an assembly language translation model based on the pre-training model and the translation model; and a translation unit, adapted to use the assembly language translation model to convert a first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

[0027] According to one aspect of the present invention, a computing device is provided, comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be suitable for execution by the at least one processor, and the program instructions include instructions for executing the deep learning-based assembly language translation method as described above.

[0028] According to one aspect of the present invention, a computer program product is provided, comprising a computer program / instruction, wherein the computer program / instruction implements the method as described above when executed by a processor.

[0029] According to one aspect of the present invention, a readable storage medium storing program instructions is provided. When the program instructions are read and executed by a computing device, the computing device executes the assembly language translation method based on deep learning as described above.

[0030] According to the technical solution of the present invention, a method for translating assembly language based on deep learning is provided, wherein the pre-training module is firstly trained to obtain a pre-training model, and then the pre-training model is used to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into the first architecture sample vector and the second architecture sample vector, respectively, and then the translation module is trained to obtain a translation model, and an assembly language translation model can be generated based on the pre-training model and the translation model, so that the assembly language translation model can be used to convert the actual assembly code block of the first architecture into the corresponding actual assembly code block of the second architecture. Based on this, the present invention can effectively represent and learn instruction-level semantics in the process of training and generating an assembly language translation model, solves the differences caused by cross-architecture heterogeneity and the problem of lack of training data, and can achieve more intelligent translation between assembly languages ​​of different architectures by training and generating an assembly language translation model, significantly improving the efficiency of cross-architecture assembly language translation.

[0031] Furthermore, the present invention adopts the Teacher Forcing training mechanism to train the translation module, which can balance the training efficiency and the generalization ability of the model; and, during the training process, a hybrid objective function combining the cross entropy loss and the BLEU score is used to calculate the loss, which can optimize the translation quality of the translation model.

[0032] In addition, in the actual translation process using the assembly language translation model, the use of the Beam Search algorithm can improve the translation quality.

[0033] In addition, the translation rule set generated according to the assembly language translation model of the present invention can greatly reduce the burden of manually defining translation rules and improve the flexibility and adaptability of binary translation. The translation rule set generated according to the present invention can improve the generalization ability of the translation rules after parameterization processing, and can improve the efficiency and quality of binary translation.

[0034] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to achieve the above and related purposes, some illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. By reading the following detailed description in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present invention will become more apparent. Throughout the present invention, the same reference numerals generally refer to the same parts or elements.

[0036] Figure 1 A schematic diagram of a computing device 100 provided according to an embodiment of the present invention is shown;

[0037] Figure 2 A flowchart of an assembly language translation method 200 based on deep learning provided according to an embodiment of the present invention is shown;

[0038] Figure 3 A schematic diagram of the structure of an assembly language translation model 300 provided according to an embodiment of the present invention is shown;

[0039] Figure 4 Some examples of translation rules according to the embodiments of the present invention are shown;

[0040] Figure 5 A schematic diagram of an assembly language translation device 500 provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0041] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0042] In view of the current problems that the application of deep learning in assembly language translation at the instruction set architecture level is very limited and there is a lack of large-scale training data, the present invention proposes an assembly language translation method based on deep learning, which can effectively represent and learn instruction-level semantics, solve the differences caused by cross-architecture heterogeneity and the problem of lack of training data. By training and generating an assembly language translation model, it can achieve more intelligent translation between assembly languages ​​of different architectures, and significantly improve the efficiency of cross-architecture assembly language translation.

[0043] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figure 1 FIG. 1 is a schematic diagram of a computing device 100 provided according to an embodiment of the present invention. Figure 1 As shown, in a basic configuration, the computing device 100 includes at least one processing unit 102 and a system memory 104. According to one aspect, depending on the configuration and type of the computing device, the processing unit 102 can be implemented as a processor. The system memory 104 includes, but is not limited to, volatile storage (e.g., random access memory), non-volatile storage (e.g., read-only memory), flash memory, or any combination of such memories. According to one aspect, the system memory 104 includes an operating system 105.

[0045] According to one aspect, operating system 105 is suitable for controlling the operation of computing device 100, for example. Furthermore, examples are practiced in conjunction with graphics libraries, other operating systems, or any other application programs, and are not limited to any particular application or system. Figure 1 The basic configuration is shown in FIG. 1 by those components within the dashed lines. According to one aspect, computing device 100 has additional features or functionality. For example, according to one aspect, computing device 100 includes additional data storage devices (removable and / or non-removable), such as magnetic disks, optical disks, or tapes. Such additional storage Figure 1 1 is illustrated by a removable storage device 109 and a non-removable storage device 110.

[0046] As stated above, according to one aspect, a program module 103 is stored in the system memory 104. According to one aspect, the program module 103 may include one or more application programs, and the present invention does not limit the type of application program, for example, the application program may include: email and contact application programs, word processing application programs, spreadsheet application programs, database application programs, slide show application programs, drawing or computer-aided application programs, web browser application programs, etc.

[0047] According to one aspect, the program module 103 may include a plurality of program instructions suitable for executing the deep learning-based assembly language translation method 200 of the present invention, so that the computing device 100 is configured to execute the deep learning-based assembly language translation method 200 of the present invention.

[0048] According to one aspect, the program module 103 may include an assembly language translation device 500 , which may be configured to execute the deep learning-based assembly language translation method 200 of the present invention.

[0049] According to one aspect, the examples may be practiced on a circuit comprising discrete electronic components, a packaged or integrated electronic chip containing logic gates, a circuit utilizing a microprocessor, or a single chip containing electronic components or a microprocessor. Figure 1 Each or many components shown in can be integrated into a system on a chip (SOC) on a single integrated circuit to practice examples. According to one aspect, such a SOC device may include one or more processing units, a graphics unit, a communication unit, a system virtualization unit, and various application functions, all of which are integrated (or "burned") into a chip substrate as a single integrated circuit. When operated via SOC, the functions described in this article can be operated via a dedicated logic integrated with other components of the computing device 100 on a single integrated circuit (chip). Embodiments of the present invention can also be practiced using other technologies capable of performing logical operations (such as AND, OR, and NOT), including but not limited to mechanical, optical, fluid, and quantum technologies. In addition, embodiments of the present invention can be practiced in a general-purpose computer or in any other circuit or system.

[0050] According to one aspect, the computing device 100 may also have one or more input devices 112, such as a keyboard, a mouse, a pen, a voice input device, a touch input device, etc. Output devices 114 may also be included, such as a display, a speaker, a printer, etc. The aforementioned devices are examples and other devices may also be used. The computing device 100 may include one or more communication connections 116 that allow communication with other computing devices 118. Examples of suitable communication connections 116 include, but are not limited to: RF transmitter, receiver and / or transceiver circuits; Universal Serial Bus (USB), parallel and / or serial ports.

[0051] The term computer-readable medium as used herein includes computer storage media. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (e.g., computer-readable instructions, data structures, or program modules 103). System memory 104, removable storage device 109, and non-removable storage device 110 are all examples of computer storage media (i.e., memory storage). Computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage, cassettes, tapes, disk storage or other magnetic storage devices, or any other products that can be used to store information and can be accessed by computing device 100. According to one aspect, any such computer storage medium can be a part of computing device 100. Computer storage media do not include carrier waves or other propagated data signals.

[0052] According to one aspect, communication media is implemented by computer readable instructions, data structures, program modules 103, or other data in a modulated data signal (e.g., a carrier wave or other transport mechanism), and includes any information delivery media. According to one aspect, the term "modulated data signal" describes a signal that has one or more characteristics set or changed in such a manner as to encode information in the signal. By way of example and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0053] In an embodiment according to the present invention, the computing device 100 is configured to execute the assembly language translation method 200 based on deep learning of the present invention. The computing device 100 includes one or more processors and one or more readable storage media storing program instructions. When the program instructions are configured to be executed by one or more processors, the computing device executes the assembly language translation method 200 based on deep learning in the embodiment of the present invention.

[0054] Figure 2 A flowchart of an assembly language translation method 200 based on deep learning provided according to an embodiment of the present invention is shown. The assembly language translation method 200 based on deep learning can be executed in a computing device (e.g., the aforementioned computing device 100). The computing device 100 can convert a first architecture assembly code block into a corresponding second architecture assembly code block by executing the assembly language translation method 200 based on deep learning of the present invention.

[0055] In some embodiments of the present invention, the first architecture may be an x86 architecture, and the second architecture may be an ARM architecture. It should be noted that in the following specific embodiments, the present invention only takes the first architecture as an x86 architecture and the second architecture as an ARM architecture as an example to specifically illustrate the assembly language translation method 200 based on deep learning, but the present invention is not limited to the specific types of the first architecture and the second architecture.

[0056] like Figure 2 As shown, the assembly language translation method 200 based on deep learning includes the following steps 210-250.

[0057] Step 210: The computing device 100 trains the pre-training module to obtain a pre-training model. The pre-training model is used to convert the assembly code block into a vector.

[0058] In some embodiments, before training the pre-training module, the computing device 100 may first obtain multiple binary programs, and the multiple binary programs include a first architecture binary program and a second architecture binary program. The multiple binary programs may specifically be binary programs such as core components of commonly used operating systems, open source software packages, system-level applications, and user-level applications. Subsequently, a disassembly tool (such as Binary ninja) may be used to disassemble the multiple binary programs to obtain the corresponding first architecture original assembly code and second architecture original assembly code. Furthermore, the first architecture original assembly code and the second architecture original assembly code are statically analyzed to extract data dependency flow and control flow from the first architecture original assembly code and the second architecture original assembly code. The data dependency flow and control flow can be used as training data sets for training the pre-training module. In addition, dynamic plugging tools (such as Pin, DynamoRIO) can also be used to collect instruction execution sequences and memory access patterns when the program is running. Furthermore, the pre-training module can be trained based on data dependency flow and control flow to obtain a pre-training model. It should be noted that before performing static analysis on the original assembly code of the first architecture and the original assembly code of the second architecture, the original assembly code of the first architecture and the original assembly code of the second architecture can be preprocessed, for example, normalizing the instruction format, unifying the operand representation, expanding complex instructions into basic instruction sequences, and removing assembler pseudo-instructions that are not related to the architecture, and other preprocessing operations.

[0059] In some embodiments, when the computing device 100 trains the pre-training module based on the data dependency flow and the control flow, the computing device 100 may adopt self-supervised learning tasks such as the masked language model (MLM) prediction task and the next sentence prediction task (NSP) to learn the semantic representation of the instruction level, so as to train the pre-training module and obtain the pre-training model. In other words, the pre-training module may be trained based on the data dependency flow and the control flow using the masked language model (MLM) prediction task and the next sentence prediction task (NSP) to obtain the pre-training model.

[0060] Step 220 : The computing device 100 may use the pre-trained model to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively.

[0061] In some embodiments, in step 220, the computing device 100 may first construct a parallel corpus between the first architecture and the second architecture (x86-ARM instruction level parallel corpus). Specifically, one or more source code files may be obtained, and corresponding first architecture binary files and second architecture binary files may be compiled and generated based on the source code files, and then the first architecture binary files and the second architecture binary files may be disassembled respectively to obtain a plurality of first architecture sample assembly code blocks and a corresponding plurality of second architecture sample assembly code blocks of a predetermined format (sequence alignment). Here, by disassembling the first architecture binary files and the second architecture binary files respectively, the corresponding first architecture assembly code files and the second architecture assembly code files may be obtained, and then data cleaning may be performed on the first architecture assembly code files and the second architecture assembly code files and a vocabulary may be constructed, and then by operations such as sequence encoding, sequence alignment and padding, a plurality of first architecture sample assembly code blocks and a corresponding plurality of second architecture sample assembly code blocks of a predetermined format (sequence alignment, fixed length) may be obtained.

[0062] Afterwards, the computing device 100 may use the pre-trained model to convert each first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively.

[0063] Step 230: The computing device 100 may train a translation module based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector, and the second architecture sample vector to obtain a translation model.

[0064] In some embodiments, in step 230, based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector, and the second architecture sample vector, the computing device 100 may use the Teacher Forcing training mechanism to train the translation module. It should be noted that the use of the Teacher Forcing training mechanism can balance the training efficiency and the model generalization ability.

[0065] Step 240: The computing device 100 may generate an assembly language translation model based on the pre-trained model and the translation model obtained through the above training.

[0066] Figure 3 FIG. 3 shows a schematic diagram of the structure of an assembly language translation model 300 provided according to an embodiment of the present invention. Figure 3 As shown, the assembly language translation model 300 generated by training according to the present invention includes a pre-training model 310 and a translation model 320 coupled to each other.

[0067] Step 250 : The computing device 100 may use the assembly language translation model 300 to convert the first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

[0068] It should be understood that the assembly language translation model 300 generated by training according to the present invention can be used to convert a first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

[0069] Specifically, Figure 3 As shown, in the actual translation process using the assembly language translation model 300 in step 250, the pre-trained model 310 of the assembly language translation model 300 can first be used to convert the first architecture actual assembly code block into the first architecture actual vector, and the first architecture actual vector can be used as the input of the translation model 320. Then, the translation model 320 of the assembly language translation model 300 can be used to convert the first architecture actual vector into the corresponding second architecture actual assembly code block.

[0070] In some embodiments, in step 250, the computing device 100 may use a Beam Search algorithm to convert the first architecture actual assembly code block into the corresponding second architecture actual assembly code block during the actual translation process using the assembly language translation model. It should be noted that, in the actual translation process using the assembly language translation model, using the Beam Search algorithm (decoding strategy) can improve the translation quality.

[0071] It should be noted that the output of the assembly language translation model is obtained sequentially based on each time step, and the result of the previous time step will affect the result of the next time step. In the process of converting the actual assembly code block of the first architecture into the corresponding actual assembly code block of the second architecture using the Beam Search algorithm, multiple candidate sequences can be generated at each time step, and the score of each candidate sequence is calculated in combination with the length penalty and the coverage penalty, and the k best candidate sequences are retained according to the score of each candidate sequence. Here, the length penalty and the coverage penalty are combined to eventually generate a high-quality actual assembly code block of the second architecture.

[0072] Specifically, in the initialization phase, the beam width k can be set, the sequence start symbol SOS and the end symbol EOS can be defined, and the scores of the k candidate sequences can be initialized to 0. K is an integer greater than or equal to 2.

[0073] In step 250, using the assembly language translation model, in the process of converting the first architecture actual assembly code block into the corresponding second architecture actual assembly code block using the Beam Search algorithm, multiple candidate sequences can be generated for the first architecture actual assembly code block at each time step t and k optimal candidate sequences can be retained, wherein, at each time step t, multiple new candidate sequences are generated based on each of the k current optimal candidate sequences, and the final score (which can be a cumulative score) of each new candidate sequence is determined based on the basic translation probability score, length penalty item and coverage penalty item of each new candidate sequence, and the k new optimal candidate sequences with the highest scores are selected from all new candidate sequences according to the final score of each new candidate sequence and retained until k final optimal candidate sequences are obtained. Here, for the optimal candidate sequence retained at each time step, it can be determined whether the optimal candidate sequence generates an EOS mark. If the optimal candidate sequence generates an EOS mark, the optimal candidate sequence can be added to the completed sequence set as the final optimal candidate sequence until the number of the final optimal candidate sequences in the completed sequence set reaches the beam width k, and the generation process is terminated, at which time k final optimal candidate sequences can be obtained. Alternatively, when the final optimal candidate sequence with the highest score in the completed sequence set ends with an EOS marker, the generation process may be terminated.

[0074] Then, the final optimal candidate sequence with the highest score can be selected from the k final optimal candidate sequences, and the final optimal candidate sequence with the highest score can be output as the actual assembly code block of the second architecture. In this way, the actual assembly code block of the first architecture can be converted into the corresponding actual assembly code block of the second architecture by using the Beam Search algorithm.

[0075] In some embodiments, the computing device 100 can train and generate the assembly language translation model 300 of the present invention based on the seq2seq model of the Transformer architecture. Specifically, the encoder of the seq2seq model can be used as a pre-training module, and the decoder of the seq2seq model can be used as a translation module. By training the pre-training module and the translation module, the assembly language translation model of the present invention can be obtained. That is, in some embodiments of the present invention, the pre-training module can be the encoder of the seq2seq model, and the translation module can be the decoder of the seq2seq model.

[0076] In some embodiments, Figure 3 As shown, the pre-training model 310 obtained by training the pre-training module (encoder) includes multiple encoding layers, and the translation model 320 obtained by training the translation module (decoder) includes multiple decoding layers.

[0077] In step 220, the computing device 100 may perform preprocessing operations such as embedding and position encoding on the first architecture sample assembly code block and the corresponding second architecture sample assembly code block in advance to obtain the first architecture sample input representation and the second architecture sample input representation, and then input the first architecture sample input representation and the second architecture sample input representation into the pre-trained model, and use the multiple encoding layers of the pre-trained model to extract the first architecture sample vector and the second architecture sample vector from the first architecture sample input representation and the second architecture sample input representation, respectively. Specifically, high-level features can be extracted from the first architecture sample input representation and the second architecture sample input representation in sequence through the multiple encoding layers of the pre-trained model to obtain the first architecture sample vector and the second architecture sample vector.

[0078] In some embodiments, before training the translation module in step 230, a hybrid objective function may be designed. During the training of the translation module, the computing device 100 may use the translation module to convert the first architecture sample vector into the corresponding second architecture prediction assembly code block (prediction result), and calculate the target loss value between the second architecture prediction assembly code block and the second architecture sample assembly code block (real result) through the hybrid objective function, and then, the translation module may be trained based on the target loss value, and finally a translation model may be obtained. That is, the parameters of the translation module are adjusted based on the target loss value until the model converges to obtain a translation model.

[0079] It should be noted that the hybrid objective function combines the cross entropy loss and the BLEU score. The hybrid objective function can be expressed as: L = L_cross_entropy-λ*BLEU_score. Among them, the cross entropy loss (L_cross_entropy) is used to measure the difference between the predicted result of the translation module and the true result (target result), and the BLEU score (BLEU_score) can be used as a reward signal to evaluate the translation quality of the translation model. In this way, according to the hybrid objective function of the present invention, the translation quality of the translation model can be optimized by a reinforcement learning method.

[0080] In one implementation, the prediction result can be obtained by:

[0081] outputs=model(source_ids=source_ids.long(), source_mask=source_mask.long(),

[0082] target_ids=target_ids.long(),

[0083] target_mask=target_mask.long())

[0084] The cross entropy loss value is as follows: _,loss,num=outputs.

[0085] It should be understood that the cross entropy loss value takes into account the difference between the predicted probability distribution of the translation module for each position and the true probability distribution.

[0086] Furthermore, when adjusting the parameters of the translation module based on the target loss value, the gradient of the target loss value to the parameters of the translation module can be calculated based on back propagation, and gradient clipping can be performed to prevent gradient explosion. Then, the optimizer (AdamW optimizer) can be used to update the parameters of the translation module.

[0087] In some embodiments, the computing device 100 can use the assembly language translation model 300 generated by the present invention to convert multiple first architecture actual assembly code blocks into corresponding multiple second architecture actual assembly code blocks. Furthermore, a translation rule set can be established using multiple first architecture actual assembly code blocks and corresponding multiple second architecture actual assembly code blocks.

[0088] Specifically, first, a mapping relationship between multiple first architecture actual assembly code blocks and multiple second architecture actual assembly code blocks can be established. Then, by parameterizing the operands in each first architecture actual assembly code block and the corresponding second architecture actual assembly code block (for example, symbols such as reg0, reg1 can be used to replace specific register names, and symbols such as imm0, imm1 can be used to represent immediate numbers), each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block can be obtained. Furthermore, a translation rule set can be generated based on each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block.

[0089] It should be noted that the translation rule set includes a plurality of parameterized translation rules. The translation rule set generated according to the present invention can be used in a binary translation process. In the binary translation process, the first architecture assembly instruction can be translated into a corresponding second architecture assembly instruction based on the corresponding translation rule in the translation rule set.

[0090] Figure 4 Some translation rule examples according to the embodiments of the present invention are shown. Figure 4 The Guest in the table corresponds to the first architecture (x86 architecture), and the Host corresponds to the second architecture (ARM architecture). Figure 4 As shown, each translation rule includes a first architecture parameterized assembly code block and a corresponding second architecture parameterized assembly code block, and these translation rules show how to convert x86 architecture assembly instructions into corresponding ARM architecture assembly instructions.

[0091] It should be noted that the present invention utilizes the assembly language translation model 300 to generate the translation rule set, which can greatly reduce the burden of manually defining the translation rules and improve the flexibility and adaptability of binary translation. The translation rule set generated according to the present invention can improve the generalization ability of the translation rules through parameterization processing, and can improve the efficiency and quality of binary translation.

[0092] In some embodiments, a plurality of important translation rules that frequently appear in actual applications and have a greater impact on performance may be screened out from the translation rule set, and each important translation rule may be formally verified to ensure the correctness and reliability of the important translation rules.

[0093] Specifically, the computing device 100 can perform formal verification on each important translation rule by symbolic execution and constructing an equivalence verification formula to determine whether the states of the first assembly code and the second assembly code in the important translation rule are equivalent. To determine whether the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule are equivalent, so as to achieve formal verification. It should be noted that by performing formal verification on important translation rules, the correctness and reliability of important rules can be verified, and then hidden errors that may exist in important rules can be eliminated.

[0094] It should be noted that formal verification is a technique that uses mathematical methods to ensure the correctness of a program or system. For binary translation scenarios, formal verification helps verify the accuracy and completeness of translation rules.

[0095] Symbolic execution is a program analysis technique commonly used in software testing. It uses symbols instead of specific input values ​​to execute a program, thereby exploring multiple paths that the program may take at the same time, which enables symbolic execution to achieve comprehensive program coverage. In some embodiments of the present invention, equivalence can be verified by evaluating the symbolic execution results of registers, memory addresses, and branch conditions.

[0096] Specifically, in some embodiments, the computing device 100 can perform formal verification on each important translation rule in the following manner to determine whether the states of the first assembly code and the second assembly code in the important translation rule are equivalent: First, the first architecture parameterized assembly code block and the second architecture parameterized assembly code block in the important translation rule are respectively passed to the symbolic execution engine (angr). Subsequently, the symbolic execution engine (angr) can be used to symbolize the first state of the first architecture parameterized assembly code block (including the first register and the first memory address of the first architecture parameterized assembly code block) and the second state of the second architecture parameterized assembly code block (including the second register and the second memory address of the second architecture parameterized assembly code block) respectively, and obtain the first symbol value of the first architecture parameterized assembly code block and the second symbol value of the second architecture parameterized assembly code block. Then, symbolic execution can be performed based on the first symbol value of the first architecture parameterized assembly code block and the second symbol value of the second architecture parameterized assembly code block to obtain the first final state of the first architecture parameterized assembly code block and the second final state of the second architecture parameterized assembly code block. Next, the first register value and the first memory address value can be extracted from the first final state, and the second register value and the second memory address value can be extracted from the second final state, and an equivalence verification formula can be constructed based on the first register value, the first memory address value, the second register value, and the second memory address value. Finally, the equivalence verification formula can be solved using an SMT solver (e.g., Z3) to determine whether the first final state of the first architecture parameterized assembly code block is equivalent to the second final state of the second architecture parameterized assembly code block. Specifically, using an SMT solver (e.g., Z3) to solve the equivalence verification formula can determine whether the first final state of the first architecture parameterized assembly code block is always equivalent to the second final state of the second architecture parameterized assembly code block under all possible symbol values. If the first final state is equivalent to the second final state of the second architecture parameterized assembly code block, it is determined that the important translation rule is correct; otherwise, it is determined that the important translation rule is incorrect, and then the hidden errors that may exist in the important rule can be eliminated.

[0097] It should be noted that, in the above embodiments, formal verification can prove the correctness of important translation rules, thereby ensuring the accuracy of the translation results.

[0098] Figure 5 A schematic diagram of an assembly language translation device 500 provided according to an embodiment of the present invention is shown. The assembly language translation device 500 may be deployed in a computing device 100, and the assembly language translation device 500 may be configured to execute the deep learning-based assembly language translation method 200 of the present invention.

[0099] like Figure 5As shown, in an embodiment of the present invention, the assembly language translation device 500 includes a first training unit, a conversion unit, a second training unit, a generation unit, and a translation unit which are sequentially communicatively connected.

[0100] The first training unit is used to train the pre-training module to obtain a pre-training model.

[0101] The conversion unit may use the pre-trained model to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively.

[0102] The second training unit may train the translation module based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector, and the second architecture sample vector to obtain a translation model.

[0103] The generating unit may generate an assembly language translation model based on the pre-training model and the translation model.

[0104] The translation unit may utilize an assembly language translation model to convert the first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

[0105] It should be noted that the first training unit, the conversion unit, the second training unit, the generation unit, and the translation unit are respectively used to execute the aforementioned steps 210 to 250. Here, the specific execution logic of each unit can be found in the description of steps 210 to 250 in the method 200 above, which will not be repeated here.

[0106] According to the assembly language translation method 200 based on deep learning in the embodiment of the present invention, the pre-training module is first trained to obtain a pre-training model, and then the pre-training model is used to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into the first architecture sample vector and the second architecture sample vector, respectively, and then the translation module is trained to obtain a translation model. An assembly language translation model can be generated based on the pre-training model and the translation model. In this way, the assembly language translation model can be used to convert the actual assembly code block of the first architecture into the corresponding actual assembly code block of the second architecture. Based on this, the present invention can effectively represent and learn instruction-level semantics in the process of training and generating an assembly language translation model, solve the differences caused by cross-architecture heterogeneity and the problem of lack of training data, and can achieve more intelligent translation between different architecture assembly languages ​​by training and generating an assembly language translation model, which significantly improves the efficiency of cross-architecture assembly language translation.

[0107] Furthermore, the present invention adopts the Teacher Forcing training mechanism to train the translation module, which can balance the training efficiency and the generalization ability of the model; and, during the training process, a hybrid objective function combining the cross entropy loss and the BLEU score is used to calculate the loss, which can optimize the translation quality of the translation model.

[0108] In addition, in the actual translation process using the assembly language translation model, the use of the Beam Search algorithm can improve the translation quality.

[0109] In addition, the translation rule set generated according to the assembly language translation model of the present invention can greatly reduce the burden of manually defining translation rules and improve the flexibility and adaptability of binary translation. The translation rule set generated according to the present invention can improve the generalization ability of the translation rules after parameterization processing, and can improve the efficiency and quality of binary translation.

[0110] In addition, the embodiment of the present invention also discloses: A7, a method as described in any one of A1-A6, wherein the translation module is trained based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector, including: based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector, the translation module is trained using the Teacher Forcing training mechanism. A8, a method as described in any one of A1-A7, wherein the translation module is trained based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector and the second architecture sample vector to obtain a translation model, including: using the translation module to convert the first architecture sample vector into a corresponding second architecture prediction assembly code block; calculating the target loss value between the second architecture prediction assembly code block and the second architecture sample assembly code block through a mixed objective function; training the translation module based on the target loss value to obtain a translation model. A9. A method as described in any one of A1-A8, wherein the actual assembly code block of the first architecture is converted into the corresponding actual assembly code block of the second architecture by using the assembly language translation model, comprising: using the assembly language translation model and adopting the Beam Search algorithm to convert the actual assembly code block of the first architecture into the corresponding actual assembly code block of the second architecture. A10. A method as described in A9, wherein the assembly language translation model is used to convert the first architecture actual assembly code block into the corresponding second architecture actual assembly code block using the Beam Search algorithm, including: using the assembly language translation model, for the first architecture actual assembly code block, generating multiple candidate sequences at each time step t and retaining k optimal candidate sequences; wherein, at each time step, multiple new candidate sequences are generated based on each current optimal candidate sequence in the k current optimal candidate sequences, and the final score of each new candidate sequence is determined based on the basic translation probability score, length penalty term and coverage penalty term of each new candidate sequence; according to the final score of each new candidate sequence, k new optimal candidate sequences with the highest scores are selected from all new candidate sequences and retained until k final optimal candidate sequences are obtained, where k is an integer greater than or equal to 2; and the final optimal candidate sequence with the highest score is selected from the k final optimal candidate sequences as the second architecture actual assembly code block and output. A11. A method as described in any one of A1-A10, which further includes: using the assembly language translation model to convert multiple first architecture actual assembly code blocks into corresponding multiple second architecture actual assembly code blocks; and establishing a translation rule set based on the multiple first architecture actual assembly code blocks and the corresponding multiple second architecture actual assembly code blocks.A12. A method as described in A11, wherein a translation rule set is established based on multiple first architecture actual assembly code blocks and corresponding multiple second architecture actual assembly code blocks, including: establishing a mapping relationship between multiple first architecture actual assembly code blocks and multiple second architecture actual assembly code blocks; parameterizing the operands in each of the first architecture actual assembly code blocks and the corresponding second architecture actual assembly code blocks to obtain each first architecture parameterized assembly code block and the corresponding second architecture parameterized assembly code block; generating a translation rule set based on each of the first architecture parameterized assembly code blocks and the corresponding second architecture parameterized assembly code blocks. A13. A method as described in any one of A1-A12, wherein the first architecture is an x86 architecture and the second architecture is an ARM architecture. A14. A method as described in any one of A1-A13, wherein the pre-training module is an encoder of a seq2seq model and the translation module is a decoder of a seq2seq model.

[0111] The various techniques described herein may be implemented in combination with hardware or software, or a combination thereof. Thus, the method and apparatus of the present invention, or some aspects or parts of the method and apparatus of the present invention may be in the form of program codes (i.e., instructions) embedded in a tangible medium, such as a removable hard disk, a USB flash drive, a floppy disk, a CD-ROM, or any other machine-readable storage medium, wherein when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0112] In the case where the program code is executed on a programmable computer, the mobile terminal generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store the program code; the processor is configured to execute the assembly language translation method based on deep learning of the present invention according to the instructions in the program code stored in the memory.

[0113] By way of example and not limitation, readable media include readable storage media and communication media. Readable storage media stores information such as computer readable instructions, data structures, program modules or other data. Communication media generally embody computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and include any information transfer medium. Any combination of the above is also included within the scope of readable media.

[0114] In the description provided herein, algorithms and displays are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the examples of the present invention. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to implement the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of the present invention.

[0115] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0116] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0117] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0118] Unless otherwise specified, the use of ordinal numbers "first", "second", "third", etc. to describe common objects merely indicates that different instances of similar objects are involved and is not intended to imply that the objects so described must have a given order in time, space, order or in any other manner.

Claims

1. A deep learning-based assembly language translation method, executed in a computing device, comprising: Train the pre-training module to obtain a pre-training model; Using the pre-trained model, converting the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively; Based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector, and the second architecture sample vector, a translation module is trained to obtain a translation model; Based on the pre-trained model and the translation model, generating an assembly language translation model; The assembly language translation model is used to convert the first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

2. The method of claim 1, wherein: Using the assembly language translation model, converting the first architecture actual assembly code block into a corresponding second architecture actual assembly code block includes: Using a pre-trained model of the assembly language translation model, converting the first architecture actual assembly code block into a first architecture actual vector; The first architecture actual vector is converted into a corresponding second architecture actual assembly code block using the translation model of the assembly language translation model.

3. The method according to claim 1 or 2, wherein: Train the pre-training module to obtain a pre-training model, including: Acquire a plurality of binary programs, the plurality of binary programs comprising a first architecture binary program and a second architecture binary program; Disassembling the multiple binary programs to obtain corresponding first architecture original assembly codes and second architecture original assembly codes; Performing static analysis on the first architecture original assembly code and the second architecture original assembly code to extract data dependency flow and control flow from the first architecture original assembly code and the second architecture original assembly code; Based on the data dependency flow and control flow, the pre-training module is trained to obtain a pre-training model.

4. The method of claim 3, wherein: Based on the data dependency flow and control flow, the pre-training module is trained to obtain a pre-training model, including: Based on the data dependency flow and control flow, a masked language model prediction task and a next sentence prediction task are used to train the pre-training module to obtain a pre-training model.

5. The method according to any one of claims 1 to 4, wherein: Using the pre-trained model, converting the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively, including: Compile and generate corresponding first architecture binary files and second architecture binary files based on the source code files; Disassembling the first architecture binary file and the second architecture binary file respectively to obtain a plurality of first architecture sample assembly code blocks and a corresponding plurality of second architecture sample assembly code blocks in a predetermined format; Using the pre-trained model, each of the first architecture sample assembly code blocks and the corresponding second architecture sample assembly code blocks are converted into a first architecture sample vector and a second architecture sample vector, respectively.

6. The method according to any one of claims 1 to 5, wherein: Using the pre-trained model, converting the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively, including: Embed and position-code the first architecture sample assembly and the corresponding second architecture sample assembly code blocks to obtain a first architecture sample input representation and a second architecture sample input representation; A first architecture sample vector and a second architecture sample vector are extracted from the first architecture sample input representation and the second architecture sample input representation, respectively, by using a plurality of encoding layers of the pre-trained model.

7. An assembly language translation device, deployed in a computing device, comprising: A first training unit is adapted to train the pre-training module to obtain a pre-training model; a conversion unit, adapted to use the pre-trained model to convert the first architecture sample assembly code block and the corresponding second architecture sample assembly code block into a first architecture sample vector and a second architecture sample vector, respectively; A second training unit is adapted to train a translation module based on the first architecture sample assembly code block, the second architecture sample assembly code block, the first architecture sample vector, and the second architecture sample vector to obtain a translation model; A generating unit, adapted to generate an assembly language translation model based on the pre-trained model and the translation model; The translation unit is adapted to utilize the assembly language translation model to convert the first architecture actual assembly code block into a corresponding second architecture actual assembly code block.

8. A computing device comprising: at least one processor; and A memory storing program instructions, wherein the program instructions are configured to be processed by the at least one processor, and the program instructions include instructions for processing the method according to any one of claims 1 to 6.

9. A computer program product comprising a computer program / instructions, wherein: When the computer program / instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A readable storage medium storing program instructions, which, when read and processed by a computing device, enables the computing device to process the method according to any one of claims 1 to 6.

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