Coherency domain cache line state tracking

Abstract

Circuitry, systems, and methods are provided for an integrated circuit that includes an acceleration functional unit to provide hardware acceleration for a host device. The integrated circuit may also include an interface circuitry that includes a cache coherence bridge / agent that includes a device cache to resolve coherence with a host cache of the host device. The interface circuitry may also include a cache line state tracker circuitry to track the state of cache lines of the device cache and the host cache. The cache line state tracker circuitry provides insight into expected state changes based on the state of cache lines of the device cache and the host cache, and the type of operation being performed.

Description

Technical Field

[0001] The present disclosure relates to resource efficient circuitry for integrated circuits that can provide visibility into the state of a cache line. Background Art

[0002] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Therefore, it is understood that these statements should be understood from this perspective and not as admissions of prior art.

[0003] Memory is increasingly becoming the most expensive component in data centers and electronic devices, driving up the total cost of ownership (TCO). Efficient use of memory via memory pools and memory tiering is seen as the most promising way to optimize memory usage. With the advent of Compute Express Link (CXL) and / or other device / CPU-to-memory standards, a fundamental shift has occurred in data center architectures regarding the use of disaggregated memory tiered architectures as a means of reducing TCO. Memory tiered architectures can include pooled memory, heterogeneous memory tiers, and / or network-attached memory tiers, all of which allow multiple nodes to share memory, thereby achieving better TCO. Intelligent memory controllers that manage memory tiers are key components of this architecture. However, tiered memory controllers residing outside of a memory consistency domain may not be able to directly access consistency information in a consistency domain, making such deployments less practical and / or impossible. One mechanism to address this consistency domain issue may be to use operating system (OS) / virtual memory manager (VMM) / hypervisor technology to track page tables to record which pages have been accessed. However, this deployment may be inefficient when only a small number (e.g., a single) cache line of a page is modified because the entire page is marked as dirty. For example, the page size may be relatively large (eg, 4KB), and the page needs to be flushed when only a relatively small cache line of the page (eg, 64B) is modified. Such coarse-grained page-based tracking may be very inefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of a system including a first device and a second device coupled together using a link according to an embodiment of the present disclosure;

[0006] Figure 2is a block diagram of a system including a first device and a second device according to an embodiment of the present disclosure, wherein the second device includes a coherency domain cache line state tracker (CLST);

[0007] Figure 3 is a block diagram of the interaction between a CLST interface in a corresponding cache coherence bridge / agent and a corresponding CLST processing slice according to an embodiment of the present disclosure; and

[0008] Figure 4 is a data processing system according to an embodiment of the present disclosure that may be incorporated into a second device. DETAILED DESCRIPTION

[0009] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as with any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be appreciated that such development work can be complex and time-consuming, but it is still a routine task of design, fabrication, and manufacturing for a person of ordinary skill who benefits from the present disclosure.

[0010] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to indicate that there are one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. Additionally, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0011] As previously described, an intelligent memory controller outside a memory consistency domain can use access to consistency information in a consistency domain to provide efficient memory usage. For example, such an intelligent memory controller can use telemetry to understand page access patterns and changes in the consistency state of cache lines of a processor (e.g., CPU). A consistency domain cache line state tracker (CLST) can be used to track such information so that an intelligent hierarchical memory controller and / or near memory accelerator outside a consistency domain can monitor cache line state changes at a cache line granularity, so that actions such as page migration can be performed efficiently. As described above, CLST is capable of monitoring the modification, exclusive, shared, and invalid (MESI) state changes of all cache lines mapped to memory controlled / owned by a device implementing CLST. For example, the device can be a compute express link (CXL) type 2 device or other device including a general-purpose accelerator (e.g., GPU, ASIC, FPGA, etc.) to work with graphics double data rate (GDDR), high bandwidth memory (HBM), or other types of local memory. Therefore, a CXL type 2 device is capable of implementing a cache that can be seen by the host without using direct memory access (DMA) operations. Conversely, even though some memory may be kept secret from the processor, memory can be exposed to the host OS like standard memory. The interface of the device that implements CLST provides real-time (or near real-time) information of any state changes, enabling the device to monitor read and write access patterns and MESI state changes for caches in the processor and device. In addition, the interface supports tracking MESI state changes at cache line granularity. Additionally, the address range (e.g., read or write address) reflected on the CLST can be monitored. If the accelerator requests a consistency state change to enable a benefit, the accelerator can use CLST to have visibility into whether the state (and associated benefits) has occurred. If a subsequent state change disables the benefit, the CLST ensures that the accelerator is notified. If the benefit is still desired, this enables the accelerator to re-enable the benefit.

[0012] Considering the above situation, Figure 1A block diagram of a system 10 including a first device 12 and a second device 14 is shown. The first device 12 and the second device 14 may include a corresponding cache 16 and a cache 18. The first device 12 and the second device 14 may be coupled together using a link 20. The link 20 may be any link type suitable for connecting the first device 12 to the second device 14. For example, the link type may be a peripheral component interconnect express (PCIe) link or other suitable link type. Additionally or alternatively, the link 20 may utilize one or more protocols built on the link type. For example, the link type may include a type that includes at least one physical layer (PHY) technology. These one or more protocols may include one or more standards to be used via the link type. For example, one or more protocols may include a computing express link (CXL) or other suitable connection types that may be used on the link 20.

[0013] In many link types, the first device 12 may not have visibility into the cache 18, the MESI state of the cache 18, and / or the operations to be performed / upcoming operations by the second device 14. Similarly, the second device 14 may not have visibility into the cache 16, the MESI state of the cache 16, and / or the operations to be performed / upcoming operations by the first device 12. Additionally or alternatively, as previously described, the OS / VMM / hypervisor may track whether pages across the link are dirty. However, such a mechanism includes a lack of granularity / predictability, which may result in inefficient use of the consistency mechanism between the first device 12 and the second device 14, as an entire page (e.g., 4kB) of the cache 16 or cache 18 may be cleaned when only a single cache line (e.g., 64B) may need to be cleaned / refreshed. To address this consistency efficiency issue, a cache line state tracker (CLST) 22 may be included in at least one device (e.g., the second device 14). As previously described, the CLST 22 provides coherence state change information to the circuit system 24, which may be outside the coherence domain of the first device 12. For example, the circuit system 24 may be an accelerated function unit (AFU) that uses a programmable structure to assist the first device 12 (e.g., a processor) in completing functions by acting as an accelerator for the first device 12. Additionally or alternatively, the circuit system 24 may include any other suitable circuit system, such as an application specific integrated circuit (ASIC), a coprocessor (e.g., a graphics processing unit (GPU)), a field programmable gate array (FPGA), and / or other circuit systems. This allows the second device 14 (e.g., the AFU) to build a custom directory or custom tracking logic, thereby enabling the second device 14 to function as an intelligent memory controller. The second device 14 is able to determine the state of cache lines in both cache 16 and cache 18, and is thereby able to take actions based on the state of cache lines in both cache 16 and cache 18.

[0014] Figure 2 is a block diagram of system 30. System 30 may be a specific embodiment of system 10. However, other embodiments may also be consistent with the teachings herein. Figure 2As shown, system 30 includes a processor 32 having a cache 34. Processor 32 is coupled to device 36 via link 38. For example, processor 32 may be an embodiment of first device 12 of system 10, and cache 34 may be an embodiment of cache 16 of system 10. Device 36 may be an embodiment of second device 16 of system 10. For example, device 36 may be an FPGA. Additionally or alternatively, device 36 may be a device that integrates an application specific integrated circuit (ASIC) with an FPGA and / or other programmable logic device, may be a dedicated ASIC device without an integrated FPGA, may include any suitable accelerator device (GPU), and / or any other suitable device that may be coupled to processor 32 via link 38 and may benefit from access to cache 34. Link 38 may be Figure 1 Any embodiment of link 20.

[0015] The device 36 also includes an interface circuit system 40. For example, the interface circuit system 40 may include an ASIC and / or other circuit system to at least partially implement an interface between the device 36 and the processor 32. For example, the interface circuit system 40 can be used to implement communications based on the CXL protocol using one or more cache consistency bridges / agents 42. The cache consistency bridge / agent 42 is an agent on the device 36 that is responsible for resolving consistency related to the device cache. Specifically, the cache consistency bridge / agent 42 may include its own cache 43, which may maintain consistency with the cache 34. In some embodiments, each device 36 may have multiple interface circuit systems 40. Additionally or alternatively, multiple devices 36 may be included in a single system.

[0016] As previously described, device 36 includes an accelerated function unit (AFU) 44. For example, AFU 44 may be included as an accelerator (e.g., FPGA, ASIC, GPU, programmable logic device, etc.) that uses logic implemented in circuit system 46 to perform functions to accelerate functions from processor 32. As previously described, AFU 44 may be an accelerator included in device 36 based on device 36 being a CXL type 2 device. AFU 44 includes logic implemented in circuit system 46. The logic implemented in circuit system 46 may include logic implemented in a programmable structure and / or hardware circuit system. The logic implemented in circuit system 46 may be used to issue a request on interface circuit system 40.

[0017] As previously described, the device 36 also includes a cache line state tracker (CLST) 50. In some embodiments, there may be multiple cache coherence bridges / agents 42, each coupled to the same CLST 50. In other words, each cache coherence bridge / agent 42 may be coupled to a slice of the CLST 50. Additionally or alternatively, there may be multiple cache coherence bridges / agents 42, multiple cache coherence bridges / agents 42 coupled to their own CLST 50.

[0018] The device 36 may also include an AFU tracking circuitry 52 that interfaces with the CLST 50 using an appropriate interface type (e.g., AXI4 ST or other interface) to provide updates to the AFU 44 and / or logic implemented in the circuitry 46. The AFU tracking circuitry 52 may reference custom directories that track the state of cache lines to decide which page to migrate and when to migrate the page. For example, the directory may be proprietary and may be built to serve a policy associated with cache line tracking for a customer, user, profile, etc. The update may indicate a change in the cache 34, such as a change in a host / HDM address. The AFU tracking circuitry 52 may be implemented using an ASIC and / or implemented using a programmable fabric.

[0019] The device 36 may also include a memory 54 that may be used by the device 36 and / or the host (e.g., the processor 32). For example, if the device 36 is a CXL type 2 device, the memory 54 may be a host management device memory (HDM). In some embodiments, the device 36 may include another interface 56 to connect to other devices / networks. For example, the interface 56 may be a high-speed serial interface subsystem that couples the device 36 to a link 58 to a network.

[0020] It will be appreciated that processor 32 may be located in host domain 60 with inherent access to cache 34. Interface circuitry 40 is located in coherent domain 62 that maintains coherence with cache 34. For example, cache 34 may be coherent with cache 43 using an appropriate protocol (CXL) over link 38. Cache 43 may have a MESI state and use a protocol (e.g., CXL) to bring other information needed / requested by the host to provide insight. For example, if ownership is sought, this other information may clarify whether ownership can be transferred correctly. Non-coherent domain 64 may typically not have access or visibility to the state of one or more caches (e.g., cache 34). However, using CLST 50 and AFU tracking circuitry 52, portions of non-coherent domain 64 may be able to have visibility into the state of one or more caches.

[0021] AFU requests may cause state changes in cache 34 and / or the cache of device 36. Host cache (CXL.$) snoops and host memory (CXL.M) requests may cause state changes in the cache of device 36 and may imply state changes in the host cache (e.g., cache 34). If any of these requests cause a state change, cache coherency bridge / agent 42 will issue an update on CLST 50. The CLST 50 update may provide a cache line address, the cache original state and / or final state of the cache of device 36, the original state and / or final state of cache 34, and the factor (e.g., source) that caused the state change.

[0022] Each cache coherence bridge / agent 42 provides a connection 65 between a dedicated port of the corresponding cache coherence bridge / agent 42 and a corresponding port of the CLST 50. In some embodiments, each port has one interface for device (HDM) address updates and one interface for host address updates. In some embodiments, the connection 65 can issue one CLST update per clock cycle.

[0023] If the CLST 50 streams information that the AFU 44 cannot absorb (e.g., because the buffer / register is full), the AFU 44 may notify the CLST 50 (or fail to acknowledge receipt of the streamed information). The CLST 50 may send backpressure to the cache coherence bridge / agent 42 and / or the host via the link 38 to prevent loss of the sent information. For example, the connection 65 / interface may provide a backpressure input to control when new CLST updates are issued from the corresponding cache coherence bridge / agent 42. For example, Figure 3A block diagram of an interaction 70 between a CLST interface 72 in a corresponding cache coherence bridge / agent 42 and a corresponding CLST processing slice 74 is shown, wherein the corresponding CLST processing slice 74 corresponds to the CLST interface 72 in the CLST 50. As shown, the CLST interface 72 sends a first signal 76 (Ip2cafu_axistNd*) to the CLST processing slice 74. The first signal 76 can be any available signal for the CLST interface 72. For example, the first signal 76 can include a stream data valid indicator that indicates the validity of the cached stream data of the device 36, a stream data indicator, a stream data byte indicator, a stream data boundary indicator, a stream data identifier, stream data routing information, stream data user information, and / or any other suitable signal type for the CLST interface 72. The various signals can be sent together in a packet and / or sent separately, and can have an appropriate bit length. For example, the validity indicator can be a flag, and the stream data indicator can have multiple (e.g., 8, 16, 32, 72, etc.) bits. Similarly, a single indicator can include multiple information. For example, the stream data indicator may include a first number of bits (e.g., 52) indicating a cache line address for device 36 and / or processor 32, a second number of bits (e.g., 4) indicating an original state of the cache of device 36, a third number of bits (e.g., 4) indicating a final state of the cache of device 36 after a change, a fourth number of bits (e.g., 4) indicating the original state of the cache of processor 32, a fifth number of bits (e.g., 4) indicating a final state of the cache of processor 32, a sixth number of bits (e.g., 1) indicating a source of the state change (e.g., processor 32 or device 36), and / or other bits carrying information about the state change.

[0024] The CLST processing slice 74 responds with a first response signal 78 (cafu2ip_axistNd_tready) or a ready signal indicating whether the CLST processing slice 74 is ready to accept streaming data. If the CLST interface 72 does not receive the ready signal, the CLST interface 72 can retain the data in the buffer via the link 38 and / or instruct the processor 32 to delay sending more data until the CLST processing slice 74 is ready to receive more streaming information. At this point, any buffered data can begin to be published from the CLST interface 72 to the CLST processing slice 74. Additionally or alternatively, when the CLST processing slice 74 is not yet ready to process more streaming data, the CLST processing slice 74 can send a not ready signal (instead of or in addition to the cafu2ip_axistNd_tready signal) to cause the CLST interface 72 to retain the data until the CLST processing slice 74 is ready.

[0025] As shown, the CLST interface 72 sends a second signal 80 (Ip2cafu_axistNh*) to the CLST processing slice 74. The second signal 80 can be any available signal for the CLST interface 72. For example, the first signal 76 may include a stream data valid indicator that indicates the validity of the stream data for the cache of the host (processor 32), a stream data indicator, a stream data byte indicator, a stream data boundary indicator, a stream data identifier, stream data routing information, stream data user information, and / or any other suitable signal type for the CLST interface 72. The various signals can be sent together in a packet and / or sent separately, and can have an appropriate bit length. For example, the validity indicator can be a flag, and the stream data indicator can have multiple (e.g., 8, 16, 32, 72, etc.) bits. Similarly, a single indicator can include various information. For example, the stream data indicator may include a first number of bits (e.g., 52) indicating a cache line address for device 36 and / or processor 32, a second number of bits (e.g., 4) indicating an original state of the cache of processor 32, a third number of bits (e.g., 4) indicating a final state of the cache of processor 32 after a change, a fourth number of bits (e.g., 4) indicating the original state of the cache of processor 32, a fifth number of bits (e.g., 4) indicating a final state of the cache of processor 32, a sixth number of bits (e.g., 1) indicating a source of the state change (e.g., processor 32 or device 36), and / or other bits carrying information about the state change.

[0026] The CLST processing slice 74 responds with a second response signal 82 (cafu2ip_axistNh_tready) or a ready signal indicating whether it is ready to accept streaming data. If the CLST interface 72 does not receive the ready signal, the CLST interface 72 can instruct the processor 32 via the link 38 to delay sending more data until the CLST processing slice 74 is ready to receive more streaming information. Additionally or alternatively, the CLST processing slice 74 can send a not ready signal (instead of or in addition to the cafu2ip_axistNh_tready signal) when the CLST processing slice 74 is not yet ready to process more streaming data.

[0027] Table 1 below describes that CLST 50 can report potential state changes based on the corresponding change source operations that cause the state transition. Table 1 includes "M" (for the modified state, indicating that the cache line is "dirty" or has changed since the last cache), "E" (for the exclusive state, indicating that the cache line is exclusive), "S" (for the shared state, indicating that the cache line is stored in at least two caches), and "I" (for the invalid state, indicating that the cache line is invalid / unused). Since the host cache state may not or may not need to be known, Table 1 includes "unknown" for this situation. In some cases, the host cache state can be one of two states, such as invalid or shared ("I / S"), or invalid or modified ("I / M"), or exclusive or modified ("E / M"). Table 1 includes "I / S", "E / M" and "I / M" and similar labels to show these states. In some embodiments of these dual possible states, the host (processor 32) can decide whether to keep or discard the cache line. Additionally, Table 1 is an illustrative and non-exclusive listing of the state changes tracked in CLST 50 based on the original / final states of the operations that resulted in those changes.

[0028]

[0029]

[0030] Table 1. Examples of CLST state changes

[0031] As used in Table 1, the use of "," between operations can indicate that two operations are performed or only one operation is performed. Additionally, the entries of Table 1 may include additional distinguishing factors for different operations, such as different meta-field values, indicating whether the host has an exclusive copy, whether it has a shared copy, whether it has a non-cacheable current value (NO-OP) with or without invalidation, whether it has ownership of a cache line with no data, whether it is requesting the device to invalidate its cache, whether it is deleting its cache from an E or S state in an I state, and / or whether it has other information that can assist CLST 50 in determining what final state the operation will result in.

[0032] Device 36 may be a component included in a data processing system, such as Figure 4 . The data processing system 100 shown in FIG. The data processing system 100 may include a device 36, a host processor (processor 32), a memory and / or storage circuit system 102, and a network interface 104. The data processing system 100 may include more or fewer components (e.g., an electronic display, a user interface structure, an application-specific integrated circuit (ASIC)). The processor 32 may include any of the aforementioned processors, which may manage data processing requests for the data processing system 100 (e.g., perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, encrypted digital currency operations, etc.). The memory and / or storage circuit system 102 may include a random access memory (RAM), a read-only memory (ROM), one or more hard disk drives, flash memory, etc. The memory and / or storage circuit system 102 may store data to be processed by the data processing system 100. In some cases, the memory and / or storage circuit system 102 may also store a configuration program (e.g., a bitstream, a mapping function) for programming the device 36. Network interface 104 may allow data processing system 100 to communicate with other electronic devices. Data processing system 100 may include several different packages, or may be contained within a single package on a single package substrate. For example, components of data processing system 100 may be located on several different packages at one location (e.g., a data center) or at multiple locations. For example, components of data processing system 100 may be located in separate geographic locations or regions, such as cities, states, or countries.

[0033] The data processing system 100 may be part of a data center that processes a variety of different requests. For example, the data processing system 100 may receive data processing requests via the network interface 104 to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, digital signal processing, or other specialized tasks.

[0034] Although the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the accompanying drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. The present disclosure is intended to encompass all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0035] The techniques presented and claimed herein are cited and applied to material objects and specific examples of a practical nature that significantly improve the art, and therefore, they are not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "a means for [performing] [the function] ..." or "a step for [performing] [the function] ...", it is intended that such element be interpreted in accordance with 35 U.S.C. § 112(f). However, for any claim containing an element designated in any other manner, it is intended that such element not be interpreted in accordance with 35 U.S.C. § 112(f).

[0036] Example Embodiments

[0037] Example embodiments 1. An integrated circuit device includes: an acceleration function unit that provides hardware acceleration for a host device; and an interface circuit system, including: a cache coherence bridge / agent, including a device cache, for resolving coherence with a host cache of the host device. The interface circuit system also includes: a cache line state tracker circuit system for tracking the state of cache lines of the device cache and the host cache, wherein the cache line state tracker circuit system is used to provide insight into expected state changes based on the state of the cache lines of the device cache and the host cache, and the type of operation performed.

[0038] Example Embodiment 2. The integrated circuit device of Example Embodiment 1, wherein the type of operation comprises a memory operation performed by a host device.

[0039] Example embodiment 3. The integrated circuit device of example embodiment 1, wherein the type of operation comprises a memory operation performed by the integrated circuit device.

[0040] Example Embodiment 4. The integrated circuit device of Example Embodiment 1, wherein the type of operation comprises a state change of a host cache.

[0041] Example embodiment 5. The integrated circuit device of example embodiment 1, wherein tracking the state of the cache line comprises tracking an original state of the device cache and tracking a final state of the device cache.

[0042] Example embodiment 6. The integrated circuit device of example embodiment 5, wherein tracking the state of the cache line comprises: using compute fast link cache operations to track an original state of the host cache and tracking a final state of the host cache.

[0043] Example embodiment 7. The integrated circuit device of example embodiment 1, wherein the cache line state tracker circuitry is to track the state of the device cache and the host cache at a cache line by cache line granularity.

[0044] Example Embodiment 8. The integrated circuit device according to Example Embodiment 1, wherein the acceleration function unit comprises a programmable logic device having a programmable structure.

[0045] Example embodiment 9. The integrated circuit device of example embodiment 8, wherein the acceleration functional unit comprises an acceleration functional unit trace implemented in a programmable structure of a programmable logic device.

[0046] Example embodiment 10. An integrated circuit device according to example embodiment 9, wherein the acceleration functional unit tracking is used to interface with the cache line status tracker circuit system and includes a custom directory that tracks the status of the cache line to decide which page to migrate and when to migrate the page.

[0047] Example embodiment 11. The integrated circuit device according to example embodiment 1, comprising a memory.

[0048] Example embodiment 12. The integrated circuit device of example embodiment 11, comprising a compute fast link type 2 device that exposes memory to a host device using compute fast link memory operations.

[0049] Example embodiment 13. An integrated circuit device includes a first portion in a first consistency domain, including an acceleration function unit that provides hardware acceleration for a host device, and a memory for storing data. The integrated circuit device also includes a second portion in a second consistency domain that is consistent with the host device. The second portion includes: an interface circuit system, the interface circuit system including: a plurality of cache consistency agents, including a plurality of device caches, for resolving consistency with one or more host caches of the host device; and a plurality of cache line state tracker circuit systems for tracking the states of cache lines of the plurality of device caches and the one or more host caches, wherein the plurality of cache line state tracker circuit systems are used to provide a prediction of a final state based on the original states of the cache lines of the plurality of device caches and the one or more host caches, and the type of operation being performed.

[0050] Example embodiment 14. The integrated circuit device of example embodiment 13, wherein the interface circuitry includes a compute fast link interface to enable the first coherency domain to have visibility into the status of the plurality of device caches or the one or more host caches.

[0051] Example Embodiment 15. The integrated circuit device according to Example Embodiment 13, wherein the first portion includes a network interface to enable the acceleration function unit to send or receive data via a network.

[0052] Example embodiment 16. An integrated circuit device according to example embodiment 14, wherein each of the multiple cache line state tracker circuit systems is configured to apply reverse pressure to a corresponding cache consistency agent in the multiple cache consistency agents to control when each of the multiple cache line state tracker circuit systems is updated.

[0053] Example embodiment 17. The integrated circuit device of example embodiment 16, wherein the back pressure comprises a ready or not ready signal indicating that the corresponding cache line state tracker circuitry is not ready to receive additional data in response to a previous signal.

[0054] Example embodiment 18. The integrated circuit device according to example embodiment 17, wherein the previous signal includes a validity of a stream data signal, a stream data indicator signal, a stream data byte indicator signal, a stream data boundary indicator signal, a stream data identifier signal, a stream data routing information signal, or a stream data user information signal.

[0055] Example embodiment 19. A programmable logic device, comprising: an interface circuit system, the interface circuit system comprising: a cache consistency bridge, the cache consistency bridge including a device cache, the cache consistency bridge is used to maintain consistency between the device cache and the host cache of the host device using a communication protocol with the host device through a link; and a cache line state tracker, the cache line state tracker is used to track the original state and final state of the host cache and the device cache based on operations performed by the host device or the programmable logic device. The programmable logic device also includes an acceleration function unit, which is used to provide hardware acceleration functions for the host device. The acceleration function unit includes: a logic circuit system for implementing the hardware acceleration function in the programmable structure of the acceleration function unit; and an acceleration function unit tracking, which is implemented in the programmable structure of the programmable logic device and is used to engage with the cache line state tracker to determine whether to migrate cached pages. The programmable logic device also includes a memory, which is exposed to the host device as a host-managed device memory for hardware acceleration functions.

[0056] Example embodiment 20. The programmable logic device of example embodiment 19, wherein the communication protocol comprises a compute fast link protocol that exposes the memory to the host device using compute fast link memory operations.

Claims

1. An integrated circuit device, comprising: An acceleration function unit, used to provide hardware acceleration for a host device; Interface circuit system, comprising: a cache coherency bridge / proxy including a device cache for resolving coherency with a host cache of said host device; and A cache line state tracker circuit system is used to track the state of cache lines of the device cache and the host cache, wherein the cache line state tracker circuit system is used to provide insight into expected state changes based on the state of the cache lines of the device cache and the host cache, and the type of operation performed.

2. The integrated circuit device according to claim 1, wherein: The type of operation includes a memory operation performed by the host device.

3. The integrated circuit device according to claim 1, wherein: The type of operation includes a memory operation performed by the integrated circuit device.

4. The integrated circuit device according to claim 1, wherein: The type of operation includes a state change of the host cache.

5. The integrated circuit device according to claim 1, wherein: Tracking the state of the cache line includes tracking an original state of the device cache and tracking a final state of the device cache.

6. The integrated circuit device according to claim 5, wherein: Tracking the state of the cache line includes tracking an original state of the host cache using compute fast link cache operations and tracking a final state of the host cache.

7. The integrated circuit device according to any one of claims 1 to 6, wherein: The cache line state tracker circuitry is for tracking the state of the device cache and the host cache at a cache line by cache line granularity.

8. The integrated circuit device according to any one of claims 1 to 6, wherein: The acceleration function unit includes a programmable logic device having a programmable structure.

9. The integrated circuit device according to claim 8, wherein: The acceleration functional unit includes an acceleration functional unit trace implemented in a programmable structure of the programmable logic device.

10. The integrated circuit device according to claim 9, wherein: The acceleration functional unit tracks for interfacing with the cache line state tracker circuitry and includes a custom directory that tracks the state of the cache line to decide which page to migrate and when to migrate the page.

11. An integrated circuit device according to any one of claims 1 to 6, comprising a memory.

12. The integrated circuit device of claim 11, comprising a compute fast link type 2 device that exposes the memory to the host device using compute fast link memory operations.

13. An integrated circuit device comprising: The first part of the first consistency domain includes: An acceleration function unit, used to provide hardware acceleration for a host device; as well as A memory for storing data; and The second part in the second consistency domain consistent with the host device includes: An interface circuit system, comprising: a plurality of cache coherence agents, including a plurality of device caches, for resolving coherence with one or more host caches of the host device; and and a plurality of cache line state tracker circuit systems for tracking states of cache lines of the plurality of device caches and the one or more host caches, wherein the plurality of cache line state tracker circuit systems are configured to provide a prediction of a final state based on an original state of the cache lines of the plurality of device caches and the one or more host caches and a type of operation being performed.

14. The integrated circuit device according to claim 13, wherein: The interface circuitry includes a computing fast link interface to enable the first coherency domain to have visibility into a state of the plurality of device caches or the one or more host caches.

15. The integrated circuit device of claim 13, wherein: The first part includes a network interface to enable the acceleration function unit to send or receive data via a network.

16. The integrated circuit device according to any one of claims 13 to 15, wherein: Each of the plurality of cache line state tracker circuitry is configured to apply back pressure to a corresponding cache coherence agent of the plurality of cache coherence agents to control when each of the plurality of cache line state tracker circuitry is updated.

17. The integrated circuit device of claim 16, wherein: Back pressure includes a ready or not ready signal indicating that the corresponding cache line state tracker circuitry is not ready to receive additional data in response to a previous signal.

18. The integrated circuit device of claim 17, wherein: The previous signal includes a validity of a stream data signal, a stream data indicator signal, a stream data byte indicator signal, a stream data boundary indicator signal, a stream data identifier signal, a stream data routing information signal, or a stream data user information signal.

19. A programmable logic device comprising: An interface circuit system, comprising: a cache coherence bridge including a device cache, the cache coherence bridge being configured to maintain coherence of the device cache with a host cache of the host device using a communication protocol with the host device over a link; and a cache line state tracker to track an original state and a final state of the host cache and the device cache based on operations performed by the host device or the programmable logic device; An acceleration function unit, used to provide a hardware acceleration function for the host device, and comprising: A logic circuit system for implementing the hardware acceleration function in the programmable structure of the acceleration function unit; and an acceleration functional unit tracking implemented in the programmable structure of the programmable logic device and used to interface with the cache line status tracker to determine whether to migrate a cached page; and A memory is exposed to the host device as host managed device memory for the hardware acceleration function.

20. The programmable logic device according to claim 19, wherein: The communication protocol includes a compute fast link protocol that exposes the memory to the host device using compute fast link memory operations.

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