Method and electronic device for cache management in a memory device

Abstract

A method, an electronic device, and an electronic system for cache management in a memory device are disclosed. The electronic system may include: a memory device, including a memory medium and a storage device medium, wherein the memory device is configured to: send access information, receive address information, and fill the memory medium with data from the storage device medium using the address information; and a training device, including one or more circuits, wherein the one or more circuits are configured to: receive access information from the memory device, determine address information using the access information and application weights, and send the address information to the memory device. The one or more circuits may also be configured to: send trajectory information to a training system; receive a weight set from the training system, wherein the weight set is based on the trajectory information; and modify the application weight based on the weight set.

Description

[0001] This application claims priority to and the benefit of U.S. Patent Application No. 63 / 541,774 filed on September 29, 2023 and U.S. Patent Application No. 18 / 749,563 filed on June 20, 2024, which are incorporated by reference. Technical Field

[0002] The present disclosure relates generally to memory devices, and more particularly to methods, electronic devices, and electronic systems for cache management in memory devices. Background Art

[0003] The memory device may include a memory medium and a storage device medium. In response to receiving a load request (e.g., a memory access request), the memory device may check the memory medium for data corresponding to the load request. In response to a cache hit (e.g., finding the data on the memory medium), the data may be returned from the memory medium. In response to a cache miss (e.g., not finding the data on the memory medium), the memory device may retrieve a region of memory including the requested data from the storage device medium.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] In some aspects, the technology described herein relates to a method, the method comprising: receiving access information for an application from a memory device; and determining address information using the access information and an application weight. In some aspects, the application weight corresponds to a usage rate of the application. In some aspects, the access information includes at least one of one or more address and timestamp information. In some aspects, the method further comprises sending the address information to the memory device. In some aspects, the method further comprises filtering entries of storage requests from the access information. In some aspects, the step of sending the address information comprises: determining an available size of a memory medium, and returning the address information based on the available size of the memory medium. In some aspects, the method further comprises: sending trajectory information to a training system, wherein the trajectory information corresponds to an operation of the application; receiving a weight set from the training system, wherein the weight set is based on the trajectory information; and modifying the application weight based on the weight set. In some aspects, the access information is first access information; wherein the trajectory information includes second access information. In some aspects, the trajectory information includes loading information of the application.

[0006] In some aspects, the technology described herein relates to an apparatus comprising: a memory medium; a storage medium; and one or more circuits configured to perform one or more operations, the one or more operations comprising: sending access information; receiving address information based on the access information; and filling the memory medium with data from the storage device medium using the address information. In some aspects, the access information includes access data for the memory medium and the application on the storage device medium. In some aspects, the address information corresponds to the application on the host device.

[0007] In some aspects, the technology described herein relates to a system, the system comprising: a memory device, including a memory medium and a storage device medium, wherein the memory device is configured to perform one or more operations, the one or more operations comprising: sending access information, receiving address information, and filling the memory medium with data from the storage device medium using the address information; and a device, including one or more circuits, wherein the one or more circuits are configured to perform one or more operations, the one or more operations comprising: receiving access information from the memory device, determining address information using the access information and application weights, and sending the address information to the memory device. In some aspects, the application weight corresponds to a usage rate of the application. In some aspects, the access information includes at least one of one or more addresses and timestamp information. In some aspects, the one or more circuits are further configured to perform one or more operations including modifying the access information. In some aspects, the process of modifying the access information includes filtering entries of storage requests from the access information. In some aspects, the process of sending the address information includes determining an available size of the memory medium, and returning the address information based on the available size of the memory medium. In some aspects, the one or more circuits are further configured to perform one or more operations, the one or more operations comprising: sending the trajectory information to the training system; receiving a weight set from the training system, wherein the weight set is based on the trajectory information; and modifying the application weight based on the weight set. In some aspects, the access information is the first access information; wherein the trajectory information includes the second access information. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings are not necessarily drawn to scale, and throughout the drawings, for the purpose of illustration, elements of similar structure or function may generally be represented by the same reference numerals or portions thereof. The drawings are intended only to facilitate the description of the various embodiments described herein. The drawings do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims. In order to prevent the drawings from becoming obscure, not all components, connections, etc. may be shown, and not all components may have reference numerals. However, the mode of component configuration may be easily clear from the drawings. The drawings, together with the specification, illustrate example embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0009] Figure 1 Embodiments of memory device schemes according to disclosed example embodiments are shown.

[0010] Figure 2A Another embodiment of a memory device scheme according to a disclosed example embodiment is shown.

[0011] Figure 2B Another embodiment of a memory device scheme according to a disclosed example embodiment is shown.

[0012] Figure 3 An example of a cache management process according to a disclosed example embodiment is shown.

[0013] Figure 4 An example of preparing a training input workload in a target system according to a disclosed example embodiment is shown.

[0014] Figure 5 An example of training in a training server according to the disclosed example embodiments is shown.

[0015] Figure 6 A flow chart illustrating a method for managing cache in a memory device according to a disclosed example embodiment.

[0016] Figure 7 An example of managing a cache in a memory device according to a disclosed example embodiment is shown.

[0017] Figure 8 A flow chart illustrating an example process of populating a cache using a training server according to an example embodiment of the disclosure. DETAILED DESCRIPTION

[0018] In some embodiments, in response to receiving a load request, the memory device may check the memory medium for data corresponding to the load request. In some embodiments, in response to a cache hit (e.g., the data is found on the memory medium), the data may be returned from the memory medium. In response to a cache miss (e.g., the data is not found on the memory medium), the memory device may retrieve a region of memory including the requested data from the storage device medium, copy the data from the region of memory to the memory medium, and return the data from the memory medium.

[0019] Typically, retrieving data from a memory medium can be performed faster than retrieving data from a storage device medium. In order to improve the performance of the memory device, in some embodiments, in anticipation of future requests, data can be copied to the memory medium to increase the cache hit rate. However, based on the cache management policy of the memory device, loading data to the memory medium may not be optimal for a particular application. Therefore, in some embodiments, by modifying the cache management policy using artificial intelligence (AI), the memory medium can be populated in a manner that allows more cache hits relative to other cache management policies.

[0020] For example, according to the disclosed embodiments, a training server may receive runtime trace data of an application from a host (e.g., a target system) (e.g., addresses, timestamps, and / or metadata for application workloads from a memory device). In some embodiments, the training server may calculate a weight of the application for the target system using the runtime trace data. In some embodiments, the target system may receive the calculated weight and infer a memory address to be loaded from a storage device medium to a memory medium based on the weight and log data from the memory device (e.g., addresses, timestamps, and / or metadata for applications from the memory device).

[0021] The present disclosure includes many aspects related to the device with memory configuration and storage device configuration. The aspects disclosed here can have independent utility and can be realized separately, and not each embodiment can utilize each aspect. In addition, these aspects can also be realized in various combinations in which some of these combinations can amplify some benefits in the independent aspects in a collaborative manner.

[0022] For purposes of illustration, some embodiments may be described in the context of certain specific implementation details, such as devices implemented as memory devices that may use specific interfaces, protocols, etc. However, the disclosed aspects are not limited to these or any other implementation details.

[0023] Figure 1 Embodiments of memory device schemes according to disclosed example embodiments are shown. Figure 1 The embodiment shown in may include one or more host devices 100 and one or more memory devices 150 configured to communicate using one or more communication connections 110 .

[0024] In some embodiments, the host device 100 may be implemented with any component or combination of components that may utilize one or more features of the memory device 150. For example, the host may be implemented with one or more of a server, a storage node, a computing node, a central processing unit (CPU), a workstation, a personal computer, a tablet computer, a smart phone, etc., or a plurality and / or combination thereof.

[0025] In some embodiments, the memory device 150 may include a communication interface 130, a memory 180 (some or all of which may be referred to as device memory), one or more computing resources 170 (which may also be referred to as computing resources), a device controller 160, and / or a device functional circuit 190. In some embodiments, the device controller 160 may control the overall operation of the memory device 150, including any of the operations, features, etc. described herein. For example, in some embodiments, the device controller 160 may parse, process, call, etc., a command received from the host device 100.

[0026] In some embodiments, the device function circuit 190 may include any hardware for implementing the main functions of the memory device 150. For example, the device function circuit 190 may include a storage device medium (such as a magnetic medium (for example, if the memory device 150 is implemented as a hard disk drive (HDD) or a tape drive), a solid-state medium (for example, one or more flash memory devices), an optical medium, etc.). For example, in some embodiments, the memory device may be implemented at least in part as a solid-state drive (SSD) based on NAND flash memory, a persistent memory (PMEM) (such as a cross-grid non-volatile memory), a memory with a body resistance change, a phase change memory (PCM), or any combination thereof. In some embodiments, the device controller 160 may include a media translation layer (such as a flash translation layer (FTL)) for interfacing with one or more flash memory devices. In some embodiments, the memory device 150 may be implemented as a computational storage driver, a computational storage processor (CSP), and / or a computational storage array (CSA).

[0027] As another example, if the memory device 150 is implemented as an accelerator, the device functional circuitry 190 may include one or more accelerator circuits, memory circuits, and the like.

[0028] In some embodiments, the computing resources 170 may be implemented with any component or combination of components that can perform operations on data that can be received, stored, and / or generated at the memory device 150. Examples of computing engines may include combinatorial logic, sequential logic, timers, counters, registers, state machines, complex programmable logic devices (CPLDs), FPGAs, application specific integrated circuits (ASICs), embedded processors, microcontrollers, CPUs (such as complex instruction set computer (CISC) processors (e.g., x86 processors) and / or reduced instruction set computer (RISC) processors (such as ARM processors)), graphics processing units (GPUs), data processing units (DPUs), neural processing units (NPUs), tensor processing units (TPUs), etc.), or combinations thereof.

[0029] In some embodiments, memory 180 may be used, for example, by one or more of computing resources 170 to store input data, output data (e.g., calculation results), intermediate data, transitional data, etc. Memory 180 may be implemented, for example, with volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and any other type of memory (such as non-volatile memory).

[0030] In some embodiments, the memory 180 and / or computing resources 170 may include software, instructions, programs, code, etc. that can be executed, run, etc. using one or more computing resources (e.g., hardware (HW) resources). Examples may include software implemented in any language (such as assembly language, C, C++, etc.), binary code, FPGA code, one or more operating systems, kernels, environments (such as eBPF), etc. The software, instructions, programs, code, etc. may be stored in a repository in the memory 180 and / or computing resources 170, for example. In some embodiments, the software, instructions, programs, code, etc. may be downloaded, uploaded, sideloaded, pre-installed, built-in, etc. to the memory 180 and / or computing resources 170. In some embodiments, the memory device 150 may receive one or more instructions, commands, etc. for selecting, enabling, activating, executing, etc. the “software, instructions, programs, code, etc.” Examples of computing operations, functions, etc. that may be implemented by memory 180, computing resources 170, software, instructions, programs, codes, etc. may include: any type of algorithm for AI, machine learning (ML), neural networks, etc., data movement, data management, data selection, filtering, encryption and / or decryption, compression and / or decompression, checksum calculation, hash value calculation, cyclic redundancy check (CRC), weight calculation, activation function calculation, training, inference, classification, regression, etc.

[0031] In some embodiments, the communication interface 120 at the host device 100, the communication interface 130 at the memory device 150, and / or the communication connection 110 may use any type of interface, protocol, etc. to implement one or more interconnects, one or more networks, a network of networks (e.g., the Internet), etc., or a combination thereof, and / or use one or more interconnects, one or more networks, a network of networks (e.g., the Internet), etc., or a combination thereof. For example, the communication connection 110 and / or one or more of the communication interface 120 and / or the communication interface 130 may implement and / or be implemented with any type of wired and / or wireless communication medium, interface, network, interconnect, protocol, etc., including: Peripheral Component Interconnect Express (PCIe), NVMe, NVMe over a network (NVMe-oF), Compute Express Link (CXL) and / or a coherent protocol (such as, CXL.mem, CXL.cache, CXL.io, etc.), Gen-Z, Open Coherent Accelerator Processor Interface (Open CAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc., Advanced Extensible Interface (AXI), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Advanced Message Queuing Protocol (AMQP), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Fibre Channel, InfiniBand, Serial ATA (Advanced Technology Attachment) (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, any generation of wireless network including 2G, 3G, 4G, 5G, 6G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc., or any combination thereof. In some embodiments, the communication connection 110 may include one or more switches, hubs, nodes, routers, etc.

[0032] In some embodiments, the memory device 150 may be implemented in any physical form factor. Examples of form factors may include 3.5 inches, 2.5 inches, 1.8 inches, etc., a storage device (e.g., a storage drive) form factor, an M.2 device form factor, an Enterprise and Data Center Standard Form Factor (EDSFF) (which may include, for example, E1.S, E1.L, E3.S, E3.L, E3.S2T, E3.L 2T, etc.), an Add-In Card (AIC) (e.g., a PCIe card (e.g., a PCIe expansion card) form factor including half-height (HH), half-length (HL), half-height half-length (HHHL), etc.), a Next Generation Small Form Factor (NGSFF), an NF1 form factor, a Compact Flash (CF) form factor, a Secure Digital (SD) card form factor, a Personal Computer Memory Card International Association (PCMCIA) device form factor, etc., or a combination thereof. Any computing device disclosed herein may be connected to a system using one or more connectors, such as a SATA connector, a SCSI connector, a SAS connector, an M.2 connector, an EDSFF connector (e.g., 1C, 2C, 4C, 4C+, etc.), a U.2 connector (which may also be referred to as an SSD Form Factor (SFF) SFF-8639 connector), a U.3 connector, a PCIe connector (e.g., a card edge connector), etc.

[0033] Any memory device disclosed herein may be used in conjunction with one or more personal computers, smart phones, tablet computers, servers, server chassis, server racks, data rooms, data centers, edge data centers, mobile edge data centers, and / or any combination thereof. In addition, the target system and the training system according to one or more embodiments may be included in an electronic system, wherein the target system and the training system may be implemented as electronic devices, respectively.

[0034] In some embodiments, memory device 150 may be implemented with any device that may include or have access to memory, storage device media, etc. for storing data that may be processed by one or more computing resources 170. Examples may include memory expansion and / or buffering devices (such as CXL Type-2 and / or CXL Type-3 devices, as well as CXL Type-1 devices that may include memory, storage media, etc.).

[0035] Figure 2A Another embodiment of a memory device scheme according to the disclosed example embodiments is shown. In some embodiments, the memory device may be a dual-mode memory device (eg, a memory device that may support both I / O block access and memory access). Figure 2A The embodiment shown in FIG. 1 may include one or more host devices 200 and one or more memory devices 250. In some embodiments, the host device 200 and the memory device 250 may be connected to Figure 1 2 is similar to the host device 100 and memory device 150 illustrated in FIG. In some embodiments, the host device 200 may include an application module 210, and the memory device 250 may include a controller 260, a memory medium 262, a storage device medium 270, and an interface 280. In some embodiments, the interface 280 and the controller 260 may be implemented on one or more circuits of the memory device 250. In some embodiments, the memory medium 262 may be a relatively fast memory (such as DRAM), and the storage device medium 270 may be a slower non-volatile memory (such as NAND flash memory). In some embodiments, the application module 210 may run an application that can access data from the memory device 250 in two ways. In some embodiments, the application module 210 may request data from the memory device 250 by using an I / O block access request 212. Specifically, by using the I / O block access request 212, the application module 210 may receive data from the storage device medium 270 through an I / O bridge to a DMA engine on the memory device 250 using a memory access protocol (e.g., CXL.io). In some embodiments, the application module 210 may also request data from the controller 260 by using an additional memory access protocol (e.g., CXL.mem) to access the memory medium 262. In some embodiments, the I / O block access request may allow the host device 200 to access the storage device medium 270 using general read and write commands, and the memory access request may allow the host to access the memory medium 262 using load and store commands.

[0036] Figure 2B Another embodiment of a memory device scheme according to a disclosed example embodiment is shown. Figure 2B The elements shown in the figure may be Figure 2A Elements similar to the elements shown in , where similar elements can be represented by reference numerals ending with and / or containing the same numbers, same letters, etc. Figure 2B The host device 200 in the embodiment may also include a device memory 220. In some embodiments, the device memory 220 may be a host managed device memory (HDM). In some embodiments, addresses of data on the memory medium 262 may be mapped to HDM addresses on the device memory 220. In some embodiments, if the host device 200 cannot directly (e.g., using a memory access request instead of using an I / O block access request) access addresses on the storage device medium 270, a memory access protocol (e.g., CXL.mem) may be used to access the HDM memory range (and the memory medium 262 mapped to the HDM memory range).

[0037] In some embodiments, the host device 200 may send a request (e.g., a memory access request 214) to the memory device 250 to retrieve data from the memory medium 262. In some embodiments, the request (e.g., the memory access request 214) may access the memory medium 262 using a memory access protocol (e.g., CXL.mem). In some embodiments, in response to receiving the memory access request 214 (e.g., a load request), the memory device 250 may request the controller 260 to check the memory medium 262 for the requested data corresponding to the load request. In some embodiments, in response to a cache hit (e.g., the data is found on the memory medium 262), the data may be returned directly from the memory medium 262. In some embodiments, in response to a cache miss (e.g., the data is not found on the memory medium 262), the controller 260 may copy the data from the storage device medium 270 to the memory medium 262 and return the data from the memory medium 262. In this way, in some embodiments, the controller 260 may play a role in managing data replacement on the memory medium 262 and facilitating memory access from the host device 200. For purposes of illustration, the size of the device memory 220 and the storage device medium 270 may be 512 GB, and the size of the storage medium 262 may be 16 GB. In some embodiments, the size of the storage medium 262 (e.g., 16 GB) may be small relative to the size of the storage device medium 270 (e.g., 512 GB), and the controller 260 may replace the data on the storage medium 262 with the data stored on the storage device medium 270. In some embodiments, as the data is replaced from the storage medium 262, the existing data on the storage medium 262 may be erased to make room for the new data. Thus, data may be copied from the storage device medium 270 to the storage medium 262 as needed. In some embodiments, as the storage medium may generally be a faster memory, using the storage medium 262 may improve bandwidth and latency compared to accessing the storage device medium 270. Thus, the cache replacement policy may be used to improve the performance of the memory device 250 as seen by the host device 200.

[0038] In some embodiments, since the memory medium can be populated with inferred data, the memory medium can be more efficiently populated, allowing for less latency, by using a memory cache management model that "uses AI" (e.g., a cache replacement policy). For example, an AI-driven cache management model can be implemented on a memory device for data on the memory medium. In some embodiments, an AI-driven cache management model for a memory device can support three stages: preparing a training input workload in a target system, training in a training server, and inferring in a target system. Each stage will be described in more detail below.

[0039] Figure 3 An example of an operating environment according to the disclosed example embodiments is shown. Figure 3 Target system 350 and training server 300 are shown. Target system 350 may include Figure 2A The target system 350 may further include an application module 360, an application weight module 370, and a memory device 380. In some embodiments, the memory device 380 may include a log module 382 and a storage medium 384. In some embodiments, the training server 300 may include a trainer 320 and a weight set module (or weight set) 330.

[0040] In some embodiments, the target system 350 may collect the trajectory data 340 using the application module 360. For example, the application module 360 ​​may run a given workload, and the target system 350 may generate the trajectory data 340 based on the output of the application module 360. In some embodiments, the trajectory data 340 may include addresses accessed from the memory device 380, timestamps of memory accesses, and / or metadata from the memory device 380. In some embodiments, the trajectory data 340 may include multiple workloads executed on the target system 350 by the application module 360. In some embodiments, the system configuration information 342 may include hardware and / or software configuration information for the target system 350. In some embodiments, the target system 350 may send the trajectory data 340 and the system configuration information 342 to the training server 300. In some embodiments, the training server 300 may receive the trajectory data 340 and the system configuration information 342, and input the trajectory data 340 and the system configuration information 342 to the trainer 320. In some embodiments, the trainer 320 may use the trajectory data 340 to calculate the value of the weight set (e.g., the weight for a given application and / or configuration) for a given system configuration (e.g., based on the system configuration information 342). For example, the trainer 320 may use the ML model to generate weights at the weight set module 330, and the weight set module 330 uses the trajectory data 340 captured from the target system 350 to capture the overall predictable pattern of the given application. In some embodiments, the weights (or application weights) may correspond to the usage of the application. In some embodiments, the training server 300 may send the updated weights 390 (the weights calculated at the weight set module 330 for the given application and / or configuration) to the target system 350, and the target system 350 may update the weights on the application weight module 370 based on the updated weights 390. In some embodiments, the training server 300 may continue to receive runtime trajectory data from the target system 350 to update the weights on the weight set module 330, and the training server 300 may send the updated weights 390 to the target system 350.

[0041] In some embodiments, the system configuration information may include one of information such as non-uniform memory access (NUMA) configuration information, memory partition information, memory partition size information, memory tiering size information, buddy algorithm information, version information, and / or interleave switching information.

[0042] In some embodiments, the memory device 380 may send log information (e.g., memory addresses and / or timestamps) from the log module 382 that may be received by the application weight module 370. In some embodiments, the application weight module 370 may output an inferred high priority access (HPA) pattern with a specific probability percentage for the expected data to the memory device 380 based on the log information and weights that may be used to populate the memory medium 384. The above steps will be further described in more detail below.

[0043] In some embodiments, data other than trajectory data 340 may be sent to training server 300. For example, system configuration or usage statistics may be sent to training server 300. Any data that can be used to calculate weights is within the scope of the disclosure. In some embodiments, updated weights 390 may not be sent to target system 350, and data for calculating weights may be received at application weight module 370, where application weight module 370 may calculate applied weights (or application weights). Any of application module 360 ​​and application weight module 370 may be implemented on one or more circuits of target system 350.

[0044] Figure 4 An example of preparing a training input workload in a target system according to a disclosed example embodiment is shown. Figure 4 The elements shown in the figure may be Figure 3, where similar elements may be represented by reference numerals ending with and / or including the same numbers, the same letters, etc. In some embodiments, target systems 400 and 402 may include application modules 410 and 412, runtime tracers 420 and 422, filters 430 and 432, CPUs 440 and 442, and memory devices 450 and 452, respectively. In some embodiments, any of the application modules 410 and 412, runtime tracers 420 and 422, and filters 430 and 432 may be implemented on one or more circuits of target systems 400 and 402. In some embodiments, target systems 400 and 402 may be servers running specific applications, or may be sample systems representing desired operating environments. In some embodiments, target systems 400 and 402 may be Figure 3 450 in the target system 350. In some embodiments, workloads 470 and 472 may be executed by application modules 410 and 412. In some embodiments, runtime tracers 420 and 422 may generate trace data using application modules 410 and 412. In some embodiments, the trace data may include information such as load addresses / store addresses, timestamps, and / or metadata. In some embodiments, applications on application modules 410 and 412 may be run multiple times to generate runtime trace data for runtime tracers 420 and 422. In some embodiments, filters 430 and 432 may filter data from runtime tracers 420 and 422. For example, filters 430 and 432 may filter data (or entries) from runtime tracers 420 and 422 related to storage requests (e.g., requests to store data on memory devices 450 and 452). In some embodiments, since the system may not infer data related to storage requests, only trace data related to load requests may be sent to the training server 300. In other words, because the storage request data is related to data stored to the memory device (rather than data read from the memory device) for a given workload, it may not be used to infer the HPA mode that will be used to load data to the memory medium. In some embodiments, filters 430 and 432 may filter memory accesses performed on host memory or device memory. In some embodiments, timestamps and other metadata may undergo a similar filtering process.

[0045] In some embodiments, memory access patterns may exhibit significant variations affected by several factors, including system software configuration, application configuration, hardware configuration, and the size and proportion of system memory. In some embodiments, runtime traces may be sensitive to the configuration of the hardware system and the software system. Therefore, in some embodiments, it may be desirable to utilize traces specific to target systems 400 and 402 as input workloads for inferring weights associated with target systems 400 and 402. In some embodiments, target systems 400 and 402 may pass filtered runtime data to training server 300. Figure 3 In the example operating environment of FIG. 4 , target systems 400 and 402 are shown. However, as explained in further detail below, additional target systems may also communicate data to training server 300, and the target systems may be grouped by training server 300 by application, memory, and / or system configuration.

[0046] In some embodiments, when an application is executed, memory devices 450 and 452 may generate physical access patterns that are stored as device physical address (DPA) patterns. In some embodiments, the DPA patterns may be stored in a log where a host device driver on target systems 400 and 402 may collect the DPA patterns. In some embodiments, target systems 400 and 402 may merge DPA patterns from multiple memory devices into a physical address data set and convert the DPA patterns to HPA patterns; for example, the HPA patterns may allow target systems 400 and 402 to know which DPA patterns are associated with which memory devices. In some embodiments, the HPA patterns may be sent to training server 300 as runtime data for training weights.

[0047] In some embodiments, the runtime data may be generated using a sample target system. For example, the target system 402 may be a sample target system for generating a weight set, and may not be a target system in, for example, a data center. In some embodiments, an application may execute multiple application workloads and output runtime data using the multiple application workloads.

[0048] In some embodiments, input data from target systems 400 and 402 may be received at input module 482. In some embodiments, the input data may be output by the input module to trainer 320. In some embodiments, the input data may be used by trainer 320 to calculate weights at weight set module 330, which will be described in more detail below. As an example, Figure 4 The weights calculated for different machine learning algorithms are shown, for example, W[DLRM], W[Rasnet], W[GPT], etc.

[0049] although Figure 4Operations on a training server are shown, but operations may be performed on a target system. For example, a target system may calculate a set of weights using application data and populate a cache using the set of weights. In addition, a target system may receive data from other target systems and use that data when calculating a set of weights.

[0050] Figure 5 An example of training in a training server according to a disclosed example embodiment is shown. Figure 5 The elements shown in the figure may be Figure 4 Elements similar to the elements shown in , where similar elements can be represented by reference numerals ending with and / or containing the same numbers, same letters, etc. Figure 5 Workload 570 may also be included. In some embodiments, target systems 400 and 402 may also include cache managers 510 and 530 and device drivers 520 and 540. In some embodiments, cache managers 510 and 530 and device drivers 520 and 540 may be implemented on one or more circuits on target systems 400 and 402. In some embodiments, cache managers 510 and 530 may include weight modules 512 and 532 and HPA modules 514 and 534. In some embodiments, weight modules 512 and 532 may receive application weights from training server 300 and calculate inferred HPA patterns (e.g., cache address information).

[0051] In some embodiments, the training server 300 may use data received from one or more target systems and calculate the weights of a specific application running on a specifically configured target system. For example, the training server 300 may receive input based on the workload 570 running on the target system 400, the target system 402, and / or any other target system. In some embodiments, the input from the input module 482 may be used by the trainer 320 to train the weights of the application. In some embodiments, the weights may be calculated using an ML algorithm. In some embodiments, the weights may be set by the first iteration of the calculated weights and may be updated when additional runtime data (e.g., input from the input module 482) is received. In some embodiments, weight sets may also be calculated for other configurations (such as use cases, other system configurations, etc.). In addition, in some embodiments, other algorithms may be used to calculate weight sets, and the ML algorithm is only one example for calculating weights.

[0052] In some embodiments, the trainer 320 may receive input at the input module 482 and calculate weights for the weight set module 330 for a given application and system configuration. In this example, the weights may be configured for a specific application. However, in some embodiments, the weights may not be for a specific application and may be weights for different configurations (such as, system type, use case, etc.). In some embodiments, the training server may not be in a one-to-one relationship with the target system and may be in a one-to-many relationship with multiple target systems. In some embodiments, as the number of target systems and the amount of runtime data increases, the trainer 320 may be continuously trained to provide updated weights 390 for a given application and configuration. In some embodiments, the input module 482, the trainer 320, and the weight set module 330 may be implemented on one or more circuits on the training server 300.

[0053] In some embodiments, training may be performed on a server provided by a service provider. For example, a service provider may be specifically configured to calculate weights for an application. In some embodiments, training in the training server 300 may generate different weights for applications, workloads, and system hardware configurations. In some embodiments, the training server 300 may virtually emulate a target system using system configuration information and generate weights using log information. In some embodiments, the training server 300 may be a dedicated system that allows it to calculate weights for a given application and configuration faster than on the target system.

[0054] In some embodiments, the training model may be able to accommodate training input workloads from a training target system (e.g., a target system for training). In some embodiments, the training server may maintain multiple sets of weights for inference of each application on each target system to ensure compatibility and optimization for each specific system. In some embodiments, the training server may support online updates, allowing weights in the target system to be replaced during runtime. This may allow real-time adjustments and enhancements to the performance of the system.

[0055] In some embodiments, weights may be generated for applications and system configurations. For example, if two systems run the same application but have different system configurations, the training server 300 may generate a single set of weights (e.g., weights) to be used by both systems. Furthermore, the training of the weight set may use only data for a specific configuration to generate a weight set for that configuration.

[0056] In some embodiments, the target systems 400 and 402 may receive weights from the weight set module 330. In some embodiments, the received weights may be used to update weights at the weight modules 512 and 532. In some embodiments, the weight modules 512 and 532 may generate an HPA mode for the HPA modules 514 and 534. In some embodiments, the HPA mode may be sent to the device drivers 520 and 540 (e.g., received at the HPA modules 522 and 542). In some embodiments, as will be described in further detail below, the device drivers 520 and 540 may send the inferred HPA mode to the memory device using the decision modules 524 and 544.

[0057] Figure 6 A method for managing a cache in a memory device according to an example embodiment of the disclosure is shown, and Figure 7 An example of managing a cache in a memory device according to a disclosed example embodiment is shown. Figure 7 The elements shown in the figure may be Figure 4 Elements similar to the elements shown in , where similar elements can be represented by reference numerals ending with and / or containing the same numbers, same letters, etc. Figure 6 Also shown is a target system 600, a decoder 630, and a memory device 650. In some embodiments, the target system 600 can communicate with the memory device 650 having an HDM decoder range (e.g., using addresses on the memory medium 262 mapped to the HDM memory range). In some embodiments, the decoder 630 can support a load interface / store interface to the memory medium 680. In some embodiments, the controller 670 can map target host memory accesses to the memory medium 680. In some embodiments, data can be copied from some areas of the storage device medium 690 to the mapped areas of the memory medium 680. These functions can be used to support load operations / store operations from the target system 600.

[0058] At block 710, access log information may be received for an application, according to an embodiment. For example, the memory device 650 may send log information from an access log module (or access log) 660 (e.g., DPA) to a log module (or log) 622 at the device driver 620 and a log module (or log) 612 at the cache manager 610. In some embodiments, the memory device 650 may have the ability to record runtime load addresses / storage addresses and timestamps. In some embodiments, the specific pattern of load addresses / storage addresses within a workload may vary depending on the configuration of both the memory device 650 and the system used therewith. Typically, the access log of the memory device may not be accessible by the target system. For example, DDR access patterns are typically not recorded by the host. However, since CXL allows asynchronous memory access, memory access is possible via some dual-mode SSDs (e.g., CXL-compatible devices). However, in some embodiments, asynchronous memory access may not support access logs since there may be no space for storing the logs. Therefore, the host may not be able to access the DPA. However, in some embodiments, the memory access protocol (e.g., CXL.io) may allow logging in memory access mode. Thus, in some embodiments, the host may retrieve the DPA from a CXL or other dual mode memory device.In some embodiments, to access the load address / store address log, the device driver may employ CXL.io and retrieve the log from the device.

[0059] In some embodiments, the log module 612 may convert the DPA to a host virtual address (HVA) or HPA mode. In some embodiments, the cache manager 610 may process / filter the log into an input workload set. In some embodiments, the input workload set may be equivalent to the input workload set utilized during the training of the model (the weights in the weight set module 330). In some embodiments, the cache manager 610 may be responsible for managing multiple inference weight sets that are "determined based on the type of application being executed". In addition, since the target system may be connected to multiple memory devices, it may know which memory device the DPA belongs to. Therefore, in some embodiments, the HVA and HPA mode may allow the host to know which storage device the DPA belongs to. Typically, the HVA may have the same value. However, the HPA mode may change continuously. Therefore, in some embodiments, it may be beneficial to convert the physical address to a virtual address. In some embodiments, if the input is a virtual address, the weight set module 614 may also generate a virtual address. In some embodiments, the log of the log module 612 may be of any size (e.g., 100 pages or 200 pages in size).

[0060] In some embodiments, the log module 612 may filter the HPA for load data. For example, the memory device 650 may send all access log information to the target system 600. In some embodiments, since the target system 600 may use, for example, load data, the log module 612 may filter out the storage request data and leave only the load data. In some embodiments, the filtering may be the same as that done when preparing the training input workload. Therefore, the training data and the runtime data may be similar, allowing the weight set module 614 to output the inferred address more accurately.

[0061] At block 720, address information (e.g., cache address information) may be determined using access log information and application weights, depending on the embodiment. In some embodiments, the weight set module 614 may receive data from the log module 612 and output the inferred HPA mode to the HPA module 616. In some embodiments, the weight set module 614 may use the weights received from the weight set module 330 and calculate the HPA mode using the received weights. In some embodiments, the target system 600 may update the weight set module 614 upon receiving the weights from the weight set module 330. In some embodiments, based on the accuracy of the data, the weight set module 614 may run at more frequent intervals.

[0062] In some embodiments, the target system may have multiple weight sets. In some embodiments, based on the application, the target system may populate the memory medium with an appropriate weight set. In some embodiments, the application may send its type to the runtime cache manager (or cache manager) 610 to assist in selecting an appropriate weight set.

[0063] In some embodiments, cache address information may be returned to the memory device. In some embodiments, the host device may determine the available size of the memory medium and return the cache address information to the memory device based on the available size of the memory medium. In some embodiments, the cache manager 610 may generate an HPA pattern based on the likelihood of future accesses (e.g., based on the weight set module 614). In some embodiments, the HPA pattern from the HPA module 616 may be received by the device driver 620 at the HPA module 624. In some embodiments, the device driver 620 may send the HPA pattern from the HPA module 624 to the decision module 626 to update the memory medium 680 after the decision is made at the decision module 626 based on the HPA set and the cache state, so that the memory medium 680 can be updated accordingly. Therefore, based on the HPA pattern from the HPA module 624, in some embodiments, the controller 670 may load the inferred HPA pattern from the storage device medium 690 to the memory medium 680 (i.e., fill the cache). In some embodiments, the cache manager 610 may generate multiple HPA pattern sets to improve cache efficiency by considering the likelihood of future accesses.

[0064] In some embodiments, the HPA pattern may be received by the decision module 626. In some embodiments, if the memory medium 680 has enough space (e.g., page), the cache may be updated via the controller 670. In some embodiments, this process may be run periodically (e.g., every minute, every 30 minutes, every hour, etc.). In some embodiments, if the decision module 626 has a high confidence, the memory medium 680 may be updated more frequently. For example, if the weight set module 614 has been trained with a large amount of training data and has good predictability, the memory medium 680 may be loaded more frequently because the data can be accessed faster.

[0065] Figure 8A flowchart of an example process of populating a cache using a training server according to an example embodiment disclosed is shown. In box 810, according to an embodiment, the target system may send runtime trace data of the application and system configuration to the training server. In some embodiments, the target system may run a workload for the application and generate trace data based on the workload. In some embodiments, the trace data may be generated using multiple workloads. In some embodiments, the runtime trace data may correspond to the operation of the application. In some embodiments, the runtime trace data may not be sent to the training server and may be processed by the target system. In addition, in some embodiments, the target system may receive weight information from the training server and configure the weight set at the target system. In some embodiments, the runtime trace data may not be sent to the training server, and other data may be sent to the training server. For example, historical data or log data may be sent to the training server.

[0066] At block 820, according to an embodiment, the training server may receive the data and use the runtime trace data to train weights for the application and system configuration. In some embodiments, the training server may aggregate data from multiple target systems to generate weights. In some embodiments, the training server may generate multiple weights for the application and determine which weights to send to the target system based on, for example, the system configuration.

[0067] At block 830, depending on an embodiment, the target system may receive the weights from the training server and update the weight set module on the target system 802. In some embodiments, the target system may receive multiple weights for an application and may determine which weight set to use based on need or resources. For example, if the target system gives a low priority to an application, a weight set with a low weight for the application may be used. In some embodiments, the target system may not update the weight set on the target system and may use the weight set on the training server when it retrieves data from the memory device.

[0068] At block 840, according to an embodiment, the target system may receive log information from a memory device (e.g., an SSD). In some embodiments, the log information may include memory accesses, timestamps, and / or metadata. In some embodiments, the target system may not receive log information, and may receive other information to retrieve data from the memory device. In some embodiments, the target system may use AI to determine what information may be retrieved from the memory device.

[0069] At block 850, the target system may use the log information and the weight set to generate an inferred HPA pattern for the application. In some embodiments, the target system may generate virtual addresses to be used to fill the memory medium. At block 860, the target system may send the inferred HPA pattern to the memory device to fill the memory medium on the memory device (or fill the cache).

[0070] The principles disclosed herein have independent utility and can be implemented separately, and not every embodiment can utilize every principle. However, these principles can also be implemented in various combinations, some of which can magnify the benefits of each principle in a synergistic manner.

[0071] For the purpose of illustrating the disclosed inventive principles, some example embodiments may be described in the context of specific implementation details, such as a processing system that may implement a NUMA architecture, a memory device and / or a memory pool that may be connected to the processing system using an interconnect interface and / or interconnect protocol Compute Express Link (CXL), etc. However, the principles are not limited to these example details and may be implemented using any other type of system architecture, interface, protocol, etc.

[0072] In some embodiments, the latency of a memory device may represent a delay between the memory device and a processor when accessing the memory. In addition, the latency may include latency caused by hardware (such as the read and write speeds of accessing the memory device and / or the structure of an array memory device that produces individual delays when reaching individual elements of the array). For example, a first memory device in the form of a DRAM may have a faster read / write speed than a second memory device in the form of a NAND device. In addition, the latency of a memory device may change over time based on conditions (such as relative network load) as well as the performance of the memory device over time and environmental factors (such as changing temperature that affects the delay on the signal path).

[0073] Although some example embodiments may be described in the context of specific implementation details (such as a processing system that may implement a NUMA architecture, a memory device and / or a memory pool that may be connected to the processing system using an interconnect interface and / or interconnect protocol CXL, etc.), the principles are not limited to these example details and may be implemented using any other type of system architecture, interface, protocol, etc. For example, in some embodiments, one or more memory devices may be connected using any type of interface and / or protocol, including: Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe-oF over a Network (NVMe oF), Advanced Extensible Interface (AXI), Ultra Path Interconnect (UPI), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, etc. or any combination thereof. In some embodiments, the interconnect interface may be implemented with one or more memory semantics and / or memory consistency interfaces and / or protocols, including one or more CXL protocols (such as CXL.mem, CXL.io, and / or CXL.cache), Gen-Z, Coherent Accelerator Processor Interface (CAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc. or any combination thereof. Any memory device may be implemented with one or more of any type of memory device interface, including DDR, DDR2, DDR3, DDR4, DDR5, LPDDRX, Open Memory Interface (OMI), NVLink, High Bandwidth Memory (HBM), HBM2, HBM3, etc.

[0074] In some embodiments, any of the memory devices, storage pools, hosts, etc., or components thereof, may be implemented in any physical configuration and / or electrical configuration and / or form factor, such as a stand-alone device, an add-on card (such as a PCIe adapter or expansion card), an insert device (e.g., a connector and / or slot that can be inserted into a server chassis (e.g., a connector on a backplane and / or midplane of a server or other device), etc.). In some embodiments, any of the memory devices, storage pools, hosts, etc., or components thereof, may be implemented using any connector configuration for an interconnect interface (such as a SATA connector, a SCSI connector, a SAS connector, an M.2 connector, a U.2 connector, a U.3 connector, etc.) in a form factor for a storage device (such as 3.5 inches, 2.5 inches, 1.8 inches, M.2, Enterprise and Data Center SSD Form Factor (EDSFF), NF1, etc.). Any device disclosed herein may be implemented in whole or in part with and / or used in conjunction with a server chassis, server rack, data room, data center, edge data center, mobile edge data center, and / or any combination thereof. In some embodiments, any of a memory device, a memory pool, a host, etc., or a component thereof, may be implemented as a CXL Type-1, a CXL Type-2 device, a CXL Type-3 device, etc.

[0075] In some embodiments, any functionality described herein (including, for example, any logic for implementing tiering, device selection, etc.) may be implemented in hardware, software, or a combination thereof, such hardware, software, or a combination thereof, including: combinatorial logic, sequential logic, one or more timers, counters, registers, and / or state machines, one or more complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), central processing units (CPUs) that execute instructions stored in any type of memory (such as complex instruction set computer (CISC) processors (such as x86 processors) and / or reduced instruction set computer (RISC) processors (such as ARM processors)), graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), etc.), or any combination thereof. In some embodiments, one or more components may be implemented as a system on a chip (SOC).

[0076] In the present disclosure, many specific details are set forth in order to provide a thorough understanding of the disclosure, but aspects of the disclosure may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0077] References throughout this specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification may not necessarily all represent the same embodiment. In addition, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as "exemplary" should not be interpreted as necessarily being preferred or advantageous over other embodiments. In addition, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, a singular term may include a corresponding plural form, and a plural term may include a corresponding singular form. Similarly, hyphenated terms (e.g., "two-dimensional", "predetermined", "pixel-specific", etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two-dimensional", "predetermined", "pixel-specific", etc.), and capitalized entries may be used interchangeably with corresponding non-capitalized versions. Such occasional interchangeable usage should not be regarded as inconsistent with each other.

[0078] In addition, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals have been repeated in the drawings to indicate corresponding and / or similar elements, if deemed appropriate.

[0079] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. When used in this specification, the terms "comprise" and / or "include" specify the presence of the features, wholes, steps, operations, elements and / or components set forth, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0080] When an element or layer is referred to as being on, "connected to" or "bonded to" another element or layer, the component or element may be directly on, directly "connected to" or "bonded to" another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to" or "directly bonded to" another element or layer, there are no intermediate elements or layers. The same reference numerals always represent the same element. As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items.

[0081] As used herein, the terms "first", "second", etc. are used as labels for the nouns that follow them, and do not imply any type of (e.g., spatial, temporal, logical, etc.) order unless explicitly defined as such. In addition, the same reference numerals may be used across two or more figures to represent parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such usage is only for simplicity of illustration and ease of discussion, and it does not imply that the construction or architectural details of such components or units are the same in all embodiments or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0082] The term "module" may represent any combination of software, firmware, and / or hardware configured to provide the functions described herein in conjunction with the module. For example, software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, alone or in any combination, components, hardwired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits. Modules may be implemented together or individually as circuits (e.g., but not limited to integrated circuits (ICs), systems on chips (SoCs), components, etc.) that form part of a larger system. The embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuits, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs (e.g., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device). Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver device executed by a data processing device). A computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or may be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. In addition, although a computer storage medium is not a propagated signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium may also be one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). In addition, the operations described in this specification may be implemented as operations performed by a data processing device on data stored on one or more computer-readable storage devices or received from other sources.

[0083] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Specific features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as functioning in a particular combination and even initially claimed as such, in some cases one or more features from the claimed combination may be deleted from the combination, and the claimed combination may point to a sub-combination or a variation of the sub-combination.

[0084] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed to obtain the desired results. In certain circumstances, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0085] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

[0086] Although specific exemplary embodiments have been described and shown in the accompanying drawings, it should be understood that such embodiments are illustrative only, and the scope of the present disclosure is not limited to the embodiments described or shown herein. The invention may be modified in arrangement and detail without departing from the inventive concept, and these changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A method for cache management in a memory device, comprising: receiving access information for the application from the memory device; as well as The address information is determined using the access information and the application weight.

2. The method according to claim 1, wherein: The application weight corresponds to the usage rate of the application.

3. The method according to claim 1, wherein: The access information includes at least one of one or more addresses and time stamp information.

4. The method according to claim 1, further comprising: Address information is sent to the memory device.

5. The method according to claim 4, further comprising: Filters the entry for storage request from access information.

6. The method according to claim 4, wherein: The steps to send address information include: determining the available size of the storage medium; and Returns address information based on the available size of the storage medium.

7. The method according to any one of claims 1 to 6, further comprising: Sending the trajectory information to the training system, wherein the trajectory information corresponds to the operation of the application; receiving a set of weights from a training system, wherein the set of weights is based on trajectory information; and Modify the application weights based on the weight set.

8. The method according to claim 7, wherein: The access information is first access information; wherein the track information includes second access information.

9. The method according to claim 7, wherein: The track information includes the loading information of the application.

10. An electronic device comprising: Storage media; Storage device media; as well as One or more circuits configured to: Send access information, receiving address information based on the access information, and The memory medium is populated with data from the storage device medium using the address information.

11. The electronic device according to claim 10, wherein: The access information includes access data for applications on the memory medium and the storage device medium.

12. The electronic device according to claim 10, wherein: The address information corresponds to an application on the host device.

13. An electronic system comprising: A memory device, comprising a memory medium and a storage device medium, wherein the memory device is configured to: Send access information, Receiving address information, and populating the memory medium with data from the storage device medium using the address information; and A training device, comprising one or more circuits, wherein the one or more circuits are configured to: receiving access information from a memory device, Use access information and application weights to determine address information, and Send address information to the memory device.

14. The electronic system according to claim 13, wherein: The application weight corresponds to the usage rate of the application.

15. The electronic system according to claim 13, wherein: The access information includes at least one of one or more addresses and time stamp information.

16. The electronic system according to claim 13, wherein: The one or more circuits are further configured to modify the access information.

17. The electronic system according to claim 16, wherein: The process of modifying the access information includes filtering the entry of the storage request from the access information.

18. The electronic system according to claim 13, wherein: The processing of sending address information includes: determining the available size of the storage medium; and Returns address information based on the available size of the storage medium.

19. The electronic system according to any one of claims 13 to 18, wherein: The one or more circuits are further configured to: Send trajectory information to the training system; receiving a set of weights from a training system, wherein the set of weights is based on trajectory information; and Modify the application weights based on the weight set.

20. The electronic system according to claim 19, wherein: The access information is first access information; wherein the track information includes second access information.

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