Method and apparatus for batching pages for use with a data movement accelerator

Abstract

A method for batching pages for use in a data movement accelerator of a processor. The method includes: determining a plurality of memory regions having similar contents according to a similarity criterion, wherein each memory region includes a plurality of pages. The method further includes: determining a plurality of page groups, wherein each page group includes a plurality of corresponding pages between the plurality of memory regions. The method then includes: providing the plurality of page groups to a data movement accelerator for parallel processing.

Description

Background Art

[0001] In modern computing, multiple virtual memory regions may contain data equivalent to the memory associated with other memory regions. In the case of cloud computing and large-scale data centers, the overall memory footprint of the same data across all regions becomes quite large, which may lead to inefficient resource utilization. For example, a cloud service provider can only provide a certain number of virtual machines (VMs) to its customers, because one of the main bottlenecks in providing more VMs is the total amount of available memory.

[0002] Different data deduplication techniques have been proposed in the past, and the most commonly implemented in the Linux kernel is the so-called Kernel Same-page Merging (KSM) technique. However, current KSM is implemented via software in a synchronous programming model without parallelism. As a result, it consumes a large portion of the central processing unit (CPU) resources and has been a source of complaints. Therefore, an improved method and apparatus for implementing KSM is desired. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Some examples of apparatus and / or methods will be described below by way of example only and with reference to the accompanying drawings, in which Figure 1 A flow chart illustrating a method for batching pages for use with a data movement accelerator of a processor; Figure 2 Shows the KSM process flow; Figure 3 shows the system architecture for KSM with and without data movement accelerators; Figure 4 shows relative page grouping for KSM preprocessing; Figure 5 shows asynchronous-based software-accelerator interaction for page comparison in KSM; Figure 6 A flow chart illustrating a method for using a data movement accelerator of a processor in page merging; Fig. 7A and Figure 7B An analysis showing the performance impact of migrating related KSM operations to a data movement accelerator; and Figure 8 Schematic diagram showing an example of an apparatus or device for performing at least one method. DETAILED DESCRIPTION

[0004] Some examples are now described in more detail with reference to the accompanying drawings. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of features and equivalents and substitutes of features. In addition, the terms used to describe certain examples herein should not limit further possible examples.

[0005] Throughout the description of the drawings, the same or similar reference numerals refer to the same or similar elements and / or features, which may be the same or implemented in a modified form while providing the same or similar functions. For clarity, the thickness of lines, layers and / or regions in the drawings may also be exaggerated.

[0006] When two elements A and B are combined using "or", it is understood that this discloses all possible combinations, i.e., only A, only B, and A and B, unless otherwise explicitly defined in individual cases. As an alternative wording for the same combination, "at least one of A and B" or "A and / or B" can be used. This is equally applicable to combinations of more than two elements.

[0007] If singular forms such as "a / an" and "the" are used and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use several elements to achieve the same function. If a function is described below as being achieved using multiple elements, further examples may use a single element or a single processing entity to achieve the same function. It is further understood that when the term "include", "including", "comprise" and / or "comprising" is used, it describes the presence of specified features, integers, steps, operations, processes, elements, parts and / or groups thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, parts and / or groups thereof.

[0008] In the following description, specific details are set forth, but examples of the techniques described herein may be implemented without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring an understanding of the present description. “An example / example,” “various examples / examples,” “some examples / examples,” and the like may include features, structures, or characteristics, but not every example necessarily includes these particular features, structures, or characteristics.

[0009] Some examples may have some, all, or none of the features described for other examples. "First," "second," "third," and the like describe common elements and indicate different instances of similar elements being referenced. Such adjectives do not imply that the elements so described must be in a given order, either temporally or spatially, in ranking, or in any other way. "Connected" may indicate that elements are in direct physical or electrical contact with each other, and "coupled" may indicate that elements cooperate or interact with each other, but these elements may or may not be in direct physical or electrical contact.

[0010] As used herein, the terms "operate," "execute," or "run" are used interchangeably when referring to software or firmware associated with a system, device, platform, or resource, and may refer to software or firmware stored in one or more computer-readable storage media accessible by a system, device, platform, or resource, even if the instructions contained in the software or firmware are not being actively executed by the system, device, platform, or resource.

[0011] The specification may use the phrases "in an example / example", "in various examples", "in some examples / examples", and / or "in various examples / examples", each of which may refer to one or more of the same or different examples. In addition, the terms "comprising", "including", "having", etc. as used with respect to the examples of the present disclosure are synonymous.

[0012] Figure 1 A method 100 for batching pages for a data movement accelerator of a processor is shown. The method includes: 110: determining a plurality of memory regions having similar contents according to a similarity criterion, wherein each memory region includes a plurality of pages. The method also includes: 120: determining a plurality of page groups, wherein each page group includes a plurality of corresponding pages between the plurality of memory regions. The method additionally includes: 130: providing the plurality of page groups to the data movement accelerator for parallel processing.

[0013] In modern computing, multiple virtual memory regions may contain data equivalent to the memory associated with other memory regions. In the case of cloud computing and large-scale data centers, the overall memory footprint of the same data across all regions becomes quite large, which may lead to inefficient resource utilization. For example, a cloud service provider can only provide a certain number of virtual machines (VMs) to its customers, because one of the main bottlenecks in providing more VMs is the total amount of available memory.

[0014] There are various data deduplication techniques, of which the most commonly implemented in the Linux kernel is the so-called kernel same-page merging (KSM). However, an important factor limiting the use of KSM in large-scale settings is the computationally expensive nature of this feature. Since memory comparisons and checksums are calculated on the central processing unit (CPU) core, KSM takes up a lot of processing time and pollutes the cache. In addition, these calculations bring a lot of data (e.g., pages) into the cache and act hostilely with other applications running together. Since KSM is usually executed via software in a synchronous programming model without parallelism, it can occupy a large portion of CPU resources and become a source of complaints.

[0015] On-chip data movement (e.g., data streaming) accelerators for handling memory page merging issues can be used to perform these calculations. By using accelerators to efficiently migrate trivial but time-intensive subtasks, KSM can be greatly improved in performance. For example, compared to software-only solutions, software programming models can efficiently utilize on-chip accelerators in a beneficial manner. In order to efficiently use on-chip accelerators, methods may include: batching memory-intensive sub-processes by batching between relative page groups. Further, the method may include: asynchronous programming models further assist new batch processing models. Both of these can reduce computational cache overhead by moving the main processing out of the main CPU core to overcome performance issues, and by alleviating cache pollution in the process. This can provide significant performance improvements and prevent CPU caches from being polluted.

[0016] A data movement accelerator may be a specialized, energy-efficient hardware component or subsystem designed to improve the efficiency and speed of data transfer and manipulation within a computer system (particularly compared to a general CPU). They are typically used to accelerate data-intensive tasks involving the movement, transformation, or processing of large amounts of data between different memory hierarchies or different components of a computer system. This can be accomplished by migrating these tasks from the CPU. Data movement accelerators are particularly valuable in scenarios where the efficiency or speed of a traditional processor core may not be sufficient to handle data movement requirements. They can support processors by using dedicated buses or data paths to achieve effective higher data transfer speeds between various memory types (such as main system memory (RAM), cache memory, storage devices). They may include hardware support for data transformation tasks such as compression, decompression, encryption, decryption, data formatting, and data encoding or decoding. Some accelerators are designed to predictively fetch data from a memory or storage device before the data is needed by the processor, thereby reducing data access latency and improving overall system performance. And the data movement accelerator can use parallel processing to handle multiple data streams simultaneously, further enhancing its data processing capabilities.

[0017] On-chip accelerators may be included on the CPU to enable fast memory movement and operation features through on-chip hardware accelerators. Such accelerators may accelerate operations for memory comparisons, calculating cyclic redundancy check (CRC) checksums, copying data from one location to another, and the like. These operations may be suitable for improving KSM by reducing high CPU utilization and cache pollution. Accelerator memory comparisons may be used when comparing memory pages to each other, and accelerator memory copies may be performed when pages are merged to obfuscate the locations of the merged pages.

[0018] A CRC checksum is a type of error checking code used in calculations to detect errors in data transmission or storage. CRC checksums are commonly used in network transmission protocols, file storage systems, and data transmission over unreliable channels. A CRC checksum works by generating a fixed-size checksum value from the data being transmitted or stored and appending it to the data. When data is received or read, the CRC checksum is recalculated, and if it does not match the checksum originally transmitted, it indicates that an error has occurred.

[0019] Figure 2KSM process flow 200 is shown. Memory is a key resource in the data center and is one of the limiting factors in the number of VM services provided by cloud providers. Due to the importance of reducing memory usage in these platforms, memory deduplication technology is critical. KSM is used to combine duplicate pages found in memory areas, thereby reducing the overall space consumed by these areas. In a virtualized environment, this process of scanning, combining and checking and calculating pages falls on the host for management. Since many key processes must be run on the host, the goal is to alleviate the time spent on KSM related tasks.

[0020] Process 200 begins at 210: creating two tree data structures, which are generally referred to as a stable tree and an unstable tree. The unstable tree is rebuilt after each scan and contains only pages that do not change frequently (e.g., are good candidates for merging). The stable tree saves pages that have been merged and remains unchanged across scans. Next, the process proceeds to 220: loading the next page in the memory area and checking the current page with the pages in the stable tree for matching 225. If a match is found, the current page, memory, and stable page are merged, and the process has finished the page compare (FPC). If no match is found with the stable tree, the process proceeds to 240: calculating the checksum hash of the current page to perform 245: finding a match. The KSM algorithm considers pages that are not frequently modified to be the best candidates for merging. In these cases, the checksum is used to quickly compare whether the page has changed since the last time the page was scanned and can also be migrated to the on-chip accelerator. This reduces the number of false negatives from the unstable tree lookup, and the checksum is used to insert into the unstable tree only those pages whose checksums have not changed recently. If the checksum does not match the stored value for the page, then proceed 250: the checksum value is updated, and the process 200 has completed its page comparison (FPC). If there is a checksum match, the process 200 then proceeds 260: checking the current page with a page within the unstable tree for a match 265. If a match is found, the process 200 proceeds 280: combining the two pages, placing the merged page in the stable tree, and performing an FPC. If no match is found, proceed 270: inserting the page into the unstable tree.

[0021] When the process 200 has completed the page comparison (FPC), it then proceeds to 285: check to see if the current page is the last page in memory. If so, it proceeds to 290: reinitialize the unstable tree, otherwise, the process 200 starts again at 220: scan and search the stable tree for the next memory page.

[0022] KSM is a popular memory deduplication technique used within the Linux kernel, but suffers from high CPU utilization and can contribute a lot of cache pollution. KSM can be greatly improved in performance by using accelerators to efficiently migrate trivial but time-intensive subtasks. On-chip data accelerators can provide a rich set of data manipulations for certain operations. For example, memory comparison, CRC checksum calculation, memory dual-casting, and append operations can all be implemented with such an accelerator. Figure 3 A system architecture 320 for KSM with an on-chip or data streaming accelerator is shown, along with a conventional architecture 310 without such an accelerator. The accelerator 325 has a software interface 322 within the host OS.

[0023] Some on-chip data accelerator operations include: memory move, which is used to transfer data from a source address to a destination address; CRC generation, which is used to generate a checksum on the transferred data; data integrity field check; double cast, which is used to copy data to two destination locations simultaneously; memory fill, which is used to fill a memory range with a fixed pattern; memory compare, which is used to compare two source buffers and return whether the buffers are the same; create a delta record containing the difference between the original buffer and the modified buffer; merge the delta record with the original source buffer to produce a copy of the modified buffer at the destination location; pattern detect or zero detect, which is used to compare the buffer to an 8-byte pattern, which may include zeros; and cache dump flush, which is used to evict all lines in a given address range from all levels of CPU cache.

[0024] A well-performing and feature-rich on-chip accelerator or data movement accelerator (e.g., with the ability to migrate asynchronously and in batches) can be used to enhance the performance of the KSM algorithm. Some on-chip accelerator operations fit very well with the work performed by the KSM process. For example, the following items can be migrated from the CPU to the on-chip accelerator: finding matches 225, 265; calculating checksums 240; and merging and moving pages to stable trees 280. For example, memory comparison enables the use of an on-chip accelerator to compare memories of any specified size, such as performing page comparisons for the current page and a stable tree or an unstable tree. Page checksums can also be calculated by the on-chip accelerator through a CRC generation operation.

[0025] By (partially) migrating KSM to an on-chip accelerator, a more efficient and well-performing solution with less performance interference and security issues can be achieved.Based on the current software KSM flow, a naive migration of KSM to an on-chip accelerator can be performed.

[0026] like Figure 2As shown in , two operations can be migrated directly to the on-chip accelerator using a naive implementation. First, compare the pages in the stable tree and the unstable tree. This operation can simply compare whether the target page completely matches the page in the tree. This can be done using the memory comparison operation of the on-chip accelerator. Second, calculate the checksum of the page to see if it has been updated recently. This can be done using the CRC generation operation of the accelerator. Since these two operations require touching the entire 4KB content of the page, they are the most expensive operations in KSM, consuming 34% and 25% of the total CPU cycles of KSM respectively.

[0027] With the current linear and synchronous execution, the corresponding software code for these two operations can be directly replaced by issuing accelerator descriptors and waiting (UMWAIT) to complete the record and proceed to the next stage. However, these benefits are not fully realized due to the synchronous use of accelerators but without the migration nature of descriptor batches. By customizing the algorithm according to the benefits and unique features of the on-chip accelerator, a more efficient version of KSM can be achieved. KSM can be parallelized and can take advantage of the asynchronous programming model of the on-chip accelerator (e.g., hardware-software co-design), using software-level hints and optimized execution flow.

[0028] Figure 1 This adaptive batching approach is shown where asynchronous CPU and accelerator processing can be used to overcome KSM overhead and ensure optimal performance. Using and coordinating (e.g., pipelining) multiple operations (CRC, compare, move) of on-chip accelerators can enable more complex use cases to take advantage of these accelerators that are more complex than straightforward memory moves. Specifically, an adaptive batching and asynchronous programming model is described to better exploit on-chip accelerators and their unique properties.

[0029] Each of the multiple memory regions referenced in method 100 may be generated by booting from the same file. This may make it easier to determine which memory regions have similar content. Partially migrating the KSM to the data accelerator may provide a more efficient and well-performing solution with less performance interference and security issues. Adaptively batching together more related pages (such as those booted from the same file) along with a carefully designed asynchronous model may allow for more efficient pipelining for uses such as the KSM.

[0030] The multiple memory regions can be memory regions of a virtual machine. KSM is most useful in scenarios where multiple VM instances with the same VM image are running on the same host platform. This is because, in such situations, pages in different VM instances are more likely to be the same, creating good conditions for potential page merging.

[0031] Figure 4 Relative page grouping 400 for KSM preprocessing is shown. The on-chip accelerator can manage batches of operations and keep many operations running, both of which reduce migration overhead or significantly improve observable throughput. This can be done by using "relative page group batching" to group candidate pages across VMs by the same relative page address, while batching and comparing asynchronously between these groups via the on-chip accelerator. This effectively amortizes access latency to the accelerator, allowing the CPU core to perform other tasks in parallel and fully utilize the processing power of the accelerator. This design is derived from two observations:

[0032] Multiple corresponding pages may include equivalent data. The same virtual address (page) in different VM instances may reference the same context (but the actual content may be different). For example, assume that there are VM instances 1 and 2, which are booted from the same image. If the page starting at virtual address X in VM-1 contains the code "glibc" (representing the GNU C language library (GLIBC)), the page starting at virtual address X in VM-2 also contains the code "glibc". Such pages can be referred to as "same location pages" across VM instances. GLIBC is a core component of the GNU operating system and many Unix-like systems. It is a C language library that provides important system calls and libraries for programming in C and C++ languages. Thus, it can be a good candidate for KSM. In addition, same-page merging will most likely occur inside the "same location pages" across VM instances, because many of such pages are common, and the actual data is unlikely to change after initialization. Since common libraries may be found in common locations, especially when they are booted from the same image, candidates for page merging can be quickly and efficiently found simply by looking at them at common locations.

[0033] Multiple corresponding pages may include the same checksum. Some operations fit well with the work done by the KSM process and can be obtained from Figure 3 For example, memory comparison enables the use of an accelerator to compare memories of any specified size, such as performing a page comparison for the current page and a stable tree or an unstable tree. The page checksum can also be calculated by the accelerator through a CRC generation operation.

[0034] The plurality of corresponding pages may be located at equivalent addresses relative to the corresponding memory region. The method may include grouping "co-located pages" as a pre-processing operation of the KSM (in Figure 3). That is, when the KSM function is invoked, the host hypervisor / OS first groups together each "same-location page" from all candidate memory region VMs. For each "same-location page" group, the corresponding stable tree and unstable tree are initialized. Subsequently, during KSM, the pages in each group will still be scanned and compared sequentially; however, pages from different groups can be operated in parallel. Note that page grouping requires disclosure of virtual address hints to the host OS / hypervisor so that pages at the same location can be identified and classified.

[0035] Disclosure addresses may be performed to enable determination that pages are in the same relative position. This allows translation of virtual addresses to physical addresses so that identical pages can be more easily batched together. Each memory region or VM may require address translation so that batching of identical pages can occur across memory regions.

[0036] The novelty of this approach lies in going beyond the common use of on-chip data movement accelerators (as seen with CRC and compare operations) and simple batching. A novel adaptive batching is proposed and, more importantly, the algorithmic use case (KSM) flow is restructured by exposing better batching opportunities and asynchronous operation of these key memory tasks. For example, batching based on relative memory space addresses builds on and improves upon the current KSM design, allowing for better coordination with accelerators that are well suited for such use.

[0037] Figure 5 5 shows an asynchronous software-accelerator interaction for page comparison in KSM. For higher efficiency, "batching between relative page groups" is introduced. The corresponding pages in each page group can be compared by the data movement accelerator 510 for merging. Figure 5 As shown in , the "search stable tree" operation is taken as an example, assuming that there are 12 "same-position page" groups. The batch method first selects one candidate page in each of the first 4 "same-position page" groups and prepares these candidate pages for the first iteration of searching the corresponding unstable tree, rather than completing each page scan and moving to the next candidate page. Moreover, the accelerator descriptor is prepared for each page comparison operation. Subsequently, four comparison descriptors are issued to the accelerator engine in batches and move to the next batch, where four pages from groups 5-8 will be prepared and compared. The same thing happens for the last batch (groups 9-12). Once the first batch of accelerator descriptors are completed, depending on the comparison results, the search is iterated to the next node in the corresponding unstable tree, or when there is a match, the page is excluded from the tree search of the next iteration. Similarly, the actual page comparison operation is performed by the accelerator 510 in an asynchronous manner.

[0038] Figure 6A method 600 for using a data movement accelerator of a processor when merging pages is shown, wherein the processor is associated with a memory. The method 600 includes: 620: loading a candidate page and a stored checksum from the memory; and when the candidate page matches or is determined to be a page in the first data structure at 625, then performing 630: merging the candidate page with the page in the first data structure. The first data structure includes multiple pages. If no match is found between the pages in the first data structure, then performing 633: calculating the current checksum of the candidate page. If the checksum matches the stored checksum of the candidate page, the method 600 further includes: if no match is found or determined to exist between the candidate page and the second data structure at 635, then performing 640: inserting the candidate page into the second data structure. The second data structure includes multiple pages. Otherwise, the method 600 includes: 650: merging the candidate page with the page in the second data structure, and moving the merged page to the first data structure. The data movement accelerator may perform: 625 : determine that there is a match between the candidate page and a page in the first data structure; 635 : determine that there is a match between the candidate page and a page in the second data structure; and 633 : calculate a current checksum.

[0039] The method 600 may further include: 610: batching pages from a plurality of memory regions for use in a data movement accelerator, wherein each memory region includes a plurality of candidate pages, wherein a plurality of page groups are determined, and wherein each page group includes a plurality of corresponding pages between the plurality of memory regions. A separate first data structure and a second data structure may be used for each page group, and the plurality of page groups are provided to the data movement accelerator for parallel processing.

[0040] like Figure 5 As shown in , grouping of "same-located pages" may be performed as a pre-processing operation for KSM. That is, when the KSM function is invoked, the host hypervisor / OS first groups together each "same-located page" from all candidate memory areas or VMs. For each "same-located page" group, the corresponding stable tree and unstable tree are initialized. Subsequently, during KSM, the pages in each group will still be scanned and compared sequentially; however, pages from different groups can be operated in parallel. Page grouping may require disclosure of virtual address hints to the host OS / hypervisor so that pages at the same location can be identified and classified.

[0041] like Figure 5As shown in , for software-accelerator interaction, the asynchronous programming model can further improve KSM efficiency and liberate the ability of the accelerator. For illustrative purposes, only 3 batches (each with 4 pages) are shown in the pipeline. However, in actual use, the accelerator computing operation may take much longer than the software part. Therefore, a larger batch size and more batches to be solved may be required. It should also be noted that other parts of KSM for different pages that have not been migrated to the accelerator can still be executed sequentially and synchronously in software.

[0042] The multiple memory areas in method 600 can be generated by booting from the same file. And, the multiple memory areas are memory areas of a virtual machine. This can increase the possibility that the memory area contains more candidate data for merging. Multiple corresponding pages may include identical data, or may include identical checksums. This can further increase the possibility that the corresponding page is a good candidate for merging. Multiple corresponding pages may be located at identical addresses relative to the corresponding memory areas. The first data structure in method 600 may be a stable tree, and the second data structure may be an unstable tree.

[0043] Fig. 7A and Figure 7B An analysis for migrating related KSM operations to a data movement accelerator is shown. Fig. 7A The improvement in operational throughput using the data movement accelerator for KSM-related operations is shown. Due to the high speed improvement, CRC32 is shown on the right axis. For all related operations, Fig. 7A In the example above, throughput improvements are immediately seen for all operations, with synchronous 4KB memory copies done only by the accelerator being almost identical to their CPU software counterparts. The more operations can be batched, the more significant the reduction in migration latency for the operations, resulting in greater gains. Since CRC32 is a compute-heavy operation, hardware acceleration results in very high speedups of between 50-440x, depending on the level of synchronization.

[0044] Figure 7BShows the CPU cycle utilization of the related KSM operations using the on-chip data movement accelerator. The figure shows the CPU cycles spent running the related operations on the accelerator. While the operations are serviced on the accelerator, the migrating core is free to run other processes while waiting for the completion of the migrated work. The fully asynchronous use of the accelerator devotes more cycles to migrating more descriptors, but still frees up CPU time once the descriptors are batched. As can be seen in actual use cases of the accelerator, moderate asynchrony and batching exhibit higher throughput and lower CPU cycle utilization. And, as we explained earlier, since the accelerator can perform memory comparisons in DRAM, there is no need to bring these pages to the CPU cache, which avoids polluting valuable cache resources and helps applications run on the core.

[0045] An apparatus for a processor or data movement accelerator may also perform the methods outlined above. The apparatus may be a processor or a data movement accelerator as described above. The hardware-software co-design approach optimizes important KSM services by leveraging on-chip accelerators, allowing candidate pages to be batched across memory regions or VMs at the same relative page address ("relative page group batching") and compared and CRC asynchronously via the accelerator. This approach can free the CPU from those heavy operations and effectively distribute access latency to the accelerator. This can also allow the CPU core to perform other tasks in parallel and fully utilize the accelerator processing power. In addition to performance gains, this approach can also greatly reduce CPU cache pollution caused by KSM's heavy memory operations. Figure 8 A schematic diagram showing an example of an apparatus 80 or device 80 for performing at least one method shown in the present disclosure, such as Figure 1 methods, Figure 2 methods and / or Figure 6 method. Figure 8 A computer system 800 including such an apparatus 80 or device 80 is further shown. The apparatus 80 includes circuitry for providing the functionality of the apparatus 80. For example, the circuitry of the apparatus 80 may be configured to provide the functionality of the apparatus 80. For example, Figure 8The device 80 includes an optional interface circuit system 82, a processor circuit system 84, and a memory circuit system 86. For example, the processor circuit system 84 may be coupled to the interface circuit system 82 and to the memory circuit system 86. For example, the processor circuit system 84 may be combined with the interface circuit system 82 (for example, exchanging information with other components inside or outside the computer system 800 including the device 80 or the apparatus 80) and the memory circuit system 86 (for storing information such as machine-readable instructions) to provide the functionality of the device. Similarly, the device 80 may include a device for providing the functionality of the device 80. For example, the device may be configured to provide the functionality of the device 80. The components of the device 80 are defined as component devices that may correspond to or be implemented by corresponding structural components of the device 80. For example, Figure 8 The device 80 includes: a device 84 for processing, which may correspond to the processor circuit system 84 or be implemented by the processor circuit system 84; a device 82 for communication, which may correspond to the interface circuit system 82 or be implemented by the interface circuit system 82; and (optionally) a device 86 for storing information, which may correspond to the memory circuit system 86 or be implemented by the memory circuit system 86. In general, the functions of the processor circuit system 84 or the device 84 for processing can be implemented by the processor circuit system 84 or the device 84 for processing executing machine-readable instructions. Therefore, any features attributed to the processor circuit system 84 or the device 84 for processing can be defined by one or more instructions of a plurality of machine-readable instructions. The device 80 or apparatus 80 may include machine-readable instructions (for example, within the memory circuit system 86, the storage circuit system (not shown), or the device 86 for storing information). For example, the processor circuit system 84 or the device 84 for processing may perform the method shown in the present disclosure, such as in combination with Figure 1 The methods discussed, combined Figure 2 The methods discussed, or a combination of Figure 6 The method discussed.

[0046] The interface circuit system 82 or the means for communicating 82 may correspond to one or more inputs and / or outputs for receiving and / or transmitting information within a module, between modules, or between modules of different entities, which information may be in the form of digital (bit) values ​​according to a specified code. For example, the interface circuit system 82 or the means for communicating 82 may include a circuit system configured to receive and / or transmit information.

[0047] For example, the processor circuit system 84 or the means for processing 84 may be implemented using one or more processing units, one or more processing devices, or any means for processing, such as a processor, a computer, or a programmable hardware component operable with correspondingly adapted software. In other words, the functions of the described processor circuit system 84 or the means for processing may also be implemented using software, which is then executed on one or more programmable hardware components. Such hardware components may include general-purpose processors, digital signal processors (DSPs), microcontrollers, etc.

[0048] For example, the memory circuitry 86 or means for storing information 86 may be a volatile memory, such as a random access memory, such as a dynamic random-access memory (DRAM) or a static random-access memory (SRAM).

[0049] For example, computer system 800 may be at least one of the following: a client computer system, a server computer system, a rack server, a desktop computer system, a mobile computer system, a security gateway, and a router. Mobile device 800 may be one of the following: a smart phone, a tablet computer, a wearable device, or a mobile computer.

[0050] An example (e.g., Example 1) relates to a method for batching pages for use in a data movement accelerator of a processor, the method comprising: determining a plurality of memory regions having similar contents according to a similarity criterion, wherein each memory region comprises a plurality of pages; determining a plurality of page groups, wherein each page group comprises a plurality of corresponding pages between the plurality of memory regions; and providing the plurality of page groups to a data movement accelerator for parallel processing.

[0051] Another example (eg, Example 2) relates to the previously described example (eg, Example 1), in which each of the plurality of memory areas is generated by booting from the same file.

[0052] Another example (eg, Example 3) relates to the previously described example (eg, Example 2), wherein the plurality of memory regions are memory regions of a virtual machine.

[0053] Another example (eg, Example 4) relates to a previously described example (eg, one of Examples 1-3), wherein a plurality of corresponding pages include identical data.

[0054] Another example (eg, Example 5) relates to a previously described example (eg, one of Examples 1-4), wherein a plurality of corresponding pages include the same checksum.

[0055] Another example (eg, Example 6) relates to a previously described example (eg, one of Examples 1-5), wherein a plurality of corresponding pages are located at identical addresses relative to respective memory regions.

[0056] Another example (eg, Example 7) relates to a previously described example (eg, one of Examples 1-6), wherein corresponding pages in each page group are compared by the data movement accelerator for merging.

[0057] An example (e.g., Example 8) relates to an apparatus for batching pages for use in a data movement accelerator of a processor, the apparatus comprising a memory circuit system, machine-readable instructions, and a processor circuit system for executing the machine-readable instructions to perform the method described in a previously described example (e.g., one of Examples 1-7).

[0058] An example (e.g., Example 9) relates to an apparatus for batching pages for use in a data movement accelerator of a processor, the apparatus comprising a processor circuit system configured to perform the method described in a previously described example (e.g., one of Examples 1-7).

[0059] An example (eg, Example 10) relates to an apparatus for batching pages for use in a data movement accelerator of a processor, the apparatus comprising means for performing a method as described in a previously described example (eg, one of Examples 1-7).

[0060] An example (e.g., Example 11) relates to a non-transitory computer-readable medium comprising program code that, when executed on a processor, a computer, or a programmable hardware component, causes the processor, the computer, or the programmable hardware component to perform the method described in a previously described example (e.g., one of Examples 1-7).

[0061] An example (eg, Example 12) relates to a computer program having a program code for executing the method described in a previously described example (eg, one of Examples 1-7) when the computer program is executed on a computer, a processor, or a programmable hardware component.

[0062] An example (e.g., Example 13) relates to a method for using a data movement accelerator of a processor when merging pages, wherein the processor is associated with a memory, the method comprising: loading a candidate page and a stored checksum from the memory; merging the candidate page with a page in a first data structure if the candidate page matches a page in a first data structure, the first data structure comprising multiple pages; and if no match is found among the pages in the first data structure and the current checksum of the candidate page matches the stored checksum of the candidate page, then: if no match is found between the candidate page and multiple pages in a second data structure, inserting the candidate page into the second data structure; or, merging the candidate page with a page in the second data structure and moving the merged page to the first data structure, wherein at least one of the following is performed using the data movement accelerator: determining a match between the candidate page and a page in the first data structure; determining a match between the candidate page and a page in the second data structure; and calculating a current checksum.

[0063] Another example (e.g., Example 14) relates to the previously described example (e.g., Example 13), further comprising: batching pages from multiple memory regions for use with a data movement accelerator, wherein each memory region includes multiple candidate pages, wherein: multiple page groups are determined, wherein each page group includes multiple corresponding pages between the multiple memory regions; and separate first and second data structures are used for each page group, and the multiple page groups are provided to the data movement accelerator for parallel processing.

[0064] Another example (eg, Example 15) relates to the previously described example (eg, Example 14), wherein each of the plurality of memory areas is generated by booting from the same file.

[0065] Another example (eg, Example 16) relates to a previously described example (eg, one of Examples 14-15), wherein the plurality of memory regions are memory regions of a virtual machine.

[0066] Another example (eg, Example 17) relates to a previously described example (eg, one of Examples 14-16), wherein a plurality of corresponding pages include identical data.

[0067] Another example (eg, Example 18) relates to a previously described example (eg, one of Examples 14-17), wherein a plurality of corresponding pages include the same checksum.

[0068] Another example (eg, Example 19) relates to a previously described example (eg, one of Examples 14-18), wherein a plurality of corresponding pages are located at identical addresses relative to a corresponding memory region.

[0069] Another example (eg, Example 20) relates to a previously described example (eg, one of Examples 13-19), wherein the first data structure is a stable tree and the second data structure is an unstable tree.

[0070] An example (e.g., Example 21) relates to an apparatus for using a data movement accelerator of a processor during page merging, the apparatus comprising a memory circuit system, machine-readable instructions, and a processor circuit system for executing the machine-readable instructions to perform the method described in a previously described example (e.g., one of Examples 13-20).

[0071] An example (e.g., Example 22) relates to an apparatus for using a data movement accelerator of a processor during page merging, the apparatus comprising a processor circuit system configured to perform the method described in a previously described example (e.g., one of Examples 13-20).

[0072] An example (eg, Example 23) relates to an apparatus for using a data movement accelerator of a processor during page merging, the apparatus comprising means for performing the method described in a previously described example (eg, one of Examples 13-20).

[0073] An example (e.g., Example 24) relates to a non-transitory computer-readable medium comprising program code that, when executed on a processor, a computer, or a programmable hardware component, causes the processor, the computer, or the programmable hardware component to perform the method described in a previously described example (e.g., one of Examples 1-7).

[0074] An example (eg, Example 25) relates to a non-transitory machine-readable storage medium comprising program code that, when executed, causes a machine to perform the method described in a previously described example (eg, one of Examples 13-20).

[0075] An example (eg, Example 26) relates to a computer program having a program code for executing the method described in a previously described example (eg, one of Examples 13-20).

[0076] The aspects and features described in relation to a specific example in the foregoing examples may also be combined with one or more of the other examples to replace the same or similar features of the other examples or to additionally introduce these features into the other examples.

[0077] Examples may further be or relate to (computer) programs, including program codes for executing one or more of the above methods when the program is executed on a computer, a processor, or other programmable hardware component. Thus, the steps, operations, or processes of the different methods in the methods described above may also be performed by a programmed computer, a processor, or other programmable hardware component. Examples may also encompass program storage devices, such as digital data storage media, which are machine-readable, processor-readable, or computer-readable and encode and / or contain machine-executable, processor-executable, or computer-executable programs and instructions. For example, a program storage device may include or may be a digital storage device, a magnetic storage medium (such as a disk and a tape), a hard drive, or an optically readable digital data storage medium. Other examples may also include a computer, a processor, a control unit, a (field) programmable logic array ((field) programmable logic array, (F) PLA), a (field) programmable gate array ((field) programmable gate array, (F) PGA), a graphics processor unit (GPU), an application-specific integrated circuit (ASIC), an integrated circuit (IC), or a system-on-a-chip (SoC) system programmed to perform the steps of the method described above.

[0078] It is also understood that the disclosure of several steps, processes, operations or functions disclosed in the specification or claims should not be interpreted as implying that these operations must be in the described order, unless explicitly stated in a separate use case or necessary for technical reasons. Therefore, the previous description does not limit the performance of several steps or functions to a certain order. In addition, in other examples, a single step, function, process or operation may include and / or be decomposed into several sub-steps, sub-functions, sub-processes or sub-operations.

[0079] If some aspects have been described in conjunction with a device or system, these aspects should also be understood as descriptions of corresponding methods. For example, a block, device, or functional aspects of a device or system may correspond to features (such as method steps) of a corresponding method. Accordingly, aspects described in conjunction with a method should also be understood as descriptions of properties or functional features of the corresponding block, corresponding element, corresponding device, or corresponding system.

[0080] As used herein, the term "module" refers to a logic for performing one or more operations in accordance with the present disclosure that can be implemented using hardware components or devices, software or firmware running on a processing unit, or a combination thereof. Software and firmware can be embodied as instructions and / or data stored on a non-transient computer-readable storage medium. As used herein, the term "circuitry" can include, alone or in any combination, non-programmable (hard-wired) circuitry, programmable circuitry (such as a processing unit), state machine circuitry, and / or firmware storing instructions that can be executed by a programmable circuitry. The modules described herein can be embodied together or individually as circuitry forming part of a computing system. Thus, any one of the modules can be implemented as a circuitry. A computing system that is referred to as being programmed to perform a method can be programmed to perform the method via software, hardware, firmware, or a combination thereof.

[0081] Any of the disclosed methods (or portions thereof) may be implemented as computer-executable instructions or computer program products. Such instructions may enable a computing system or one or more processing units capable of executing computer-executable instructions to perform any of the disclosed methods. As used herein, the term "computer" refers to any computing system or device described or mentioned herein. Thus, the term "computer-executable instructions" refers to instructions that can be executed by any computing system or device described or mentioned herein.

[0082] Computer executable instructions may be, for example, part of an operating system of a computing system, an application stored locally on a computing system, or a remote application accessible to a computing system (e.g., via a web browser). Any of the methods described herein may be performed by computer executable instructions, which are executed by a single computing system or by one or more networked computing systems operating in a network environment. Computer executable instructions and updates to computer executable instructions may be downloaded from a remote server to a computing system.

[0083] Further, it should be understood that implementation of the disclosed techniques is not limited to any particular computer language or program. For example, the disclosed techniques may be implemented by software written in C++, C#, Java, Perl, Python, JavaScript, Adobe Flash, C#, assembly language, or any other programming language. Likewise, the disclosed techniques are not limited to any particular computer system or any particular type of hardware.

[0084] In addition, any of the software-based examples (including, for example, computer-executable instructions for causing a computer to perform any of the disclosed methods) can be uploaded, downloaded, or remotely accessed via suitable communication means. Such suitable communication means include, for example, the Internet, the World Wide Web, an intranet, cables (including fiber optic cables), magnetic communications, electromagnetic communications (including RF, microwave, ultrasonic, and infrared communications), electronic communications, or other such communication means.

[0085] The disclosed methods, apparatuses, and systems should not be interpreted as limiting in any way. Instead, the present disclosure is directed to all novel and non-obvious features and aspects of each disclosed example, individually and in various combinations and sub-combinations with each other. The disclosed methods, apparatuses, and systems are not limited to any specific aspect, feature, or combination thereof, nor do the disclosed examples require the existence of any one or more specific advantages or the resolution of any one or more specific problems.

[0086] The theories of operation, scientific principles or other theoretical descriptions proposed herein with reference to the devices or methods of the present disclosure are provided for the purpose of better understanding and are not intended to limit the scope. The devices and methods in the attached claims are not limited to those devices and methods that work in the manner described by such operational theories. The attached claims are thus included in the specific implementation, wherein each claim itself can be used as a separate example. It should also be noted that although the dependent claims in the claims refer to a specific combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are explicitly proposed here, unless it is stated in individual cases that a specific combination is not intended. In addition, even if a claim is not directly limited to citing any other independent claim, the features of the claim should also be included for any other independent claim.

Claims

1. A method for batching pages for use in a data movement accelerator of a processor, the method comprising: determining a plurality of memory regions having similar contents according to a similarity criterion, wherein each memory region includes a plurality of pages; determining a plurality of page groups, wherein each page group includes a plurality of corresponding pages between the plurality of memory regions; as well as The plurality of page groups are provided to the data movement accelerator for parallel processing.

2. The method of claim 1, wherein: Each of the plurality of memory areas is generated by booting from the same file.

3. The method of claim 2, wherein: The plurality of memory areas are memory areas of a virtual machine.

4. The method according to any one of claims 1 to 3, wherein: The plurality of corresponding pages include identical data.

5. The method according to any one of claims 1 to 3, wherein: The plurality of corresponding pages include a same checksum.

6. The method according to any one of claims 1 to 3, wherein: The plurality of corresponding pages are located at identical addresses relative to the respective memory regions.

7. The method according to any one of claims 1 to 3, wherein: The plurality of corresponding pages in each page group are compared by the data movement accelerator for merging.

8. An apparatus for batching pages for use in a data movement accelerator of a processor, the apparatus comprising memory circuitry, machine readable instructions, and processor circuitry for executing the machine readable instructions to perform the method of any one of claims 1 to 7.

9. A non-transitory computer-readable medium comprising a program code, which, when executed on a processor, a computer or a programmable hardware component, causes the processor, the computer or the programmable hardware component to perform the method as claimed in any one of claims 1 to 7.

10. A method for using a data movement accelerator of a processor during page merging, wherein: The processor is associated with a memory, and the method comprises: load the candidate page and the stored checksum from memory; If the candidate page matches a page in a first data structure, merging the candidate page with the page in the first data structure, the first data structure comprising a plurality of pages; and If no match is found among the pages in the first data structure and the current checksum of the candidate page matches the stored checksum of the candidate page, then: If no match is found between the candidate page and a plurality of pages in the second data structure, inserting the candidate page into the second data structure, or, merging the candidate page with a page in the second data structure, and moving the merged page to the first data structure, Wherein at least one of the following is performed using the data movement accelerator: determining a match between the candidate page and a page in the first data structure; determining a match between the candidate page and a page in the second data structure; and calculating the current checksum.

11. The method of claim 10, further comprising: Pages are batched from a plurality of memory regions for use in the data movement accelerator, wherein each memory region includes a plurality of candidate pages, wherein: A plurality of page groups are determined, wherein each page group includes a plurality of corresponding pages between the plurality of memory regions; and A separate first data structure and second data structure are used for each page group, and The plurality of page groups are provided to the data movement accelerator for parallel processing.

12. The method of claim 11, wherein: Each of the plurality of memory areas is generated by booting from the same file.

13. The method of claim 11, wherein: The plurality of memory areas are memory areas of a virtual machine.

14. The method of claim 11, wherein: The plurality of corresponding pages include identical data.

15. The method according to any one of claims 11 to 14, wherein: The plurality of corresponding pages include a same checksum.

16. The method according to any one of claims 11 to 14, wherein: The plurality of corresponding pages are located at identical addresses relative to the respective memory regions.

17. The method according to any one of claims 10 to 14, wherein: The first data structure is a stable tree and the second data structure is an unstable tree.

18. An apparatus for using a data movement accelerator of a processor when merging pages, the apparatus comprising memory circuitry, machine readable instructions, and processor circuitry, the processor circuitry being configured to execute the machine readable instructions to perform the method of any one of claims 10 to 17.

19. A non-transitory computer-readable medium comprising a program code, which, when executed on a processor, a computer or a programmable hardware component, causes the processor, the computer or the programmable hardware component to perform the method as claimed in any one of claims 10 to 17.

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