AXI bus matrix interface based on priority queue

Abstract

The invention relates to the technical field of integrated circuits, and particularly discloses an AXI bus matrix interface based on a priority queue, which comprises a data wrapper, a priority decoder, a first data distributor, a second data distributor, a plurality of FIFO queues, a first data selector, a second data selector and a priority arbiter, the data wrapper is connected with the first data distributor, the priority decoder is respectively connected with the first data distributor, the second data distributor and the second data selector, and each FIFO queue is respectively connected with the first data distributor, the second data distributor, the first data selector, the second data selector and the priority arbiter. And the priority arbiter is connected with the first data selector. According to the method, priority decoding and scheduling can be carried out on the transactions, so that priority processing of the transactions with high priorities is ensured, the problem of priority overturning is eliminated, and the real-time performance of the system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to an AXI bus matrix interface based on a priority queue. Background Art

[0002] The AXI (Advanced eXtensible Interface) bus is a high-performance, high-bandwidth bus protocol that is widely used in system-on-chip (SoC) to connect processors, storage controllers, peripherals and other modules. The design of the AXI bus protocol provides multi-channel concurrent transmission capabilities, including read and write data channels, address channels and control channels, so that data transmission can be carried out efficiently and quickly. Especially in the application scenarios of multi-core processors, complex peripherals and high-speed storage devices, the high bandwidth and low latency characteristics of the AXI bus are fully utilized.

[0003] The AXI bus matrix is ​​an interconnect structure that connects multiple hosts and slaves, and is responsible for caching, routing, and arbitrating transactions between multiple hosts and slaves. The bus matrix is ​​usually composed of a bus matrix interface (host interface and slave interface), a routing module, and an arbiter module. The bus matrix interface usually uses a FIFO (First-In-First-Out) queue as a cache queue to temporarily store transmission transactions. The design of the FIFO queue is widely used because of its simple structure and easy implementation. Each transaction is queued in the order of its arrival and waits for processing in the queue, ensuring the orderly transmission and processing of data. This FIFO queue method can effectively improve the data transmission efficiency, especially for simple transactions with no priority differences.

[0004] However, as the complexity of the system increases, the number of transactions that need to be processed in the AXI bus matrix increases significantly, and the priority differences of transactions become increasingly important. In particular, in modern on-chip systems, there are usually multiple hosts that initiate requests to multiple slaves at the same time, and the priority and timing requirements of these requests often differ. In order to implement the Outstanding feature in the AXI protocol, that is, the ability of the host to initiate multiple transaction transmissions when no response is received. It is necessary to design FIFOs in the bus matrix interface (including slave interface and host interface) to cache unfinished transactions. At this time, in the traditional FIFO queue, the order of transaction processing is strictly based on the "first in, first out" principle, which means that the first transaction in the queue must be processed before the later transaction. However, the FIFO queue cannot be dynamically scheduled according to the priority of the transaction, which causes the "priority flip" problem. Specifically, when a low-priority transaction arrives at the FIFO queue before a high-priority transaction, the high-priority transaction needs to wait for the low-priority transaction to be executed before it can be processed, thereby delaying the execution of the high-priority transaction. This delay not only affects the real-time performance of the system, but may also cause the system to respond slowly and affect the overall performance.

[0005] like Figure 1 As shown in the figure, a traditional AXI bus matrix slave interface first packages and splices the signal in a certain channel of the AXI bus, such as the AW channel, and then stores it in the FIFO queue. The handshake signal AWVALID in the AXI protocol acts as the write enable of the FIFO, and the non-full signal of the FIFO acts as the handshake signal AWREADY of the slave. When the host pulls up AWVALID and the FIFO is not full, that is, AWREADY is 1, the transaction is written into the FIFO queue. This approach is simple and easy to implement, but the problem is that it ignores the priority in the transaction. The transactions entering the FIFO queue are strictly stored and read out according to the "first in, first out" rule. This design will cause priority reversal, affecting the real-time performance and communication efficiency of the system. Figure 2 As shown, it is assumed that priority 1 is greater than priority 0. Transaction 0 enters the FIFO queue first, followed by transaction 1, and finally transaction 2. According to the "first in, first out" principle of the FIFO queue, the order of transaction processing is transaction 0 → transaction 1 → transaction 2. Although the priority of transaction 2 (priority 1) is higher than the priority of transaction 0 and transaction 1 (priority 0), it enters the queue later and must wait for the previous low-priority transaction to be processed before it can be processed. This waiting will cause a delay in the high-priority transaction (transaction 2), which will cause a priority flip problem. Therefore, the traditional AXI bus matrix interface uses a FIFO queue and cannot be dynamically scheduled according to the priority of the transaction, resulting in a priority flip problem, which affects the real-time performance and communication efficiency of the system. Summary of the invention

[0006] In order to solve the deficiencies in the prior art, the present invention provides an AXI bus matrix interface based on priority queues. By introducing multiple FIFO queues and combining the QoS signal in the AXI protocol, transactions are prioritized and scheduled, thereby ensuring that transactions with high priority can be processed first, eliminating the priority flip problem, improving the real-time performance of the system, and reducing congestion.

[0007] As a first aspect of the present invention, an AXI bus matrix interface based on a priority queue is provided, wherein the AXI bus matrix interface based on the priority queue comprises a data encapsulator, a priority decoder, a first data distributor, a second data distributor, a plurality of FIFO queues, a first data selector, a second data selector and a priority arbitrator, wherein the plurality of FIFO queues constitute a priority queue for storing AXI transaction signals of different priorities, the data encapsulator is connected to the first data distributor, the priority decoder is respectively connected to the first data distributor, the second data distributor and the second data selector, each of the FIFO queues is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector and the priority arbitrator, the priority arbitrator is connected to the first data selector, wherein, The data encapsulator is responsible for packaging and splicing different signals in a single channel in the AXI protocol into a multi-bit AXI transaction signal; The priority decoder is responsible for decoding the Qos signal in the single channel to obtain the priority of the AXI transaction signal; The first data distributor distributes the AXI transaction signal to the data input end of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal; the second data distributor distributes the VALID signal in the single channel to the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal; the second data selector selects the non-full signal of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal, so as to use the non-full signal of the FIFO queue of the corresponding priority as the READY signal in the single channel; when the VALID signal and the READY signal in the single channel are 1 at the same time, the write enable of the FIFO queue of the corresponding priority is valid, and the first data distributor stores the AXI transaction signal in the FIFO queue of the corresponding priority; The priority arbitrator performs priority arbitration according to non-empty signals of multiple FIFO queues to obtain priority arbitration results of multiple FIFO queues; wherein the arbitration principle is that the AXI transaction signal in the high-priority FIFO queue is transmitted first; The first data selector transmits the AXI transaction signal in the high-priority FIFO queue to the subsequent polling arbiter and routing module of the bus matrix.

[0008] Furthermore, in the AXI protocol, the Qos signal is a quality of service signal extension signal, which is used to indicate the priority of the AXI transaction signal, wherein the two-bit Qos signals 00, 01, 10, 11 represent priority 0, priority 1, priority 2, and priority 3 respectively.

[0009] Further, four FIFO queues form a priority queue, FIFO queue 0 is used to store AXI transaction signals with a priority of 0, FIFO queue 1 is used to store AXI transaction signals with a priority of 1, FIFO queue 2 is used to store AXI transaction signals with a priority of 2, and FIFO queue 3 is used to store AXI transaction signals with a priority of 3. Taking the AW channel as an example, the data encapsulator splices and encapsulates the AWID, AWADDR, AWLEN, AWSIZE, AMUSER, AWLOCK, AWPROT, AWREGION, and AWQOS signals in the AW channel sent by the host into a multi-bit AXI transaction signal AW_Trancation; The priority decoder is responsible for decoding the two-bit AWQOS signal in the AW channel to obtain the priority of the AXI transaction signal AW_Trancation; The first data distributor distributes the AXI transaction signal AW_Trancation to the data input end of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data distributor distributes the AWVALID signal in the AW channel to a FIFO queue of corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data selector selects a non-full signal of a FIFO queue of a corresponding priority according to the priority of the AXI transaction signal AW_Trancation, so as to use the non-full signal of the FIFO queue of the corresponding priority as the AWREADY signal in the AW channel; when the AWVALID signal and the AWREADY signal in the AW channel are both 1, the write enable of the FIFO queue of the corresponding priority is valid, and the first data distributor stores the AXI transaction signal AW_Trancation into the FIFO queue of the corresponding priority for caching; The priority arbitrator performs priority arbitration according to the non-empty signals of the four FIFO queues to obtain priority arbitration results of the four FIFO queues; wherein the arbitration principle is that the AXI transaction signal AW_Trancation in the high-priority FIFO queue is transmitted first; The first data selector transmits the AXI transaction signal AW_Trancation in the high-priority FIFO queue to the subsequent polling arbiter and routing module of the bus matrix.

[0010] Furthermore, an empty flag signal of 1 indicates that there is no data in the FIFO queue. Conversely, the empty flag signal is inverted to obtain a non-empty signal. A non-empty signal of 1 indicates that there is unread data in the FIFO queue. Therefore, the non-empty signals of the four FIFO queues are derived as arbitration request signals of the four FIFO queues.

[0011] Furthermore, the write enable of the FIFO queue is determined by the AWVALID signal and the AWREADY signal of the AW channel, which are handshake signals in the AXI protocol; the transmission of an AXI transaction signal can be completed only when the AWVALID signal and the AWREADY signal are both high levels; When the AWVALID signal is high, it indicates that the AXI transaction signal of this cycle is valid, otherwise it is invalid; When the AWREADY signal is high, it indicates that the FIFO queue of this cycle is idle and can receive AXI transaction signals. When the AWREADY signal is low, it indicates that the FIFO queue of this cycle is full and cannot receive AXI transaction signals.

[0012] Furthermore, when the host sends three AW channel transaction signals in succession, in the time order of transaction 0, transaction 1 and transaction 2, the priority of transaction 0 is 0, and the priorities of transaction 1 and transaction 2 are both 1, and priority 1 is specified to be higher than priority 0; The host first sends transaction 0, the data encapsulator encapsulates each signal of the AW channel, the Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 0 is 0, and the second data selector selects the non-full signal of FIFO queue 0 as the AWREADY signal according to the decoding result, and the AWREADY signal is 1 at this time; similarly, the second data distributor sends the AWVALID signal to FIFO queue 0 according to the decoding result, the AWVALID signal and the AWREADY signal are 1 at the same time, the write enable of FIFO queue 0 is valid, and the first data distributor stores transaction 0 in the corresponding FIFO queue 0; Next, the host sends transaction 1. Similarly, the data encapsulator encapsulates each signal of the AW channel. The Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 1 is 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. The AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are 1 at the same time, the write enable of FIFO queue 1 is valid, and the first data distributor stores transaction 1 in the corresponding FIFO queue 1. Next, the host sends transaction 2. Similarly, the data encapsulator encapsulates each signal of the AW channel. The Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 2 is also 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. The AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are 1 at the same time. The write enable of FIFO queue 1 is valid. At this time, FIFO queue 1 is not full and can be written normally. Therefore, the first data distributor also stores transaction 2 in the corresponding FIFO queue 1. When transactions 0, 1, and 2 are all stored in the corresponding FIFO queues, there are transactions in both FIFO queues 0 and 1, and the non-empty signals of FIFO queues 0 and 1 are both 1, acting as arbitration request signals. Because FIFO queue 1 has a high priority, the priority arbitrator first allows transactions in FIFO queue 1 to be read out. Because the rule of the FIFO queue is first-in-first-out, transaction 1 in FIFO queue 1 is read out first. In the next cycle, because there are still transactions stored in FIFO queues 0 and 1, the next round of arbitration is carried out, and the priority arbitrator also allows FIFO queue 1 to be read out first. At this time, transaction 2 in FIFO queue 1 is read out. In the next cycle, because all the data in FIFO queue 1 has been read out, only FIFO queue 0 participates in arbitration. The priority arbitrator allows FIFO queue 0 to be read out, and transaction 0 in FIFO queue 0 is read out.

[0013] The present invention provides an AXI bus matrix interface based on a priority queue, which has the following advantages: by introducing a priority queue and combining the Qos signal in the AXI protocol, transactions are prioritized and scheduled, thereby effectively solving the performance problem caused by improper priority scheduling in a traditional FIFO queue, ensuring that high-priority transactions can be processed first, eliminating the priority flip problem, improving the throughput and real-time performance of the system, and avoiding the transaction delay problem caused by priority flip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0015] Figure 1 It is a structural diagram of a traditional AXI bus matrix interface.

[0016] Figure 2 A “first-in, first-out” diagram of a FIFO queue in a traditional AXI bus matrix interface.

[0017] Figure 3 The figure is a schematic diagram of the structure of the AXI bus matrix interface based on priority queue proposed by the present invention.

[0018] Figure 4 This is a schematic diagram of the application of the priority queue-based AXI bus matrix interface proposed by the present invention. DETAILED DESCRIPTION

[0019] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation method, structure, features and effects of an AXI bus matrix interface based on a priority queue proposed by the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] In the interpretation of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense unless otherwise specified. For example, the connection can be a fixed connection, or it can be connected through a special interface, or it can be indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] In this embodiment, an AXI bus matrix interface based on a priority queue is provided, such as Figure 3 As shown, the AXI bus matrix interface based on the priority queue includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, a plurality of FIFO queues, a first data selector, a second data selector and a priority arbitrator, wherein the plurality of FIFO queues constitute a priority queue for storing AXI transaction signals of different priorities, the data encapsulator is connected to the first data distributor, the priority decoder is respectively connected to the first data distributor, the second data distributor and the second data selector, each of the FIFO queues is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector and the priority arbitrator, the priority arbitrator is connected to the first data selector, wherein, The data encapsulator is responsible for packaging and splicing different signals in a single channel in the AXI protocol into a multi-bit AXI transaction signal so that it can be stored in a single FIFO queue without the need for multiple FIFO queues to cache different signals in the channel respectively; The priority decoder is responsible for decoding the Qos signal in the single channel to obtain the priority of the AXI transaction signal; The first data distributor distributes the AXI transaction signal to the data input end of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal; the second data distributor distributes the VALID signal in the single channel to the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal; the second data selector selects the non-full signal of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal, so as to use the non-full signal of the FIFO queue of the corresponding priority as the READY signal in the single channel; when the VALID signal and the READY signal in the single channel are 1 at the same time, the write enable of the FIFO queue of the corresponding priority is valid, and the first data distributor stores the AXI transaction signal in the FIFO queue of the corresponding priority; The priority arbitrator performs priority arbitration according to non-empty signals of multiple FIFO queues to obtain priority arbitration results of multiple FIFO queues; wherein the arbitration principle is that the AXI transaction signal in the high-priority FIFO queue is transmitted first; The first data selector transmits the AXI transaction signal in the high-priority FIFO queue to the subsequent polling arbiter and routing module of the bus matrix.

[0023] Specifically, in the AXI protocol, the Qos signal is a quality of service signal extension signal, which is used to indicate the priority of the AXI transaction signal, wherein the two-bit Qos signals 00, 01, 10, 11 represent priority 0, priority 1, priority 2, and priority 3, respectively.

[0024] Preferably, four FIFO queues form a priority queue, FIFO queue 0 is used to store AXI transaction signals with a priority of 0, FIFO queue 1 is used to store AXI transaction signals with a priority of 1, FIFO queue 2 is used to store AXI transaction signals with a priority of 2, and FIFO queue 3 is used to store AXI transaction signals with a priority of 3. Taking the AW channel as an example, the data encapsulator concatenates and encapsulates the AWID, AWADDR, AWLEN, AWSIZE, AMUSER, AWLOCK, AWPROT, AWREGION, and AWQOS signals in the AW channel sent by the host into a multi-bit AXI transaction signal AW_Trancation; the encapsulated AXI transaction signal AW_Trancation needs to be cached in the FIFO queue. Since multiple FIFO queues are designed to form a priority queue to store transactions of different priorities, a signal is needed to distinguish the priority of the transaction.

[0025] The priority decoder is responsible for decoding the two-bit AWQOS signal in the AW channel to obtain the priority of the AXI transaction signal AW_Trancation; The first data distributor distributes the AXI transaction signal AW_Trancation to the data input end of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data distributor distributes the AWVALID signal in the AW channel to a FIFO queue of corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data selector selects a non-full signal of a FIFO queue of a corresponding priority according to the priority of the AXI transaction signal AW_Trancation, so as to use the non-full signal of the FIFO queue of the corresponding priority as the AWREADY signal in the AW channel, so as to ensure that the writing of the transaction is stopped when the corresponding FIFO queue is full; when the AWVALID signal and the AWREADY signal in the AW channel are both 1, the write enable of the FIFO queue of the corresponding priority is valid, and the first data distributor stores the AXI transaction signal AW_Trancation into the FIFO queue of the corresponding priority for caching; The priority arbitrator performs priority arbitration according to the non-empty signals of the four FIFO queues to obtain the priority arbitration results of the four FIFO queues; wherein, the arbitration principle is that the AXI transaction signal AW_Trancation in the high-priority FIFO queue is transmitted first; the first data selector transmits the AXI transaction signal AW_Trancation in the high-priority FIFO queue to the subsequent polling arbitrator and routing module of the bus matrix. For example, if FIFO queue 3 and FIFO queue 2 send arbitration requests at the same time, the priority arbitrator will pass the request of FIFO queue 3, and the arbitration result will act on data selector 1. Data selector 1 selects the transaction of FIFO queue 3 and transmits it to the subsequent polling arbitrator and routing module of the bus matrix.

[0026] It should be noted that the empty flag signal is generally empty. Empty is 1, which means there is no data in the FIFO queue. Conversely, the empty flag signal is inverted to obtain a non-empty signal, which is generally represented by the signal name !empty. The non-empty signal is 1, which means there is unread data in the FIFO queue. Therefore, the non-empty signals of the four FIFO queues are derived as arbitration request signals of the four FIFO queues.

[0027] Specifically, the AWREADY signal is controlled by the FIFO queue. The FIFO queue usually has an empty flag and a full flag to indicate the storage status inside the FIFO queue. The full flag is generally represented by the signal name full. The full signal is 1, indicating that the data stored in the FIFO queue has reached the upper limit and no more data should be written to it. In the AXI bus matrix interface, it is necessary to ensure that the FIFO queue used to cache transactions will not overflow, that is, stop writing when the FIFO queue is full, so the full signal is inverted to obtain the non-full signal !full.

[0028] Preferably, the write enable of the FIFO queue is determined by the AWVALID signal and the AWREADY signal of the AW channel, and the AWVALID signal and the AWREADY signal are handshake signals in the AXI protocol; the transmission of an AXI transaction signal can be completed only when the AWVALID signal and the AWREADY signal are both high level; When the AWVALID signal is high, it indicates that the AXI transaction signal of this cycle is valid, otherwise it is invalid; When the AWREADY signal is high, it indicates that the FIFO queue of this cycle is idle and can receive AXI transaction signals. When the AWREADY signal is low, it indicates that the FIFO queue of this cycle is full and cannot receive AXI transaction signals.

[0029] Specifically, when the host sends three AW channel transaction signals in succession, in chronological order, they are transaction 0, transaction 1, and transaction 2. The priority of transaction 0 is 0, and the corresponding two-bit Qos signal value is 00; the priority of transaction 1 and transaction 2 are both 1, and the corresponding two-bit Qos signal value is 01, which stipulates that priority 1 is higher than priority 0; The host first sends transaction 0, the data encapsulator encapsulates each signal of the AW channel, the Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 0 is 0, and the second data selector selects the non-full signal of FIFO queue 0 as the AWREADY signal according to the decoding result, and the AWREADY signal is 1 at this time; similarly, the second data distributor sends the AWVALID signal to FIFO queue 0 according to the decoding result, the AWVALID signal and the AWREADY signal are 1 at the same time, the write enable of FIFO queue 0 is valid, and the first data distributor stores transaction 0 in the corresponding FIFO queue 0; Next, the host sends transaction 1. Similarly, the data encapsulator encapsulates each signal of the AW channel. The Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 1 is 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. The AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are 1 at the same time, the write enable of FIFO queue 1 is valid, and the first data distributor stores transaction 1 in the corresponding FIFO queue 1. Next, the host sends transaction 2. Similarly, the data encapsulator encapsulates each signal of the AW channel. The Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 2 is also 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. The AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are 1 at the same time. The write enable of FIFO queue 1 is valid. At this time, FIFO queue 1 is not full and can be written normally. Therefore, the first data distributor also stores transaction 2 in the corresponding FIFO queue 1. When transactions 0, 1, and 2 are stored in the corresponding FIFO queues, the subsequent polling arbitrator and routing module in the AXI bus matrix send signals to read out the transactions in the interface, and the priority arbitrator is needed to determine the order in which the transactions are read out. At this time, there are transactions in both FIFO queue 0 and FIFO queue 1, and the non-empty signals of FIFO queue 0 and FIFO queue 1 are both 1, acting as arbitration request signals. Because FIFO queue 1 has a high priority, the priority arbitrator first allows the transaction in FIFO queue 1 to be read out. Because the rule of the FIFO queue is first-in-first-out, transaction 1 in FIFO queue 1 is read out first; in the next cycle, because there are still transactions stored in FIFO queue 0 and FIFO queue 1, the next round of arbitration is carried out, and the priority arbitrator also allows FIFO queue 1 to be read out first. At this time, transaction 2 in FIFO queue 1 is read out; in the next cycle, because all the data in FIFO queue 1 has been read out, only FIFO queue 0 participates in arbitration, and the priority arbitrator allows FIFO queue 0 to be read out. At this time, transaction 0 in FIFO queue 0 is read out. It can be seen that in the AXI bus matrix interface of the present invention, the order in which transactions are read is transaction 1, transaction 2, and transaction 0, following the rule that high priority first-out under different priorities and first-in first-out under the same priority, rather than reading transaction 0, transaction 1, and transaction 2 in sequence in the traditional order.

[0030] like Figure 4 As shown, in an AXI interconnect structure of 3 hosts and 3 slaves supporting Outstanding characteristics, the middle AXI interconnect is an AXI bus interconnect matrix. There are 3 slave interfaces (slave interface 0, slave interface 1, slave interface 2) and 3 host interfaces (host interface 0, host interface 1, host interface 2) in this interconnect matrix. The 3 slave interfaces and 3 host interfaces are all priority queue-based AXI bus matrix interfaces provided by the present invention; each host (host 0, host 1, host 2) is connected to the corresponding slave interface in the interconnect matrix, and the host interface in the interconnect matrix is ​​connected to the corresponding slave (slave 0, slave 1, slave 2).

[0031] Taking write transactions as an example, host 0 continuously issues 3 outstanding transactions on the AW channel. If the traditional interconnect matrix interface is used, these 3 transactions will enter the slave interface 0 in the interconnect matrix and be spliced ​​there, and then these transactions will enter the FIFO queue cache. Transactions in the FIFO queue will be processed strictly according to the first-in-first-out principle. When a transaction enters the FIFO queue, the polling arbitrator will arbitrate in the order in which the transaction arrives, and route these transactions one by one to the corresponding host interface through the routing module, and finally disassemble the data through the signal of the AW channel and transmit it to the corresponding slave. Although this design is simple, it does not take into account the priority of the transaction, resulting in high-priority transactions having to wait for the processing of low-priority transactions to be completed, thereby causing priority flipping problems and affecting the real-time and efficiency of the system.

[0032] Different from the traditional design, the present invention adopts a design based on priority queue, combining multiple FIFO queues, data selectors, data distributors and priority arbitrators to realize the scheduling of transaction priorities in the AXI bus matrix interface. In this improved design, when the host 0 continuously issues 3 outstanding transactions, in the slave interface 0, the transaction will first be decoded according to the priority signal and distributed to different FIFO queues by the data distributor. The priority arbitrator determines which transactions are read and processed from the queue first according to the priority, ensuring that high-priority transactions can be processed first and avoiding the priority flip phenomenon. Specifically, in this process, the transaction will first enter the priority queue, and when reading out the transaction, the data selector selects the transaction with the highest priority from the FIFO queue for reading out according to the control signal of the priority arbitrator. Then, these transactions are transferred to the target host interface through the polling arbitrator and routing module inside the AXI bus matrix, and finally the data is disassembled into the data of the AW channel and sent to the corresponding slave.

[0033] The AXI bus matrix interface based on priority queue provided by the present invention effectively solves the performance problem caused by improper priority scheduling in the traditional FIFO queue, and can ensure the timely response of high-priority transactions. By introducing multiple FIFO queues and priority arbitration mechanism, the system can dynamically schedule according to the priority of the transaction, thereby improving the throughput and real-time performance of the system and avoiding the transaction delay problem caused by priority flipping.

[0034] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. An AXI bus matrix interface based on a priority queue, characterized in that: The AXI bus matrix interface based on priority queue includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, multiple FIFO queues, a first data selector, a second data selector and a priority arbitrator, wherein the multiple FIFO queues constitute a priority queue for storing AXI transaction signals of different priorities, the data encapsulator is connected to the first data distributor, the priority decoder is respectively connected to the first data distributor, the second data distributor and the second data selector, each of the FIFO queues is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector and the priority arbitrator, the priority arbitrator is connected to the first data selector, wherein, The data encapsulator is responsible for packaging and splicing different signals in a single channel in the AXI protocol into a multi-bit AXI transaction signal; The priority decoder is responsible for decoding the Qos signal in the single channel to obtain the priority of the AXI transaction signal; The first data distributor distributes the AXI transaction signal to the data input end of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal; the second data distributor distributes the VALID signal in the single channel to the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal; the second data selector selects the non-full signal of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal, so as to use the non-full signal of the FIFO queue of the corresponding priority as the READY signal in the single channel; when the VALID signal and the READY signal in the single channel are 1 at the same time, the write enable of the FIFO queue of the corresponding priority is valid, and the first data distributor stores the AXI transaction signal in the FIFO queue of the corresponding priority; The priority arbitrator performs priority arbitration according to non-empty signals of multiple FIFO queues to obtain priority arbitration results of multiple FIFO queues; wherein the arbitration principle is that the AXI transaction signal in the high-priority FIFO queue is transmitted first; The first data selector transmits the AXI transaction signal in the high-priority FIFO queue to the subsequent polling arbiter and routing module of the bus matrix.

2. The AXI bus matrix interface based on priority queue according to claim 1, characterized in that: In the AXI protocol, the Qos signal is a quality of service signal extension signal, which is used to indicate the priority of the AXI transaction signal, wherein the two-bit Qos signals 00, 01, 10, and 11 represent priority 0, priority 1, priority 2, and priority 3, respectively.

3. The AXI bus matrix interface based on priority queue according to claim 1, characterized in that: Four FIFO queues form a priority queue, FIFO queue 0 is used to store AXI transaction signals with a priority of 0, FIFO queue 1 is used to store AXI transaction signals with a priority of 1, FIFO queue 2 is used to store AXI transaction signals with a priority of 2, and FIFO queue 3 is used to store AXI transaction signals with a priority of 3. Taking the AW channel as an example, the data encapsulator splices and encapsulates the AWID, AWADDR, AWLEN, AWSIZE, AMUSER, AWLOCK, AWPROT, AWREGION, and AWQOS signals in the AW channel sent by the host into a multi-bit AXI transaction signal AW_Trancation; The priority decoder is responsible for decoding the two-bit AWQOS signal in the AW channel to obtain the priority of the AXI transaction signal AW_Trancation; The first data distributor distributes the AXI transaction signal AW_Trancation to the data input end of the FIFO queue of the corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data distributor distributes the AWVALID signal in the AW channel to a FIFO queue of corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data selector selects a non-full signal of a FIFO queue of a corresponding priority according to the priority of the AXI transaction signal AW_Trancation, so as to use the non-full signal of the FIFO queue of the corresponding priority as the AWREADY signal in the AW channel; when the AWVALID signal and the AWREADY signal in the AW channel are both 1, the write enable of the FIFO queue of the corresponding priority is valid, and the first data distributor stores the AXI transaction signal AW_Trancation into the FIFO queue of the corresponding priority for caching; The priority arbitrator performs priority arbitration according to the non-empty signals of the four FIFO queues to obtain priority arbitration results of the four FIFO queues; wherein the arbitration principle is that the AXI transaction signal AW_Trancation in the high-priority FIFO queue is transmitted first; The first data selector transmits the AXI transaction signal AW_Trancation in the high-priority FIFO queue to the subsequent polling arbiter and routing module of the bus matrix.

4. The AXI bus matrix interface based on priority queue according to claim 3, characterized in that: The empty flag signal is 1, which indicates that there is no data in the FIFO queue. Conversely, the empty flag signal is inverted to obtain a non-empty signal. The non-empty signal is 1, which indicates that there is unread data in the FIFO queue. Therefore, the non-empty signals of the four FIFO queues are derived as arbitration request signals of the four FIFO queues.

5. The AXI bus matrix interface based on priority queue according to claim 3, characterized in that: The write enable of the FIFO queue is determined by the AWVALID signal and AWREADY signal of the AW channel. The AWVALID signal and AWREADY signal are handshake signals in the AXI protocol. The transmission of an AXI transaction signal can only be completed when the AWVALID signal and AWREADY signal are both high levels. When the AWVALID signal is high, it indicates that the AXI transaction signal of this cycle is valid, otherwise it is invalid; When the AWREADY signal is high, it indicates that the FIFO queue of this cycle is idle and can receive AXI transaction signals. When the AWREADY signal is low, it indicates that the FIFO queue of this cycle is full and cannot receive AXI transaction signals.

6. The AXI bus matrix interface based on priority queue according to claim 3, characterized in that: When the host sends three AW channel transaction signals in succession, they are transaction 0, transaction 1, and transaction 2 in chronological order. The priority of transaction 0 is 0, and the priorities of transaction 1 and transaction 2 are both 1. It is stipulated that priority 1 is higher than priority 0. The host first sends transaction 0, the data encapsulator encapsulates each signal of the AW channel, the Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 0 is 0, and the second data selector selects the non-full signal of FIFO queue 0 as the AWREADY signal according to the decoding result, and the AWREADY signal is 1 at this time; similarly, the second data distributor sends the AWVALID signal to FIFO queue 0 according to the decoding result, the AWVALID signal and the AWREADY signal are 1 at the same time, the write enable of FIFO queue 0 is valid, and the first data distributor stores transaction 0 in the corresponding FIFO queue 0; Next, the host sends transaction 1. Similarly, the data encapsulator encapsulates each signal of the AW channel. The Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 1 is 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. The AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are 1 at the same time, the write enable of FIFO queue 1 is valid, and the first data distributor stores transaction 1 in the corresponding FIFO queue 1. Next, the host sends transaction 2. Similarly, the data encapsulator encapsulates each signal of the AW channel. The Qos decoder decodes the value of its Qos signal and obtains that the priority of transaction 2 is also 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. The AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are 1 at the same time. The write enable of FIFO queue 1 is valid. At this time, FIFO queue 1 is not full and can be written normally. Therefore, the first data distributor also stores transaction 2 in the corresponding FIFO queue 1. When transactions 0, 1, and 2 are all stored in the corresponding FIFO queues, there are transactions in both FIFO queues 0 and 1, and the non-empty signals of FIFO queues 0 and 1 are both 1, acting as arbitration request signals. Because FIFO queue 1 has a high priority, the priority arbitrator first allows transactions in FIFO queue 1 to be read out. Because the rule of the FIFO queue is first-in-first-out, transaction 1 in FIFO queue 1 is read out first. In the next cycle, because there are still transactions stored in FIFO queues 0 and 1, the next round of arbitration is carried out, and the priority arbitrator also allows FIFO queue 1 to be read out first. At this time, transaction 2 in FIFO queue 1 is read out. In the next cycle, because all the data in FIFO queue 1 has been read out, only FIFO queue 0 participates in arbitration. The priority arbitrator allows FIFO queue 0 to be read out, and transaction 0 in FIFO queue 0 is read out.

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