An AXI bus matrix interface based on a priority queue

Abstract

The present invention relates to the field of integrated circuit technology, and specifically discloses an AXI bus matrix interface based on a priority queue, which includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, a plurality of FIFO queues, a first data selector, a second data selector, and a priority arbiter. Among them, the data encapsulator is connected to the first data distributor, the priority decoder is respectively connected to the first data distributor, the second data distributor, and the second data selector, each FIFO queue is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector, and the priority arbiter, and the priority arbiter is connected to the first data selector. The present invention can perform priority decoding and scheduling on transactions, so as to ensure that transactions with higher priorities are processed first, eliminate the priority inversion problem, and improve the real-time performance of the system.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more particularly, to an AXI bus matrix interface based on a priority queue. Background Art

[0002] The AXI (Advanced eXtensible Interface) bus is a high-performance and high-bandwidth bus protocol, which is widely used in system-on-chip (SoC) to connect modules such as processors, memory controllers, and peripherals. The design of the AXI bus protocol provides multi-channel concurrent transmission capabilities, including read / write data channels, address channels, and control channels, enabling efficient and fast data transmission. Especially in the application scenarios of multi-core processors, complex peripherals, and high-speed storage devices, the high-bandwidth and low-latency characteristics of the AXI bus are fully utilized.

[0003] The AXI bus matrix is an interconnection structure that connects multiple masters and slaves, and is responsible for caching, routing, and arbitrating transactions between multiple masters and slaves. The bus matrix usually consists of a bus matrix interface (master interface and slave interface), a routing module, and an arbiter module. A FIFO (First-In-First-Out) queue is usually used as a cache queue in the bus matrix interface to temporarily store transmission transactions. The design of the FIFO queue has been widely used because of its simple structure and easy implementation. Each transaction is queued in order of its arrival and waits for processing in the queue, ensuring the orderly transmission and processing of data. This way of the FIFO queue can effectively improve the data transmission efficiency, especially suitable for processing simple transactions without priority differences.

[0004] However, with the increase in system complexity, the number of transactions to be processed in the AXI bus matrix has increased significantly, and the priority differences among transactions have become increasingly important. Especially in modern systems-on-chip, there are usually multiple masters simultaneously sending requests to multiple slaves, and the priority and timing requirements of these requests often vary. To implement the Outstanding feature in the AXI protocol, that is, the ability of the master to initiate multiple transaction transmissions without receiving an acknowledgment. It is necessary to design FIFOs in the bus matrix interface (including the slave interface and the master interface) to cache the unfinished transactions. At this time, in a traditional FIFO queue, the processing order of transactions strictly follows the "first in, first out" principle, which means that the transactions that arrive earlier in the queue must be processed before those that arrive later. However, the FIFO queue cannot perform dynamic scheduling based on the priority of transactions, which leads to the "priority inversion" problem. Specifically, when a low-priority transaction arrives at the FIFO queue before a high-priority transaction, the high-priority transaction needs to wait for the low-priority transaction to complete before it can be processed, thus delaying the execution of the high-priority transaction. This delay not only affects the real-time performance of the system but may also cause the system response to slow down, affecting the overall performance.

[0005] As Figure 1 shown, in a traditional AXI bus matrix slave interface, first, the signals in a certain channel of the AXI bus, such as the AW channel, are packed and concatenated, and then stored in the FIFO queue. The handshake signal AWVALID in the AXI protocol serves as the write enable of the FIFO, and the non-full signal of the FIFO serves as the handshake signal AWREADY of the slave. When the master raises AWVALID and the FIFO is not full, that is, AWREADY is 1, the transaction is written into the FIFO queue. This approach is simple and easy to implement, but the problem is that it ignores the priority in the transaction. The transactions entering the FIFO queue are stored and read out strictly according to the "first in, first out" rule. This design will lead to priority inversion, affecting the real-time performance and communication efficiency of the system. As Figure 2 shown, assume that priority 1 is greater than priority 0. Transaction 0 first enters the FIFO queue, followed by transaction 1, and finally transaction 2. According to the "first in, first out" principle of the FIFO queue, the processing order of transactions is transaction 0 → transaction 1 → transaction 2. Although the priority of transaction 2 (priority 1) is higher than the priorities of transaction 0 and transaction 1 (priority 0), because it enters the queue later, it must wait for the previous low-priority transactions to be processed before it can be processed. This waiting will cause a delay in the high-priority transaction (transaction 2), thus triggering the priority inversion problem. Therefore, the traditional AXI bus matrix interface using a FIFO queue cannot perform dynamic scheduling based on the priority of transactions, resulting in the priority inversion problem and affecting the real-time performance and communication efficiency of the system. Summary of the Invention

[0006] To solve the deficiencies in the prior art, the present invention provides an AXI bus matrix interface based on a priority queue. By introducing multiple FIFO queues and combining with the Qos signal in the AXI protocol, priority decoding and scheduling of transactions are performed, so as to ensure that transactions with higher priority can be processed preferentially, eliminate the priority inversion problem, improve the real-time performance of the system, and reduce blocking.

[0007] As a first aspect of the present invention, there is provided an AXI bus matrix interface based on a priority queue. The AXI bus matrix interface based on a priority queue includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, multiple FIFO queues, a first data selector, a second data selector, and a priority arbiter. Among them, the multiple FIFO queues form a priority queue for storing AXI transaction signals with different priorities. The data encapsulator is connected to the first data distributor, and the priority decoder is respectively connected to the first data distributor, the second data distributor, and the second data selector. Each FIFO queue is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector, and the priority arbiter. The priority arbiter is connected to the first data selector, where

[0008] The data encapsulator is responsible for packing and splicing different signals in a single channel of the AXI protocol into a multi-bit AXI transaction signal;

[0009] The priority decoder is responsible for decoding the Qos signal in the single channel to obtain the priority of the AXI transaction signal;

[0010] The first data distributor distributes the AXI transaction signal to the data input end of the FIFO queue corresponding to the priority according to the priority of the AXI transaction signal; the second data distributor distributes the VALID signal in the single channel to the FIFO queue corresponding to the priority according to the priority of the AXI transaction signal; the second data selector selects the non-full signal of the FIFO queue corresponding to the priority according to the priority of the AXI transaction signal, and uses the non-full signal of the FIFO queue corresponding to the priority as the READY signal in the single channel; when the VALID signal and the READY signal in the single channel are both 1, the write enable of the FIFO queue corresponding to the priority is effective, and the first data distributor stores the AXI transaction signal into the FIFO queue corresponding to the priority;

[0011] The priority arbiter performs priority arbitration according to the non-empty signals of multiple FIFO queues to obtain the priority arbitration result of multiple FIFO queues; among them, the arbitration principle is that the AXI transaction signal in the FIFO queue with higher priority is transmitted preferentially;

[0012] The first data selector transmits the AXI transaction signals in the high-priority FIFO queue to the subsequent polling arbiter and routing module of the bus matrix.

[0013] Furthermore, in the AXI protocol, the Qos signal is a service quality signal extension signal used to represent the priority of the AXI transaction signal. Among them, the two-bit Qos signals 00, 01, 10, and 11 represent priority 0, priority 1, priority 2, and priority 3 respectively.

[0014] Furthermore, four FIFO queues form a priority queue. FIFO queue 0 is used to store AXI transaction signals with priority 0, FIFO queue 1 is used to store AXI transaction signals with priority 1, FIFO queue 2 is used to store AXI transaction signals with priority 2, and FIFO queue 3 is used to store AXI transaction signals with priority 3. Taking the AW channel as an example, the data encapsulator splices and encapsulates the AWID, AWADDR, AWLEN, AWSIZE, AWUSER, AWLOCK, AWPROT, AWREGION, and AWQOS signals in the AW channel sent by the host into a multi-bit AXI transaction signal AW_Trancation;

[0015] The priority decoder is responsible for decoding the two-bit AWQOS signal in the AW channel to obtain the priority of the AXI transaction signal AW_Trancation;

[0016] The first data distributor distributes the AXI transaction signal AW_Trancation to the data input end of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation;

[0017] The second data distributor distributes the AWVALID signal in the AW channel to the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation;

[0018] The second data selector selects the non-full signal of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation, and uses the non-full signal of the FIFO queue with the corresponding priority as the AWREADY signal in the AW channel; when the AWVALID signal and the AWREADY signal in the AW channel are both 1 at the same time, the write enable of the FIFO queue with the corresponding priority is effective, and the first data distributor stores the AXI transaction signal AW_Trancation into the FIFO queue with the corresponding priority for caching;

[0019] The priority arbiter performs priority arbitration based on the non-empty signals of the four FIFO queues to obtain the priority arbitration results of the four FIFO queues. Among them, the arbitration principle is that the AXI transaction signal AW_Trancation in the FIFO queue with a higher priority is preferentially transmitted.

[0020] The first data selector transmits the AXI transaction signal AW_Trancation in the FIFO queue with a higher priority to the subsequent polling arbiter and routing module of the bus matrix.

[0021] Furthermore, when the empty flag signal is 1, it indicates that there is no data in the FIFO queue. Conversely, the non-empty signal is obtained by inverting the empty flag signal. When the non-empty signal is 1, it indicates that there is unread data in the FIFO queue. Therefore, the non-empty signals of the four FIFO queues are led out as the arbitration request signals of the four FIFO queues.

[0022] Furthermore, the write enable of the FIFO queue is determined by the AWVALID signal and the AWREADY signal of the AW channel. The AWVALID signal and the AWREADY signal are handshake signals in the AXI protocol. Only when both the AWVALID signal and the AWREADY signal are at a high level can the transmission of an AXI transaction signal be completed.

[0023] When the AWVALID signal is at a high level, it indicates that the AXI transaction signal in this cycle is valid, otherwise it is invalid.

[0024] When the AWREADY signal is at a high level, it indicates that the FIFO queue is idle in this cycle and can receive the AXI transaction signal. When it is at a low level, it indicates that the FIFO queue is full in this cycle and cannot receive the AXI transaction signal.

[0025] Furthermore, when the host continuously sends 3 AW channel transaction signals, in chronological order, they are transaction 0, transaction 1, and transaction 2. The priority of transaction 0 is 0, and the priorities of transaction 1 and transaction 2 are both 1. It is stipulated that priority 1 is higher than priority 0.

[0026] The host first issues transaction 0. The data encapsulator encapsulates each signal of the AW channel. The priority decoder decodes according to the value of its Qos signal and obtains that the priority of transaction 0 is 0. The second data selector selects the non-full signal of FIFO queue 0 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 0 according to the decoding result. Both the AWVALID signal and the AWREADY signal are 1, and the write enable of FIFO queue 0 is valid. The first data distributor stores transaction 0 into the corresponding FIFO queue 0.

[0027] Next, the host issues Transaction 1. Similarly, the data encapsulator encapsulates each signal on the AW channel. The priority decoder decodes based on the value of its Qos signal and obtains that the priority of Transaction 1 is 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result, and the AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are both 1, and the write enable of FIFO queue 1 is effective. The first data distributor stores Transaction 1 into the corresponding FIFO queue 1;

[0028] Next, the host issues Transaction 2. Similarly, the data encapsulator encapsulates each signal on the AW channel. The priority decoder decodes based on the value of its Qos signal and obtains that the priority of Transaction 2 is also 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result, and the AWREADY signal is 1 at this time. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are both 1, and the write enable of FIFO queue 1 is effective. At this time, FIFO queue 1 is not full and can be written normally. Therefore, the first data distributor also stores Transaction 2 into the corresponding FIFO queue 1;

[0029] After Transactions 0, 1, and 2 are all stored in the corresponding FIFO queues, there are transactions in both FIFO queue 0 and FIFO queue 1 at this time. The non-empty signals of FIFO queue 0 and FIFO queue 1 are both 1 and act as arbitration request signals. Because the priority of FIFO queue 1 is high, the priority arbiter first allows the transaction in FIFO queue 1 to be read out. Because the rule of the FIFO queue is first in first out, the transaction 1 in FIFO queue 1 is read out first; in the next cycle, because there are still transactions stored in FIFO queue 0 and FIFO queue 1, a new round of arbitration is performed. The priority arbiter also allows FIFO queue 1 to be read out first. At this time, the transaction 2 in FIFO queue 1 is read out; in the next cycle, because all the data in FIFO queue 1 has been read out and only FIFO queue 0 participates in the arbitration, the priority arbiter allows FIFO queue 0 to be read out. At this time, the transaction 0 in FIFO queue 0 is read out.

[0030] The AXI bus matrix interface based on a priority queue provided by the present invention has the following advantages: By introducing a priority queue and combining it with the Qos signal in the AXI protocol, priority decoding and scheduling of transactions are performed, thus effectively solving the performance problems caused by improper priority scheduling in traditional FIFO queues, ensuring that high-priority transactions can be processed first, eliminating the priority inversion problem, improving the throughput and real-time performance of the system, and avoiding the transaction delay problem caused by priority inversion. Brief Description of the Drawings

[0031] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation to the present invention.

[0032] Figure 1 It is a schematic structural diagram of a traditional AXI bus matrix interface.

[0033] Figure 2 It is a schematic diagram of "first in, first out" of the FIFO queue in a traditional AXI bus matrix interface.

[0034] Figure 3 It is a schematic structural diagram of the AXI bus matrix interface based on a priority queue proposed by the present invention.

[0035] Figure 4 It is an application schematic diagram of the AXI bus matrix interface based on a priority queue proposed by the present invention. Detailed Description of the Invention

[0036] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following, in combination with the drawings and preferred embodiments, details the specific embodiments, structures, features and effects of an AXI bus matrix interface based on a priority queue proposed by the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0038] In the interpretation of the present invention, it should be noted that the terms "installed", "connected", "linked" should be understood in a broad sense unless otherwise specified. For example, the connection can be a fixed connection, can also be connected through a special interface, or can be indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] In this embodiment, a priority queue-based AXI bus matrix interface is provided, as Figure 3 shown. The priority queue-based AXI bus matrix interface includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, a plurality of FIFO queues, a first data selector, a second data selector and a priority arbiter. Among them, the plurality of FIFO queues form a priority queue for storing AXI transaction signals of different priorities. The data encapsulator is connected to the first data distributor. The priority decoder is respectively connected to the first data distributor, the second data distributor and the second data selector. Each FIFO queue is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector and the priority arbiter. The priority arbiter is connected to the first data selector, where

[0040] the data encapsulator is responsible for packing and splicing different signals in a single channel in the AXI protocol into a multi-bit AXI transaction signal so as to store it in a single FIFO queue, without the need for multiple FIFO queues to separately cache each different signal in the channel;

[0041] the priority decoder is responsible for decoding the Qos signal in the single channel to obtain the priority of the AXI transaction signal;

[0042] The first data distributor distributes the AXI transaction signal to the data input end of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal; the second data distributor distributes the VALID signal in the single channel to the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal; the second data selector selects the non-full signal of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal, and uses the non-full signal of the FIFO queue with the corresponding priority as the READY signal in the single channel; when the VALID signal and the READY signal in the single channel are both 1, the write enable of the FIFO queue with the corresponding priority is effective, and the first data distributor stores the AXI transaction signal into the FIFO queue with the corresponding priority;

[0043] The priority arbiter performs priority arbitration based on the non-empty signals of multiple FIFO queues to obtain the priority arbitration results of multiple FIFO queues; among them, the arbitration principle is that the AXI transaction signals in the FIFO queue with a higher priority are transmitted first;

[0044] The first data selector transmits the AXI transaction signal in the FIFO queue with a higher priority to the subsequent polling arbiter and routing module of the bus matrix.

[0045] Specifically, in the AXI protocol, the Qos signal is a service quality signal extension signal used to represent the priority of the AXI transaction signal. Among them, the two-bit Qos signals 00, 01, 10, and 11 represent priority 0, priority 1, priority 2, and priority 3 respectively.

[0046] Preferably, four FIFO queues form a priority queue. FIFO queue 0 is used to store AXI transaction signals with priority 0, FIFO queue 1 is used to store AXI transaction signals with priority 1, FIFO queue 2 is used to store AXI transaction signals with priority 2, and FIFO queue 3 is used to store AXI transaction signals with priority 3. Taking the AW channel as an example, the data encapsulator splices and encapsulates the AWID, AWADDR, AWLEN, AWSIZE, AWUSER, AWLOCK, AWPROT, AWREGION, and AWQOS signals in the AW channel sent by the host into a multi-bit AXI transaction signal AW_Trancation; the encapsulated AXI transaction signal AW_Trancation needs to be cached in the FIFO queue. Since multiple FIFO queues are designed to form a priority queue to store transactions with different priorities, signals are needed to distinguish the priorities of transactions.

[0047] The priority decoder is responsible for decoding the two-bit AWQOS signal in the AW channel to obtain the priority of the AXI transaction signal AW_Trancation;

[0048] The first data distributor distributes the AXI transaction signal AW_Trancation to the data input end of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation;

[0049] The second data distributor distributes the AWVALID signal in the AW channel to the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation;

[0050] The second data selector selects the non-full signal of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation, and uses the non-full signal of the FIFO queue with the corresponding priority as the AWREADY signal in the AW channel, so as to ensure that the transaction writing stops when the corresponding FIFO queue is full; when the AWVALID signal and the AWREADY signal in the AW channel are both 1 at the same time, the write enable of the FIFO queue with the corresponding priority is valid, and the first data distributor stores the AXI transaction signal AW_Trancation into the FIFO queue with the corresponding priority for caching;

[0051] The priority arbiter performs priority arbitration according to the non-empty signals of the four FIFO queues to obtain the priority arbitration result of the four FIFO queues; among them, the arbitration principle is that the AXI transaction signal AW_Trancation in the FIFO queue with the higher priority is transmitted first; the first data selector transmits the AXI transaction signal AW_Trancation in the FIFO queue with the higher priority to the subsequent polling arbiter and routing module of the bus matrix. For example, if FIFO queue 3 and FIFO queue 2 send arbitration requests at the same time, the priority arbiter will pass the request of FIFO queue 3, and the arbitration result acts on data selector 1. Data selector 1 selects the transaction of FIFO queue 3 and passes it to the subsequent polling arbiter and routing module of the bus matrix.

[0052] It should be noted that the empty flag signal is generally empty. When empty is 1, it means that there is no data in the FIFO queue. On the contrary, the empty flag signal is inverted to obtain the non-empty signal, which is generally represented by the signal name!empty. When the non-empty signal is 1, it means that there is unread data in the FIFO queue. Therefore, the non-empty signals of the four FIFO queues are led out as the arbitration request signals of the four FIFO queues.

[0053] Specifically, the AWREADY signal is controlled by the FIFO queue. The FIFO queue usually has an empty flag and a full flag to indicate the storage status inside the FIFO queue. The full flag is generally represented by the signal name full. When the full signal is 1, it means that the data stored in the FIFO queue has reached the upper limit at this time, and no more data should be written into it. In the AXI bus matrix interface, it is necessary to ensure that the FIFO queue used to cache transactions does not overflow, that is, stop writing when the FIFO queue is full. Therefore, the full signal is inverted to obtain the non-full signal!full.

[0054] Preferably, the write enable of the FIFO queue is determined by the AWVALID signal and the AWREADY signal of the AW channel. The AWVALID signal and the AWREADY signal are handshake signals in the AXI protocol; only when the AWVALID signal and the AWREADY signal are both high can a transmission of an AXI transaction signal be completed;

[0055] When the AWVALID signal is high, it indicates that the AXI transaction signal of this cycle is valid, otherwise it is invalid;

[0056] When the AWREADY signal is high, it indicates that the FIFO queue is idle in this cycle and can receive the AXI transaction signal. When the AWREADY signal is low, it means that the FIFO queue is full in this cycle and cannot receive the AXI transaction signal.

[0057] Specifically, when the host continuously sends 3 AXI transaction signals of the AW channel, in chronological order, they are transaction 0, transaction 1, and transaction 2. The priority of transaction 0 is 0, and the corresponding two-bit Qos signal value is 00; the priorities of transaction 1 and transaction 2 are both 1, and the corresponding two-bit Qos signal values are 01. It is stipulated that priority 1 is higher than priority 0;

[0058] The host first issues transaction 0. The data encapsulator encapsulates each signal of the AW channel. The priority decoder decodes the priority of transaction 0 as 0 according to the value of its Qos signal. The second data selector selects the non-full signal of FIFO queue 0 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1; similarly, the second data distributor sends the AWVALID signal to FIFO queue 0 according to the decoding result. The AWVALID signal and the AWREADY signal are both 1, and the write enable of FIFO queue 0 is valid. The first data distributor stores transaction 0 into the corresponding FIFO queue 0;

[0059] Next, the host issues Transaction 1. Similarly, the data encapsulator encapsulates each signal on the AW channel. The priority decoder decodes based on the value of its Qos signal and obtains that the priority of Transaction 1 is 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are both 1 at the same time, and the write enable of FIFO queue 1 is effective. The first data distributor stores Transaction 1 into the corresponding FIFO queue 1;

[0060] Next, the host issues Transaction 2. Similarly, the data encapsulator encapsulates each signal on the AW channel. The priority decoder decodes based on the value of its Qos signal and obtains that the priority of Transaction 2 is also 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. The AWVALID signal and the AWREADY signal are both 1 at the same time, and the write enable of FIFO queue 1 is effective. At this time, FIFO queue 1 is not full and can be written normally. Therefore, the first data distributor also stores Transaction 2 into the corresponding FIFO queue 1;

[0061] After Transactions 0, 1, and 2 are all stored in the corresponding FIFO queues, the subsequent polling arbiter and routing module in the AXI bus matrix send signals to read the transactions in the interface, and the priority arbiter is required to determine the order of reading the transactions. At this time, there are transactions in both FIFO queue 0 and FIFO queue 1, and the non-empty signals of FIFO queue 0 and FIFO queue 1 are both 1, acting as arbitration request signals. Because the priority of FIFO queue 1 is high, the priority arbiter first allows the transaction in FIFO queue 1 to be read out. Because the rule of the FIFO queue is first in first out, the transaction 1 in FIFO queue 1 is read out first; in the next cycle, because there are still transactions stored in FIFO queue 0 and FIFO queue 1, the next round of arbitration is performed. The priority arbiter also allows FIFO queue 1 to be read out first. At this time, the transaction 2 in FIFO queue 1 is read out; in the next cycle, because all the data in FIFO queue 1 has been read out and only FIFO queue 0 participates in the arbitration, the priority arbiter allows FIFO queue 0 to be read out. At this time, the transaction 0 in FIFO queue 0 is read out. It can be seen that in the AXI bus matrix interface of the present invention, the order of reading the transactions is Transaction 1, Transaction 2, Transaction 0, following the rule that at different priorities, the higher priority comes out first, and at the same priority, first in first out. Instead of reading Transactions 0, 1, and 2 in the traditional order.

[0062] As Figure 4 shown, in a 3-host 3-slave AXI interconnect structure that supports the Outstanding feature, the middle AXI interconnect is an AXI bus interconnect matrix. There are 3 slave interfaces (slave interface 0, slave interface 1, slave interface 2) and 3 host interfaces (host interface 0, host interface 1, host interface 2) in this interconnect matrix. The 3 slave interfaces and 3 host interfaces are all AXI bus matrix interfaces based on priority queues provided by the present invention; each host (host 0, host 1, host 2) is connected to the corresponding slave interface in the interconnect matrix, and the host interfaces in the interconnect matrix are connected to the corresponding slaves (slave 0, slave 1, slave 2).

[0063] Taking the write transaction as an example, host 0 continuously issues 3 Outstanding transactions on the AW channel. If according to the traditional interconnect matrix interface, these 3 transactions will enter slave interface 0 in the interconnect matrix and be spliced therein, and then these transactions will enter the FIFO queue buffer. The transactions in the FIFO queue will be processed strictly according to the first-in-first-out principle. When the transactions enter the FIFO queue, the polling arbiter will arbitrate according to the order in which the transactions arrive, and route these transactions one by one to the corresponding host interfaces through the routing module, and finally disassemble the data through the signals on the AW channel and transmit it to the corresponding slaves. Although this design is simple, it does not consider the priority of transactions, resulting in high-priority transactions having to wait for low-priority transactions to be processed, thus causing the priority inversion problem and affecting the real-time performance and efficiency of the system.

[0064] Different from the traditional design, the present invention adopts a design based on a priority queue, and combines multiple FIFO queues, data selectors, data distributors and priority arbiters to realize the scheduling of transaction priorities in the AXI bus matrix interface. In this improved design, when host 0 continuously issues 3 Outstanding transactions, in slave interface 0, the transactions will first be decoded according to the priority signal and distributed to different FIFO queues by the data distributor. The priority arbiter determines which transactions are read from the queue first and processed according to the priority, ensuring that high-priority transactions can be processed first and avoiding the priority inversion phenomenon. Specifically, in this process, the transactions will first enter the priority queue. When reading out the transactions, the data selector selects the transaction with the highest priority from the FIFO queue according to the control signal of the priority arbiter. Then, these transactions are passed to the target host interface through the polling arbiter and routing module inside the AXI bus matrix, and finally the data is disassembled into the data on the AW channel and sent to the corresponding slaves.

[0065] The AXI bus matrix interface based on the priority queue provided by the present invention effectively solves the performance problems caused by improper priority scheduling in the traditional FIFO queue, and can ensure the timely response of high-priority transactions. By introducing multiple FIFO queues and a priority arbitration mechanism, the system can dynamically schedule according to the priority of transactions, thereby improving the throughput and real-time performance of the system and avoiding the transaction delay problem caused by priority inversion.

[0066] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. An AXI bus matrix interface based on a priority queue, characterized in that The AXI bus matrix interface based on the priority queue includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, multiple FIFO queues, a first data selector, a second data selector, and a priority arbiter. Among them, the multiple FIFO queues form a priority queue for storing AXI transaction signals with different priorities. The data encapsulator is connected to the first data distributor. The priority decoder is respectively connected to the first data distributor, the second data distributor, and the second data selector. Each FIFO queue is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector, and the priority arbiter. The priority arbiter is connected to the first data selector. Among them, The data encapsulator is responsible for packing and splicing different signals in a single channel of the AXI protocol into a multi-bit AXI transaction signal; The priority decoder is responsible for decoding the Qos signal in the single channel to obtain the priority of the AXI transaction signal; The first data distributor distributes the AXI transaction signal to the data input end of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal; the second data distributor distributes the VALID signal in the single channel to the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal; the second data selector selects the non-full signal of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal to use the non-full signal of the FIFO queue with the corresponding priority as the READY signal in the single channel; when the VALID signal and the READY signal in the single channel are both 1, the write enable of the FIFO queue with the corresponding priority is valid, and the first data distributor stores the AXI transaction signal into the FIFO queue with the corresponding priority; The priority arbiter performs priority arbitration according to the non-empty signals of multiple FIFO queues to obtain the priority arbitration result of multiple FIFO queues; among them, the arbitration principle is that the AXI transaction signal in the FIFO queue with a higher priority is transmitted first; The first data selector transmits the AXI transaction signal in the FIFO queue with a higher priority to the subsequent polling arbiter and routing module of the bus matrix.

2. The AXI bus matrix interface based on a priority queue according to claim 1, wherein In the AXI protocol, the Qos signal is a service quality signal extension signal used to represent the priority of the AXI transaction signal. Among them, the two-bit Qos signals 00, 01, 10, and 11 respectively represent priority 0, priority 1, priority 2, and priority 3.

3. The AXI bus matrix interface based on a priority queue according to claim 1, characterized in that, Four FIFO queues form a priority queue. FIFO queue 0 is used to store AXI transaction signals with priority 0, FIFO queue 1 is used to store AXI transaction signals with priority 1, FIFO queue 2 is used to store AXI transaction signals with priority 2, and FIFO queue 3 is used to store AXI transaction signals with priority 3. Taking the AW channel as an example, the data encapsulator splices and encapsulates the AWID, AWADDR, AWLEN, AWSIZE, AWUSER, AWLOCK, AWPROT, AWREGION, and AWQOS signals in the AW channel sent by the host into a multi-bit AXI transaction signal AW_Trancation; The priority decoder is responsible for decoding the two-bit AWQOS signal in the AW channel to obtain the priority of the AXI transaction signal AW_Trancation; The first data distributor distributes the AXI transaction signal AW_Trancation to the data input end of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data distributor distributes the AWVALID signal in the AW channel to the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation; The second data selector selects the non-full signal of the FIFO queue with the corresponding priority according to the priority of the AXI transaction signal AW_Trancation, and uses the non-full signal of the FIFO queue with the corresponding priority as the AWREADY signal in the AW channel; when the AWVALID signal and the AWREADY signal in the AW channel are both 1 at the same time, the write enable of the FIFO queue with the corresponding priority is valid, and the first data distributor stores the AXI transaction signal AW_Trancation into the FIFO queue with the corresponding priority for caching; The priority arbiter performs priority arbitration according to the non-empty signals of the four FIFO queues to obtain the priority arbitration result of the four FIFO queues; among them, the arbitration principle is that the AXI transaction signal AW_Trancation in the FIFO queue with a higher priority is transmitted first; The first data selector transmits the AXI transaction signal AW_Trancation in the FIFO queue with a higher priority to the subsequent polling arbiter and routing module of the bus matrix.

4. The AXI bus matrix interface based on a priority queue according to claim 3, wherein, The empty flag signal being 1 indicates that there is no data in the FIFO queue. Conversely, the empty flag signal is inverted to obtain the non-empty signal. The non-empty signal being 1 indicates that there is unread data in the FIFO queue. Therefore, the non-empty signals of the four FIFO queues are led out as the arbitration request signals of the four FIFO queues.

5. The AXI bus matrix interface based on a priority queue according to claim 3, wherein The write enable of the FIFO queue is determined by the AWVALID signal and the AWREADY signal of the AW channel. The AWVALID signal and the AWREADY signal are handshake signals in the AXI protocol. Only when both the AWVALID signal and the AWREADY signal are high can the transmission of an AXI transaction signal be completed. When the AWVALID signal is high, it indicates that the AXI transaction signal in this cycle is valid; otherwise, it is invalid. When the AWREADY signal is high, it indicates that the FIFO queue is idle in this cycle and can receive the AXI transaction signal. When it is low, it indicates that the FIFO queue is full in this cycle and cannot receive the AXI transaction signal.

6. The AXI bus matrix interface based on a priority queue according to claim 3, characterized in that When the host continuously sends 3 AW channel transaction signals, in chronological order, they are transaction 0, transaction 1, and transaction 2. The priority of transaction 0 is 0, and the priorities of both transaction 1 and transaction 2 are 1. It is stipulated that priority 1 is higher than priority 0. The host first issues transaction 0. The data encapsulator encapsulates each signal of the AW channel. The priority decoder decodes according to the value of its Qos signal and obtains that the priority of transaction 0 is 0. The second data selector selects the non-full signal of FIFO queue 0 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 0 according to the decoding result. Since both the AWVALID signal and the AWREADY signal are 1, the write enable of FIFO queue 0 is valid, and the first data distributor stores transaction 0 into the corresponding FIFO queue 0. Next, the host issues transaction 1. Similarly, the data encapsulator encapsulates each signal of the AW channel. The priority decoder decodes according to the value of its Qos signal and obtains that the priority of transaction 1 is 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. Since both the AWVALID signal and the AWREADY signal are 1, the write enable of FIFO queue 1 is valid, and the first data distributor stores transaction 1 into the corresponding FIFO queue 1. Next, the host issues transaction 2. Similarly, the data encapsulator encapsulates each signal of the AW channel. The priority decoder decodes according to the value of its Qos signal and obtains that the priority of transaction 2 is also 1. The second data selector selects the non-full signal of FIFO queue 1 as the AWREADY signal according to the decoding result. At this time, the AWREADY signal is 1. Similarly, the second data distributor sends the AWVALID signal to FIFO queue 1 according to the decoding result. Since both the AWVALID signal and the AWREADY signal are 1, the write enable of FIFO queue 1 is valid. At this time, FIFO queue 1 is not full and can be written normally. Therefore, the first data distributor also stores transaction 2 into the corresponding FIFO queue 1. After transactions 0, 1, and 2 are all stored in their corresponding FIFO queues, there are transactions in both FIFO queue 0 and FIFO queue 1 at this time. The non-empty signals of FIFO queue 0 and FIFO queue 1 are both 1, acting as arbitration request signals. Because the priority of FIFO queue 1 is high, the priority arbiter first allows the transaction in FIFO queue 1 to be read out. Since the rule of the FIFO queue is first in, first out, transaction 1 in FIFO queue 1 is read out first; in the next cycle, because there are still transactions stored in FIFO queue 0 and FIFO queue 1, the next round of arbitration is carried out. The priority arbiter also allows FIFO queue 1 to be read out first. At this time, transaction 2 in FIFO queue 1 is read out; in the next cycle, because all the data in FIFO queue 1 has been read out and only FIFO queue 0 participates in the arbitration, the priority arbiter allows FIFO queue 0 to be read out. At this time, transaction 0 in FIFO queue 0 is read out.

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