System on chip and control method

Abstract

The present invention provides a system on chip and a control method. The system on chip includes a substrate and a plurality of CPU cores integrated in the substrate. The system on chip also includes a plurality of clock networks respectively configured for each CPU core, and the clock network includes a plurality of delay chains. For any clock network, two sections of the delay chains are connected end to end through a signal controller to form an entry circuit. Through the control of the signal controller, the entry circuit has a first state and a second state. In the first state, a standard clock signal enters the clock network through one section of the delay chain. In the second state, the standard clock signal oscillates between the two sections of the delay chain. Through the setting of the entry circuit in the clock network, a part of the clock network can be flexibly converted into a ring oscillation network to generate an oscillation frequency signal. The reliability of the CPU core can be evaluated by analyzing the oscillation frequency signal generated by the entry circuit, thereby realizing online reliability testing of the system on chip.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU system structure, and in particular to a system on chip and a control method. Background Art

[0002] With the rapid development of semiconductor technology, the integration of system-on-chip (SoC) has been significantly improved, from thousands of transistors in the beginning to tens of billions today. Therefore, SoC can integrate multiple functional modules, including processor cores (such as CPU and GPU), memory modules (such as RAM and ROM), high-speed interfaces (such as PCIe), high-speed storage controllers (such as DDR), complex bus networks, and security processing modules. Currently, the CPU in a cloud server is a typical system-on-chip.

[0003] Compared with client CPUs, server CPUs need to work in a 24-hour uninterrupted operating environment. Therefore, the reliability of server CPUs is particularly important. However, it is currently impossible to accurately determine the true reliability or service life of each CPU chip on the production line. This is because the reliability of the chip is affected by its inherent manufacturing quality and is closely related to the workload in actual applications. Therefore, traditionally, the evaluation of the reliability and life of CPU chips mainly relies on statistical models and conservative verification and screening methods for prediction. After the CPU chip is actually deployed, due to the lack of effective online reliability testing methods, it can only be maintained by passively monitoring faults and replacing them. Summary of the invention

[0004] The object of the present invention is to provide a system on chip and a control method which can perform online testing on its own reliability during actual operation.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a system on chip, which includes a substrate and a plurality of CPU cores integrated in the substrate, the system on chip also includes a plurality of clock networks respectively configured for each of the CPU cores, the clock network includes a plurality of delay chains, the delay chain includes a plurality of basic delay circuits connected to each other, the delay chain is used to delay a standard clock signal to obtain a corresponding target clock signal; for any of the clock networks, two of the delay chains are connected end to end through a signal controller to form an entry circuit; through the control of the signal controller, the entry circuit has a first state and a second state, in the first state, the standard clock signal enters the clock network via one of the delay chains; in the second state, the standard clock signal oscillates between the two delay chains.

[0006] Preferably, the signal controller includes a first signal selector, a second signal selector and a signal switch;

[0007] A first one of the two delay chains in the entry circuit includes a first end and a second end, and a second one of the two delay chains in the entry circuit includes a third end and a fourth end;

[0008] The signal output end of the first signal selector is connected to the first end, the output end of the second signal selector is connected to the third end, and the signal switch is located between the input end of the first signal selector and the fourth end; the signal input end of the second signal selector is connected to the second end, and the input end of the first signal selector is also used to receive the standard clock signal; the first signal selector, the second signal selector and the signal switch change their working states according to the received control signal so that the entry circuit switches between the first state and the second state.

[0009] Preferably, the entry circuit further includes a frequency calculator, which is connected to one end of the signal switch close to the first signal selector, and is used to calculate the oscillation frequency of the entry circuit in the second state.

[0010] Preferably, a plurality of interface modules are integrated in the substrate, and the entry circuit is configured in the clock network corresponding to the interface modules.

[0011] Preferably, the basic delay circuit includes any one of a gate circuit, a buffer, and a trigger.

[0012] The present invention also provides a system-on-chip control method, wherein the system-on-chip includes a substrate and a plurality of CPU cores integrated in the substrate, the system-on-chip also includes a plurality of clock networks respectively configured for each of the CPU cores, the clock network includes a plurality of delay chains, the delay chain includes a plurality of basic delay circuits connected to each other, the delay chain is used to delay a standard clock signal to obtain a corresponding target clock signal; for any of the clock networks, two sections of the delay chain are connected end to end through a signal controller to form an entry circuit; the standard clock signal enters the clock network via the entry circuit;

[0013] The control method includes a first method for controlling the system on chip to be in a working mode and a second method for controlling the system on chip to be in a self-test mode;

[0014] The first method comprises: the signal controller controls the entry circuit to enter a first state according to a received first control signal, in which the standard clock signal enters the clock network via one section of the delay chain;

[0015] The second method comprises: the signal controller controls the entry circuit to enter a second state according to the received second control signal, in which the standard clock signal oscillates between the two delay chains;

[0016] When the system on chip is in the self-test mode, an oscillation frequency signal of the entry circuit is received, and the reliability of the CPU core to which the entry circuit belongs is analyzed based on the oscillation frequency signal.

[0017] Preferably, the signal controller includes a first signal selector, a second signal selector and a signal switch;

[0018] A first one of the two delay chains in the entry circuit includes a first end and a second end, and a second one of the two delay chains in the entry circuit includes a third end and a fourth end;

[0019] The signal output end of the first signal selector is connected to the first end, the output end of the second signal selector is connected to the third end, and the signal switch is located between the input end of the first signal selector and the fourth end; the signal input end of the second signal selector is connected to the second end, and the input end of the first signal selector is also used to receive the standard clock signal; the first signal selector, the second signal selector and the signal switch change their working states according to the received control signal, so that the entry circuit changes between the first state and the second state;

[0020] The first method comprises: the first signal selector opens a channel for receiving signals according to the first control signal received, the second signal selector closes the channel for receiving signals according to the first control signal, the signal switch closes the signal channel passing therethrough according to the first control signal, and the standard clock signal enters the clock network via the first signal selector, the first end, and the second end in sequence;

[0021] The second method includes: the first signal selector and the second signal selector open a channel for receiving signals according to the received second control signal, the signal switch opens a signal channel passing therethrough according to the second control signal, and the standard clock signal oscillates between the first end, the second end, the third end, and the fourth end.

[0022] Preferably, the entry circuit further comprises a frequency calculator, and the frequency calculator is connected to one end of the signal switch close to the first signal selector;

[0023] When the system on chip is in the self-test mode, the frequency calculator calculates the oscillation frequency of the entry circuit and outputs the oscillation frequency signal.

[0024] Preferably, the overall reliability of the system on chip is evaluated based on the oscillation frequency signals of all CPU cores.

[0025] Preferably, a plurality of interface modules are integrated in the substrate, and the entry circuit is configured in the clock network corresponding to the interface modules.

[0026] Compared with the prior art, the system on chip and control method provided by the above technical solution of the present invention configure a clock network for each CPU core on the system on chip, and transform a part of the delay chain of the clock network into an entry circuit through a signal controller, so that when the system on chip is in normal working state, the entry circuit is part of the clock network, receiving and transmitting the standard clock signal; when the system on chip is in self-test mode, the standard clock signal oscillates in the entry circuit to generate an oscillation frequency signal, and the reliability of the CPU core is closely related to the oscillation frequency of the clock network therein. Therefore, the reliability of the CPU core can be evaluated by analyzing the oscillation frequency signal generated by the entry circuit, thereby realizing online reliability testing of the system on chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. 4 is a schematic diagram of the system structure of the system on chip in an embodiment of the present invention.

[0028] Figure 2 Schematic diagram of the structure of a clock network adapted to each CPU core in an embodiment of the present invention.

[0029] Figure 3 for Figure 2 Circuit schematic of the middle entry circuit in the first state.

[0030] Figure 4 for Figure 2 Circuit schematic of the middle entry circuit in the second state. DETAILED DESCRIPTION

[0031] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0032] Although today's on-chip systems all have on-chip sensors, such as temperature sensors, voltage monitors, and process detectors, these sensors are only used for safety protection systems or production line chip screening, and do not have an online detection function for their own reliability. In this regard, this embodiment discloses a system on chip with a reliability self-test function.

[0033] like Figure 1 and Figure 2, the system on chip includes a substrate and several CPU cores integrated in the substrate. The system on chip also includes several clock networks TW configured for each CPU core respectively, and the clock network TW is used to provide working timing for the CPU core. In the application process, the workload of each CPU core in the system on chip cannot be the same for a long time. Therefore, the loss and aging degree of each CPU core are ultimately different. In order to avoid the situation where all are damaged due to excessive loss of a certain CPU core, the actual loss or aging degree of each CPU core is accurately detected, and the future workload is appropriately arranged according to the situation, so as to effectively optimize the reliability of the system on chip and extend its life.

[0034] like Figure 2 and Figure 3 The clock network TW includes several delay chains DC, and the delay chains DC include several basic delay circuits UT connected to each other. The delay chains DC are used to delay the standard clock signal CLKI to obtain the corresponding target clock signal.

[0035] For any clock network TW, two delay chains DC are connected end to end through a signal controller to form a ring-shaped entry circuit. The standard clock signal CLKI enters the clock network TW through the entry circuit, and the entry circuit has a first state and a second state through the control of the signal controller.

[0036] In the first state, Figure 3 , the standard clock signal CLKI enters the clock network TW through one of the delay chains DC1.

[0037] In the second state, Figure 4 , the standard clock signal CLKI oscillates between the two delay chains DC, that is, in the second state, the entry circuit is a ring oscillation circuit.

[0038] Based on the above-mentioned system on chip, the control method for controlling its working state includes a first method for controlling the system on chip to be in a working mode and a second method for controlling the system on chip to be in a self-test mode.

[0039] In the working mode, the system on chip is in a normal working state, so the first method includes: the signal controller controls the entry circuit to enter the first state according to the received first control signal C1.

[0040] In the self-test mode, the system on chip exits the working state and enters the test state to test its own reliability. Therefore, the second method includes: the signal controller controls the entry circuit to enter the second state according to the received second control signal C2. Then, the oscillation frequency signal PX of the entry circuit is received, and the reliability of the CPU core to which the entry circuit belongs can be analyzed based on the oscillation frequency signal PX.

[0041] Specifically, the basic delay circuit UT includes any one of a gate circuit, a buffer, and a trigger.

[0042] On the other hand, the signal controller includes a first signal selector U1 , a second signal selector U2 and a signal switch K.

[0043] The first one DC1 of the two delay chains DC in the entry circuit includes a first terminal D1 and a second terminal D2 , and the second one DC2 of the two delay chains DC in the entry circuit includes a third terminal D3 and a fourth terminal D4 .

[0044] The signal output terminal of the first signal selector U1 is connected to the first terminal D1, the output terminal of the second signal selector U2 is connected to the third terminal D3, and the signal switch K is located between the input terminal of the first signal selector U1 and the fourth terminal D4.

[0045] The signal input end of the second signal selector U2 is connected to the second end D2, and the input end of the first signal selector U1 is also used to receive the standard clock signal CLKI.

[0046] The first signal selector U1, the second signal selector U2 and the signal switch K change their working states according to the received control signal, so that the entry circuit switches between the first state and the second state.

[0047] To this end, the first method includes: Figure 3 The first signal selector U1 opens the channel for receiving the signal according to the received first control signal C1, the second signal selector U2 closes the channel for receiving the signal according to the first control signal C1, the signal switch K closes the signal channel passing through it according to the first control signal C1, and the standard clock signal CLKI enters the clock network TW via the first signal selector U1, the first terminal D1, the second terminal D2 and the output port CLKO in sequence.

[0048] The second method also includes: Figure 4 The first signal selector U1 and the second signal selector U2 open the channel for receiving the signal according to the received second control signal C2, the signal switch K opens the signal channel passing therethrough according to the second control signal C2, and the standard clock signal CLKI oscillates between the first terminal D1, the second terminal D2, the third terminal D3 and the fourth terminal D4.

[0049] On the other hand, the input circuit further includes a frequency calculator, which is connected to a terminal of the signal switch K close to the first signal selector U1.

[0050] In this regard, when the system on chip is in the self-test mode, the frequency calculator calculates the oscillation frequency of the input circuit and outputs an oscillation frequency signal PX. Then, the oscillation frequency signal PX can be obtained by reading the output data of the frequency calculator through the detection terminal.

[0051] Since a system on chip has multiple CPU cores, the overall reliability of the system on chip can be evaluated based on the oscillation frequency signals PX of all CPU cores. Specifically, the aging degree of each CPU core, that is, the loss rate, is analyzed by the oscillation frequency signal PX corresponding to each CPU core, and then the loss rates of multiple CPU cores are compared to evaluate the reliability of the entire system on chip with the maximum loss rate.

[0052] On the other hand, Figure 1 The matrix also integrates several interface modules, and the clock network TW corresponding to the interface modules is also configured with an entry circuit having the above structure. Therefore, by controlling the entry circuit in the interface module, the reliability of each interface module can also be evaluated.

[0053] In summary, the present invention discloses a system on chip and a control method, wherein a clock network TW is configured for each CPU core on the system on chip, and a part of the delay chain DC of the clock network TW is transformed into an entry circuit through a signal controller, so that when the system on chip is in a normal working state, the entry circuit is a part of the clock network TW, receiving and transmitting a standard clock signal CLKI; and when the system on chip is in a self-test mode, the standard clock signal CLKI oscillates in the entry circuit to generate an oscillation frequency signal PX, and the reliability of the CPU core is closely related to the oscillation frequency of the clock network TW therein. Therefore, the reliability of the CPU core can be evaluated by analyzing the oscillation frequency signal PX generated by the entry circuit, thereby realizing online reliability testing of the system on chip.

[0054] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A system on chip, characterized in that: It includes a substrate and a plurality of CPU cores integrated in the substrate, and the system on chip also includes a plurality of clock networks respectively configured for each of the CPU cores, the clock network includes a plurality of delay chains, the delay chain includes a plurality of basic delay circuits connected to each other, and the delay chain is used to delay a standard clock signal to obtain a corresponding target clock signal; for any of the clock networks, two sections of the delay chain are connected end to end through a signal controller to form an entry circuit; through the control of the signal controller, the entry circuit has a first state and a second state, in the first state, the standard clock signal enters the clock network via one section of the delay chain; in the second state, the standard clock signal oscillates between the two sections of the delay chain.

2. The system on chip according to claim 1, characterized in that: The signal controller includes a first signal selector, a second signal selector and a signal switch; A first one of the two delay chains in the entry circuit includes a first end and a second end, and a second one of the two delay chains in the entry circuit includes a third end and a fourth end; The signal output end of the first signal selector is connected to the first end, the output end of the second signal selector is connected to the third end, and the signal switch is located between the input end of the first signal selector and the fourth end; the signal input end of the second signal selector is connected to the second end, and the input end of the first signal selector is also used to receive the standard clock signal; the first signal selector, the second signal selector and the signal switch change their working states according to the received control signal so that the entry circuit switches between the first state and the second state.

3. The system on chip according to claim 2, characterized in that: The entry circuit further includes a frequency calculator, which is connected to one end of the signal switch close to the first signal selector, and is used to calculate the oscillation frequency of the entry circuit in the second state.

4. The system on chip according to claim 1, characterized in that: Several interface modules are also integrated in the substrate, and the entry circuit is configured in the clock network corresponding to the interface modules.

5. The system on chip according to claim 1, characterized in that: The basic delay circuit includes any one of a gate circuit, a buffer, and a trigger.

6. A system on chip control method, characterized in that: The system on chip includes a substrate and a plurality of CPU cores integrated in the substrate, and the system on chip also includes a plurality of clock networks respectively configured for each of the CPU cores, the clock network includes a plurality of delay chains, the delay chain includes a plurality of basic delay circuits connected to each other, and the delay chain is used to delay a standard clock signal to obtain a corresponding target clock signal; for any of the clock networks, two sections of the delay chain are connected end to end through a signal controller to form an entry circuit; The standard clock signal enters the clock network via the entry circuit; The control method includes a first method for controlling the system on chip to be in a working mode and a second method for controlling the system on chip to be in a self-test mode; The first method comprises: the signal controller controls the entry circuit to enter a first state according to a received first control signal, in which the standard clock signal enters the clock network via one section of the delay chain; The second method comprises: the signal controller controls the entry circuit to enter a second state according to the received second control signal, in which the standard clock signal oscillates between the two delay chains; When the system on chip is in the self-test mode, an oscillation frequency signal of the entry circuit is received, and the reliability of the CPU core to which the entry circuit belongs is analyzed based on the oscillation frequency signal.

7. The system on chip control method according to claim 6, characterized in that: The signal controller includes a first signal selector, a second signal selector and a signal switch; A first one of the two delay chains in the entry circuit includes a first end and a second end, and a second one of the two delay chains in the entry circuit includes a third end and a fourth end; The signal output end of the first signal selector is connected to the first end, the output end of the second signal selector is connected to the third end, and the signal switch is located between the input end of the first signal selector and the fourth end; the signal input end of the second signal selector is connected to the second end, and the input end of the first signal selector is also used to receive the standard clock signal; the first signal selector, the second signal selector and the signal switch change their working states according to the received control signal, so that the entry circuit changes between the first state and the second state; The first method comprises: the first signal selector opens a channel for receiving signals according to the first control signal received, the second signal selector closes the channel for receiving signals according to the first control signal, the signal switch closes the signal channel passing therethrough according to the first control signal, and the standard clock signal enters the clock network via the first signal selector, the first end, and the second end in sequence; The second method includes: the first signal selector and the second signal selector open a channel for receiving signals according to the received second control signal, the signal switch opens a signal channel passing therethrough according to the second control signal, and the standard clock signal oscillates between the first end, the second end, the third end, and the fourth end.

8. The system on chip control method according to claim 7, characterized in that: The entry circuit further comprises a frequency calculator, which is connected to a terminal of the signal switch close to the first signal selector; When the system on chip is in the self-test mode, the frequency calculator calculates the oscillation frequency of the entry circuit and outputs the oscillation frequency signal.

9. The system on chip control method according to claim 6, characterized in that: The overall reliability of the system on chip is evaluated based on the oscillation frequency signals of all CPU cores.

10. The system on chip control method according to claim 6, characterized in that: Several interface modules are also integrated in the substrate, and the entry circuit is configured in the clock network corresponding to the interface modules.

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