Electronic device method and data processing method

Abstract

The present application discloses an electronic device and a data processing method, wherein the electronic device includes a central processing unit and a field programmable gate array that support a computing fast link protocol, and based on the computing fast link protocol, the last level cache of the central processing unit and the block random access memory of the field programmable gate array are set as a shared cache, and both the central processing unit and the field programmable gate array can access the shared cache; the shared cache stores a hash data table to be processed; the central processing unit is used to process the hash data table to be processed to realize hash connection.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of data processing, and relate to but are not limited to an electronic device and a data processing method. Background Art

[0002] Large relational databases usually rely on fast joins to achieve good database performance. Especially with the current explosive growth of data, the performance of the database core algorithm hash join is restricting the development of current databases. When executing hash joins, due to the limited cache capacity of the processor and the mixing with other application data, the data table to be hash joined is easily replaced out of the cache. During the execution process, since the large table to be hash joined is divided into multiple small tables and stored in the cache, the replacement of table items also causes hash join delays, greatly reducing the acceleration performance. Summary of the invention

[0003] In view of this, an embodiment of the present application provides an electronic device and a data processing method.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides an electronic device, including a central processing unit supporting a computing fast link protocol and a field programmable logic gate array,

[0006] The last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as a shared cache based on the computing fast link protocol, and both the central processing unit and the field programmable logic gate array can access the shared cache;

[0007] The shared cache stores the hash data table to be processed;

[0008] The central processing unit is used to process the hash data table to be processed and realize hash connection.

[0009] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to an electronic device, including a central processing unit and a field programmable logic gate array that support a computing fast link protocol, and the method includes:

[0010] The central processing unit processes the hash data table to be processed stored in the shared cache to realize hash connection, wherein the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as shared caches based on the computing fast link protocol, and both the central processing unit and the field programmable logic gate array can access the shared cache.

[0011] In a third aspect, an embodiment of the present application provides a data processing device for processing a hash data table to be processed stored in a shared cache to realize a hash connection, wherein the last level cache of a central processing unit and a block random access memory of a field programmable logic gate array are set as a shared cache based on a computing fast link protocol, and both the central processing unit and the field programmable logic gate array can access the shared cache.

[0012] In a fourth aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the above method is implemented when the processor executes the program.

[0013] In a fifth aspect, an embodiment of the present application provides a storage medium storing executable instructions for implementing the above method when executed by a processor.

[0014] In a sixth aspect, a computer program product includes a computer program or instructions, and when the computer program or instructions are executed by a processor, the steps in the above method are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A A schematic diagram of a hash connection provided in an embodiment of the present application;

[0016] Figure 1B A schematic diagram of an electronic device provided in an embodiment of the present application;

[0017] Figure 1C A diagram of a hash-connected central processing unit cooperating with a field programmable logic gate array acceleration structure provided in an embodiment of the present application;

[0018] Figure 2A A schematic diagram of an implementation flow of a data processing method provided in an embodiment of the present application;

[0019] Figure 2B A schematic diagram of the implementation process of a hash connection method provided in an embodiment of the present application;

[0020] Figure 3 A processing flow chart of a hash connection provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a hash connection processing flow provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0023] Figure 6 A hardware entity schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the embodiments of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0025] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0028] Figure 1A A schematic diagram of a hash connection provided in an embodiment of the present application, such as Figure 1A As shown, the schematic diagram includes: a build table (Build Table) 11, a probe table (Probe Table) 12 and a hash table (Hash Table) 13, wherein:

[0029] The construction table 11 is the table selected for constructing the hash table during the hash join process. Usually, the table with the smaller estimated data volume among the two tables to be joined can be selected as the construction table 11. This is because the table with the smaller data volume can construct the hash table faster and occupies relatively less memory resources.

[0030] The exploration table 12 refers to the table selected for matching and searching with the constructed hash table during the hash join process. Usually, the exploration table 12 is the table with the larger data volume expected in the two tables to be joined. This is because the table with the larger data volume needs to traverse more rows for matching and searching, and the hash join accelerates this process by constructing a hash table.

[0031] Join is a common operation between database tables. It extracts tuples with the same columns from multiple tables to form a new table. If there are too many tuples in two tables, the overhead of traversing them one by one is very high. Hash join is a method to improve the efficiency of join. Hash join is mainly divided into two phases: build phase and probe phase.

[0032] Establishment phase: select a construction table 11, use a hash function to obtain a hash value for the join attribute on each tuple therein, and thus establish a hash table.

[0033] Detection phase: For the exploration table 12, scan each row of it and calculate the hash value of the connection attribute, compare it with the hash table established by the construction table 11, and if there are rows that fall into the same bucket and satisfy the connection predicate, they are connected to form a new table.

[0034] Large relational databases often rely on fast join implementations to achieve good database performance. Especially with the current explosive growth of data, the performance of the database core algorithm hash join is restricting the development of current databases. Academia and industry have also been developing new architectures that may further improve performance. Hashing is a common method for implementing table joins, but its poor spatial locality may hinder the performance of processor architectures.

[0035] Multithreaded architectures can better cope with poor spatial locality by masking the memory / cache latency of many outstanding requests. Also, if the memory is large enough, the entire hash table is in memory during the process of building the hash table, and is only put on disk after the join operation is completed.

[0036] However, this process will also bring a lot of I / O operations. In addition, the current memory latency is too long to meet the growing requirements of a large number of database operations.

[0037] The present application embodiment provides an electronic device, such as Figure 1B As shown, the electronic device includes a central processing unit 14 and a field programmable logic gate array 15, wherein:

[0038] The last level cache (LLC) of the central processing unit (CPU) 15 and the block random access memory (BRAM) of the field programmable gate array (FPGA) 14 are set as a shared cache based on the computing fast link protocol (CXL), and both the central processing unit 15 and the field programmable gate array 14 can access the shared cache;

[0039] Here, CXL is an interconnection technology used between the CPU and the accelerator (FPGA). It provides a cache-based consistency protocol. The host (CPU) and the accelerator share the cache and ensure data consistency. Data interaction and transmission can be achieved by directly operating the cache line between the host and FPGA and other accelerators. Compared with the traditional data sharing memory method, the cache consistency method based on CXL greatly reduces the delay problem of data transmission and improves the transmission bandwidth.

[0040] The last level cache is the highest level cache in the multi-level cache hierarchy in computer architecture. It is usually located between processor cores and serves as a high-speed data exchange buffer between main memory (DRAM) and processor cores. In a multi-core processor system, the last level cache is usually shared by all cores to store larger data blocks for fast access.

[0041] Block random access memory refers to a high-speed, large-capacity memory integrated inside the FPGA.

[0042] In the implementation process, the CPU can be connected to one or more FPGA accelerator cards with CXL characteristics by using CXL type 1 and type 2. Among them, both CXL type 1 and type 2 can interact with the host through the CXL.cache protocol. Figure 1B As shown, both the CPU 15 and the FPGA 14 can access the shared cache via the CXL.cache protocol.

[0043] The identifiers 1 to N in the central processor 15 represent different cores, and L1 and L2 represent caches corresponding to different cores.

[0044] Combining the advantages of software CPU processing and FPGA processing, the capacity of the cache expanded horizontally by CXL can be obtained using the following formula (1):

[0045] Shared cache capacity = CPU LLC capacity + N × FPGA BRAM capacity (1);

[0046] During implementation, both the CPU 15 and the FPGA 14 can access data stored in the shared cache.

[0047] The shared cache stores a hash data table to be processed;

[0048] Here, the two large tables (construction table 11 and exploration table 12) of the large-capacity database hash connection can be placed in the shared cache for processing as much as possible, which greatly reduces the number of block times of the large table, thereby reducing the overhead caused by data replacement and data merging.

[0049] Here, the hash data table to be processed includes a construction table 11 and a search table 12 .

[0050] During implementation, the build table 11 and the probe table 12 may be stored in the shared cache.

[0051] The central processor 15 is used to process the hash data table to be processed to implement hash connection.

[0052] In some embodiments, the overall task can be divided into two parts, a portion of the data is hashed in the CPU, and a portion of the data is hashed in the FPGA.

[0053] In some embodiments, the build table can be stored in the block random access memory of the FPGA, and the probe table can be stored in the last level cache of the central processing unit. The CPU and FPGA can be used in parallel to implement a hash connection solution, that is, the CPU can be used alone to process the hash connection of the build table and the probe table, or the FPGA can be used alone to process the hash connection of the build table and the probe table.

[0054] The above solutions are better than the pure software CPU implementation and the pure hardware FPGA acceleration method. The CPU can use the last level cache to implement partition hash join.

[0055] In an embodiment of the present application, an electronic device includes a central processing unit and a field programmable logic gate array that support a fast computing link protocol. Based on the fast computing link protocol, the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as a shared cache, and both the central processing unit and the field programmable logic gate array can access the shared cache; the hash data table to be processed is stored in the shared cache; the central processing unit is used to process the hash data table to be processed to realize hash connection. In this way, by using the fast computing link technology, the cache consistency sharing mode of the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array is set, and the software and hardware simultaneously realize hash connection. The central processing unit and the field programmable logic gate array quickly share the result synchronization mechanism through the cache consistency, and the results processed by the central processing unit and the field programmable logic gate array can be quickly shared through cache consistency, thereby reducing the communication delay between the central processing unit and the field programmable logic gate array. By extending the block random access memory of the field programmable logic gate array to the last level cache of the central processing unit, the number of entries that can accommodate table entries is increased in a way of increasing the capacity of the shared memory. The central processing unit and the field programmable logic gate array are realized to accelerate the hash connection process at the same time.

[0056] In some embodiments, the to-be-processed hash data table includes a build table and a probe table;

[0057] The central processor is used to process the hash data table to be processed and implement hash connection, including:

[0058] The central processor is configured to load the construction table into the block random access memory and load the probe table into the last level cache when determining that the first data amount of the construction table is less than or equal to the storage capacity of the block random access memory;

[0059] During implementation, the central processing unit may first compare the first data amount of the build table with the storage capacity of the block random access memory of the field programmable logic gate array, and load the build table into the block random access memory when it is determined that the first data amount of the build table is less than or equal to the storage capacity of the block random access memory, that is, the build table can be fully loaded into the block random access memory. At the same time, the probe table is loaded into the last level cache.

[0060] Figure 1C A hash-connected CPU coordinated with a field programmable logic gate array acceleration structure diagram provided in an embodiment of the present application is shown in FIG. Figure 1C As shown, the structure diagram includes a field programmable gate array (FPGA) 14, a central processing unit (CPU) 15, a build table (Build Table) 11 and a probe table (Probe Table) 12, wherein:

[0061] When performing hash connection, when it is determined that the first data amount of the construction table 11 is less than or equal to the block random access memory capacity of the FPGA, the construction table 11 can be loaded into the block random access memory of the field programmable logic gate array, and the search table 12 can be loaded into the last level cache of the central processing unit 15.

[0062] By utilizing the cache consistency of the computing fast link protocol, the central processor is further used to control the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table.

[0063] During implementation, the shared cache consistency of CXL can be used to control the field programmable logic gate array to collaboratively process the build table and the probe table to implement the hash join operation.

[0064] In the embodiment of the present application, first, when the central processing unit determines that the first data amount of the build table is less than or equal to the storage capacity of the block random access memory, the build table is loaded into the block random access memory, and the probe table is loaded into the last level cache; then, by calculating the cache consistency of the fast link protocol, the central processing unit also controls the field programmable logic gate array to collaboratively process the build table and the probe table to achieve the hash connection of the build table and the probe table. In this way, the build table is loaded into the block random access memory, and the probe table is loaded into the last level cache, and the central processing unit or the field programmable logic gate array collaboratively processes the overall hash connection task, so that the processing performance of the overall hash connection is maximized.

[0065] In some embodiments, the field programmable logic gate array is provided with a computing fast link interface, and receives instructions sent by the central processing unit through the computing fast link interface;

[0066] Here, CXL.cache, defines the interaction between the processor and the device, allowing connected hardware accelerators (such as FPGAs) to efficiently cache processor memory with extremely low latency.

[0067] During the implementation process, the CXL interface circuit on the FPGA can be designed according to the CXL protocol specification, including the design of the physical layer, data link layer, and transaction layer. The CXL interface on the FPGA can meet the needs of high-speed data transmission and memory access.

[0068] The CPU can send instructions to the FPGA via CXL.

[0069] The central processor is further used to control the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table, including:

[0070] The central processing unit is used to process the construction table and the exploration table to achieve a hash connection between the construction table and the exploration table;

[0071] During implementation, the central processing unit may separately process the build table and the probe table stored in the shared cache to implement a hash connection of the build table and the probe table.

[0072] or,

[0073] The central processing unit is used to send instructions to the field programmable logic gate array through the computing fast link interface, so that the field programmable logic gate array processes the construction table and the exploration table to achieve hash connection of the construction table and the exploration table.

[0074] Here, the field programmable gate array can independently implement hash connection, that is, utilize the powerful parallel data processing capability of the field programmable gate array to realize high-performance hash connection.

[0075] During implementation, the central processor may send an instruction for instructing the field programmable logic gate array to perform hash connection on the build table and the probe table through the computing fast link interface; after receiving the instruction, the field programmable logic gate array performs hash connection on the build table and the probe table.

[0076] In the embodiment of the present application, the central processing unit can process the build table and the probe table stored in the shared cache separately to realize the hash connection of the build table and the probe table. The central processing unit can also send instructions to the field programmable logic gate array through the computing fast link interface, so that the field programmable logic gate array processes the build table and the probe table to realize the hash connection. In this way, the overall processing performance can be maximized by processing the build table and the probe table by the central processing unit or the field programmable logic gate array, and a high-performance hash connection can be realized.

[0077] In some embodiments, the central processor is further configured to, when determining that the first data amount of the build table is greater than the storage capacity of the block random access memory, perform block processing on the build table and the probe table based on the capacity of the shared cache, determine the first build table and the first probe table to be loaded into the last level cache, and the second build table and the second probe table to be loaded into the block random access memory;

[0078] Here, since the first data volume of the build table is larger than the storage capacity of the block random access memory, the build table and the exploration table are divided into blocks based on the capacity of the shared cache, so that the two large tables (build table and exploration table) hashed together by the large-capacity database can be placed in the shared cache as much as possible for processing, which greatly reduces the number of times the large table is divided into blocks, thereby reducing the overhead caused by data replacement in and out and data merging.

[0079] The central processor is further configured to perform a first hash connection between the first build table and the first search table, and simultaneously send an instruction to the field programmable logic gate array so that the field programmable logic gate array performs a second hash connection between the second build table and the second search table;

[0080] Here, the overall task can be divided into two parts. A portion of the data (the first build table and the first search table) is hashed in the central processing unit, and a portion of the data (the second build table and the second search table) is hashed in the field programmable logic gate array.

[0081] The central processing unit is further configured to summarize the first hash connection and the second hash connection to obtain a hash connection between the construction table and the exploration table.

[0082] During the implementation process, the central processing unit collects the second hash connection result of the field programmable logic gate array, and overall merges the results of the first hash connection and the second hash connection through the consistency of the shared cache.

[0083] In the embodiment of the present application, when the central processing unit determines that the first data volume of the construction table is greater than the storage capacity of the block random access memory, the construction table and the exploration table are respectively processed in blocks based on the capacity of the shared cache, and the first construction table and the first exploration table loaded into the last level cache, as well as the second construction table and the second exploration table loaded into the block random access memory are determined; then the central processing unit executes the first hash connection of the first construction table and the first exploration table, and sends an instruction to the field programmable logic gate array at the same time, so that the field programmable logic gate array executes the second hash connection of the second construction table and the second exploration table; finally, the central processing unit summarizes the first hash connection and the second hash connection to obtain the hash connection of the construction table and the exploration table. In this way, a cache sharing method with shared cache consistency is adopted to realize seamless cache sharing of the hash connection calculation results of the field programmable logic gate array and the hash connection calculation results of the central processing unit, realize a low-latency hash connection result sharing method, and improve the overall hash connection performance.

[0084] In some embodiments, the electronic device includes a plurality of field programmable logic gate arrays, and a block random access memory is provided in each of the field programmable logic gate arrays;

[0085] The method of setting the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array as a shared cache based on the computing fast link protocol includes:

[0086] The last level cache of the central processing unit and the plurality of block random access memories corresponding to the plurality of field programmable logic gate arrays are set as the shared cache based on the computing fast link protocol.

[0087] During the implementation process, multiple field programmable gate arrays can be set in the electronic device to increase the number of FPGA board links. Multiple FPGA boards can expand the last-level cache capacity of the CPU, that is, effectively increase the capacity of the shared cache, so that heterogeneous computing can be processed in the CPU or FPGA according to its characteristics.

[0088] In the embodiment of the present application, the last level cache of the central processing unit and multiple block random access memories corresponding to multiple field programmable logic gate arrays are set as shared caches based on the computing fast link protocol. In this way, by sharing the cache with more field programmable logic gate arrays, the task of hash connection can be further shared, and a larger hash connection data set can be executed, thereby increasing the overall database performance.

[0089] The present application provides a data processing method, which is applied to an electronic device, wherein the electronic device includes a central processing unit and a field programmable logic gate array that support a computing fast link protocol, such as Figure 2A As shown, this can be achieved by following the steps below:

[0090] Step S200, the central processing unit processes the hash data table to be processed stored in the shared cache to realize hash connection, wherein the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as the shared cache based on the calculation of the fast link protocol, and the central processing unit and the field programmable logic gate array can both access the shared cache.

[0091] In the implementation process, the CPU can be connected to one or more FPGA accelerator cards with CXL characteristics by using CXL type 1 and type 2. Among them, both CXL type 1 and type 2 can interact with the host through the CXL.cache protocol.

[0092] Combining the advantages of software CPU processing and FPGA processing, the capacity of the cache expanded horizontally by CXL can be obtained using the following formula (1):

[0093] Shared cache capacity = CPU LLC capacity + N × FPGA BRAM capacity (1);

[0094] During the implementation process, Figure 1B As shown, the CPU 15 and the FPGA 14 can both access the data stored in the shared cache. The shared cache can store the build table 11 and the probe table 12. The CPU 15 processes the hash data table to be processed to implement hash connection.

[0095] In the embodiment of the present application, the computing fast link technology is used to set the cache consistency sharing mode of the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array, and the software and hardware simultaneously realize the hash connection. The central processing unit and the field programmable logic gate array quickly share the result synchronization mechanism through the cache consistency. The results processed by the central processing unit and the field programmable logic gate array can be quickly shared through cache consistency, reducing the communication delay between the central processing unit and the field programmable logic gate array. By extending the block random access memory of the field programmable logic gate array to the last level cache of the central processing unit, the number of entries that can accommodate table entries is increased in a way that increases the shared memory capacity. The central processing unit and the field programmable logic gate array are realized to accelerate the hash connection process at the same time.

[0096] In some embodiments, the hash data table to be processed includes a construction table and a search table; in the above step S200, "the central processor processes the hash data table to be processed stored in the shared cache to implement hash connection", such as Figure 2B As shown, this can be achieved by following the steps below:

[0097] Step S201, the central processing unit determines that the first data amount of the construction table is less than or equal to the storage capacity of the block random access memory set in the field programmable logic gate array;

[0098] During implementation, the central processor may first compare the first data volume of the construction table with the storage capacity of the block random access memory of the field programmable logic gate array to determine that the first data volume of the construction table is less than or equal to the storage capacity of the block random access memory.

[0099] Step S202, the central processing unit loads the construction table into the block random access memory, and loads the search table into the last level cache set in the central processing unit;

[0100] Here, if the build table can be fully loaded into the block random access memory, the build table is loaded into the block random access memory, and the probe table is loaded into the last level cache at the same time.

[0101] Step S203: using the cache consistency of the computing fast link protocol, the central processing unit controls the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table.

[0102] In the embodiment of the present application, first, when the central processing unit determines that the first data amount of the build table is less than or equal to the storage capacity of the block random access memory, the build table is loaded into the block random access memory, and the probe table is loaded into the last level cache; then, by calculating the cache consistency of the fast link protocol, the central processing unit also controls the field programmable logic gate array to collaboratively process the build table and the probe table to achieve the hash connection of the build table and the probe table. In this way, the build table is loaded into the block random access memory, and the probe table is loaded into the last level cache, and the central processing unit or the field programmable logic gate array collaboratively processes the overall hash connection task, so that the processing performance of the overall hash connection is maximized.

[0103] In some embodiments, the field programmable logic gate array is provided with a computing fast link interface, and receives instructions sent by the central processing unit through the computing fast link interface; the above step S203 "using the cache consistency of the computing fast link protocol, the central processing unit controls the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table" can be implemented by the following steps:

[0104] Step 2031, the central processing unit processes the construction table and the exploration table to implement a hash connection between the construction table and the exploration table;

[0105] Here, we can design the CXL interface circuit on the FPGA according to the CXL protocol specification, including the design of the physical layer, data link layer, and transaction layer. Implementing the CXL interface on the FPGA can meet the needs of high-speed data transmission and memory access.

[0106] During implementation, the central processing unit may separately process the build table and the probe table stored in the shared cache to implement a hash connection of the build table and the probe table.

[0107] or,

[0108] Step 2032: The central processing unit sends instructions to the field programmable gate array through the computing fast link interface, so that the field programmable gate array processes the build table and the probe table to achieve a hash connection between the build table and the probe table.

[0109] Here, the field programmable gate array can independently implement hash connection, that is, utilize the powerful parallel data processing capability of the field programmable gate array to realize high-performance hash connection.

[0110] During implementation, the central processor may send an instruction for instructing the field programmable logic gate array to perform hash connection on the build table and the probe table through the computing fast link interface; after receiving the instruction, the field programmable logic gate array performs hash connection on the build table and the probe table.

[0111] In the embodiment of the present application, the central processing unit can process the build table and the probe table stored in the shared cache separately to realize the hash connection of the build table and the probe table. The central processing unit can also send instructions to the field programmable logic gate array through the computing fast link interface, so that the field programmable logic gate array processes the build table and the probe table to realize the hash connection. In this way, the overall processing performance can be maximized by processing the build table and the probe table by the central processing unit or the field programmable logic gate array, and a high-performance hash connection can be realized.

[0112] In some embodiments, in the above step S200, "the central processor processes the hash data table to be processed stored in the shared cache to implement hash connection" can also be implemented by the following steps:

[0113] Step S204, the central processor determines that the first data amount of the construction table is greater than the storage capacity of the block random access memory;

[0114] Step S205: block-processing the build table and the probe table based on the capacity of the shared cache, and determine a first build table and a first probe table to be loaded into the last-level cache, and a second build table and a second probe table to be loaded into the block random access memory;

[0115] Here, since the first data volume of the build table is larger than the storage capacity of the block random access memory, the central processing unit can perform block processing on the build table and the exploration table respectively based on the capacity of the shared cache, so that the two large tables (build table and exploration table) hashed together by the large-capacity database can be placed in the shared cache for processing as much as possible, which greatly reduces the number of block partitions of the large table, thereby reducing the overhead caused by data replacement in and out and data merging.

[0116] Step S206, performing a first hash connection between the first construction table and the first exploration table;

[0117] During implementation, the central processing unit performs a first hash connection between a first build table stored in the last level cache and a first search table.

[0118] Step S207: sending an instruction to the field programmable logic gate array, so that the field programmable logic gate array performs a second hash connection between the second construction table and the second search table;

[0119] During implementation, the CPU sends an instruction to the FPGA, so that the FPGA executes a second hash connection between the second build table and the second search table stored in the block random access memory.

[0120] Step S208: Summarize the first hash connection and the second hash connection to obtain a hash connection of the construction table and the exploration table.

[0121] During the implementation process, the central processing unit collects the second hash connection result of the field programmable logic gate array, and overall merges the results of the first hash connection and the second hash connection through the consistency of the shared cache.

[0122] In the embodiment of the present application, a cache sharing method with shared cache consistency is adopted to achieve seamless cache sharing of the hash connection calculation results of the field programmable logic gate array and the hash connection calculation results of the central processing unit, thereby realizing a low-latency hash connection result sharing method and improving the overall hash connection performance.

[0123] In some embodiments, the electronic device includes multiple field programmable logic gate arrays, and a block random access memory is set in each of the field programmable logic gate arrays; based on the computing fast link protocol, the last level cache of the central processing unit and the multiple block random access memories corresponding to the multiple field programmable logic gate arrays are set as the shared cache.

[0124] During the implementation process, multiple field programmable gate arrays can be set in the electronic device to increase the number of FPGA board links. Multiple FPGA boards can expand the last-level cache capacity of the CPU, that is, effectively increase the capacity of the shared cache, so that heterogeneous computing can be processed in the CPU or FPGA according to its characteristics.

[0125] In the embodiment of the present application, the last level cache of the central processing unit and multiple block random access memories corresponding to multiple field programmable logic gate arrays are set as shared caches based on the computing fast link protocol. In this way, by sharing the cache with more field programmable logic gate arrays, the task of hash connection can be further shared, and a larger hash connection data set can be executed, thereby increasing the overall database performance.

[0126] Figure 3 A processing flow chart of a hash connection provided in an embodiment of the present application is as follows: Figure 3 As shown, the processing flow chart includes the following steps:

[0127] Step S310, obtaining table size;

[0128] During the implementation process, the construction table and the exploration table to be executed hash join can be obtained from the Hbase database. Call HashJoin.java to call the hash join interface to obtain the table. Among them, HBase is a distributed, column-oriented open source database.

[0129] Step S320: whether the comparison table is larger than the capacity of the FPGA;

[0130] If it is determined that the construction table is larger than the block random access memory of the FPGA, step S330 is executed; if it is determined that the construction table is less than or equal to the block random access memory of the FPGA, step S340 is executed.

[0131] In the implementation process, from the application side, when the software side receives a hash connection query request, it first determines the size of the two hash connection table entries, determines the construction table and the exploration table, and then compares the size of the construction table with the block random access memory of the FPGA.

[0132] Step S330, FPGA and CPU respectively perform hash connection;

[0133] When it is determined that the table is larger than the FPGA's block random access memory, the FPGA and CPU jointly and synchronously process the hash join mechanism, split the hash join's probe table and build table into multiple copies, load them into the FPGA's block random access memory and the CPU's last-level cache respectively, perform hash joins separately in the FPGA and CPU, and then share the results through CXL cache consistency, thus realizing the FPGA and CPU joint hash join.

[0134] During the implementation process, the interface function FPGA_CPU_u.c may be called to execute step S330.

[0135] Step S340: The FPGA stores the construction table, and the CPU stores the search table.

[0136] When it is determined that the table is smaller than the block random access memory of the FPGA, the build table is loaded into the block random access memory of the FPGA, and the large table probe is loaded into the last level cache of the CPU, so that the FPGA and the CPU can achieve a hash connection process through CXL cache consistency. There are many ways to load data into the last level cache of the CPU, for example, the probe table can be read multiple times so that the probe table resides in the last level cache. The FPGA's CXL IP directly provides a cache data interface, which can directly write the build table into the block random access memory of the FPGA.

[0137] During implementation, the interface function FPGA_CPU_s.c may be called to execute step S340.

[0138] In the embodiment of the present application, the FPGA and CPU are implemented to collaboratively process the hash join solution, reduce the number of large table blocks, reduce the number of data replacements, and improve the collaborative performance of FPGA and CPU accelerated hash joins. The cache consistency of the CXL protocol solves the latency problem of data movement and result sharing between the CPU and FPGA accelerator, and the FPGA and CPU distributed computing results are quickly shared through cache consistency.

[0139] Figure 4 A schematic diagram of a hash connection processing flow provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the hash connection process includes an FPGA processing flow and a CPU processing flow, wherein:

[0140] The CPU processing flow can be achieved through the following steps:

[0141] Step S401, Hash connection data allocation;

[0142] During the implementation process, data partitions can be divided according to the overall cache capacity (the last-level cache capacity of the CPU and the block random access memory capacity of the FPGA), and then the data processed by the CPU is loaded into the CPU cache, and the FPGA data is loaded into the block random access memory of the FPGA.

[0143] Step S402: CPU acquires data;

[0144] Step S403: The CPU alone performs hash connection; or the CPU and FPGA perform hash connection simultaneously;

[0145] When it is determined that the build table can be completely loaded into the block random access memory of the FPGA, the build table is loaded into the block random access memory of the FPGA, and the probe table is loaded into the last level cache of the CPU. That is, when the build table items are less than or equal to the storage size of the block random access memory of the FPGA, all the build table items are placed in the FPGA, and the large table probe table is loaded into the last level cache of the CPU, and the two table items are hashed together across devices through CXL cache consistency. The hash connection algorithm operation is performed by the CPU or FPGA alone.

[0146] When it is determined that the build table cannot be completely loaded into the block random access memory of the FPGA, that is, the build table entry is larger than the storage size of the block random access memory of the FPGA, the build table and the probe table are split into multiple table entries, and hash connections are performed separately in the FPGA and the CPU respectively, and then the results are shared through CXL cache consistency.

[0147] During the implementation, the CPU loads data into the last-level cache and performs hash join operations on multiple cores.

[0148] Step S404, determine whether the processing is completed;

[0149] If it is determined that the processing has been completed, execute step S405; if it is determined that the processing has not been completed, execute step S403.

[0150] Step S405: retain the result;

[0151] Step S406: The results are merged through the shared cache.

[0152] During the implementation process, the CPU uses cache consistency to merge the calculation results as a whole, and starts the next round of hash connection calculation process and data distribution calculation process in collaboration with the FPGA.

[0153] The FPGA processing flow can be implemented by following the steps below:

[0154] Step S411, CXL FPGA card initialization;

[0155] Step S412, FPGA data import;

[0156] Step S413, FPGA performs hash connection;

[0157] When it is determined that the construction table items are less than or equal to the storage size of the FPGA's block random access memory, all the construction table items are placed in the FPGA, and the large table exploration table is loaded into the CPU's last-level cache, and the two table items are hash-joined across devices through CXL cache consistency. The CPU or FPGA executes the hash join algorithm operation independently.

[0158] When it is determined that the build table cannot be completely loaded into the block random access memory of the FPGA, that is, the build table entry is larger than the storage size of the block random access memory of the FPGA, the build table and the probe table are split into multiple table entries, and hash connections are performed separately in the FPGA and the CPU respectively, and then the results are shared through CXL cache consistency.

[0159] During implementation, the FPGA loads data into a block random access memory, and if there are multiple FPGAs, the multiple FPGAs can logically calculate and process the hash connection data in parallel.

[0160] Step S414, determine whether the processing is completed;

[0161] If it is determined that the processing has been completed, execute step S415; if it is determined that the processing has not been completed, execute step S413.

[0162] Step S415: FPGA writes the result into the shared cache.

[0163] After executing the iteration, the FPGA writes the data to the shared cache.

[0164] In the embodiment of the present application, a cross-device hash connection method is supported, that is, part of the data is in the CPU cache, and part of the data is in the FPGA block random access memory, and the hash connection operation is implemented between the two devices through cache consistency. Based on the CPU and FPGA collaborative method of hash connection with shared cache consistency of CXL, a cache sharing method with cache consistency is adopted to realize seamless cache sharing of the hash connection calculation results of the FPGA and the hash connection calculation results of the CPU, realize a low-latency hash connection result sharing method, and improve the overall hash connection performance.

[0165] Based on the foregoing embodiments, an embodiment of the present application provides a data processing device, which includes the modules included, each module includes sub-modules, and can be implemented by a processor in an electronic device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0166] Figure 5 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the device 500 is used to process the hash data table to be processed stored in the shared cache to realize hash connection, wherein the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as the shared cache based on the calculation of the fast link protocol, and both the central processing unit and the field programmable logic gate array can access the shared cache.

[0167] In some embodiments, the hash data table to be processed includes a build table and a probe table; the processing device includes a first determination module 510, a first loading module 520 and a first processing module 530, wherein the first determination module 510 is used to determine that the first data volume of the build table is less than or equal to the storage capacity of the block random access memory set in the field programmable logic gate array; the first loading module 520 is used to load the build table into the block random access memory, and at the same time load the probe table into the last level cache set in the central processing unit; the first processing module 530 is used to utilize the cache consistency of the computational fast link protocol to control the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table.

[0168] In some embodiments, the field programmable logic gate array is provided with a computing fast link interface, and receives instructions sent by the central processing unit through the computing fast link interface; the first processing module 510 includes a processing submodule or an instruction sending submodule, wherein the processing submodule is used to process the build table and the probe table to realize the hash connection of the build table and the probe table; the instruction sending submodule is used to send instructions to the field programmable logic gate array through the computing fast link interface, so that the field programmable logic gate array processes the build table and the probe table to realize the hash connection of the build table and the probe table.

[0169] In some embodiments, the data processing device further includes a second determination module, a second processing module, a hash connection module, an instruction sending module and a summary module, wherein the second determination module is used to determine that the first data volume of the build table is greater than the storage capacity of the block random access memory; the second processing module is used to perform block processing on the build table and the probe table respectively based on the capacity of the shared cache, and determine the first build table and the first probe table loaded into the last level cache, and the second build table and the second probe table loaded into the block random access memory; the hash connection module is used to execute the first hash connection of the first build table and the first probe table; the instruction sending module is used to send an instruction to the field programmable logic gate array so that the field programmable logic gate array executes the second hash connection of the second build table and the second probe table; the summary module is used to summarize the first hash connection and the second hash connection to obtain the hash connection of the build table and the probe table.

[0170] In some embodiments, the electronic device includes multiple field programmable logic gate arrays, and a block random access memory is set in each of the field programmable logic gate arrays; based on the computing fast link protocol, the last level cache of the central processing unit and the multiple block random access memories corresponding to the multiple field programmable logic gate arrays are set as the shared cache.

[0171] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0172] It should be noted that in the embodiment of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable an electronic device (which can be a mobile phone, a tablet computer, a laptop computer, a desktop computer, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific combination of hardware and software.

[0173] Correspondingly, an embodiment of the present application provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the data processing method provided in the above embodiment are implemented.

[0174] Correspondingly, an embodiment of the present application provides an electronic device, Figure 6 A hardware entity diagram of an electronic device provided in an embodiment of the present application, such as Figure 6 As shown, the hardware entity of the device 600 includes: a memory 601 and a processor 602, wherein the memory 601 stores a computer program that can be run on the processor 602, and the processor 602 implements the steps in the data processing method provided in the above embodiment when executing the program.

[0175] The memory 601 is configured to store instructions and applications executable by the processor 602, and can also cache data to be processed or processed by the processor 602 and various modules in the electronic device 600 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0176] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0177] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0178] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0179] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0180] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0181] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0182] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0183] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly reflected in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable an electronic device (which can be a mobile phone, a tablet computer, a laptop computer, a desktop computer, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0184] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0185] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0186] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0187] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An electronic device comprising a central processing unit and a field programmable logic gate array supporting a computing fast link protocol, The last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as a shared cache based on the computing fast link protocol, and both the central processing unit and the field programmable logic gate array can access the shared cache; The shared cache stores a hash data table to be processed; The central processing unit is used to process the hash data table to be processed to achieve hash connection.

2. The electronic device as claimed in claim 1, wherein the hash data table to be processed comprises a construction table and a probe table; The central processor is used to process the hash data table to be processed and implement hash connection, including: The central processor is configured to load the construction table into the block random access memory and load the probe table into the last level cache when determining that the first data amount of the construction table is less than or equal to the storage capacity of the block random access memory; By utilizing the cache consistency of the computing fast link protocol, the central processor is further used to control the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table.

3. The electronic device according to claim 2, wherein the field programmable logic gate array is provided with a computing fast link interface, and receives the instruction sent by the central processing unit through the computing fast link interface; The central processor is further used to control the field programmable logic gate array to collaboratively process the build table and the probe table to achieve a hash connection between the build table and the probe table, including: The central processing unit is used to process the construction table and the exploration table to achieve a hash connection between the construction table and the exploration table; or, The central processing unit is used to send instructions to the field programmable logic gate array through the computing fast link interface, so that the field programmable logic gate array processes the construction table and the exploration table to achieve hash connection of the construction table and the exploration table.

4. The electronic device according to claim 2, The central processor is further configured to, when determining that the first data amount of the build table is greater than the storage capacity of the block random access memory, perform block processing on the build table and the probe table based on the capacity of the shared cache, determine the first build table and the first probe table to be loaded into the last level cache, and the second build table and the second probe table to be loaded into the block random access memory; The central processor is further configured to perform a first hash connection between the first build table and the first search table, and simultaneously send an instruction to the field programmable logic gate array so that the field programmable logic gate array performs a second hash connection between the second build table and the second search table; The central processing unit is further configured to summarize the first hash connection and the second hash connection to obtain a hash connection between the construction table and the exploration table.

5. The electronic device according to any one of claims 1 to 4, wherein the electronic device comprises a plurality of field programmable logic gate arrays, each of the field programmable logic gate arrays is provided with a block random access memory; The method of setting the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array as a shared cache based on the computing fast link protocol includes: The last level cache of the central processing unit and the plurality of block random access memories corresponding to the plurality of field programmable logic gate arrays are set as the shared cache based on the computing fast link protocol.

6. A data processing method, applied to an electronic device, the electronic device comprising a central processing unit and a field programmable logic gate array supporting a computing fast link protocol, the method comprising: The central processing unit processes a hash data table to be processed stored in a shared cache to implement a hash connection, wherein the last level cache of the central processing unit and the block random access memory of the field programmable logic gate array are set as the shared cache based on a computing fast link protocol, and both the central processing unit and the field programmable logic gate array can access the shared cache.

7. The method according to claim 6, wherein the hash data table to be processed comprises a construction table and a probe table; The central processing unit processes the hash data table to be processed stored in the shared cache to implement hash connection, including: The central processing unit determines that the first data amount of the construction table is less than or equal to the storage capacity of the block random access memory provided in the field programmable logic gate array; The central processing unit loads the construction table into the block random access memory and simultaneously loads the probe table into a last level cache provided in the central processing unit; By utilizing the cache consistency of the computing fast link protocol, the central processing unit controls the field programmable logic gate array to collaboratively process the build table and the probe table to implement a hash connection between the build table and the probe table.

8. The method according to claim 7, wherein the field programmable logic gate array is provided with a computing fast link interface, and receives the instruction sent by the central processing unit through the computing fast link interface; The method of utilizing the cache consistency of the computing fast link protocol and controlling the field programmable logic gate array to collaboratively process the build table and the probe table to implement a hash connection between the build table and the probe table comprises: The central processing unit processes the build table and the probe table to implement a hash connection between the build table and the probe table; or, The central processing unit sends instructions to the field programmable logic gate array through the computing fast link interface, so that the field programmable logic gate array processes the construction table and the exploration table to achieve hash connection of the construction table and the exploration table.

9. The method of claim 7, further comprising: The central processor determines that the first data amount of the construction table is greater than the storage capacity of the block random access memory; Based on the capacity of the shared cache, the build table and the probe table are respectively processed in blocks to determine a first build table and a first probe table to be loaded into the last level cache, and a second build table and a second probe table to be loaded into the block random access memory; performing a first hash join of the first build table and the first search table; Sending an instruction to the field programmable logic gate array to cause the field programmable logic gate array to perform a second hash connection of the second build table and the second search table; The first hash connection and the second hash connection are summarized to obtain a hash connection of the build table and the exploration table.

10. The method according to any one of claims 6 to 9, wherein the electronic device comprises a plurality of field programmable gate arrays, each of the field programmable gate arrays is provided with a block random access memory; based on the computing fast link protocol, the last level cache of the central processing unit and the plurality of block random access memories corresponding to the plurality of field programmable gate arrays are set as the shared cache.

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