Ceramic chip packaging process parameter optimization method based on machine learning

Abstract

The invention relates to the technical field of machine learning, and discloses a ceramic chip packaging process parameter optimization method based on machine learning, and the method comprises the steps: collecting first historical data of a target ceramic chip in a packaging process, and carrying out the preprocessing of the first historical data, and extracting second historical data; constructing a chip stress prediction model according to the second historical data; after real-time data is collected and preprocessed, the stress level of the chip in the future time period is predicted by combining the prediction model; if the predicted stress level is a warning or danger level, dynamically adjusting packaging process parameters of the ceramic chip; according to the method, the future stress risk level of the chip is predicted through a machine learning method, and the packaging process parameters are dynamically optimized and adjusted according to the prediction result, so that the stress failure risk in the packaging process of the ceramic chip is effectively reduced, and the reliability and yield of the chip are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of machine learning technology, and more specifically, to a method for optimizing ceramic chip packaging process parameters based on machine learning. Background Art

[0002] With the continuous development of electronic information technology, the application fields of ceramic chips are becoming more and more extensive. In the process of ceramic chip packaging, various process parameters need to be optimized and controlled to ensure the performance and reliability of ceramic chips. At present, there are some methods for optimizing chip packaging process parameters.

[0003] A Chinese patent application with publication number CN117634263A discloses a multi-objective chip plastic encapsulation process parameter optimization method. This method establishes a chip finite element model of the transfer molding process, uses the response surface method and the optimal Latin hypercube sampling design experiment, and uses a multi-objective optimization algorithm to find the best process parameters. However, this method is mainly aimed at the plastic encapsulation process and does not consider the particularity of the ceramic chip packaging process. In addition, this method does not use historical data and real-time data to predict the stress level of the chip, and lacks dynamic monitoring and control of chip stress risks.

[0004] A Chinese patent with the authorization announcement number CN117234171B discloses a process parameter control method and system for chip production. The method adjusts the tolerance threshold of the preset process parameter set by obtaining the equipment reliability factor and the quality deviation factor, and performs parameter optimization to obtain the target optimal process parameters. However, the method is mainly aimed at the chip dicing process and does not consider the characteristics of the ceramic chip packaging process. In addition, the method does not use machine learning technology to predict the stress risk level of the chip, and lacks intelligent decision-making support capabilities.

[0005] In summary, the existing chip packaging process parameter optimization method does not take into account the particularity of the ceramic chip packaging process and lacks targeted optimization measures. It fails to dynamically adjust the packaging process parameters according to the predicted stress risk level and cannot effectively reduce the stress failure risk of ceramic chips. Summary of the invention

[0006] In order to overcome the above-mentioned defects of the prior art, the present invention provides a ceramic chip packaging process parameter optimization method based on machine learning.

[0007] To achieve the above object, the present invention provides the following technical solutions: A ceramic chip packaging process parameter optimization method based on machine learning, comprising: Collecting first historical data of the target ceramic chip during the packaging process; preprocessing the first historical data to extract second historical data; According to the second historical data, a chip stress prediction model is constructed; the first real-time data in the ceramic chip packaging process is collected, and the first real-time data is preprocessed to obtain the second real-time data; according to the second real-time data and the chip stress prediction model, a chip stress prediction time series is obtained, and the chip stress prediction time series includes a future time period n chip stress prediction values ​​within the package; based on the chip stress prediction timing, determine the future time period of the ceramic chip during the packaging process The stress level within the device includes a safety level, a warning level and a danger level; n is a positive integer; If the stress level is a warning level or a danger level, the packaging process parameters of the ceramic chip are dynamically adjusted.

[0008] Further, the first historical data includes environmental state time series data and chip state time series data; the environmental state time series data includes environmental temperature time series data, environmental pressure time series data and environmental humidity time series data; the chip state time series data includes chip stress time series data and chip temperature time series data; The second historical data includes environmental state change rate time series data and chip state change rate time series data; the environmental state change rate time series data includes environmental temperature change rate time series data, environmental pressure change rate time series data, and environmental humidity change rate time series data; the chip state change rate time series data includes chip stress change rate time series data and chip temperature change rate time series data; The preprocessing of the first historical data to extract the second historical data includes: Differentiate the ambient temperature time series data to obtain the ambient temperature change rate time series data; Differentiate the environmental pressure time series data to obtain the environmental pressure change rate time series data; Differentiate the time series data of ambient humidity to obtain the time series data of ambient humidity change rate; Differentiate the chip stress time series data to obtain the chip stress change rate time series data; The chip temperature timing data is differentiated to obtain the chip temperature change rate timing data.

[0009] Furthermore, the construction of the chip stress prediction model includes: Performing feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environmental statistical time series features, historical chip statistical time series features, historical environmental energy time series features, historical chip energy time series features and associated time series features; A chip stress prediction model is constructed based on the historical comprehensive timing feature set.

[0010] Furthermore, the performing feature engineering processing on the second historical data includes: Extract the statistical characteristics of the time series data of the environmental state change rate and generate the historical environmental statistical time series characteristics; Extract the statistical features of the chip state change rate time series data to generate historical chip statistical time series features; Extract the energy distribution of the environmental state change rate time series data at different time scales to obtain the historical environmental energy time series characteristics; Extract the energy distribution of chip state change rate time series data at different time scales to obtain the historical chip energy time series characteristics; The mutual correlation coefficient between the time series data of the environment state change rate and the time series data of the chip state change rate is calculated to obtain the correlation time series characteristics.

[0011] Furthermore, the chip stress prediction timing is used to determine the future time period of the ceramic chip during the packaging process. The stress levels within include: Calculate the chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t n ,σ n )] σ and standard deviation σ σ ; where t n For future time periods At the nth moment in n For future time periods The predicted chip stress value at the nth moment within ; Calculate the chip stress prediction value σ at the future i-th moment in the chip stress prediction time series i PSI i ; When PSI i ≥λ', the mean μ σ As the chip stress prediction correction value σ' at the i-th moment in the future i , that is, σ' i =μ σ ; When PSI i <λ', then σ' i =(1-w)μ σ +w×σ i-1 ; σ i-1 is the predicted chip stress value at the i-1th moment in the future, w is σ i-1 The weight of , 2≤i≤n, λ' is the structural mutual information threshold; The predicted correction value σ' of chip stress at the future i-th moment i The chip stress prediction and correction time series [(t1,σ'1),(t2,σ'2),…,(t n ,σ' n)]; where σ' n is the chip stress prediction correction value at the nth moment in the future; Based on the chip stress prediction and correction timing, determine the future time period of the ceramic chip during the packaging process Stress level within.

[0012] Furthermore, the chip stress prediction and correction timing is used to determine the future time period of the ceramic chip during the packaging process. The stress levels within include: If σ w ≤σ' i <σ s , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the safety level, where σ s is the upper safety limit, σ w is the upper warning limit; If σ d ≤σ' i <σ w , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the warning level, where σ d is the upper limit of danger, σ s >σ w >σ d ; If σ' i <σ d , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is a dangerous level.

[0013] Furthermore, the chip stress prediction and correction timing is used to determine the future time period of the ceramic chip during the packaging process. The stress levels within also include: Traverse all chip stress prediction and correction values ​​in the chip stress prediction and correction time series, and count the future time periods respectively The number of moments when the internal stress level is the safety level is n2, the number of moments when the stress level is the warning level is n3, and the number of moments when the stress level is the danger level is n4; n2+n3+n4=n; Set the weight coefficient w at the security level moment s , the weight coefficient w at the warning level w and the weight coefficient w at the danger level d , according to n2, n3, n4, w s 、w w and w d , calculate the future time period The weighted proportion of the internal warning level moments P w and the weighted proportion of the dangerous level moment P d ; According to Pw and P d Determine the future time period of the ceramic chip during the packaging process The stress level inside is the dangerous level.

[0014] Further, according to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress levels within the dangerous level include: If P d >α, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the danger level; where α is the danger ratio threshold; If P d ≤α and P w >β, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the warning level; where β is the warning proportion threshold; If P d ≤α and P w ≤β, then determine the future time period of the ceramic chip during the packaging process The stress level within is the safety level.

[0015] Further, the packaging process parameters include heating rate, cooling rate and pressure fluctuation range; The dynamic adjustment of the packaging process parameters of the ceramic chip includes: If the stress level is at the warning level, the heating rate is increased from the standard heating rate value Adjust to the first heating rate value , change the cooling rate from the standard cooling rate value Adjust to the first cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Narrowed to the first pressure fluctuation range ,in, , , ; If the stress level is dangerous, the heating rate is increased from the standard heating rate value Adjust to the second heating rate value , change the cooling rate from the standard cooling rate value Adjust to the second cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Reduced to the second pressure fluctuation range ,in, , , .

[0016] A ceramic chip packaging process parameter optimization system based on machine learning, which is used to implement the above-mentioned ceramic chip packaging process parameter optimization method based on machine learning, the system comprises: Historical data acquisition module: used to collect the first historical data of the target ceramic chip during the packaging process; pre-process the first historical data and extract the second historical data; Chip stress prediction module: used to build a chip stress prediction model based on the second historical data; collect the first real-time data in the ceramic chip packaging process, pre-process the first real-time data, and obtain the second real-time data; obtain the chip stress prediction time series based on the second real-time data and the chip stress prediction model, and the chip stress prediction time series includes the future time period n chip stress prediction values ​​within; n is a positive integer; Chip stress level determination module: used to determine the future time period of the ceramic chip during the packaging process based on the chip stress prediction timing The stress level within the device includes a safety level, a warning level and a danger level; Parameter optimization module: If the stress level is a warning level or a danger level, the packaging process parameters of the ceramic chip are dynamically adjusted.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The ceramic chip packaging process parameter optimization method based on machine learning provided by the present invention can make full use of historical data to mine the intrinsic relationship between environmental factors and chip performance parameters in the packaging process, and establish an accurate stress prediction model. Through the analysis of real-time collected data, the method can dynamically estimate the stress level of the chip in the future period of time and discover potential high stress risks in advance. When the predicted stress level exceeds the safe range, the method can automatically adjust the key process parameters such as the heating rate, cooling rate, and pressure fluctuation amplitude of the packaging process according to the level of the risk level, and control the chip stress at a reasonable level by reducing thermal stress, reducing pressure fluctuations, and other measures. This forward-looking risk warning and proactive process optimization strategy can avoid packaging stress failure to the greatest extent, reduce scrap and rework losses, and comprehensively improve the yield and reliability level of ceramic chips. In addition, the method adopts the intelligent means of machine learning, which can continuously learn and optimize the prediction model from new data to adapt to changes in process conditions, and has good adaptability and robustness. Therefore, the present invention can not only significantly improve the packaging effect of a single device, but also support the consistency control of product performance in mass production, which is of great significance to improving the level of ceramic chip packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a principle flow chart of a ceramic chip packaging process parameter optimization method based on machine learning in the present invention; Figure 2 A flowchart of a method for preprocessing first historical data and extracting second historical data in a ceramic chip packaging process parameter optimization method based on machine learning of the present invention; Figure 3 A flow chart of a method for performing feature engineering processing on second historical data in a ceramic chip packaging process parameter optimization method based on machine learning of the present invention; Figure 4 In the ceramic chip packaging process parameter optimization method based on machine learning of the present invention, based on chip stress prediction and correction timing, the future time period of the ceramic chip in the packaging process is determined Flow chart of the method for determining the stress level within; Figure 5 According to P in a ceramic chip packaging process parameter optimization method based on machine learning of the present invention w and P d Determine the future time period of the ceramic chip during the packaging process Flow chart of the method of determining the stress level within the hazardous level; Figure 6 This is a functional module diagram of a ceramic chip packaging process parameter optimization system based on machine learning in the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Example 1

[0022] See also Figure 1 As shown, this embodiment provides a ceramic chip packaging process parameter optimization method based on machine learning, including: Step S1000, collecting first historical data of the target ceramic chip during the packaging process; preprocessing the first historical data, and extracting second historical data.

[0023] Furthermore, step S1000 includes: Step S1100, collecting first historical data of the target ceramic chip during the packaging process; the first historical data includes environmental state timing data and chip state timing data; the environmental state timing data includes environmental temperature timing data, environmental pressure timing data and environmental humidity timing data; the chip state timing data includes chip stress timing data and chip temperature timing data; Specifically, the environmental state time series data reflects the dynamic changes of environmental factors in the ceramic chip packaging process, mainly including the data series of environmental temperature, environmental pressure and environmental humidity changing over time. These environmental factors have an important impact on the stress state of ceramic chips. For example, the increase in ambient temperature will cause the internal thermal stress of the chip to increase, the fluctuation of ambient pressure will cause uneven stress on the chip, and the change of ambient humidity will affect the moisture absorption and expansion of the chip surface. Therefore, by collecting environmental state time series data, the external conditions of the ceramic chip can be fully characterized.

[0024] The chip status timing data reflects the dynamic changes in the performance parameters of the ceramic chip itself, mainly including the data series of chip stress and chip temperature changes over time. Among them, chip stress is a key indicator for evaluating chip reliability. Excessive stress can lead to failure modes such as chip cracking and delamination. The chip temperature is closely related to the thermal stress inside the chip, and uneven temperature distribution will aggravate stress concentration. By collecting chip status timing data, the health status of the chip can be monitored in real time and potential risks can be discovered in a timely manner.

[0025] Aggregating environmental status and chip status data to form the first historical data can establish the relationship between environmental factors and chip performance, providing a data basis for subsequent modeling and analysis. This time series data collection method fully considers the dynamic characteristics of the packaging process, can truly reflect the evolution of each parameter, and has high data quality and reliability. By learning and mining historical data, we can summarize empirical laws and guide process optimization, thereby improving the packaging quality of ceramic chips.

[0026] Step S1200, preprocessing the first historical data to extract second historical data; the second historical data includes environmental state change rate time series data and chip state change rate time series data; the environmental state change rate time series data includes environmental temperature change rate time series data, environmental pressure change rate time series data, and environmental humidity change rate time series data; the chip state change rate time series data includes chip stress change rate time series data and chip temperature change rate time series data; Furthermore, if Figure 2 As shown, step S1200 includes: Step S1210, performing differentiation on the ambient temperature time series data to obtain ambient temperature change rate time series data; Step S1220, performing differentiation on the environmental pressure time series data to obtain environmental pressure change rate time series data; Step S1230, performing differentiation on the ambient humidity time series data to obtain ambient humidity change rate time series data; Step S1240, performing differentiation on the chip stress time series data to obtain chip stress change rate time series data; Step S1250, performing differentiation on the chip temperature time series data to obtain chip temperature change rate time series data.

[0027] Specifically, the first historical data is preprocessed to extract implicit information about the environment-chip coupling effect, in preparation for subsequent feature engineering and modeling analysis. The core of preprocessing is to convert the original state time series data into state change rate time series data. The state change rate reflects the speed and severity of the change of state parameters over time, and can more sensitively capture the impact of environmental disturbances on chip performance.

[0028] State change rate data can reflect the instantaneous change characteristics of environmental factors and chip performance, and explore the dynamic coupling between environment and chip. By converting state to change rate data, redundant information in time series data can be reduced, key change patterns can be highlighted, and more targeted features can be provided for subsequent modeling and analysis. At the same time, change rate data is also scale invariant, which can eliminate the influence of different state parameter dimensions and facilitate comprehensive evaluation and comparative analysis.

[0029] This step uses the difference operator to achieve the conversion from state to rate of change. Difference is a commonly used numerical algorithm that approximates the instantaneous rate of change by dividing the difference between the state values ​​at two adjacent moments by the time interval. The difference operator is simple in form and efficient in calculation, and can quickly complete the preprocessing of large-scale time series data. The original state data sequences such as temperature, pressure, humidity, and stress are subjected to difference processing to obtain the corresponding rate of change data sequences. These rate of change data form the second historical data, which provides a basis for subsequent feature engineering and modeling analysis.

[0030] It should be noted that the difference operator is sensitive to data noise and can easily amplify the impact of random errors. Therefore, before applying the difference operator, the original data can be smoothed and filtered to remove high-frequency noise. At the same time, in actual engineering, algorithms such as central difference and high-order difference can be selected according to specific needs to improve the accuracy of the change rate calculation. The selection of the difference order requires a balance between computational efficiency and information loss. Although a too high order can characterize more complex change patterns, it may also introduce cumulative errors.

[0031] In summary, this step realizes the data conversion from state to rate of change through the differential operator, highlighting the instantaneous change characteristics of environmental factors and chip performance. This preprocessing method is simple and efficient, and can effectively mine the environment-chip coupling law contained in the time series data, laying the foundation for subsequent modeling and analysis. At the same time, the rate of change data also has good scale invariance and noise resistance, which is convenient for comprehensive evaluation and comparative analysis. The second historical data extracted by preprocessing can fully characterize the dynamic characteristics of the ceramic chip packaging process and provide reliable data support for process optimization.

[0032] Step S2000, constructing a chip stress prediction model based on the second historical data; collecting the first real-time data in the ceramic chip packaging process, preprocessing the first real-time data to obtain the second real-time data; obtaining the chip stress prediction time series based on the second real-time data and the chip stress prediction model, wherein the chip stress prediction time series includes a future time period n chip stress prediction values ​​within the package; based on the chip stress prediction timing, determine the future time period of the ceramic chip during the packaging process The stress level within the device includes a safety level, a warning level and a danger level; Furthermore, step S2000 includes: Step S2100, constructing a chip stress prediction model according to the second historical data; Furthermore, step S2100 includes: Step S2110, performing feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environment statistical time series features, historical chip statistical time series features, historical environment energy time series features, historical chip energy time series features and associated time series features; Furthermore, if Figure 3 As shown, step S2110 includes: Step S2111, extracting statistical features of the environmental state change rate time series data to generate historical environmental statistical time series features; Step S2112, extracting the statistical features of the chip state change rate time series data to generate historical chip statistical time series features; Step S2113, extracting the energy distribution of the environmental state change rate time series data on different time scales to obtain the historical environmental energy time series characteristics; Step S2114, extracting the energy distribution of the chip state change rate time series data on different time scales to obtain the historical chip energy time series characteristics; Step S2115, calculating the correlation coefficient between the time series data of the environment state change rate and the time series data of the chip state change rate to obtain the correlation time series feature.

[0033] Specifically, step S2110 performs multi-level feature extraction on the second historical data to form an information-rich feature set. The comprehensive time series feature set consists of five types of features, each of which describes the association pattern between environmental factors and chip performance from different angles.

[0034] The historical environment statistical time series characteristics and the historical chip statistical time series characteristics reflect the overall distribution characteristics of the environmental state change rate and the chip state change rate. By calculating the mean, variance, maximum value, minimum value, peak-to-peak value and other statistics of each state change rate time series, the fluctuation level of environmental factors and chip performance can be quantitatively evaluated. These statistical characteristics characterize the central trend and discreteness of the state change rate data, which helps to judge the stability of environmental conditions and chip states. In addition, higher-order moments such as skewness and kurtosis of the state change rate can also be calculated to evaluate the skewness and sharpness of the data distribution, and further refine the characterization of environmental disturbances and chip responses. The historical chip statistical time series characteristics include historical chip temperature statistical time series characteristics and historical chip stress statistical time series characteristics; the historical chip temperature statistical time series characteristics are extracted from the chip temperature change rate time series data; the historical chip stress statistical time series characteristics are extracted from the chip stress change rate time series data.

[0035] The historical environmental energy time series characteristics and the historical chip energy time series characteristics analyze the energy distribution pattern of the state change rate data from the perspective of time and frequency domain. By using time-frequency analysis methods such as short-time Fourier transform and wavelet transform, the energy intensity of the state change rate at different time scales and frequency scales can be extracted. Although the environmental state change rate and chip state change rate data here are different from the signal form in traditional signal analysis, in essence, any data sequence that changes with time can be regarded as a generalized signal. In the scenario of the present invention, the changes in the environmental state change rate (such as the environmental temperature change rate, the environmental pressure change rate, etc.) and the chip state change rate (such as the chip stress change rate, the chip temperature change rate) over time also contain rich information, and these changes are closely related to the physical phenomena in the ceramic chip packaging process. Taking the environmental temperature change rate as an example, in the ceramic chip packaging process, when the heating or cooling system of the packaging equipment is working, the environmental temperature change rate will change. This change presents a certain fluctuation pattern in the time series, just like the fluctuation of the signal. From the perspective of physical principles, these fluctuations in change rates are caused by various factors in the packaging process, such as the adjustment of heating power, changes in heat dissipation conditions, etc., and their changing patterns reflect the dynamic characteristics of the packaging environment.

[0036] The core principle of time-frequency analysis methods such as short-time Fourier transform and wavelet transform is to decompose time series data in two dimensions: time and frequency. For environmental and chip state change rate data, these methods can be used to decompose their complex changes into components at different time scales and frequency scales. Taking wavelet transform as an example, it has the characteristics of multi-resolution analysis and can observe data at different scales. At a smaller scale, the rapid fluctuation details of the change rate data can be captured. These details may correspond to some sudden environmental changes or microscopic physical changes inside the chip during the packaging process; at a larger scale, the overall trend of the change rate data can be seen, such as the approximate change trend of the ambient temperature change rate during the entire packaging cycle. By calculating the energy of these decomposed components, the energy intensity at different time scales and frequency scales can be obtained. For example, when the ambient temperature change rate has a higher energy intensity within a certain frequency range, it means that the ambient temperature changes more drastically at the time scale corresponding to the frequency, and this drastic change may have an important impact on chip stress. By analyzing the energy distribution at different frequency scales, it is possible to determine which frequency components have a greater impact on environmental condition changes and chip performance, that is, to obtain key frequency components. These energy characteristics reveal the multi-scale variation of environmental factors and chip performance, and reflect the strength distribution of disturbance signals in different frequency bands. By analyzing the energy time series characteristics, we can find the key frequency components of environmental condition changes, determine the dominant time scale of environment-chip coupling, and provide targeted basis for optimizing process parameters.

[0037] The correlation time series feature measures the similarity between the two types of time series data by calculating the cross-correlation coefficient between the environmental state change rate and the chip state change rate. Cross-correlation analysis can reveal the delay effect between environmental factor changes and chip performance responses, that is, the dynamic response law of chip states to environmental disturbances. By calculating the cross-correlation coefficients under different time lags, the causal relationship strength and action delay between the environment and the chip can be quantified. The cross-correlation feature helps to understand the multi-physics field coupling mechanism in the packaging process and consider the cumulative effect and hysteresis effect of environmental factor changes when optimizing process parameters.

[0038] It should be noted that although the historical environment statistical time series features, historical chip statistical time series features and associated time series features are not continuous time series data in the traditional sense, they are closely related to time series. The historical environment statistical time series features and historical chip statistical time series features are obtained by statistically calculating the time series data of the environment and chip state change rate. These statistical values ​​reflect the overall trend and fluctuation of environmental factors and chip performance changes over a period of time. For example, the mean can reflect the average level of environmental temperature or chip stress changes in a certain stage, and the variance can reflect its degree of fluctuation. This kind of statistical information on historical data actually contains characteristics in the time dimension. It is the result of the accumulation of changes in time series data at different times. It can provide the LSTM model with information about the long-term trend of changes in the environment and chip state, and help the model better grasp the overall law of the environment-chip coupling effect. The associated time series features measure the temporal correlation and delay effect of the environment and chip state changes by calculating the mutual correlation coefficients between different time series data. It reveals the temporal relationship between environmental factor changes and chip performance responses from another perspective, and provides the model with dynamic time information about the environment-chip coupling effect. Although these features are not in the form of simple time series, the time-related information they carry is crucial for the LSTM model to understand the changes in the environment-chip coupling system in the time dimension, and is an indispensable part of building an accurate prediction model.

[0039] In summary, step S2110 adopts a multi-level feature engineering method, starting from statistical features, energy features, correlation features, etc., to deeply explore the intrinsic connection between environmental factors and chip performance, and form an information-rich feature set. These timing features provide comprehensive prior knowledge for the chip stress prediction model, which helps to improve the generalization ability and prediction accuracy of the model. Modeling and analysis based on the comprehensive timing feature set can reveal the multi-scale dynamic laws of the environment-chip coupling effect in the packaging process, provide a quantitative basis for process parameter optimization, and improve the reliability level of ceramic chips.

[0040] The correlation coefficient between the time series data of the calculation environment state change rate and the time series data of the chip state change rate includes: Assume that the environmental state change rate time series data ,in Indicates The change rate timing data of environmental state parameters (such as ambient temperature, pressure, humidity, etc.). Chip state change rate timing data ,in Indicates The change rate timing data of chip status parameters (such as chip stress, temperature, etc.)

[0041] To analyze Environmental status parameters With Chip status parameters The strength of the association and the hysteresis effect between them are defined in terms of the time delay The mutual correlation coefficient is:

[0042] in: Indicates Environmental status parameters With Chip status parameters In delay The mutual correlation coefficients below.

[0043] Respectively and The mean of .

[0044] Indicates the total length of the time series.

[0045] Indicates the time index of the time series, .

[0046] Indicates the delay, the value range is .

[0047] is the delay penalty coefficient, which can be set based on experience to control the speed at which the cross-correlation coefficient decays with delay. It can be set based on historical experience of the packaging process, or the best value can be obtained through verification set tuning.

[0048] This formula takes into account the impact of two factors on the mutual correlation coefficient:

[0049] (1) Estimation bias caused by limited time series length: multiply by Make corrections.

[0050] (2) Correlation decays naturally as the delay increases: multiply by To punish.

[0051] Mutual Correlation Coefficient Measured in latency Next, the environmental state change rate time series data Timing data of chip status change rate The value range is , the larger the absolute value, the stronger the correlation: when When Hysteresis Time units and Positive correlation, that is Rise / fall often causes back Ascend / descend.

[0052] when When Hysteresis Time units and Negative correlation, that is Rise / fall often causes back Descending / ascending.

[0053] when When it is close to 0, it means and Not relevant.

[0054] The formula of the mutual correlation coefficient describes the dynamic correlation and hysteresis effect between the environmental state change rate and the chip state change rate: it helps to understand how environmental disturbances affect chip stress. The mutual correlation coefficient shows a trend of first increasing and then decreasing with time delay: its peak position can indicate the characteristic time scale of the impact of the environmental change rate on the chip change rate. By setting the delay penalty coefficient , the rate at which the correlation coefficient decays with time delay can be flexibly controlled to make it consistent with the physical mechanism. The cross-correlation estimation bias caused by the limited time series length can be eliminated better.

[0055] The cross-correlation coefficient formula can quantitatively evaluate the time characteristics of the environment-chip coupling effect, provide key correlation features for building a more accurate chip stress prediction model, and is of great significance for guiding the optimization of packaging process parameters. Cross-correlation analysis helps process personnel understand the path and effect size of various environmental factors affecting chip stress formation, and provides a theoretical basis for the active regulation and suppression of chip stress.

[0056] Step S2120, constructing a chip stress prediction model based on the historical comprehensive timing feature set.

[0057] Specifically, the chip stress prediction model uses the long short-term memory network (LSTM) algorithm to effectively model long-term dependencies in time series data. LSTM is a special recurrent neural network specifically designed to process and predict time series data. Compared with traditional feedforward neural networks, LSTM can learn long-term dependencies in data and can capture the complex nonlinear relationship between changes in environmental factors and chip stress in chip stress prediction tasks.

[0058] The LSTM model is mainly composed of four parts: input gate, forget gate, output gate, and memory unit, each of which performs its own functions and works together. The input gate controls the intensity of new environmental feature information entering the memory unit, which determines the model's sensitivity to new information. The forget gate controls the intensity of old information being forgotten in the memory unit, which determines the speed at which the model forgets historical information. The memory unit stores the long-term memory representation of the environment-chip coupling effect extracted by the LSTM model, which contains causal relationships and related patterns in the time dimension.

[0059] In the model training phase, the LSTM model takes the historical environmental statistical time series features, historical chip temperature statistical time series features, historical chip energy time series features, historical environmental energy time series features and associated time series features in the comprehensive time series feature set as input, and the historical chip stress statistical time series features at the corresponding moment as the supervision signal, and optimizes the model parameters through the back propagation algorithm. By minimizing the error function between the predicted value and the true value, the LSTM model gradually learns the inherent law of the environment-chip coupling effect. The trained LSTM model takes the environmental state change rate feature at the current moment as input and outputs the chip stress change rate prediction sequence in the future.

[0060] When the historical chip stress statistical time series features are used as supervisory signals for LSTM model training, a loss function is constructed based on these statistical features to guide model learning. The predicted output of the LSTM model is compared point by point with the historical chip stress statistical time series features. Taking the mean value in the historical chip stress statistical time series features as an example, assuming that at a certain moment, the chip stress change rate predicted by the LSTM model is converted to the predicted stress value , and the corresponding mean value in the historical chip stress statistical timing characteristics is , the common mean square error (MSE) loss function can be used to measure the difference between the two, that is, ,in is the number of training samples, is the index of the training sample. Similarly, for other statistical features such as variance, maximum value, minimum value, etc., the loss function can be constructed in a similar way. For example, the loss function constructed for variance can be ,here is the value related to the stress variance predicted by the model, is the variance value in the historical chip stress statistical time series characteristics. The total loss function is obtained by weighted summing multiple loss functions constructed based on different statistical characteristics. ,in For the The weight of the loss function, 1≤ ≤z, which can be adjusted according to actual conditions. During the training process, the LSTM model uses the back propagation algorithm to minimize the total loss function To update the model weights and biases. For example, when When it is large, it means that there is a large difference between the model prediction value and the historical chip stress statistical timing characteristics. The back propagation algorithm will adjust the model parameters to make the predicted value closer to the actual statistical characteristic value, so that the model can gradually learn the inherent laws of the environment-chip coupling effect.

[0061] The historical environmental energy time series characteristics are obtained through time-frequency analysis methods, which reflect the energy distribution of the environmental state change rate on different time scales and frequency scales. Although the frequency sequence of the change rate is different from the sequence form of the change rate itself, it contains rich information. During the training process, the LSTM model does not directly predict the future change rate based on the frequency sequence, but learns the environmental change pattern represented by the frequency sequence. For example, when the environmental temperature change rate has energy fluctuations within a certain frequency range, it may indicate that the environmental temperature is about to change significantly, which in turn affects the chip stress. The LSTM model can capture the relationship between this frequency energy distribution and subsequent environmental state changes, as well as the relationship between environmental changes and chip stress changes. By learning such frequency characteristics in a large amount of historical data, the model can understand the response law of chip stress under different environmental energy frequency modes. This learning process is not a simple linear mapping, but uses the powerful nonlinear learning ability of the LSTM model to dig out the complex causal relationship between the environmental energy frequency characteristics and the future chip stress change rate. In theory, according to the principles of time-frequency analysis such as Fourier transform and wavelet transform, frequency information is a deep characterization of signal changes, including the trend of signal changes on different time scales. The LSTM model can learn the trend information contained in these frequency features, thereby predicting the future chip stress change rate.

[0062] The historical chip energy time series features also contain the energy distribution information of the chip state change rate in the time-frequency domain. During the chip packaging process, the physical changes inside the chip will show energy fluctuations at different frequencies. For example, when stress concentration or structural changes occur inside the chip, energy changes will occur within a specific frequency range. These frequency features are closely related to the development trend of chip stress. When training, the LSTM model can identify the patterns of energy changes inside the chip and the relationship between these patterns and chip stress changes by learning the historical chip energy time series features. Although the frequency sequence is different from the direct change rate sequence, it provides key information about the physical process inside the chip. From the actual case, when analyzing the data of a large number of ceramic chip packaging processes, it is found that when the energy of a certain frequency segment in the historical chip energy time series features continues to rise, the chip stress often changes accordingly at subsequent moments. The LSTM model can learn this empirical pattern, so as to effectively predict the future chip stress change rate using the historical chip energy time series features. This is not simply to directly derive the future change rate from the frequency sequence, but to learn and summarize the relationship between frequency features and chip stress changes in a large amount of historical data through the model.

[0063] The LSTM model has a strong learning ability and can handle various types of input data. For historical environmental statistical time series features, historical chip temperature statistical time series features, and associated time series features, the LSTM model does not simply treat them as isolated data independent of time. Taking the historical environmental statistical time series features as an example, during the training process, the model will combine these statistical values ​​with other time-related input features (such as historical environmental energy time series features) to learn the relationship between environmental factors and chip stress from multiple dimensions. The time accumulation information contained in these statistical features will complement other time series features to help the model capture the complex time dependency in the environment-chip coupling effect. The associated time series features provide dynamic time information for the model by reflecting the time correlation between the environment and chip state changes. The LSTM model can use this information to understand how environmental changes affect chip stress at different time points, so as to better learn the inherent laws of the environment-chip coupling effect. In this way, the LSTM model organically integrates these seemingly non-time series features with time series features, so as to accurately predict future chip stress changes. The trained LSTM model takes the environmental state change rate feature at the current moment as input and outputs the chip stress prediction time series for a period of time in the future.

[0064] Step S2100 aims to use the coupling relationship between the environmental factors and the chip state contained in the second historical data to establish a machine learning model that can predict future chip stress changes. The key to building a prediction model lies in two aspects: feature engineering and algorithm selection.

[0065] Feature engineering refers to the process of extracting key features that have a significant impact on the prediction target from the original data and quantifying these features. Through feature engineering, complex time series data can be converted into structured feature vectors to provide suitable input for model training. This embodiment adopts a multi-level and multi-angle feature extraction strategy to characterize the environment-chip coupling effect from three dimensions: statistical features, energy features, and correlation features to form an information-rich feature set. This comprehensive feature representation helps to capture the influence of changes in environmental factors on chip performance and provide sufficient prior knowledge for subsequent modeling and analysis.

[0066] In terms of algorithm selection, this embodiment uses the long short-term memory network (LSTM) as the core structure of the chip stress prediction model. Using LSTM for chip stress modeling and prediction can capture the long-term dependencies in time series data, characterize the lag effect and cumulative impact between environmental factors and chip stress; it has long-term memory ability, can learn the physical mechanism behind the environment-chip coupling effect, and form an internal representation of knowledge; it has a strong ability to characterize the changing trend and fluctuation pattern of time series data, and can predict the dynamic changes of chip stress; the model has strong generalization ability, can adapt to different chip types and packaging processes, and has good mobility and scalability.

[0067] In general, step S2100 converts the original time series data into a chip stress model with predictive capabilities through feature engineering and LSTM modeling. This data-driven modeling paradigm makes full use of the statistical laws and causal mechanisms contained in historical data, and can overcome the limitations of traditional physical models under complex working conditions. Chip stress prediction based on machine learning provides new ideas and means for packaging process optimization, and is expected to significantly improve the reliability and yield level of ceramic chips.

[0068] Step S2200, collecting first real-time data in the ceramic chip packaging process, preprocessing the first real-time data, and obtaining second real-time data; The first real-time data includes real-time environment status data and real-time chip status data; The real-time environmental status data includes real-time environmental temperature sequence data, real-time environmental pressure sequence data and real-time environmental humidity sequence data; the real-time chip status sequence data includes real-time chip stress sequence data and real-time chip temperature sequence data; The second real-time data includes real-time environment state change rate time series data and real-time chip state change rate time series data; the real-time environment state change rate time series data includes real-time environment temperature change rate time series data, real-time environment pressure change rate time series data, and real-time environment humidity change rate time series data; the real-time chip state change rate time series data includes real-time chip stress change rate time series data and real-time chip temperature change rate time series data; Specifically, step S2200 is essentially the application of the historical data collection and preprocessing method in step S1000 in a real-time scenario. The two are highly consistent in terms of data type, preprocessing algorithm, etc. The difference is that step S2200 processes real-time data streams rather than historical data sets.

[0069] The first real-time data includes real-time environmental status data and real-time chip status data, which have the same composition as historical data. Among them, the real-time environmental status data includes real-time environmental temperature, pressure, and humidity time series data, which reflects the current state and instantaneous changes of the environmental conditions in which the chip is located. The real-time chip status data includes real-time chip stress and temperature time series data, which reflects the current level and dynamic response of chip performance parameters. The first real-time data acquisition can be achieved by deploying a sensor system on the packaging equipment, and the collected data is aggregated to the data processing platform through a real-time transmission channel for normalization, synchronization and other pre-processing.

[0070] The preprocessing process of the first real-time data is basically the same as step S1000, including performing differential operations on various types of state data to obtain corresponding state change rate data. The second real-time data after preprocessing includes real-time environmental state change rate time series data and real-time chip state change rate time series data, which have the same structure and semantics as the second historical data. It should be noted that real-time data preprocessing has higher requirements on computing timeliness and resource consumption, and it is necessary to design an efficient streaming computing framework to balance the time consumption of data processing and model reasoning to achieve real-time prediction of chip stress.

[0071] Step S2200 is the data basis for realizing real-time prediction of chip stress. Through efficient and stable real-time data acquisition and preprocessing system, continuous feature input can be provided for LSTM prediction model to ensure the real-time and continuity of prediction results. This is a key link in building a closed-loop feedback intelligent packaging optimization system, which is of great significance for improving chip production efficiency and quality.

[0072] Step S2300: According to the second real-time data and the chip stress prediction model, a chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t n ,σ n )]; the chip stress prediction time series includes a future time period The stress prediction values ​​of n chips in the chip; n is a positive integer; t n For future time periods The nth moment within σ n For future time periods The predicted chip stress value at the nth moment within .

[0073] Specifically, S2300 is the online reasoning process of the chip stress prediction model, which drives the LSTM model to perform continuous rolling prediction by receiving the second real-time data output by step S2200 in real time.

[0074] In the specific implementation, the feature engineering method in step S2100 is first used to extract features from the second real-time data, and then a sliding time window is used to generate a prediction time series. Assume that the current time is ', the time span of chip stress prediction timing is the future , the time granularity is , then the length of the predicted time series It can be expressed as:

[0075]

[0076] in Indicates rounding operation.

[0077] At time t', the feature extraction result of the second real-time data is used as the input of the LSTM model to obtain the chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t n ,σ n )]; As time goes by, the prediction window keeps sliding forward, and each time step generates a prediction time series of the future Δt time span, realizing the real-time outlook of the chip stress evolution trend. By adjusting the parameters Δt and δt of the prediction time series, the predicted future time range and prediction granularity can be flexibly set to meet different process optimization requirements.

[0078] The generation of chip stress prediction timing is an important basis for chip stress warning and active control. By analyzing the prediction timing, we can find signs of abnormal chip stress fluctuations in advance and predict potential failure risks. In addition, the prediction timing can also be used as an input for dynamic optimization of packaging process parameters. The mapping relationship between stress prediction values ​​and process parameters is established through machine learning algorithms, and the control variables of packaging equipment are adaptively adjusted to achieve closed-loop control of chip stress levels, thereby achieving the effect of suppressing abnormal stress fluctuations and balancing stress distribution.

[0079] In summary, step S2300 generates a chip stress prediction time series within a period of time based on the LSTM prediction model and real-time preprocessing data, revealing the dynamic evolution law of chip stress. As a quantitative characterization of the future chip stress change trend, the prediction time series is an important tool for achieving active early warning, intelligent control and dynamic optimization. Through real-time early warning, feedback control and other measures, the impact of environmental stress on chip performance and reliability can be minimized, and the level of ceramic packaging process can be improved. The prediction-driven intelligent packaging optimization mode provides a disruptive alternative to traditional passive process adjustment, which is of great significance for reducing costs, increasing efficiency, improving quality and speed, and represents the future development direction of advanced packaging technology.

[0080] Step S2400, based on the chip stress prediction timing, determine the future time period of the ceramic chip during the packaging process Stress level within.

[0081] Further, step S2400 includes: Step S2410, calculating the mean μ of the chip stress prediction time series σ and standard deviation σ σ ; Step S2420, calculating the chip stress prediction value σ at the i-th moment in the future in the chip stress prediction time series i PSI i ; When PSI i ≥λ', the mean μ σ As the chip stress prediction correction value σ' at the i-th moment in the future i , that is, σ' i =μ σ ; When PSI i <λ', then σ' i =(1-w)μ σ +w×σ i-1 ; σ i-1 is the predicted chip stress value at the i-1th moment in the future, w is σ i-1 The weight of , 2≤i≤n, λ' is the structural mutual information threshold; Step S2430: predict the chip stress correction value σ' at the future i-th moment i The chip stress prediction and correction time series [(t1,σ'1),(t2,σ'2),…,(t n ,σ' n )]; where σ' n is the chip stress prediction correction value at the nth moment in the future; Step S2440, based on the chip stress prediction correction timing, determine the future time period of the ceramic chip in the packaging process Stress level within.

[0082] Furthermore, if Figure 4 As shown, step S2440 includes: Step S2441, if σ w ≤σ' i <σ s , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the safety level, where σ s is the upper safety limit, σ w is the upper warning limit; Step S2442, if σ d ≤σ' i <σ w , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the warning level, where σ d is the upper limit of danger, σ s >σ w >σ d ; Step S2443, if σ' i <σ d , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is a dangerous level; Step S2444, traverse all chip stress prediction and correction values ​​in the chip stress prediction and correction sequence, and count the future time periods respectively. The number of moments when the internal stress level is the safety level is n2, the number of moments when the stress level is the warning level is n3, and the number of moments when the stress level is the danger level is n4; n2+n3+n4=n; Step S2445, setting the weight coefficient w of the security level at the moment s , the weight coefficient w at the warning level w and the weight coefficient w at the danger level d , according to n2, n3, n4, w s 、w w and w d , calculate the future time period The weighted proportion of the internal warning level moments P w and the weighted proportion of the dangerous level moment P d ;

[0083]

[0084] Step S2446, according to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress level inside is the dangerous level.

[0085] Furthermore, if Figure 5 As shown, step S2446 includes: Step S24461, if P d >α, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the danger level; where α is the danger ratio threshold; Step S24462, if P d ≤α and P w >β, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the warning level; where β is the warning proportion threshold; Step S24463, if P d ≤α and P w ≤β, then determine the future time period of the ceramic chip during the packaging process The stress level within is the safety level.

[0086] Specifically, step S2400 is based on the chip stress prediction time series data, comprehensively considers the stress state at different moments in the future, and finally determines the future time period of the ceramic chip in the packaging process. The core of this step is to make an overall assessment of the future stress change trend, determine the stress risk level of the chip in the future, and provide a decision-making basis for subsequent process parameter optimization.

[0087] Step S2410 calculates the mean μ of the chip stress prediction time series σ and standard deviation σ σ , describing the overall distribution characteristics of future stress levels. Mean μ σ reflects the average level of future stress, while the standard deviation σ σ The fluctuation range of future stress relative to the mean is measured. Through these two statistics, the central trend and dispersion of stress in the future can be quantitatively evaluated, and the stress state of the chip can be preliminarily judged.

[0088] Step S2420 introduces the structural mutual information index PSI (Permutation Structural Information) to measure the structural similarity between the stress prediction value at each future moment and the historical data. Structural mutual information originates from the field of information theory. It measures the structural correlation between two sets of data through permutation technology and mutual information theory. The larger the PSI value, the closer the predicted value at that moment is to the change pattern of the historical data, and the higher the prediction credibility. By setting the threshold structural mutual information λ', the reliability of each predicted value can be judged: when PSI ≥ λ', the overall mean μ is directly used. σ As the prediction correction value σ' at this moment, ignoring local fluctuations; when PSI < λ', the linearly weighted local prediction value σi and the overall mean μ σ， The compromise prediction correction value σ' is obtained. The weight w reflects the importance of local information and is generally an empirical value. This adaptive correction strategy can take into account both the overall trend and local characteristics, and improve the stability and accuracy of the prediction value.

[0089] Step S2430 generates a chip stress prediction correction sequence, which consists of the predicted correction value σ' at each future moment and the corresponding timestamp t i The correction time series reflects the dynamic change trend of future stress levels over time and provides a time series data basis for subsequent stress level determination.

[0090] Step S2440 is the core step of stress level determination; Steps S2441-S2443 determine the stress state of the ceramic chip at a certain moment in the future. By setting three stress thresholds σ s , σ w , σ d , the chip stress prediction correction value σ' i Divided into three levels: safety, warning, and danger. s is the upper safety limit, σ w is the upper warning limit, σ d The upper limit of danger. Setting multi-level stress thresholds can achieve a fine division of chip stress state. Discretizing continuous stress values ​​into a limited number of levels makes it easier for process personnel to understand intuitively. At the same time, different levels correspond to different risk levels, providing a clear optimization direction for subsequent process parameter adjustments. For example, when it is predicted that the stress will enter the danger zone at some point in the future, timely measures need to be taken to lower the stress level of the packaging process to avoid chip cracking and failure.

[0091] Steps S2444-S2446 further evaluate the entire future time period based on the single moment risk judgment Step S2444 Statistics The number of moments n2, n3, and n4 for each of the three stress levels reflects the overall distribution of the chip stress state during the time period. However, different risk levels have different impacts on chip reliability, and only considering the number of moments cannot accurately assess the comprehensive risk. Therefore, step S2445 introduces the weight coefficient w s 、w w and w d , respectively represent the risk weights of safety, warning, and danger levels, and the general value satisfies w s <w w <w d By multiplying the number of moments at each level by the corresponding weight, we can get the weighted number of moments, and then calculate the weighted proportion of warning and danger level moments P. w , Pd . Weighted proportion P w , P d It comprehensively considers the duration and risk level of each level and can more comprehensively reflect the overall risk level in the future time period.

[0092] Finally, step S2446 calculates the weighted proportion P w , P d Compare with the preset thresholds α and β to get the final comprehensive risk level. By setting the two thresholds α and β, the strictness of risk judgment can be flexibly controlled. The smaller the threshold, the easier it is to judge as a high risk level and the more sensitive the warning; conversely, the larger the threshold, the looser the risk judgment. For example, you can set α=0.2 and β=0.5, that is, when the danger ratio exceeds 20% or the warning ratio exceeds 50%, you need to be vigilant, pay close attention to the chip status, and optimize the packaging process parameters in time.

[0093] The above steps convert the predicted timing chip stress data into intuitive risk level information, which is convenient for process personnel to quickly understand the changing trend of chip stress status in the future. By considering the difference in the impact of different risk levels through weighted calculation and setting the risk judgment threshold, multi-level early warning of chip status can be achieved, thereby guiding the active control and optimization adjustment of the packaging process. Compared with the stress value at a single moment, the comprehensive risk level in the future time period can better reflect the overall effect of the process parameter setting over a period of time. Process personnel can refer to the comprehensive level to formulate targeted optimization strategies and make trade-offs between reliability and cost.

[0094] This stress prediction method based on machine learning provides a new idea for evaluating chip reliability. Traditional methods often find problems only after the chip fails, while the prediction model can proactively predict the health status of the chip, thereby gaining more time windows for preventive maintenance. Through timely early warning and dynamic optimization, the uncontrolled rise of chip stress can be suppressed to the maximum extent, thereby reducing the failure rate of ceramic chips and improving the yield level. The stress prediction method combines big data analysis with process experience, overcomes the subjectivity and uncertainty of empirical judgment, and uses data-driven intelligence to upgrade traditional packaging processes. This is of great significance for building an intelligent chip manufacturing process and realizing flexible quality control.

[0095] In summary, steps S2441-S2446 construct a multi-level risk warning mechanism by setting stress thresholds, weighted proportions, risk criteria and other parameters. This method makes full use of time series prediction data to dynamically evaluate the stress state of the chip from two dimensions of time and space. It can not only judge the instantaneous risk at a single moment, but also evaluate the comprehensive risk level over a period of time. Quantitative risk information makes it easier for packaging process personnel to intuitively understand the chip status and grasp the timing and direction of parameter optimization. Through timely warning and active control, this machine learning method can guide the prevention of stress runaway, thereby improving the reliability and yield of ceramic chips. The multi-level risk warning mechanism complements expert experience and provides new ideas for intelligent chip manufacturing and dynamic quality control.

[0096] Steps S24461-S24463 further refine the comprehensive risk level determination rule. This determination rule follows the basic principle of "short-term risk first, long-term risk in mind", focusing on the dangerous state in the future time period. d When the preset threshold α is exceeded, the comprehensive risk level in this time period is directly judged as dangerous, and there is no need to consider the warning state at this time. This is because the dangerous state corresponds to a high risk of chip stress out of control, which often leads to irreparable losses once it occurs. In order to ensure chip reliability, the probability of dangerous states must be controlled at a low level. The setting of the threshold α requires a balance between the timeliness of risk prevention and control and cost investment. It can refer to factors such as the process yield requirements and quality cost accounting, and can generally be taken as 0.1-0.2.

[0097] When the risk ratio P d If it does not exceed α, the weighted proportion P of the warning state is further considered. w If P w If the preset threshold β is exceeded, the comprehensive risk level in this time period is judged as a warning. This indicates that although the serious risks are under control, the chip stress level is still at a high level, and its dynamic changes need to be closely monitored so that optimization measures can be taken in a timely manner. The threshold β can be set slightly higher than α, such as 0.3-0.5, to avoid triggering warnings too frequently and to reserve buffer space for stress runaway.

[0098] When the risk ratio P d And warning ratio P w When both stress levels do not exceed their respective thresholds, it indicates that the chip stress state is generally controllable in the future period, and the comprehensive risk level is determined to be safe. At this time, the packaging process is basically stable, the stress level is acceptable, and the impact on the yield rate is small in the short term. However, it is still necessary to track and monitor the long-term change trend of stress, evaluate the rationality of process parameters through big data analysis, and perform preventive optimization when necessary.

[0099] The above judgment rules form a hierarchical early warning system from strict to loose. By setting the danger threshold α and the warning threshold β, the dynamic adjustment of risk control can be achieved. When the risk of chip stress out of control is high, the α and β values ​​can be appropriately reduced to trigger early warnings with sensitive parameters; when the process level is stable, the threshold can be appropriately increased to avoid excessive intervention in production. The optimal setting of the threshold can be verified with historical data and simulation to seek a balance between risk control and production efficiency.

[0100] In summary, steps S24461-S24463 provide a comprehensive risk determination method based on weighted proportion thresholds. This method fully considers the time proportion and severity of different risk levels and forms a multi-level early warning mechanism. By reasonably setting the danger threshold and warning threshold, the intensity of risk control can be dynamically adjusted according to the process requirements, and a balance optimization can be made between chip reliability and production efficiency. Compared with a single stress threshold, this method can more comprehensively evaluate the overall risk level over a period of time and provide a basis for the dynamic optimization of packaging process parameters. Process personnel can refer to the comprehensive risk level and take preventive or corrective measures in time to avoid the cumulative deterioration of adverse stress states. Scientific threshold settings need to be determined through data analysis and simulation experiments, and dynamically adjusted in combination with expert experience. The risk warning method based on big data and machine learning has injected intelligent genes into the traditional chip manufacturing process, providing a new means of actively controlling stress runaway, which is of great significance to improving the reliability and yield of ceramic chips.

[0101] Exemplarily, assume that through steps S2420-S2430, the stress prediction correction value is obtained every 10 seconds in the next 10 minutes. After the statistics of steps S2441-S2444, in the next 10 hours, 20% of the time is at the danger level, 30% of the time is at the warning level, and 50% of the time is at the safety level. The weight coefficients of the three levels of danger, warning, and safety are set to 5, 3, and 1, respectively, representing the degree of risk. Set the danger ratio threshold α to 15%, and the warning ratio threshold β to 25%. Calculate the weighted ratio, the danger ratio is 20%×5 / (20%×5+30%×3+50%×1)=38.5%>α, so according to step S2446, it is determined that the stress level of the chip packaging process in the next 10 minutes is a danger level, and the process parameters need to be adjusted in time to reduce the risk.

[0102] In summary, step S2400 adopts a method that combines adaptive timing prediction with multi-level risk assessment, fully considering the characteristics of stress data such as timing correlation, local volatility, and uncertainty, and comprehensively analyzes future stress changes in terms of time and risk, and finally gives a stress level warning for the chip packaging process in the future. This evaluation result is intuitive and reliable, can reflect the future health status of the chip, and has guiding significance for process optimization. By timely discovering the danger level, key parameters such as temperature and pressure can be adjusted in advance to avoid quality problems caused by excessive chip stress, thereby improving the yield and reliability of ceramic chips. In addition, when the future stress level is a warning, it is also necessary to pay close attention to the production status, optimize the process in a timely manner, and control the risk within an acceptable range. When the future stress level is safe, the current process can be maintained to maintain production stability. This risk classification management and control mode is conducive to balancing efficiency and quality, maximizing the effect of machine learning prediction, and providing a scientific basis for intelligent process optimization decisions.

[0103] Step S3000: If the stress level is a warning level or a danger level, dynamically adjust the packaging process parameters of the ceramic chip.

[0104] Furthermore, step S3000 includes: Step S3100, if the stress level is a warning level or a danger level, dynamically adjusting the packaging process parameters of the ceramic chip; the packaging process parameters include a heating rate, a cooling rate, and a pressure fluctuation range; Further, step S3100 includes: Step S3110: if the stress level is a warning level, the heating rate is increased from the standard heating rate value to Adjust to the first heating rate value , change the cooling rate from the standard cooling rate value Adjust to the first cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Narrowed to the first pressure fluctuation range ,in, , , ; Step S3120: If the stress level is a dangerous level, the heating rate is increased from the standard heating rate value to Adjust to the second heating rate value , change the cooling rate from the standard cooling rate value Adjust to the second cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Reduced to the second pressure fluctuation range ,in, , , .

[0105] Specifically, step S3100 aims to dynamically adjust key process parameters in the ceramic chip packaging process, including heating rate, cooling rate and pressure fluctuation range, according to the predicted stress level, so as to reduce the risk of stress concentration inside the chip and avoid failure modes such as chip cracking and delamination. Different stress levels correspond to different degrees of parameter adjustment, and corresponding process optimization measures need to be taken for warning and danger levels.

[0106] In step S3110, when the predicted stress level is a warning level, it indicates that the chip faces a certain risk of stress instability and the packaging process parameters need to be appropriately adjusted. , , They respectively represent the standard heating rate, cooling rate and pressure fluctuation range under normal operating conditions, and are optimized process parameters determined based on product requirements and equipment capabilities. , , It means that when the stress level is the warning level, the new value after adjusting the standard parameters can reduce the thermal stress caused by the temperature difference inside and outside the chip by reducing the heating rate and cooling rate; and can improve the uniformity of chip stress by reducing the pressure fluctuation range. , , It reflects the direction and magnitude of parameter adjustment.

[0107] In step S3120, when the predicted stress level is a dangerous level, it means that the chip is in a high stress state and faces a serious risk of instability, and the packaging process parameters need to be significantly adjusted. , , This shows that the parameter adjustment range is larger under the dangerous level. By significantly reducing the heating rate, cooling rate and pressure fluctuation range, the stress level inside the chip can be alleviated to the greatest extent and failure accidents can be avoided. This graded adjustment strategy can tailor optimization measures according to the severity of the stress warning, ensuring chip reliability while taking into account production efficiency.

[0108] Step S3200, repeating steps S2000-S3000 until the ceramic chip packaging process is completed.

[0109] Step S3200 is an iterative optimization process, that is, steps S2000-S3000 are repeatedly executed until the ceramic chip completes the entire packaging process. This closed-loop control method can realize real-time monitoring and regulation of chip stress. By continuously collecting and analyzing environmental conditions and chip conditions, the stress prediction model is dynamically updated, and process parameters are adjusted in time according to the prediction results, forming an intelligent packaging control logic of environmental perception-prediction and warning-optimization decision-making-effect feedback. Each iteration will generate new status data and optimization measures to support the next round of prediction and optimization tasks, so that the control accuracy is continuously improved.

[0110] The above optimization methods can alleviate the stress distribution inside the chip from two dimensions: time and space. In the time dimension, by reducing the heating rate and cooling rate, the time gradient of temperature can be reduced, the action time of thermal stress can be prolonged, and the stress can be fully relaxed; in the space dimension, by reducing the pressure fluctuation range, the uniformity of stress distribution inside the chip can be improved to avoid local stress concentration. The coordinated optimization of the two can control the stress level of the chip from both macro and micro levels to prevent problems before they occur. At the same time, the solution is both targeted and adaptable. It can tailor optimization strategies according to the real-time stress state of different chips. It can handle common working conditions as well as extreme situations, and has strong robustness. In addition, the closed-loop iterative operation mode can continuously accumulate process knowledge and optimization experience, and realize the continuous evolution of packaging control level through the autonomous iteration of machine learning algorithms.

[0111] In summary, the dynamic optimization method based on stress prediction proposed in this step integrates multi-parameter control, graded response, closed-loop iteration and other mechanisms, and can accurately perceive the stress state of the chip and take targeted measures in a timely manner. While ensuring process stability, it can minimize the risk of chip failure and provide new ideas and methods for improving the quality of ceramic packaging processes. Compared with traditional empirical parameter adjustment, this method is predictive and intelligent, and can significantly improve the efficiency and reliability of process optimization, which is of great significance to further improve the performance and service life of ceramic chips.

[0112] Example 2

[0113] This embodiment provides a ceramic chip packaging process parameter optimization system based on machine learning on the basis of embodiment 1. Figure 6 As shown, including: Historical data acquisition module: used to collect the first historical data of the target ceramic chip during the packaging process; pre-process the first historical data and extract the second historical data; Chip stress prediction module: used to build a chip stress prediction model based on the second historical data; collect the first real-time data in the ceramic chip packaging process, pre-process the first real-time data, and obtain the second real-time data; obtain the chip stress prediction time series based on the second real-time data and the chip stress prediction model, and the chip stress prediction time series includes the future time period Stress prediction values ​​of n chips within; Chip stress level determination module: used to determine the future time period of the ceramic chip during the packaging process based on the chip stress prediction timing The stress level within the device includes a safety level, a warning level and a danger level; n is a positive integer; Parameter optimization module: If the stress level is a warning level or a danger level, the packaging process parameters of the ceramic chip are dynamically adjusted.

[0114] In the historical data acquisition module, the preprocessing of the first historical data to extract the second historical data includes: Step S1210, performing differentiation on the ambient temperature time series data to obtain ambient temperature change rate time series data; Step S1220, performing differentiation on the environmental pressure time series data to obtain environmental pressure change rate time series data; Step S1230, performing differentiation on the ambient humidity time series data to obtain ambient humidity change rate time series data; Step S1240, performing differentiation on the chip stress time series data to obtain chip stress change rate time series data; Step S1250, performing differentiation on the chip temperature time series data to obtain chip temperature change rate time series data.

[0115] In the chip stress prediction module, the construction of the chip stress prediction model includes: Step S2110, performing feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environment statistical time series features, historical chip statistical time series features, historical environment energy time series features, historical chip energy time series features and associated time series features; Step S2120, constructing a chip stress prediction model based on the historical comprehensive timing feature set.

[0116] The step S2110 includes: Step S2111, extracting statistical features of the environmental state change rate time series data to generate historical environmental statistical time series features; Step S2112, extracting the statistical features of the chip state change rate time series data to generate historical chip statistical time series features; Step S2113, extracting the energy distribution of the environmental state change rate time series data on different time scales to obtain the historical environmental energy time series characteristics; Step S2114, extracting the energy distribution of the chip state change rate time series data on different time scales to obtain the historical chip energy time series characteristics; Step S2115, calculating the correlation coefficient between the time series data of the environment state change rate and the time series data of the chip state change rate to obtain the correlation time series feature.

[0117] In the chip stress prediction module, the first real-time data includes real-time environmental status data and real-time chip status data; The real-time environmental status data includes real-time environmental temperature sequence data, real-time environmental pressure sequence data and real-time environmental humidity sequence data; the real-time chip status sequence data includes real-time chip stress sequence data and real-time chip temperature sequence data; The second real-time data includes real-time environment state change rate time series data and real-time chip state change rate time series data; the real-time environment state change rate time series data includes real-time environment temperature change rate time series data, real-time environment pressure change rate time series data, and real-time environment humidity change rate time series data; the real-time chip state change rate time series data includes real-time chip stress change rate time series data and real-time chip temperature change rate time series data; In the chip stress level determination module, the chip stress prediction timing is used to determine the future time period of the ceramic chip during the packaging process. The stress levels within include: Step S2410, calculating the mean μ of the chip stress prediction time series σ and standard deviation σ σ ; Step S2420, calculating the chip stress prediction value σ at the i-th moment in the future in the chip stress prediction time series i PSI i ; When PSI i ≥λ', the mean μ σ As the chip stress prediction correction value σ' at the i-th moment in the future i , that is, σ' i =μ σ ; When PSI i <λ', then σ' i =(1-w)μ σ +w×σ i-1 ; σ i-1 is the predicted chip stress value at the i-1th moment in the future, w is σ i-1 The weight of , 2≤i≤n, λ' is the structural mutual information threshold; Step S2430: predict the chip stress correction value σ' at the future i-th moment i The chip stress prediction and correction time series [(t1,σ'1),(t2,σ'2),…,(t n ,σ' n )]; where σ' n is the chip stress prediction correction value at the nth moment in the future; Step S2440, based on the chip stress prediction correction timing, determine the future time period of the ceramic chip in the packaging process Stress level within.

[0118] The step S2440 includes: Step S2441, if σ w ≤σ' i <σ s , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the safety level, where σ s is the upper safety limit, σ w is the upper warning limit; Step S2442, if σ d ≤σ' i <σ w , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the warning level, where σ d is the upper limit of danger, σ s >σ w >σ d ; Step S2443, if σ' i <σ d , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is a dangerous level; Step S2444, traverse all chip stress prediction and correction values ​​in the chip stress prediction and correction sequence, and count the future time periods respectively. The number of moments when the internal stress level is the safety level is n2, the number of moments when the stress level is the warning level is n3, and the number of moments when the stress level is the danger level is n4; n2+n3+n4=n; Step S2445, setting the weight coefficient w of the security level at the moment s , the weight coefficient w at the warning level w and the weight coefficient w at the danger level d , according to n2, n3, n4, w s 、w w and w d , calculate the future time period The weighted proportion of the internal warning level moments P w and the weighted proportion of the dangerous level moment P d ; Step S2446, according to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress level inside is the dangerous level.

[0119] The step S2446 includes: Step S24461, if P d >α, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the danger level; where α is the danger ratio threshold; Step S24462, if P d ≤α and P w >β, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the warning level; where β is the warning proportion threshold; Step S24463, if P d ≤α and P w ≤β, then determine the future time period of the ceramic chip during the packaging process The stress level within is the safety level.

[0120] In the parameter optimization module, the dynamic adjustment of the packaging process parameters of the ceramic chip includes: Step S3100, if the stress level is a warning level or a danger level, dynamically adjusting the packaging process parameters of the ceramic chip; the packaging process parameters include a heating rate, a cooling rate, and a pressure fluctuation range; Step S3200, repeatedly performing chip stress prediction, chip stress level determination and parameter optimization until the ceramic chip packaging process is completed.

[0121] The step S3100 includes: Step S3110: if the stress level is a warning level, the heating rate is increased from the standard heating rate value to Adjust to the first heating rate value , change the cooling rate from the standard cooling rate value Adjust to the first cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Narrowed to the first pressure fluctuation range ,in, , , ; Step S3120: If the stress level is a dangerous level, the heating rate is increased from the standard heating rate value to Adjust to the second heating rate value , change the cooling rate from the standard cooling rate value Adjust to the second cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Reduced to the second pressure fluctuation range ,in, , , .

[0122] In addition, the parts of the above-mentioned technical solutions provided in the embodiments of the present application that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail to avoid excessive redundancy.

[0123] The specific implementation modes as described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation mode of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A ceramic chip packaging process parameter optimization method based on machine learning, characterized in that: The method comprises: Collecting first historical data of the target ceramic chip during the packaging process; preprocessing the first historical data to extract second historical data; According to the second historical data, a chip stress prediction model is constructed; the first real-time data in the ceramic chip packaging process is collected, and the first real-time data is preprocessed to obtain the second real-time data; according to the second real-time data and the chip stress prediction model, a chip stress prediction time series is obtained, and the chip stress prediction time series includes a future time period n chip stress prediction values ​​within the package; based on the chip stress prediction timing, determine the future time period of the ceramic chip during the packaging process The stress level within the device includes a safety level, a warning level and a danger level; n is a positive integer; If the stress level is a warning level or a danger level, the packaging process parameters of the ceramic chip are dynamically adjusted.

2. The ceramic chip packaging process parameter optimization method based on machine learning according to claim 1 is characterized in that: The first historical data includes environmental state timing data and chip state timing data; the environmental state timing data includes environmental temperature timing data, environmental pressure timing data and environmental humidity timing data; the chip state timing data includes chip stress timing data and chip temperature timing data; The second historical data includes environmental state change rate time series data and chip state change rate time series data; the environmental state change rate time series data includes environmental temperature change rate time series data, environmental pressure change rate time series data, and environmental humidity change rate time series data; the chip state change rate time series data includes chip stress change rate time series data and chip temperature change rate time series data; The preprocessing of the first historical data to extract the second historical data includes: Differentiate the ambient temperature time series data to obtain the ambient temperature change rate time series data; Differentiate the environmental pressure time series data to obtain the environmental pressure change rate time series data; Differentiate the time series data of ambient humidity to obtain the time series data of ambient humidity change rate; Differentiate the chip stress time series data to obtain the chip stress change rate time series data; The chip temperature timing data is differentiated to obtain the chip temperature change rate timing data.

3. The ceramic chip packaging process parameter optimization method based on machine learning according to claim 1 is characterized in that: The constructing of the chip stress prediction model comprises: Performing feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environmental statistical time series features, historical chip statistical time series features, historical environmental energy time series features, historical chip energy time series features and associated time series features; A chip stress prediction model is constructed based on the historical comprehensive timing feature set.

4. The ceramic chip packaging process parameter optimization method based on machine learning according to claim 3 is characterized in that: The feature engineering processing of the second historical data includes: Extract the statistical characteristics of the time series data of the environmental state change rate and generate the historical environmental statistical time series characteristics; Extract the statistical features of the chip state change rate time series data to generate historical chip statistical time series features; Extract the energy distribution of the environmental state change rate time series data at different time scales to obtain the historical environmental energy time series characteristics; Extract the energy distribution of chip state change rate time series data at different time scales to obtain the historical chip energy time series characteristics; The mutual correlation coefficient between the time series data of the environmental state change rate and the time series data of the chip state change rate is calculated to obtain the correlation time series characteristics.

5. The method for optimizing ceramic chip packaging process parameters based on machine learning according to claim 1, characterized in that: The chip stress prediction timing is based on determining the future time period of the ceramic chip during the packaging process. The stress levels within include: Calculate the chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t n ,σ n )] σ and standard deviation σ σ ; where t n For future time periods At the nth moment in n For future time periods The predicted chip stress value at the nth moment within ; Calculate the chip stress prediction value σ at the future i-th moment in the chip stress prediction time series i PSI i ; When PSI i ≥λ', the mean μ σ As the chip stress prediction correction value σ' at the i-th moment in the future i , that is, σ' i =μ σ ; When PSI i <λ', then σ' i =(1-w)μ σ +w×σ i-1 ; σ i-1 is the predicted chip stress value at the i-1th moment in the future, w is σ i-1 The weight of , 2≤i≤n, λ' is the structural mutual information threshold; The predicted correction value σ' of chip stress at the future i-th moment i The chip stress prediction and correction time series [(t1,σ'1),(t2,σ'2),…,(t n ,σ' n )]; where σ' n is the chip stress prediction correction value at the nth moment in the future; Based on the chip stress prediction and correction timing, determine the future time period of the ceramic chip during the packaging process Stress level within.

6. The ceramic chip packaging process parameter optimization method based on machine learning according to claim 5, characterized in that: The chip stress prediction and correction timing is based on determining the future time period of the ceramic chip during the packaging process. The stress levels within include: If σ w ≤σ' i <σ s , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the safety level, where σ s is the upper safety limit, σ w is the upper warning limit; If σ d ≤σ' i <σ w , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is the warning level, where σ d is the upper limit of danger, σ s >σ w >σ d ; If σ' i <σ d , then the stress level of the ceramic chip at the i-th moment in the future during the packaging process is a dangerous level.

7. The method for optimizing ceramic chip packaging process parameters based on machine learning according to claim 6, characterized in that: The chip stress prediction and correction timing is based on determining the future time period of the ceramic chip during the packaging process. The stress levels within also include: Traverse all chip stress prediction and correction values ​​in the chip stress prediction and correction time series, and count the future time periods respectively The number of moments when the internal stress level is the safety level is n2, the number of moments when the stress level is the warning level is n3, and the number of moments when the stress level is the danger level is n4; n2+n3+n4=n; Set the weight coefficient w at the security level moment s , the weight coefficient w at the warning level w and the weight coefficient w at the danger level d , according to n2, n3, n4, w s 、w w and w d , calculate the future time period The weighted proportion of the internal warning level moments P w and the weighted proportion of the dangerous level moment P d ; According to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress level inside is the dangerous level.

8. The method for optimizing ceramic chip packaging process parameters based on machine learning according to claim 7, characterized in that: According to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress levels within the dangerous level include: If P d >α, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the danger level; where α is the danger ratio threshold; If P d ≤α and P w >β, it is determined that the ceramic chip will be in the future time period during the packaging process The stress level within is the warning level; where β is the warning proportion threshold; If P d ≤α and P w ≤β, then determine the future time period of the ceramic chip during the packaging process The stress level within is the safety level.

9. The method for optimizing ceramic chip packaging process parameters based on machine learning according to claim 8, characterized in that: The packaging process parameters include heating rate, cooling rate and pressure fluctuation range; The dynamic adjustment of the packaging process parameters of the ceramic chip includes: If the stress level is at the warning level, the heating rate is increased from the standard heating rate value Adjust to the first heating rate value , change the cooling rate from the standard cooling rate value Adjust to the first cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Narrowed to the first pressure fluctuation range ,in, ; If the stress level is dangerous, the heating rate is increased from the standard heating rate value Adjust to the second heating rate value , change the cooling rate from the standard cooling rate value Adjust to the second cooling rate value , change the pressure fluctuation range from the standard pressure fluctuation range Reduced to the second pressure fluctuation range ,in, .

10. A ceramic chip packaging process parameter optimization system based on machine learning, which is used to implement a ceramic chip packaging process parameter optimization method based on machine learning as described in any one of claims 1 to 9, characterized in that: The system comprises: Historical data acquisition module: used to collect the first historical data of the target ceramic chip during the packaging process; pre-process the first historical data and extract the second historical data; Chip stress prediction module: used to build a chip stress prediction model based on the second historical data; collect the first real-time data in the ceramic chip packaging process, pre-process the first real-time data, and obtain the second real-time data; obtain the chip stress prediction time series based on the second real-time data and the chip stress prediction model, and the chip stress prediction time series includes the future time period n chip stress prediction values ​​within; n is a positive integer; Chip stress level determination module: used to determine the future time period of the ceramic chip during the packaging process based on the chip stress prediction timing The stress level within the device includes a safety level, a warning level and a danger level; Parameter optimization module: If the stress level is a warning level or a danger level, the packaging process parameters of the ceramic chip are dynamically adjusted.

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