Alarm signal during operation activates test mode

Abstract

The system enables an alarm signal test mode. The system has an alarm signal line between a memory device and a memory controller. The memory device has a register for controlling entry into the alarm signal test mode. The memory controller sends a command to trigger the memory device to enter the alarm signal test mode. In response to the command, the memory device asserts the alarm signal line with an alarm signal in response to entering the alarm signal test mode.

Description

[0001] priority

[0002] This application is based upon and claims the benefit of priority to U.S. Provisional Application No. 63 / 541,728. Technical Field

[0003] The description relates generally to memory systems and, more particularly, to subsystem signaling. Background Art

[0004] The interface between a memory device (e.g., a DRAM (dynamic random access memory) device) and a host includes a plurality of signal lines that interconnect the devices. The interface includes a CA (command / address) bus, a data bus, and one or more additional signal lines. One common signal line is an alarm signal line that the DRAM device can assert to signal an alarm condition. The memory controller is typically unaware of the timing associated with the alarm signaling from the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following description includes a discussion of the accompanying drawings, in which illustrations are provided in the form of examples of implementations. The accompanying drawings should be understood in an illustrative manner and not in a limiting manner. As used herein, reference to one or more examples should be understood to describe specific features, structures, or characteristics included in at least one implementation of the present invention. Phrases such as "in one example" or "in an alternative example" that appear herein provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0006] Figure 1 is a block diagram of an example of a system having a memory that can perform an alarm signal test.

[0007] Figure 2 is a block diagram of an example of a register for triggering an alarm test mode.

[0008] Figure 3 is a timing diagram of an example of an alarm signal test.

[0009] Figure 4 is a block diagram of an example of a memory device that performs per-row activation counting.

[0010] Figure 5 is a block diagram of an example of a system that tracks activations at a memory device.

[0011] Figure 6 is a flow chart for an example of an alarm signal testing process.

[0012] Figure 7is a block diagram of an example of a memory subsystem in which an alert signal test may be implemented.

[0013] Figure 8A-B is a block diagram of an example in which a CAMM (Compression-attached memory module) system may be implemented.

[0014] Fig. 9 is a block diagram of an example of a computing system in which an alarm signal test may be implemented.

[0015] Fig.10 is a block diagram of an example of a multi-node network in which alarm signal testing may be implemented.

[0016] What follows is a description of specific details and implementations, including a non-limiting description of the accompanying drawings, which may depict some or all examples, as well as other potential implementations. DETAILED DESCRIPTION

[0017] Volatile memory devices, such as DRAM (Dynamic Random Access Memory) devices, have a known attack vector referred to as row hammer or row disturb. The row hammer condition refers to flipping the bits of an adjacent row (victim row) by repeatedly accessing a target row (aggressor row) over a period of time. Repeated accesses to the target row cause the values ​​of victim rows adjacent or close to the target / aggressor row to change. Repeated activation of the target row causes charge to migrate across the channel gates of the victim row. By repeatedly manipulating the target row with a known pattern, an attacker can intentionally flip the bits of the victim row.

[0018] Using PRHT (Perfect Row Hammer Tracking), PRAC (Per Row Activation Count), or related techniques, a DRAM device can internally track the number of activations of a row. The DRAM can internally increment an internal counter, the bits of which are stored in the DRAM row. The storage of the internal activation count ensures that the DRAM knows how many times each row has been activated. Thus, the DRAM can internally monitor for row hammer conditions and trigger an alarm signal in response to a row reaching a threshold number of activations.

[0019] Recent memory device specifications may support refresh mitigation commands, such as RFM (Refresh Management) commands, ARFM (Adaptive Refresh Management) commands, and DRFM (Directed Refresh Management) commands, to mitigate attacked neighbor WLs (Word Lines). Such commands enable a memory controller to send commands to allow a memory device to mitigate a row hammer condition. In response to activating the trace, the DRAM may assert an alert signal, and the memory controller may send a refresh mitigation command.

[0020] As described herein, a system enables an alarm signal test mode. The system has an alarm signal line between a memory device and a memory controller. The memory device has a register for controlling entry into the alarm signal test mode. The memory controller sends a command to trigger the memory device to enter the alarm signal test mode. In response to the command, the memory device asserts the alarm signal line with an alarm signal in response to entering the alarm signal test mode.

[0021] The ALERT signal line test enables the system to know the timing of the ALERT signaling, which can improve system performance when using ALERT signaling to trigger a mitigation response. The new row hammer mitigation technique involves sending an ALERT from the DRAM to the memory controller (host) by setting the ALERT signal line. A refresh management (RFM) is a command from the host that allows the DRAM to perform a refresh internally. The host sends the RFM command in response to the ALERT.

[0022] The alarm signal test can provide an alarm signal activation operation for the system to detect and check the mitigation operation during system operation. Therefore, the alarm signal test can be a runtime operation. For the system, the alarm signal test mode can easily activate the alarm signal for the system to check the mitigation function on the system side during system operation.

[0023] In one example, the alert signal test mode is an optional test mode for DRAM devices that can be included to check the host's ability to handle the ALERT_n signal and verify the system mitigation flow. In one example, test mode support is indicated by MR71:OP[6]=1. In one example, the test mode is enabled by setting MR71:OP[7]=1. In one example, the DRAM asserts ALERT_n after a maximum delay tMR_ALERT. In one example, the DRAM can set ABO (alert backoff) flag at MR70:OP[5], indicating that ALERT_n is asserted due to the requirement for additional RFM. In one example, the test mode field (e.g., MR71 OP[7]) is defined as a write-only bit and is self-clearing.

[0024] To ensure that the DRAM can refresh the row that triggers the row hammer condition, the host must send the RFM command shortly after the row hammer condition occurs. Therefore, the system benefits from an ALERT signal with deterministic timing. To determine the timing for the ALERT signal, the memory subsystem can trigger an alert signal test mode.

[0025] With the alert signal test mode, the host sets a register bit / field (e.g., a MRW command that sets the alert signal test mode bit / field) to trigger the DRAM to enter the alert signal test mode. Once the register bit is set, the DRAM drives the ALERT signal to the host. The host knows when the alert signal test mode is set, and knows the delay (tMR_ALERT) required for the DRAM to set the ALERT signal. Therefore, based on the test mode, the memory controller knows how long it takes for the DRAM to set the ALERT signal.

[0026] Compared to the conventional procedure of counting ACT issues and detecting reaching the count threshold, the response time from MR Write (mode register write) to "ALERT_n" assertion is quite fast. Thereafter, the memory controller can initiate the row hammer mitigation protocol process, including hardware and software logic operations on the memory controller side.

[0027] Figure 1 1 is a block diagram of an example of a system having a memory that can perform an alarm signal test. System 100 includes a host 110 having a processor 114 and a controller 120. Controller 120 can be a memory controller. In one example, controller 120 is an integrated memory controller (iMC).

[0028] System 100 includes a memory device 130 having an array 134, which represents a memory array. Memory device 130 includes a decoder 136 for decoding commands and a register 140 for storing configuration information. In one example, register 140 is a mode register. Register 140 includes a field or bit for controlling an alarm test mode. Alarm test 142 represents an alarm test mode control.

[0029] The memory device 130 includes a column DEC (decoder) 152 for managing access to specific columns and bits of memory. The memory device 130 includes a row DEC (decoder) 154 for managing access to selected rows of memory.

[0030] I / O (input / output) 112 represents the hardware interface of the host 110 for coupling to the I / O (input / output) 132 of the memory device 130. The interface includes CA (command / address) 162, which represents the signal lines for the command and address bus. The CA bus is a unidirectional bus from the controller 120 to the memory device 130.

[0031] The interface includes DQ (data) 164, which represents a signal line for a data bus. The DQ bus is a bidirectional bus that allows the host 110 and the memory device 130 to exchange data with each other. The interface includes an alarm 166, which represents an alarm signal line through which the memory device 130 can send an alarm to the host 110.

[0032] Array 134 shows target row 158, which represents a row that is repeatedly accessed within the refresh window, which can cause a row hammering condition. Victim row 156 represents a row physically close to target row 158 that is written due to the accumulation of charge on the channel caused by repeated access to target row 158.

[0033] In one example, the controller 120 includes a CMD (command) control 122 and a REF (refresh) control 124. The command control 122 represents the logic in the controller 120 for generating and sending commands to the memory device 130. The refresh control 124 represents the logic in the controller 120 for generating and sending refreshes to the memory device 130. In one example, the memory device 130 tracks row activations and sends an alarm signal to the controller 120 via the alarm 166 when a row reaches a threshold number of activations.

[0034] In one example, the system 100 enables an alarm signal test. The host 110, through the controller 120, can set the alarm test 142 of the register 140 to trigger the memory device 130 to enter an alarm signal test mode. Entering the alarm signal test mode enables the timing of the alarm signal to be determined. In the alarm signal test mode, the memory device 130 can assert the alarm signal whenever the host triggers the test mode. Therefore, the controller 120 can determine the expected timing for the memory device 130 to assert the alarm signal on the alarm 166.

[0035] Figure 2 2 is a block diagram of an example of a register for triggering an alarm test mode. Mode register 210 represents mode register MRx, which is a mode register designation within a memory device, such as MR71 for mode register 71. Mode register 210 represents a configuration register. Mode register 210 represents an example of a mode register in a DRAM device that supports an alarm signal test mode.

[0036] As shown, address 214 (Az) represents a bit that triggers an alarm test mode, which represents an alarm signal test mode according to any description herein. Address 212 (Ay) represents a bit that indicates that an alarm test mode is supported. Although the description refers to a "bit", it should be understood that a field can include one or more bits. An address can indicate the address of a field or a bit.

[0037] In the example where Ay represents a bit, "0" may indicate that the alarm test mode is not supported, and "1" may indicate that the alarm test mode is supported. In the example where Az represents a bit, "0" may indicate a normal operation mode, and "1" may indicate an alarm test mode. When the alarm test mode is set, the memory device may immediately send an alarm signal.

[0038] Register 220 represents an example of mode register 210, arranged as a bit field. As shown, the mode register includes 8 bits, where MR[6] (MRx OP[6]) is the address for Ay, and MR[7] (MRx OP[7]) is the address for Az.

[0039] Figure 3 300 is a timing diagram for an example of an alarm signal test. Figure 300 shows a timing diagram for a system implementing an alarm signal test mode. Signal 310 represents a CLK (clock) signal, with a solid line representing the clock signal (CLK_t) and a dashed line representing the complement (CLK_c). The moment indications represent examples where the timing can be different based on the length of the interrupt / delay time between clock transitions.

[0040] Signal 320 represents a CMD (command) signal indicating a signal provided by the memory controller to the memory device via the CA bus. At 322, the memory controller sends a MRW (mode register write) or other command to trigger the memory device to enter the alarm signal test mode. The timing of setting the mode register using MRW can be in the range of about 14 nanoseconds.

[0041] Signal 330 represents an Alert_n signal, which indicates that there is a separate alert signal line for each individual memory device to the memory controller. In one example, the memory device asserts the alert signal immediately in response to the MRW command. The time it takes for the memory device to assert the alert signal from issuing the MRW command represents tMR_ALERT, or the delay from the mode register command to the alert signal line transition. In one example, the memory controller sets tMR_ALERT to the maximum time for the alert to be asserted, making the signal deterministic because the memory controller then knows the time delay. tMR_ALERT can represent the maximum delay from receiving the mode register command to the time to assert the alert signal.

[0042] At 332, the memory device drives signal 330. As shown, when ALERT_n is a disable signal (e.g., zero is asserted, and one is deasserted), assertion of the alert signal line occurs at a logic low. The memory device interface hardware can pull the alert signal line to a logic low. In one example, the memory device asserts signal 330 for a period of time tABO_PW, which is the alert backoff (ABO) time. The time tABO_ACT is the minimum delay time from the alert signal to a subsequent ACT (activate) command.

[0043] After tABO_ACT, at 324, the memory controller may send an RFM or other command to manage refresh at the memory device. The command at 326 shows an RFM command sent by the memory controller that was not triggered by an alert from the memory device. Thus, the memory controller may send an RFM command in response to a trigger of the memory device, and the memory controller may also schedule an RFM command.

[0044] Figure 4 is a block diagram of an example of a memory device that performs per row activation counting. System 400 represents a memory device that performs activation tracking or PRHT (Perfect Row Hammer Tracking). Activation tracking may be referred to as PRAC (Per Row Activation Count).

[0045] System 400 shows a configuration with eight data signal line interfaces (DQs), indicated as DQ7:DQ0. It should be understood that the configuration of the subarrays providing bits to the different DQs can be the same as shown in system 400, or can be a different configuration. Additionally, the ECC (error checking and correction) subarray can be located in a different location.

[0046] Data subarray 412 shows a subarray for data DQ. ECC subarray 414 represents a subarray for ECC bits. Row DEC (decoder) 422 represents row decoding hardware for system 400. COL (column) DEC (decoder) 424 represents column decoding hardware for system 400. ECC 426 represents ECC hardware for internal ECC for system 400. Internal ECC represents ECC hardware at the memory device for bits stored in the ECC subarray.

[0047] ACNT (Activation Count) represents a subarray for counting activations (counting subarray 416). ACNT represents a subarray that keeps a count per row to track activations for a row hammering threshold. The row hammering threshold is the number of activations that is set / configured to cause the device to perform a refresh to avoid the risk of triggering a row hammering condition. Adder 434 and queue 436 represent the logic for the system 400 to count and track activations per row. PRAC ECC 432 represents the ECC hardware for the counting subarray.

[0048] In one example, in response to the activation count reaching the threshold count, the memory device can send an alert signal to the host. The host and memory device can test the alert signal according to any description herein to ensure that the memory controller knows the timing for the alert to schedule refresh mitigation for the memory device.

[0049] Figure 5 5 is a block diagram of an example of a system for tracking activation at a memory device. System 500 provides an example of a system according to the example of system 100 or the example of system 400, wherein details of DRAM are shown. In system 500, the memory is specifically shown as a DRAM (dynamic random access memory) device. DRAM 540 represents one of a plurality of DRAM devices that can be coupled to host 510.

[0050] Host 510 represents a hardware platform for system 500, having processor 520 and memory controller 530. Processor 520 may be referred to as a host processor. Processor 520 executes OS (operating system) 522, and OS 522 provides a software platform for system 500, and other applications and processes will be executed on the hardware platform of host 510 on this software platform. Applications (APPS) 524 represent other applications or services in system 500. The execution of OS 522 and application 524 generates access requests for DRAM 540.

[0051] The memory controller 530 manages access to the DRAM 540. In one example, the memory controller 530 includes a command (CMD) logic 532 for generating access commands to be sent to the DRAM 540. The command is represented as a CMD on a command bus to the DRAM 540. The command can be any type of command that generates or accompanies an activate command. In one example, the command logic 532 generates a command to indicate the count that the DRAM 540 should use to increase its internal activation count. The command can be an activate command, a precharge command, or another command with a field indicating an increase in the memory side activation count.

[0052] In one example, the memory controller 530 includes a row hammer (RH) control 534, which represents circuitry or logic at the memory controller 530 for determining when to send commands to allow the DRAM 540 to mitigate a row hammer condition.

[0053] System 500 also shows a data bus (denoted as DATA) that couples memory controller 530 to DRAM 540 to exchange data. The command bus is a unidirectional bus, and the data bus is a bidirectional bus.

[0054] DRAM 540 includes a memory array having a plurality of bit cells 544, which represent memory cells or storage locations of the memory array. The bit cells 544 are connected to word lines (WL) and bit lines (BL), where a particular WL / BL location represents an address identifiable by a combination of a row (WL) and a column (BL) address, which may also require a bank and bank group address to specify a portion of the array to be accessed.

[0055] Row decoder (DEC) 554 represents decoding hardware for selecting a row or word line for reading, writing, or other access. Column decoder (DEC) 552 represents decoding hardware for selecting a column or bit line. Typically, selection includes charging rows and columns to access a group of bit cells. DRAM 540 does not specifically illustrate memory banks, but it is understood that the bit cell array can be organized into memory banks and memory bank groups. Sense amplifier (amplifier) ​​556 represents a sense amplifier that is used to temporarily store data for accessing array 550. For writing, write data is written into sense amplifier 556 and then written into array 550. For reading, data is read from array 550 into sense amplifier 556 and returned to memory controller 530 via the data bus.

[0056] DRAM 540 includes array 550, which represents an array of core memory cells for storing data. Count 560 represents a memory cell for storing an activation count or an activation count for each row. In one example, count 560 represents a bit at the end of each row of array 550 for providing storage for the count. Count 560 holds a value to indicate the number of activations since the last refresh of the row, and the value can be reset when refreshing.

[0057] When memory controller 530 sends a memory access command to DRAM 540, command decoder (DEC) 542 recognizes the command and controls the appropriate column decoder circuitry and row decoder circuitry to select the specified address. In one example, each command that triggers row activation of array 550 causes activation tracking 570 to increment count 560.

[0058] Each time a command from the memory controller 530 triggers a row activation, the circuitry in the DRAM 540 (represented by the activation tracking 570) can read the count 560 of the selected row into the sense amplifier 564. This value is the count value, which can be compared to a threshold using a comparator. If the row activation count for any particular row reaches the threshold, the memory chip recognizes the presence of a row hammer condition for the particular row. The activation tracking 570 can write the count back to the count 560 via the write device 562.

[0059] In one example, when activation tracking 570 identifies a row hammer condition, it can trigger DRAM 540 to assert an alarm signal. Alarm 580 represents a hardware interface for driving an alarm signal line to host 510.

[0060] Figure 6 600 illustrates an example of a test alarm signal according to any of the example systems herein. In one example, at 602, a memory controller determines to test an alarm signal. The test may be part of an initialization routine. In one example, at 604, the memory controller sends a mode register write command to write a field that controls the alarm signal test.

[0061] After an alert test delay (e.g., tMR_alert), at 606, the DRAM device drives the alert signal line to assert the alert signal. In one example, after the alert is asserted, at 608, a field that controls the alert signal test may be reset. In one example, at 610, the memory controller may write to the field to reset it. In one example, after the alert signal is asserted, the field automatically resets. In one example, after a delay period after setting the field, the field automatically resets.

[0062] In one example, the memory controller sends a command to allow the DRAM device to perform a refresh internally. For example, the memory controller may send a DRFM, RFM, or ARFM command. In one example, at 612, the system may perform other operations to complete the alarm signal test.

[0063] Figure 7 700 is a block diagram of an example of a memory subsystem in which an alarm signal test may be implemented. System 700 includes elements of a processor and a memory subsystem in a computing device. System 700 is an example of a system according to an example of system 100, system 400, or system 500.

[0064] In one example, system 700 includes an alert test 790 representing logic in memory controller 720, logic in memory device 740, or a combination of logic in memory controller 720 and memory device 740 to implement an alert signal test mode according to any example herein.

[0065] Processor 710 represents a processing unit of a computing platform, and the processing unit can execute an operating system (OS) and applications, which can be collectively referred to as a host or user of memory. The OS and applications perform operations that result in memory access. Processor 710 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a main processor (e.g., a CPU (central processing unit)), a peripheral processor (e.g., a GPU (graphics processing unit)), or a combination. Memory access may also be initiated by devices such as a network controller or a hard disk controller. Such devices may be integrated with the processor in some systems, or attached to the processor via a bus (e.g., PCI Express), or a combination. System 700 may be implemented as a SOC (system on chip), or may be implemented using independent components.

[0066] References to memory devices may apply to different memory types. Memory devices generally refer to volatile memory technologies. Volatile memory is memory whose state (and the data stored thereon) is uncertain if the power to the device is interrupted. Non-volatile memory refers to memory whose state is determined even if the power to the device is interrupted. Dynamic volatile memory requires refreshing the data stored in the device to maintain the state. An example of dynamic volatile memory includes DRAM (dynamic random access memory), or some variants (e.g., synchronous DRAM (SDRAM)). The memory subsystem described herein may be compatible with a variety of memory technologies, such as DDR4 (Double Data Rate Version 4, JESD79-4, originally released by JEDEC (Joint Electron Device Engineering Council, now JEDEC Solid State Technology Association) in September 2012), LPDDR4 (Low Power DDR Version 4, JESD209-4, originally released by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, originally released by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, originally released by JEDEC in November 2015), DDR5 (DDR Revision 5, originally released by JEDEC in July 2020), LPDDR5 (LPDDR Revision 5, JESD209-5, originally released by JEDEC in February 2019), HBM2 (HBM Revision 2, JESD235C, originally released by JEDEC in January 2020), HBM3 (HBM Revision 3, JESD238, originally released by JEDEC in January 2022), or other or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0067] The memory controller 720 represents one or more memory controller circuits or devices for the system 700. The memory controller 720 represents control logic that generates memory access commands in response to operations performed by the processor 710. The memory controller 720 accesses one or more memory devices 740. The memory device 740 can be a DRAM device according to any of the above. In one example, the memory device 740 is organized and managed as different channels, wherein each channel is coupled to a bus and a signal line, which are coupled to multiple memory devices in parallel. Each channel is independently operable. Therefore, each channel is independently accessed and controlled, and the timing, data transfer, command and address exchange, and other operations for each channel are independent. Coupling can refer to electrical coupling, communication coupling, physical coupling, or a combination of these. Physical coupling can include direct contact. Electrical coupling includes an interface or interconnection that allows current to flow between components or allows signal transmission between components, or both. Communication coupling includes connections (including wired or wireless) that enable components to exchange data.

[0068] In one example, the settings for each channel are controlled by a separate mode register or other register settings. In one example, each memory controller 720 manages a separate memory channel, although the system 700 can be configured to have multiple channels managed by a single controller, or to have multiple controllers on a single channel. In one example, the memory controller 720 is part of the host processor 710, such as logic implemented on the same die as the processor or logic implemented in the same package space as the processor.

[0069] The memory controller 720 includes an I / O interface logic 722 to couple to a memory bus, such as a memory channel as described above. The I / O interface logic 722 (and the I / O interface logic 742 of the memory device 740) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or a combination of these. The I / O interface logic 722 may include a hardware interface. As shown, the I / O interface logic 722 includes at least a driver / transceiver for a signal line. Typically, wires within an integrated circuit interface are coupled to pads, pins, or connectors to engage with signal lines or traces or other wires between devices. The I / O interface logic 722 may include a driver, a receiver, a transceiver, or a terminal, or other circuit systems or combinations of circuit systems to exchange signals on signal lines between devices. The exchange of signals includes at least one of sending or receiving. Although the figure shows that the I / O 722 of the memory controller 720 is coupled to the I / O 742 of the memory device 740, it is understood that in implementations of the system 700 where multiple groups of memory devices 740 are accessed in parallel, multiple memory devices may include an I / O interface to the same interface of the memory controller 720. In implementations of the system 700 that include one or more memory modules 770, the I / O 742 may include interface hardware for the memory modules in addition to the interface hardware on the memory devices themselves. Other memory controllers 720 will include separate interfaces with other memory devices 740.

[0070] The bus between the memory controller 720 and the memory device 740 can be implemented as a plurality of signal lines coupling the memory controller 720 to the memory device 740. The bus can typically include at least a clock (CLK) 732, a command / address (CMD) 734, and write data (DQ) and read data (DQ) 736, and zero or more other signal lines 738. In one example, the bus or connection between the memory controller 720 and the memory can be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line for CMD can be referred to as a "C / A bus" (or ADD / CMD bus, or some other name indicating the transmission of command (C or CMD) and address (A or ADD) information), and the signal line for writing and reading DQ can be referred to as a "data bus". In one example, independent channels have different clock signals, C / A buses, data buses, and other signal lines. Therefore, the system 700 can be considered to have multiple "buses", that is, independent interface paths can be considered as separate buses. It can be understood that, in addition to the circuit clearly shown, bus can also include at least one of the following: strobe signal line, alarm line, auxiliary line or other signal lines or combination.It can also be understood that serial bus technology can be used for the connection between memory controller 720 and memory device 740.An example of serial bus technology is to utilize embedded clock to carry out 8B10B encoding and transmission high-speed data by a single differential pair of signal in each direction.In one example, CMD 734 represents the signal line shared in parallel with multiple memory devices.In one example, multiple memory devices share the coded command signal line of CMD 734, and each memory device has a separate chip selection (CS_n) signal line to select each memory device.

[0071] It should be understood that in the example of system 700, the bus between the memory controller 720 and the memory device 740 includes an auxiliary command bus CMD 734 and an auxiliary bus DQ 736 for carrying write and read data. In one example, the data bus may include a bidirectional line for reading data and for writing / command data. In another example, the auxiliary bus DQ 736 may include a unidirectional write signal line for writing and data from the host to the memory, and may include a unidirectional line for reading data from the memory to the host. Depending on the selected memory technology and system design, other signals 738 may accompany the bus or sub-bus, such as a strobe line DQS. Based on the design of the system 700, or if the design supports multiple implementations, the data bus may have more or less bandwidth for each memory device 740, depending on the implementation. For example, the data bus may support a memory device with a x4 interface, an x8 interface, an x16 interface, or other interfaces. Conventional "xW" represents the number of signal lines that exchange data with the memory controller 720, where W is an integer, referring to the interface size of the memory device 740 or the width of the interface. The interface size of the memory device is a controlling factor regarding how many memory devices can be used simultaneously per channel or how many memory devices can be coupled in parallel to the same signal line in the system 700. In one example, a high bandwidth memory device, a wide interface device, or a stacked memory configuration, or combination can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface widths.

[0072] In one example, the memory device 740 and the memory controller 720 exchange data through the data bus in a burst or continuous data transmission sequence. The burst corresponds to the number of transmission cycles, which is related to the bus frequency. In one example, the transmission cycle can be the entire clock cycle of the transmission that occurs on the same clock or selection signal edge (e.g., on the rising edge). In one example, each clock cycle (referring to the cycle of the system clock) is divided into a plurality of unit intervals (UI), wherein each UI is a transmission cycle. For example, double data rate transmission is triggered on two edges (e.g., rising and falling edges) of the clock signal. The number of UIs that can be configured in a burst can be continuously configured, which can be a configuration stored in a register, or triggered instantly. For example, a sequence of eight continuous transmission cycles can be regarded as a burst length of eight (BL8), and each memory device 740 can transmit data on each UI. Therefore, an x8 memory device operating on BL8 can transmit 64 bits of data (8 data signal lines multiplied by 8 data bits transmitted by each line in the burst). It can be understood that this simple example is only an illustration and is not a limitation.

[0073] The memory devices 740 represent memory resources for the system 700. In one example, each memory device 740 is a separate memory die. In one example, each memory device 740 can be coupled to multiple (e.g., 2) channels of each device or die. Each memory device 740 includes an I / O interface logic 742, which has a bandwidth determined by the implementation of the device (e.g., x16 or x8 or some other interface bandwidth). The I / O interface logic 742 enables the memory device to be coupled to the memory controller 720. The I / O interface logic 742 may include a hardware interface and may be consistent with the I / O 722 of the memory controller, but at the memory device end. In one example, multiple memory devices 740 are connected in parallel to the same command and data bus. In another example, multiple memory devices 740 are connected in parallel to the same command bus and to different data buses. For example, the system 700 can be configured with multiple parallel coupled memory devices 740, each memory device responds to a command, and accesses the memory resources 760 inside each memory device. For a write operation, a single memory device 740 may write a portion of an overall data word, and for a read operation, a single memory device 740 may retrieve a portion of an overall data word. The remaining bits of the word will be provided or received in parallel by other memory devices.

[0074] In one example, the memory device 740 is directly disposed on the motherboard of the computing device or the host system platform (e.g., a PCB (printed circuit board) or substrate on which the processor 710 is disposed). In one example, the memory device 740 can be organized into a memory module 770. In one example, the memory module 770 represents a dual in-line memory module (DIMM). In one example, the memory module 770 represents other organizations of multiple memory devices to share at least a portion of the access or control circuit system, which can be a circuit, a separate device, or a separate board separated from the host system platform. The memory module 770 may include multiple memory devices 740, and the memory module may include support for multiple separate channels of the included memory devices disposed thereon. In another example, the memory device 740 may be incorporated into the same package as the memory controller 720, for example, by technologies such as multi-chip modules (MCMs), package-on-package, through-silicon vias (TSVs), or other technologies or combinations. Similarly, in one example, multiple memory devices 740 can be incorporated into a memory module 770, which itself can be incorporated into the same package as the memory controller 720. It can be appreciated that for these and other implementations, the memory controller 720 can be part of the host processor 710.

[0075] Each of the memory devices 740 includes one or more memory arrays 760. The memory array 760 represents an addressable memory location or storage location for data. Typically, the memory array 760 is managed as a data row, and access is controlled via word lines (rows) and bit lines (individual bits within a row). The memory array 760 can be organized into separate memory channels, memory ranks, and memory banks. A channel can refer to an independent control path to a storage location within the memory device 740. A storage group can refer to a common location across multiple memory devices in parallel (e.g., the same row address within different devices). A storage body can refer to a sub-array of memory locations within the memory device 740. In one example, a storage body of a memory is divided into sub-storage bodies, wherein at least a portion of a shared circuit system (e.g., a driver, a signal line, a control logic) is provided for the sub-storage body, thereby allowing separate addressing and access. It can be understood that other organizations of channels, storage groups, storage bodies, sub-storage bodies, storage body groups, or memory locations, and combinations of these organizations can overlap when applied to physical resources. For example, the same physical memory location as a specific memory bank can be accessed through a specific channel, which can also belong to a memory group. Therefore, the organization of memory resources will be understood in an inclusive rather than exclusive manner.

[0076] In one example, the memory device 740 includes one or more registers 744. The register 744 represents one or more storage devices or storage locations, and one or more storage devices or storage locations provide configuration or settings for the operation of the memory device. In one example, the register 744 can provide a storage location for the memory device 740 to store data for access by the memory controller 720 as part of the control or management operation. In one example, the register 744 includes one or more mode registers. In one example, the register 744 includes one or more multi-purpose registers. The configuration of the position within the register 744 can configure the memory device 740 to operate in different "modes", where command information can trigger different operations within the memory device 740 based on the mode. In addition or as an alternative, different modes can also trigger different operations from address information or other signal lines depending on the mode. The settings of the register 744 can indicate the configuration for the I / O settings (e.g., timing, termination or ODT (on-die termination) 746, driver configuration, or other I / O settings).

[0077] In one example, the memory device 740 includes an ODT 746 as part of the interface hardware associated with the I / O 742. The ODT 746 can be configured as described above and provides impedance settings for the interface to be applied to a specified signal line. In one example, the ODT 746 is applied to the DQ signal line. In one example, the ODT 746 is applied to the command signal line. In one example, the ODT 746 is applied to the address signal line. In one example, the ODT 746 can be applied to any combination of the foregoing. The ODT setting can be changed based on whether the memory device is a selected target or a non-target device for the access operation. The ODT 746 setting can affect the timing and reflection of the signaling on the termination line. Careful control of the ODT 746 can achieve higher speed operation while improving the matching of the applied impedance and load. The ODT 746 can be applied to specific signal lines of the I / O interface 742, 722 (e.g., ODT for DQ lines or ODT for CA lines), and is not necessarily applied to all signal lines.

[0078] The memory device 740 includes a controller 750, which represents the control logic within the memory device for controlling the internal operation within the memory device. For example, the controller 750 decodes the command sent by the memory controller 720 and generates an internal operation to execute or satisfy the command. The controller 750 can be called an internal controller and is separated from the memory controller 720 of the host. The controller 750 can determine which mode to select based on the register 744, and configure the execution of the internal operation for accessing the memory resource 760 or other operations based on the selected mode. The controller 750 generates a control signal to control the bit routing within the memory device 740, thereby providing an appropriate interface for the selected mode and directing the command to the appropriate memory location or address. The controller 750 includes a command logic 752, which can decode the command encoding received on the command and address signal lines. Therefore, the command logic 752 can be or include a command decoder. Using the command logic 752, the memory device can identify the command and generate an internal operation to execute the requested command.

[0079] Referring again to the memory controller 720, the memory controller 720 includes command (CMD) logic 724, which represents the logic or circuit system that generates commands to send to the memory device 740. The generation of commands can refer to the command before scheduling, or to the preparation of queued commands ready to be sent. Typically, signaling in the memory subsystem includes address information within or accompanying the command to indicate or select one or more memory locations where the memory device should execute the command. In response to the transaction scheduling for the memory device 740, the memory controller 720 can issue a command via I / O 7022 to cause the memory device 740 to execute the command. In one example, the controller 750 of the memory device 740 receives and decodes the command and address information received from the memory controller 720 via I / O 742. Based on the received command and address information, the controller 750 can control the timing of the operation of the logic and circuit system within the memory device 740 to execute the command. The controller 750 is responsible for complying with the standards or specifications within the memory device 740, such as timing and signaling requirements. The memory controller 720 may implement compliance with standards or specifications through access scheduling and control.

[0080] The memory controller 720 includes a scheduler 730, which represents a logic or circuit system for generating transactions and ordering transactions to be sent to the memory device 740. From one perspective, the main function of the memory controller 720 can be said to be to schedule memory access and other transactions to the memory device 740. Such scheduling may include generating the transaction itself to implement the processor 710 request for data and maintain the integrity of the data (e.g., such as commands related to refresh). A transaction may include one or more commands, and result in the transmission of commands or data or both within one or more timing cycles (e.g., clock cycles or unit intervals). Transactions can be used for access (e.g., read or write or related commands or combinations), and other transactions may include memory management commands for configuration, settings, data integrity, or other commands or combinations.

[0081] The memory controller 720 typically includes logic such as a scheduler 730 to allow transactions to be selected and ordered, thereby improving the performance of the system 700. Thus, the memory controller 720 can select which outstanding transactions should be sent to the memory device 740 in what order, which is typically achieved by logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 720 manages the transmission of transactions to the memory device 740 and manages the timing associated with the transactions. In one example, the transactions have deterministic timing, which can be managed by the memory controller 720 and used to determine how to schedule transactions using the scheduler 730.

[0082] In one example, the memory controller 720 includes refresh (REF) logic 726. The refresh logic 726 can be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, the refresh logic 726 indicates the location for refresh, and the type of refresh to be performed. The refresh logic 726 can trigger a self-refresh within the memory device 740, or perform an external refresh by sending a refresh command or combination (this can be called an automatic refresh command). In one example, the controller 750 within the memory device 740 includes refresh logic 754 to apply refresh within the memory device 740. In one example, the refresh logic 754 generates internal operations to perform refresh based on the external refresh received from the memory controller 720. The refresh logic 754 can determine whether the refresh is for the memory device 740, and which memory resources 760 to refresh in response to the command.

[0083] Figure 8A-B is a block diagram of an example of a CAMM system in which alarm signal testing may be implemented.

[0084] refer to Fig. 8A , system 802 includes a memory stack architecture monitored by a memory fault tracker that can perform mirroring. System 802 is an example of a system according to an example of system 100, system 400, or system 500.

[0085] Substrate 810 shows a SOC package substrate or a mainboard or system board. Substrate 810 includes contacts 812, which represent contacts for connecting to memory. CPU 814 represents a processor or a central processing unit (CPU) chip or a graphics processing unit (GPU) chip to be arranged on substrate 810. CPU 814 performs computing operations in system 802. In one example, CPU 814 includes multiple cores (not specifically shown), and multiple cores can generate operations requesting to read data from memory and write data to memory. CPU 814 may include a memory controller to manage access to memory devices.

[0086] Compression-attached memory module (CAMM) 830 represents a module with memory devices that are not specifically shown in system 802. Substrate 810 is coupled to CAMM 830 and its memory devices by compression mounting technology (CMT) connector 820. Connector 820 includes contact 822, which is a contact based on compression. Compression-based contacts are compressible pins or devices, and their shapes are compressed as pressure is applied to connector 820. In one example, contact 822 represents a C-shaped pin as shown. In one example, contact 822 represents another compressible pin shape, such as a spring-shaped, S-shaped or pin with other compressible shapes.

[0087] CAMM 830 includes contacts 832 on one side of the CAMM board that engages with connector 820. Contacts 832 connect to memory devices on the CAMM board. Plate 840 represents a plate or housing that provides a structure to apply pressure to compress contacts 822 of connector 820.

[0088] refer to Figure 8B , system 804 is a perspective view of a system according to system 802. System 804 shows a memory controller 850, which is not specifically shown in system 802. Memory controller 850 can provide row hammer mitigation for DRAM 836. DRAM 836 can be connected to memory controller 850 using an alert signal line. System 804 enables DRAM 836 to perform an alert signal test mode with memory controller 850 according to any example herein.

[0089] CAMM 830 is shown with memory chips or memory dies, identified as DRAM 836, on one or both sides of a PCB located on CAMM 830. DRAM 836 is coupled to conductive contacts via conductive traces in or on the PCB, which is coupled to contacts 832, which in turn are coupled to contacts 822 of connector 820.

[0090] System 804 shows holes 842 in plate 840 for receiving fasteners, represented by screws 844. There are corresponding holes in CAMM 830, connector 820, and substrate 810. Screws 844 can compressibly attach CAMM 830 to substrate 810 via connector 820.

[0091] Fig. 9 is a block diagram of an example of a computing system in which an alarm signal test may be implemented. System 900 represents a computing device according to any example herein, and may be a laptop, desktop computer, tablet computer, server, gaming or entertainment control system, embedded computing device, or other electronic device.

[0092] System 900 is an example of a system according to an example of system 100, system 400, or system 500. In one example, system 900 includes an alarm test 990, which represents logic in memory controller 922, logic in memory 930, or a combination of logic in memory controller 922 and memory 930 to implement an alarm signal test mode according to any example herein.

[0093] The system 900 includes a processor 910, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination, to provide processing or execution of instructions for the system 900. The processor 910 may be a host processor device. The processor 910 controls the overall operation of the system 900 and may be or include one or more programmable general or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0094] The system 900 includes a boot / configuration 916, which represents a storage device for storing boot code (e.g., a basic input / output system (BIOS)), configuration settings, security hardware (e.g., a trusted platform module (TPM)), or other system-level hardware operating outside of a host OS. The boot / configuration 916 may include a non-volatile memory device, such as a read-only memory (ROM), flash memory, or other memory device.

[0095] In one example, the system 900 includes an interface 912 coupled to a processor 910, which may represent a higher speed interface or a high throughput interface for system components (e.g., a memory subsystem 920 or a graphics interface component 940) that require a higher bandwidth connection. The interface 912 represents an interface circuit, which may be a separate component or integrated onto a processor chip. The interface 912 may be integrated onto a processor die as a circuit or onto a system on a chip as a component. If present, a graphics interface 940 is coupled to a graphics component for providing a visual display to a user of the system 900. The graphics interface 940 may be a separate component or integrated onto a processor die or onto a system on a chip. In one example, the graphics interface 940 may drive a high definition (HD) display or an ultra high definition (UHD) display to provide output to a user. In one example, the display may include a touch screen display. In one example, the graphics interface 940 generates a display based on data stored in the memory 930 or based on operations performed by the processor 910 or both.

[0096] The memory subsystem 920 represents the main memory of the system 900 and provides storage for the code to be executed by the processor 910 or the data value to be used to perform the routine. The memory subsystem 920 may include one or more random access memories (RAM), such as DRAM, 3DXP (three-dimensional crosspoint), or other memory devices, or a combination of such devices. The memory 930 stores and hosts an operating system (OS) 932 and other elements to provide a software platform for executing instructions in the system 900. Additionally, applications 934 can be executed on the software platform of the OS 932 from the memory 930. Applications 934 represent programs with their own operating logic to perform the execution of one or more functions. Processes 936 represent agents or routines that provide auxiliary functions to the OS 932 or one or more applications 934 or combinations. The OS 932, applications 934, and processes 936 provide software logic to provide functions for the system 900. In one example, the memory subsystem 920 includes a memory controller 922, which is a memory controller for generating commands and issuing commands to the memory 930. It is understood that the memory controller 922 can be a physical part of the processor 910 or a physical part of the interface 912. For example, the memory controller 922 can be an integrated memory controller integrated into a circuit with the processor 910, such as integrated into a processor die or a system on a chip.

[0097] Although not specifically described, it is understood that system 900 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or other. A bus or other signal line may couple components together communicatively or electrically, or both communicatively and electrically. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit systems or combinations. For example, a bus may include one or more of the following: a system bus, a peripheral component interconnect (PCI) bus, a hypertransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or other buses, or combinations.

[0098] In one example, system 900 includes an interface 914, which can be coupled to interface 912. Interface 914 can be an interface with a lower speed than interface 912. In one example, interface 914 represents an interface circuit, which can include independent components and integrated circuit systems. In one example, multiple user interface components or peripheral components or both are coupled to interface 914. Network interface 950 provides system 900 with the ability to communicate with remote devices (e.g., servers or other computing devices) via one or more networks. Network interface 950 may include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB (universal serial bus), or other wired or wireless standard or proprietary interface. Network interface 950 can exchange data with a remote device, which can include sending data stored in a memory or receiving data to be stored in a memory.

[0099] In one example, the system 900 includes one or more input / output (I / O) interfaces 960. The I / O interfaces 960 may include one or more interface components through which a user interacts with the system 900 (e.g., audio, alphanumeric, tactile / touch, or other interfaces). The peripheral interfaces 970 may include any hardware interfaces not explicitly mentioned above. Peripheral devices generally refer to devices that are dependently connected to the system 900. A dependent connection refers to a connection in which the system 900 provides a software platform or a hardware platform or both, operations are performed on it, and the user interacts with it.

[0100] In one example, the system 900 includes a storage subsystem 980 for storing data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of the storage subsystem 980 may overlap with components of the memory subsystem 920. The storage subsystem 980 includes a storage device 984, which may be or include any conventional media for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, NAND, 3DXP, or optical disks, or a combination. The storage device 984 saves code or instructions and data 986 in a persistent state (i.e., the value is retained even if the power to the system 900 is interrupted). The storage device 984 can be generally considered to be "memory", although the memory 930 is typically an execution or operating memory for providing instructions to the processor 910. Although the storage device 984 is non-volatile, the memory 930 may include volatile memory (i.e., if the power to the system 900 is interrupted, the value or state of the data is uncertain). In one example, storage subsystem 980 includes controller 982 for interfacing with storage device 984. In one example, controller 982 is a physical part of interface 914 or processor 910, or may include circuitry or logic in both processor 910 and interface 914.

[0101] The power supply 902 provides power to the components of the system 900. More specifically, the power supply 902 is typically coupled to one or more power supplies 904 in the system 900 for providing power to the components of the system 900. In one example, the power supply 904 includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. This AC power can be a renewable energy (e.g., solar) power supply 902. In one example, the power supply 902 includes a DC power source, such as an external AC to DC converter. In one example, the power supply 902 or the power supply 904 includes wireless charging hardware for charging via proximity to a charging field. In one example, the power supply 902 can include an internal battery or fuel cell source.

[0102] Fig.10 1 is a block diagram of an example of a multi-node network in which alarm signal testing can be implemented. In one example, system 1000 represents a data center. In one example, system 1000 represents a server farm. In one example, system 1000 represents a data cloud or a processing cloud.

[0103] Node 1030 of system 1000 represents a system according to an example of system 100, system 400, or system 500. In one example, node 1030 includes an alarm test 1090, which represents logic in controller 1042, logic in memory 1040, or a combination of logic in controller 1042 and memory 1040 to implement an alarm signal test mode according to any example herein.

[0104] One or more clients 1002 send requests to the system 1000 through the network 1004. The network 1004 represents one or more local networks, or wide area networks, or a combination. The client 1002 can be a human or machine client that generates a request for the system 1000 to perform an operation. The system 1000 performs the application or data computing task requested by the client 1002.

[0105] In one example, system 1000 includes one or more racks, one or more racks representing structural and interconnection resources for housing and interconnecting multiple computing nodes. In one example, rack 1010 includes multiple nodes 1030. In one example, rack 1010 hosts multiple blade components, blade 1020[0], ..., blade 1020[N-1], collectively referred to as blade 1020. Hosting refers to providing power, structural or mechanical support, and interconnection. Blade 1020 can refer to computing resources on a printed circuit board (PCB), where the PCB houses hardware components for one or more nodes 1030. In one example, blade 1020 does not include a chassis or housing or other "box" other than that provided by rack 1010. In one example, blade 1020 includes a housing with exposed connectors to connect to rack 1010. In one example, system 1000 does not include rack 1010, and each blade 1020 includes a chassis or housing, which can be stacked or otherwise reside near other blades and allow interconnection of nodes 1030.

[0106] The system 1000 includes a fabric 1070, which represents one or more interconnects for the nodes 1030. In one example, the fabric 1070 includes a plurality of switches 1072 or routers or other hardware for routing signals between the nodes 1030. Additionally, the fabric 1070 can couple the system 1000 to a network 1004 for access by clients 1002. In addition to routing devices, the fabric 1070 can be considered to include cables or ports or other hardware devices to couple the nodes 1030 together. In one example, the fabric 1070 has one or more associated protocols for managing the routing of signals through the system 1000. In one example, the one or more protocols rely, at least in part, on the hardware devices used in the system 1000.

[0107] As shown, rack 1010 includes N blades 1020. In one example, in addition to rack 1010, system 1000 also includes rack 1050. As shown, rack 1050 includes M blade assemblies, blade 1060[0], ..., blade 1060[M-1], collectively referred to as blades 1060. M is not necessarily the same as N; therefore, it should be understood that a variety of different hardware device components can be used and coupled to system 1000 through structure 1070. Blade 1060 can be the same as or similar to blade 1020. Node 1030 can be any type of node, and is not necessarily all nodes of the same type. System 1000 is not limited to homogeneity or non-homogeneity.

[0108] The nodes in the system 1000 may include computing nodes, memory nodes, storage nodes, accelerator nodes, or other nodes. Rack 1010 is represented by memory nodes 1022 and storage nodes 1024, which represent shared system memory resources and shared persistent storage, respectively. One or more nodes of rack 1050 may be memory nodes or storage nodes.

[0109] Node 1030 represents an example of a computing node. For simplicity, only the computing nodes in blade 1020[0] are shown in detail. However, other nodes in system 1000 can be the same or similar. At least some of nodes 1030 are computing nodes, having a processor (proc) 1032 and a memory 1040. A computing node refers to a node having processing resources (e.g., one or more processors) that executes an operating system and can receive and process one or more tasks. In one example, at least some of nodes 1030 are server nodes, where a server is a processing resource represented by processor 1032 and memory 1040.

[0110] Memory node 1022 represents an example of a memory node whose system memory is located outside the compute node. The memory node may include a controller 1082, which represents a processor on the node for managing access to memory. The memory node includes memory 1084 as a memory resource to be shared between multiple compute nodes.

[0111] Storage node 1024 represents an example of a storage server, which refers to a node that has more storage resources than a computing node, and the storage server does not have a processor for performing tasks, but includes processing resources for managing access to storage nodes within the storage server. The storage node may include a controller 1086 for managing access to the storage device 1088 of the storage node.

[0112] In one example, the node 1030 includes an interface controller 1034, which represents the logic of controlling the access of the node 1030 to the structure 1070. The logic may include hardware resources for interconnecting to the physical interconnect hardware. The logic may include software or firmware logic for managing the interconnection. In one example, the interface controller 1034 is or includes a host structure interface, which may be a structure interface according to any example described herein. The interface controllers for the memory node 1022 and the storage node 1024 are not explicitly shown.

[0113] Processor 1032 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a main processor (e.g., a CPU (central processing unit)), a peripheral processor (e.g., a GPU (graphics processing unit)), or a combination. Memory 1040 may be or include a memory device represented by memory 1040 and a memory controller represented by controller 1042.

[0114] Generally, with respect to the description herein, in one aspect, a memory device includes: a register having a bit field for controlling the memory device to enter an alarm signal test mode; a hardware interface to an alarm signal line between the memory device and a memory controller; and an interface circuit system coupled to the memory controller, the interface circuit system receiving a command to set the bit field to a value to cause the memory device to enter the alarm signal test mode, the memory device asserting the alarm signal line using an alarm signal in response to entering the alarm signal test mode.

[0115] In one example of a memory device, the register includes a mode register. According to any of the foregoing examples of the memory device, in one example, the command includes a mode register write (MRW) command. According to any of the foregoing examples of the memory device, in one example, the bit field includes a self-clearing write-only bit field. Consistent with any of the foregoing examples of the memory device, in one example, a memory device for asserting an alarm signal includes a hardware interface for pulling an alarm signal line to a logic low. According to any of the foregoing examples of the memory device, in one example, the memory device asserts the alarm signal in response to entering an alarm signal test mode within a defined delay period. According to any of the foregoing examples of the memory device, in one example, the defined delay period includes a maximum delay from receiving the command. According to any of the foregoing examples of the memory device, in one example, the memory device also sets an alarm backoff (ABO) flag in response to asserting the alarm signal. According to any of the foregoing examples of the memory device, in one example, assertion of the alarm signal is used to trigger a memory controller to provide row hammer mitigation for the memory device. According to any of the foregoing examples of the memory device, in one example, the row hammer mitigation includes a refresh management (RFM) command. According to any of the preceding examples of a memory device, in one example, row hammer mitigation comprises a directed refresh management (DRFM) command. According to any of the preceding examples of a memory device, in one example, row hammer mitigation comprises an adaptive refresh management (ARFM) command to the memory device. According to any of the preceding examples of a memory device, in one example, the memory device comprises a double data rate (DDR) dynamic random access memory (DRAM) device.

[0116] Generally, with respect to the description herein, in one aspect, a system for memory interface testing includes: an alarm signal line; a memory controller coupled to the alarm signal line; a memory device coupled to the alarm signal line, the memory device including a register having a bit field for controlling the memory device to enter an alarm signal test mode; and an interface circuit system coupled to the memory controller, the interface circuit system receiving a command to set the bit field to a value to cause the memory device to enter the alarm signal test mode, the memory device asserting the alarm signal line using an alarm signal in response to entering the alarm signal test mode.

[0117] In one example of the system, the register comprises a mode register. According to any of the foregoing examples of the system, in one example, the command comprises a mode register write (MRW) command. According to any of the foregoing examples of the system, in one example, the bit field comprises a write-only bit field that is self-clearing. According to any of the foregoing examples of the system, in one example, the memory device for asserting the alarm signal comprises a memory device that pulls the alarm signal line to a logic low. According to any of the foregoing examples of the system, in one example, the memory device asserts the alarm signal in response to entering the alarm signal test mode within a defined delay period. According to any of the foregoing examples of the system, in one example, the defined delay period comprises a maximum delay since receiving the command. According to any of the foregoing examples of the system, in one example, the memory device asserts the alarm signal in response to entering the alarm signal test mode within a defined delay period, the defined delay period indicating a maximum delay since receiving the command. According to any of the foregoing examples of the system, in one example, the memory device further sets an alarm backoff (ABO) flag in response to asserting the alarm signal. According to any of the foregoing examples of the system, in one example, assertion of the alarm signal is used to trigger the memory controller to provide row hammer mitigation for the memory device. According to any of the foregoing examples of the system, in one example, row hammer mitigation includes refresh management (RFM) commands. According to any of the foregoing examples of the system, in one example, row hammer mitigation includes directed refresh management (DRFM) commands. According to any of the foregoing examples of the system, in one example, row hammer mitigation includes adaptive refresh management (ARFM) commands to a memory device. According to any of the foregoing examples of the system, in one example, the memory device includes a double data rate (DDR) dynamic random access memory (DRAM) device. According to any of the foregoing examples of the system, in one example, the system includes a host processor coupled to the memory controller. According to any of the foregoing examples of the system, in one example, the system includes a display communicatively coupled to the host processor. According to any of the foregoing examples of the system, in one example, the system includes a network interface communicatively coupled to the host processor. According to any of the foregoing examples of the system, in one example, the system includes a battery for powering the system.

[0118] Generally, with respect to the description herein, in one aspect, a memory controller includes: a hardware interface for an alarm signal line between the memory controller and a memory device; and an interface circuit system coupled to the memory device, the interface circuit system sending a command to set a bit field in a register of the memory device to control the memory device to enter an alarm signal test mode; wherein the memory controller receives an alarm signal on the alarm signal line from the memory device in response to entering the alarm signal test mode.

[0119] In one example of a memory controller, a register of the memory device includes a mode register. According to any of the foregoing examples of the memory controller, in one example, the command includes a mode register write (MRW) command. According to any of the foregoing examples of the memory controller, in one example, the bit field includes a write-only bit field that is self-clearing. According to any of the foregoing examples of the memory controller, in one example, the memory device that asserts the alarm signal includes a hardware interface to pull the alarm signal line to a logic low. According to any of the foregoing examples of the memory controller, in one example, the memory device asserts the alarm signal in response to entering an alarm signal test mode within a defined delay period. According to any of the foregoing examples of the memory controller, in one example, the defined delay period includes a maximum delay from receiving the command. According to any of the foregoing examples of the memory controller, in one example, the memory device also sets an alarm backoff (ABO) flag in response to asserting the alarm signal. According to any of the foregoing examples of the memory controller, in one example, asserting the alarm signal is used to trigger the memory controller to provide row hammer mitigation for the memory device. According to any of the foregoing examples of the memory controller, in one example, the row hammer mitigation includes a refresh management (RFM) command. According to any of the foregoing examples of the memory controller, in one example, the row hammer mitigation includes a directed refresh management (DRFM) command. According to any of the preceding examples of the memory controller, in one example, row hammer mitigation comprises adaptive refresh management (ARFM) commands to the memory device. According to any of the preceding examples of the memory controller, in one example, the memory device comprises a double data rate (DDR) dynamic random access memory (DRAM) device.

[0120] Generally, with respect to the description herein, in one aspect, a method for performing an alarm signal test includes: receiving a command at a memory device to set a bit field of a register to a value to cause the memory device to enter an alarm signal test mode; and in response to entering the alarm signal test mode, asserting an alarm signal on an alarm signal line between the memory device and a memory controller.

[0121] In one example of the method, the register comprises a mode register. According to any of the foregoing examples of the method, in one example, the command comprises a mode register write (MRW) command. According to any of the foregoing examples of the method, in one example, the bit field comprises a write-only bit field that is self-clearing. According to any of the foregoing examples of the method, in one example, asserting the alarm signal comprises pulling the alarm signal line to a logic low. According to any of the foregoing examples of the method, in one example, asserting the alarm signal comprises asserting the alarm signal within a defined delay period after entering an alarm signal test mode. According to any of the foregoing examples of the method, in one example, the defined delay period comprises a maximum delay from receiving the command. According to any of the foregoing examples of the method, in one example, the method comprises setting an alarm backoff (ABO) flag in response to asserting the alarm signal. According to any of the foregoing examples of the method, in one example, asserting the alarm signal is used to trigger a memory controller to provide row hammer mitigation for a memory device. According to any of the foregoing examples of the method, in one example, the row hammer mitigation comprises a refresh management (RFM) command. According to any of the foregoing examples of the method, in one example, the row hammer mitigation comprises a directed refresh management (DRFM) command. According to any preceding example of the method, in one example, the row hammer mitigation comprises an adaptive refresh management (ARFM) command to the memory device. According to any preceding example of the method, in one example, the memory device comprises a double data rate (DDR) dynamic random access memory (DRAM) device.

[0122] Generally, with respect to the description herein, in one aspect, an article of manufacture includes a computer-readable storage medium having content stored thereon, which, when executed, causes a machine to perform operations to execute a method for performing an alarm signal test, comprising: receiving a command at a memory device to set a bit field of a register to a value to cause the memory device to enter an alarm signal test mode; and in response to entering the alarm signal test mode, asserting an alarm signal on an alarm signal line between the memory device and a memory controller.

[0123] In one example of an article of manufacture, the register comprises a mode register. According to any of the foregoing examples of the article of manufacture, in one example, the command comprises a mode register write (MRW) command. According to any of the foregoing examples of the article of manufacture, in one example, the bit field comprises a write-only bit field that is self-clearing. According to any of the foregoing examples of the article of manufacture, in one example, asserting the alarm signal comprises pulling the alarm signal line to a logic low. According to any of the foregoing examples of the article of manufacture, in one example, asserting the alarm signal comprises asserting the alarm signal within a defined delay period after entering an alarm signal test mode. According to any of the foregoing examples of the article of manufacture, in one example, the defined delay period comprises a maximum delay from receiving the command. According to any of the foregoing examples of the article of manufacture, in one example, the method comprises setting an alarm backoff (ABO) flag in response to asserting the alarm signal. According to any of the foregoing examples of the article of manufacture, in one example, asserting the alarm signal is used to trigger a memory controller to provide row hammer mitigation for a memory device. According to any of the foregoing examples of the article of manufacture, in one example, the row hammer mitigation comprises a refresh management (RFM) command. According to any of the foregoing examples of the article of manufacture, in one example, the row hammer mitigation comprises a directed refresh management (DRFM) command. According to any of the preceding examples of an article of manufacture, in one example, row hammer mitigation comprises adaptive refresh management (ARFM) commands to a memory device. According to any of the preceding examples of an article of manufacture, in one example, the memory device comprises a double data rate (DDR) dynamic random access memory (DRAM) device.

[0124] Flowcharts as shown herein provide examples of sequences of various process actions. Flowcharts may indicate operations to be performed by software or firmware routines as well as physical operations. Flowcharts may illustrate examples of implementations of states of finite state machines (FSMs), which may be implemented in hardware and / or software. Although displayed in a particular sequence or order, the order of actions may be modified unless otherwise specified. Therefore, the figures shown should be understood only as examples, and processes may be performed in different orders, and some actions may be performed in parallel. Additionally, one or more actions may be omitted; therefore, not all implementations will perform all actions.

[0125] To the extent that various operations or functions described herein are concerned, they may be described or defined as software code, instructions, configurations, and / or data. Content may be directly executable ("object" or "executable" form), source code, or differential code ("incremental" or "patch" code). The software content described herein may be provided via a manufactured product storing content, or via a method of operating a communication interface to send data via a communication interface. A machine-readable storage medium may enable a machine to perform the functions or operations, and includes any mechanism for storing information in a form accessible to a machine (e.g., a computing device, an electronic system, etc.), such as a recordable / unrecordable medium (e.g., a read-only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory device, etc.). A communication interface includes any mechanism for engaging with any hardwired, wireless, optical, or other medium to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters and / or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface may be accessed via one or more commands or signals sent to the communication interface.

[0126] The various components described herein may be means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of the two. The components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuit systems, etc.

[0127] In addition to what is described herein, various modifications may be made to the disclosed content and implementation of the present invention without departing from its scope. Therefore, the description and examples herein should be understood in an illustrative rather than a restrictive sense. The scope of the present invention should be measured only with reference to the appended claims.

Claims

1. A memory device, comprising: a register having a bit field for controlling the memory device to enter an alarm signal test mode; a hardware interface to an alert signal line between the memory device and a memory controller; as well as Interface circuitry coupled to the memory controller, the interface circuitry for receiving a command to set the bit field to a value that causes the memory device to enter the alert signal test mode, the memory device asserting the alert signal line with an alert signal in response to entering the alert signal test mode.

2. The memory device according to claim 1, wherein: The registers include a mode register.

3. The memory device according to claim 1, wherein: The commands include a mode register write (MRW) command.

4. The memory device according to claim 1, wherein: The bit field comprises a write-only bit field that is self-clearing.

5. The memory device according to claim 1, wherein: The memory device for asserting the alert signal includes the hardware interface for pulling the alert signal line to a logic low.

6. The memory device according to claim 1, wherein: The memory device asserts the alert signal in response to entering the alert signal test mode within a defined delay period.

7. The memory device according to claim 6, wherein: The defined delay period comprises a maximum delay from receipt of the command.

8. The memory device according to claim 1, wherein: The memory device also sets an alert backoff (ABO) flag in response to asserting the alert signal.

9. The memory device according to claim 1, wherein: Asserting the alarm signal is used to trigger the memory controller to provide row hammer mitigation for the memory device.

10. The memory device of claim 9, wherein: The row hammer mitigation includes a refresh management (RFM) command, a directed refresh management (DRFM) command, or an adaptive refresh management (ARFM) command to the memory device.

11. The memory device of claim 1, wherein: The memory device includes a double data rate (DDR) dynamic random access memory (DRAM) device.

12. A system for memory interface testing, comprising: Alarm signal line; a memory controller coupled to the alert signal line; a memory device coupled to the alarm signal line, the memory device comprising: a register having a bit field for controlling the memory device to enter an alarm signal test mode; as well as Interface circuitry coupled to the memory controller, the interface circuitry for receiving a command to set the bit field to a value that causes the memory device to enter the alert signal test mode, the memory device asserting the alert signal line with an alert signal in response to entering the alert signal test mode.

13. The system according to claim 12, wherein: The registers include a mode register.

14. The system according to claim 12, wherein: The commands include a mode register write (MRW) command.

15. The system of claim 12, wherein: The bit field comprises a write-only bit field that is self-clearing.

16. The system of claim 12, wherein: The memory device for asserting the alert signal includes the memory device for pulling the alert signal line to a logic low.

17. The system of claim 12, wherein: The memory device asserts the alert signal in response to entering the alert signal test mode within a defined delay period, the defined delay period indicating a maximum delay from receiving the command.

18. The system of claim 12, wherein: The memory device also sets an alert backoff (ABO) flag in response to asserting the alert signal.

19. The system of claim 12, wherein: Asserting the alert signal is used to trigger the memory controller to send a refresh management (RFM) command, a directed refresh management (DRFM) command, or an adaptive refresh management (ARFM) command to provide row hammer mitigation for the memory device.

20. The system of claim 12, comprising one or more of the following: a host processor coupled to the memory controller; a display communicatively coupled to the host processor; a network interface communicatively coupled to a host processor; or A battery for powering the system.

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