Deep cavity metallization and reference arrangement for embedded die and assembly thereof on integrated circuit package

Abstract

An electronic package includes: a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer and a plurality of metallization layers including an uppermost metallization layer; an integrated circuit (IC) die embedded within the dielectric material layer and underneath the uppermost metallization layer; and at least one conductive feature underneath and coupled to the IC die. A downwardly facing surface of the conductive feature is on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upward facing surface that faces a direction of the IC die adjacent to the conductive feature, the upward facing surface being vertically offset from the horizontal plane.

Description

Background Art

[0001] A bridge die couples one integrated circuit (IC) die to another IC die on an integrated circuit (IC) package. Some bridge dies are placed in a deep cavity on the IC package so that the bridge die is embedded within the dielectric layer of the package. A bridge die such as an embedded multi-die interconnect bridge (EMIB) with through silicon vias (EMIB-T) has a bottom with electrical pads or contacts to couple to a metallization pattern such as a conductive redistribution layer (RDL) connected to the bottom of the cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The material described herein is illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where deemed appropriate, reference labels are repeated in the drawings to indicate corresponding or similar elements. In the drawings:

[0003] Figure 1 is a schematic cross-sectional view of an example integrated circuit (IC) package having two deep cavity embedded IC dies according to at least one of the embodiments disclosed herein;

[0004] Figure 2 According to at least one embodiment of the embodiments disclosed herein Figure 1 A close-up cross-sectional schematic diagram of an example IC package;

[0005] Figure 3 is a method of manufacturing an IC package according to at least one of the embodiments disclosed herein;

[0006] Figure 4-6 According to at least one of the embodiments disclosed herein Figure 1 A schematic cross-sectional view of an IC package during a manufacturing stage of an IC package;

[0007] Figure 7-9 According to at least one of the embodiments disclosed herein Figure 1 A schematic cross-sectional view of a detailed IC package manufacturing stage of an IC package;

[0008] Fig.10 A device having different types of dies according to at least one of the embodiments disclosed herein Figure 1 A schematic cross-sectional view of a first alternative IC package at a stage of IC package manufacturing;

[0009] Fig.11 A method of manufacturing a device having an underfill protection rail according to at least one embodiment of the embodiments disclosed herein Figure 1 A schematic cross-sectional view of a second alternative IC package at a stage of IC package manufacturing;

[0010] Figure 12-16 According to at least one embodiment of the embodiments disclosed herein, there is a hybrid joint Figure 1 A schematic cross-sectional view of a third alternative IC package at a stage of IC package manufacturing;

[0011] Fig.17 is another method of manufacturing an IC package according to at least one of the embodiments disclosed herein;

[0012] Figure 18-20 According to at least one of the embodiments disclosed herein Fig.17 A schematic cross-sectional view of an example IC package manufacturing stage of a manufacturing method;

[0013] Fig.21 According to at least one embodiment of the embodiments disclosed herein, Fig.17 A top view of an IC package formed by the method;

[0014] Fig. 22 is yet another method of manufacturing an IC package according to at least one of the embodiments disclosed herein;

[0015] Figure 23-25 According to at least one of the embodiments disclosed herein Fig. 22 A schematic cross-sectional view of an example IC package manufacturing stage of a manufacturing method;

[0016] Fig.26 is a schematic cross-sectional view of an example IC package with a fiducial according to at least one of the embodiments disclosed herein;

[0017] Fig. 27 According to at least one of the embodiments disclosed herein Fig.26 A top view of the IC package benchmark;

[0018] Figure 28-31 According to at least one of the embodiments disclosed herein Fig.26 A schematic cross-sectional view of an IC package during a manufacturing stage of an IC package;

[0019] Fig.32 is a functional block diagram of an electronic computing device including an IC package having a deep cavity IC die according to various embodiments herein; and

[0020] Fig.33is a schematic diagram of a mobile computing platform and a data server machine employing an IC package having a deep cavity IC die, according to various embodiments. DETAILED DESCRIPTION

[0021] The embodiments discussed herein variously describe the assembly of an electronic package having a deep cavity arrangement for an embedded die, wherein a significant improvement in assembly efficiency is achieved by using an excimer laser to form a deep cavity and directly expose the metallization in the cavity, thereby omitting many operations previously used to protect the metallization during drilling. The sequence of operations can also provide higher efficiency by performing cavity drilling before placing and / or patterning metallization at the bottom of the cavity. In addition, the fiducials disclosed herein also provide higher precision alignment of lithography, laser, drilling, and / or die attachment at the deep cavity. These deep cavity arrangements are according to various embodiments.

[0022] The technology described herein can be implemented in one or more electronic devices. Non-limiting examples of electronic devices that can utilize the technology described herein include any kind of mobile device and / or fixed device, such as a camera, a cellular phone, a computer terminal, a desktop computer, an e-reader, a fax machine, an information kiosk, a laptop computer, a netbook computer, a notebook computer, an Internet device, a payment terminal, a personal digital assistant, a media player and / or a recorder, a server (e.g., a blade server, a rack-mounted server, a combination thereof, etc.), a set-top box, a smart phone, a tablet personal computer, an ultra-mobile personal computer, a wired telephone, a combination thereof, etc. More generally, the technology described herein can be used for any electronic device in a variety of electronic devices, including the integrated circuit architecture with an integrated circuit package large cavity architecture described herein.

[0023] Embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, it should be understood that this is for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the specification. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein can be used in a variety of other systems and applications, in addition to those described in detail herein. The axes in the figures show the orientation of the cross-sections, and the axes of the first assembly stage in a series of stages apply to all stages unless otherwise specified.

[0024] It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used only to facilitate description of features and relationships between features in the drawings. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the claimed subject matter is defined solely by the appended claims and their equivalents.

[0025] In the following description, many details are set forth. However, it is apparent to those skilled in the art that embodiments can be practiced without these specific details. In some cases, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments.

[0026] References in this specification to "an embodiment" or "one embodiment" or "some embodiments" mean that a particular feature, structure, function, or characteristic described in conjunction with that embodiment is included in at least one embodiment. Therefore, the phrases "in an embodiment," "in one embodiment," or "some embodiments" appearing in various places throughout the specification do not necessarily refer to the same embodiment. In addition, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever the particular features, structures, functions, or characteristics associated with each of the first embodiment and the second embodiment are not mutually exclusive.

[0027] As used in the specification and the appended claims, the singular forms "a", "an", and "the" shall include the plural forms as well, unless the context clearly indicates otherwise. It shall also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0028] The terms "coupled" and "connected" and their derivatives can be used to describe the functional or structural relationship between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in a specific embodiment, "connected" can be used to indicate that two or more elements are in direct physical, optical and / or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in direct or indirect (with other intervening elements) physical, optical or electrical contact with each other, and / or two or more elements cooperate or interact with each other (e.g., in a cause-and-effect relationship).

[0029] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the case of materials, a material or structure disposed above or below another material or structure may be in direct contact or may have one or more intervening materials. Additionally, a material disposed between two materials may be in direct contact with both materials or may have one or more intervening materials. Conversely, a first material or structure that is "above" a second material or structure is in direct contact with the second material / structure. Similar distinctions may be made in the context of component assembly where a first component may be "on" or "over" a second component.

[0030] As used in this specification and claims, a list of items connected by the term "at least one" or "one or more" may refer to any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean: A; B; C; A and B; A and C; B and C; or A, B, and C.

[0031] Here, the term "conductive feature" or "metal feature" may refer to any metal structure within a package that is part of the additional chip circuitry and is typically embedded within the dielectric material of the package. Structures include traces, caps, contacts, and pads within a metallization layer or plane (e.g., within a plane). Also included are vias or posts that form interconnects that interconnect within-plane conductive features within adjacent metallization levels. In this disclosure, "conductive feature" may sometimes be replaced with "metal feature" or just "feature."

[0032] Here, the term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal or data / clock signal.

[0033] The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / -10% of a target value (unless otherwise specified). Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are referenced, and are not intended to imply that the objects described must be in a given sequence, whether in time, space, ranking, or in any other manner.

[0034] Furthermore, chemical compounds without stoichiometric designations are not necessarily limited to 1: 1 amounts. Thus, for example, "FeCo", "FeNi", "SnCuIn", "NiWP" do not imply or limit the compound to having a specific stoichiometry of those elements.

[0035] Deep cavity metallization and fiducial placement for embedded die and their assembly on integrated circuit packages are described herein.

[0036] The redistribution layer (RDL) at the bottom of the deep cavity for the bridge die has conductive metallization to transmit electrical signals and / or electrical power through the bottom of the bridge die. In these arrangements, the bridge die or EMIB-T die (or just EMIB-T) receives signals and / or power and / or provides signals and power to additional dies that are coupled to each other through the EMIB-T.

[0037] The RDL may have a Cu pad inside the deep cavity to establish electrical interconnection between the EMIB-T and the substrate. Forming and protecting the Cu pad in the cavity in a condition to form an interconnection with the EMIB-T is not a trivial task. Conventional lasers such as CO 2000 are used to skive the cavity for die embedding. 2 Lasers have a relatively large, uncontrolled range of varying ablation depths and ablation rates. This can result in too much variation in cavity depth, which can affect the amount of Cu pads and / or contacts exposed at the bottom of the cavity and affect the bond between the cavity pads and the pads on the EMIB-T die. This CO 2 Drilling can result in uncontrolled depth variations of + / - 10-20 microns and can result in undesirably deep trenches, rendering the dielectric layer unusable.

[0038] In this case, although the Cu pad at the bottom of the cavity itself will not be significantly damaged, it is most effective to simply cover the entire bottom of the cavity (including the pad) to provide a laser stop layer or just a laser stop portion so that the CO 2 Or other conventional lasers will not ablate the dielectric layer at the bottom of the cavity. The laser stop can also be a diffusion protection layer, or a diffusion layer covering the Cu pad to reduce the heat reaching the Cu pad, especially if a solder cap is provided on the Cu pad before the cavity is drilled. The combination of the Cu pad and the solder cap is prone to excessive intermetallic compounds (IMC).

[0039] However, the deposition and subsequent removal of the laser stop may involve a large number of manufacturing operations, which can increase costs and increase manufacturing run time. A conventional process for processing the laser stop uses photolithography and involves the following operations: (1) forming a pad that remains at the bottom of the cavity by photolithographic plating of metallization on a dielectric layer on a substrate core; (2) depositing a separation layer on and above the pad by photolithographic plating of a separation layer of a different metal to keep the external laser stop layer independent of the pad so that subsequent etching will not damage the pad; and (3) depositing the laser stop layer on top of the separation layer. Each plating process includes a series of photolithographic operations such as acid cleaning, dry film resist (DFR) and resist stack deposition and patterning, pressing of the DFR, exposure, development, cleaning, plating, and resist stripping to remove the resist. After the cavity is drilled, further photolithographic operations are performed, including etching away the external laser stop layer and the separation plate. The formation and etching operations include wet chemical processes.

[0040] In addition to the above disadvantages, etching will cause residues to adhere to the surface of the pad, which can be challenging and expensive to remove. The residues should be removed because they can reduce the surface area of ​​the connection on the interconnect between the pad and the IC die.

[0041] Furthermore, once the dielectric film is laminated, the depth of the cavity and the height of the via cannot usually be adjusted. The height is largely dependent on the thickness of the dielectric layer, which limits the flexibility of the metallization layout that can be used.

[0042] With regard to aligning EMIB-T (i.e. "die mount") for assembly into a substrate package cavity, it is difficult to perform alignment and / or determine the true positional error between the EMIB-T, substrate RDL, and silicon DIE connections because these entities must span multiple patterned layers. This can be significant because die mount is one of the processes that requires high precision between the pattern on the die and the pads in the cavity to provide a suitable working final product.

[0043] One approach is to simply align the die to the RDL at the bottom of the cavity. However, this can result in significant alignment errors because each subsequent layer above the cavity RDL can continue to be misaligned. This can result in significant differences in the alignment of the topmost surface layer (above the cavity) to the initial cavity RDL layer, especially as each layer adds additional error. This cumulative error is absorbed into the true position error between the EMIB-T and the silicon die.

[0044] By another known approach, each dielectric layer forming the cavity and the area around the cavity can have a fiducial formed by photolithography, laser, or both, and overlapped layer by layer in a top view. Assume that the substrate has layers 1 to 4, where layer 1 is the highest and layer 4 is the lowest. The fabrication can prepare pads inside the deep cavity at layer 2 using alignment fiducials at the lower layer 3. After building layers 1 and 2, the fiducials on layer 2 can be used to align the metallization outside the cavity area. The cavity can then be drilled through layer 1. The die can then also be mounted inside the cavity using the fiducials on layer 1.

[0045] Since the die mounting and pad formation at the bottom of the cavity are built using different fiducials on different layers, this also introduces positional errors. Furthermore, as with the use of the RDL itself as an alignment guide, each additional alignment layer may introduce a certain amount of error due to tool accuracy. Therefore, here too, the use of many layers and components accumulates layer-to-layer offsets and becomes a potential constraint on package size and performance, resulting in large process errors due to different types of misalignment and poor imaging.

[0046] To address many of these issues, a method of manufacturing IC packages includes drilling and milling deep cavities with an excimer laser having good ablation depth and ablation rate control. The dynamic depth control capability of the excimer laser, referred to herein as selective ablation rate or depth, enables the cavity to be drilled to a target depth with a desired accuracy and surface roughness, thereby eliminating or limiting the need for expensive and time-consuming laser stops.

[0047] Specifically, an excimer laser, which is short for "excited dimer laser," is a laser that produces short, high-energy pulses of ultraviolet (UV) light. Excimer lasers use a gain medium that includes a mixture of a rare gas, such as xenon (Xe), krypton (Kr), or argon (Ar), and a halogen gas, typically chlorine (Cl) or fluorine (F). "Excited dimer laser" refers to the excited states of the molecules in this mixture. In the gain medium, the rare gas atoms are in an excited state due to an electrical discharge or other energy input. These excited rare gas atoms can then form temporary molecules (dimers) with halogen atoms, such as XeCl, KrF, or ArF. When these excimer molecules return to their ground state, they release energy in the form of high-energy ultraviolet photons (UV light) due to spontaneous emission. The specific wavelength of the emitted ultraviolet light depends on the choice of the rare gas and halogen used in the mixture. The gain medium is placed in an optical cavity that includes mirrors at each end. One of these mirrors is partially reflective, allowing a small portion of the emitted UV light to pass through, while the rest is reflected back into the gain medium. This creates a resonant cavity in which the light reflects back and forth, stimulating more emission and amplification. Excimer lasers generate extremely short pulses of UV light, typically in the nanosecond (billionth of a second) or even femtosecond (trillionth of a second) range. The short pulse duration is a result of the rapid deexcitation of the excited excimer molecules.

[0048] With respect to package substrate assembly, the excimer laser has a selective ablation depth or laser absorptivity. In other words, the ablation or drilling depth of the excimer laser varies predictably over a wide range of depths depending on the material being drilled. Therefore, metals such as copper, which can reflect most of the incident light, dissipate a lot of heat faster and have a higher melting point, can be ablated only by a negligible (if any) amount (such as less than one micron), while dielectrics, such as a layer of deposited film dielectric material, can be ablated by 15 microns when desired and set to a depth to do so. The depth of excimer ablation can be controlled by setting the number of laser pulses to be used. This is advantageous when the excimer laser can be used to drill a deep cavity for die embedding on a package substrate. The metallization pattern that has been embedded before the cavity is drilled can be exposed by the excimer laser without significantly reducing the height of the metallization pattern or significantly damaging the metallization pattern, while the laser removes the surrounding dielectric material to form the bottom of the deep cavity. All this can be done without the need for a protective laser stop layer covering the metallization pattern.

[0049] The use of excimer and its greater control over ablation depth and selective wear of dielectrics enables a wider range of EMIB-T structures, including more cost-effective fine pitch solutions in cavities. Since this is a dry approach, it is much faster (better operating speed) than wet laser stop technology because it eliminates at least eight pre-drilling operations and two post-drilling operations associated with laser stops, showing great potential for creating and scaling features as needed for next-generation products.

[0050] The use of excimer lasers and EMIB-T also allows flexibility to implement certain alternative substrate arrangements. Thus, for example, different types of embedded dies can be on a single package substrate, such as EMIB and EMIB-T, each in their own cavity.

[0051] In addition, barriers may be placed at the level of the RDL and around other metallization patterns beneath the RDL or embedded IC die and near the periphery of the IC die. The barriers may be used to limit lateral expansion of encapsulant or underfill (such as non-conductive film (NCF) and molded underfill technology, etc.) from between the IC die and the dielectric layer below the IC die.

[0052] By another option, the pads or other conductive features at the bottom of the embedded die and the conductive features or pads in the cavity can be connected by hybrid bonding. The pads in the cavity and on the die can all be within a directly bondable film flash layer around the pads to achieve a better supported direct Cu to Cu bonding interface for potential fine pitch interconnects, z height reduction and Imax improvement.

[0053] A complete package substrate with a die embedded in a cavity drilled by an excimer laser will have different properties at the cross section of the substrate and below the embedded die, which reveals that the cavity drilling was performed by an excimer laser. Specifically, the cavity bottom pads below the IC die and solder have bottom surfaces that engage the dielectric layer below them, and a horizontal plane is formed at the engagement or junction between the pads and the lower dielectric layer (or dielectric material layer). This same plane is the boundary between the lower dielectric layer outside the horizontal periphery of the IC die and the adjacent immediately adjacent higher dielectric layer.

[0054] When an excimer laser is used, the upward-facing surface of the lower dielectric layer (and facing the IC die and underfill) will deviate from the horizontal plane (higher or lower) because it is formed directly by the laser. The surface between the two pads may also be uneven, typically with a middle portion that is at a different height or offset from portions closer to the pads. In contrast, if another laser is used that requires a laser stop in the cavity, the laser stop will be removed by etching after the cavity is drilled, and the etching will not significantly change the dielectric surface of the lower dielectric material layer, which will remain relatively smooth along the horizontal plane.

[0055] By other solutions, the order of the cavity drilling operations can be changed to drill the cavity before the metallization pattern or RDL is plated on the bottom of the cavity. Once the cavity is drilled, a drill can be used to drill a via hole in the bottom of the cavity and expose the interconnect metallization (when present) below the cavity for interconnection with the RDL. With this arrangement, since there will be no etching or dielectric residue on the pad before the die is bonded, the pad will be cleaner, so better bonding between the pad in the cavity and the die is expected. Better bonding in turn can reduce package size, increase data bandwidth, and improve product performance.

[0056] The scheme also provides flexibility in the depth of the cavity and the via at the bottom of the cavity. Usually, the height of the cavity and the via is controlled by the thickness of the stacked dielectric layer, but now the cavity and via height can be adjusted to the desired height by using an excimer laser, because the drilling of the via and the plating of the via and pad at the bottom of the cavity are performed after the drilling of the cavity.

[0057] It should be noted that for this option, the laser that forms the deep cavity does not have to be an excimer laser, and the laser that ablates the via holes does not need to be the same laser that forms the deep cavity.

[0058] By using yet another solution of the previous cavity drilling operation, a metal blanket layer is embedded in the stack of dielectric layers at the level of the bottom of the cavity for forming the RDL or metallization pattern after the cavity is drilled. Thus, in this case, as with the above option, a complete stack of dielectric layers is created. Here, instead of drilling via holes after the cavity is drilled, the embedded blanket layer can first be used as a laser stop to protect the dielectric material under the cavity from being damaged. After the cavity is drilled, the laser stop itself is etched to form the RDL metallization pad at the bottom of the cavity. As a second advantage, when the metal blanket layer plays a protective role, a subsequent etch can be used to remove excess metal on the blanket layer to form the pad. Thus, the process omits wet chemistry and other lithography operations that would be used to create the RDL or metallization pattern at the bottom of the cavity.

[0059] With regard to the reduction of alignment errors, by one solution, the same reference pattern on the uppermost dielectric layer can be used to reduce the photolithography pad plating, laser drilling and / or die mounting alignment errors. In this case, the upper reference or reference pattern is only on the uppermost dielectric layer in the stack of layers to be used to form the deep cavity for die embedding. Therefore, the reference pattern is close to the cavity area, but can also be used to position the metallization of other layers outside the cavity. By one form, the reference pattern includes two circular grooves that can be formed by laser and two metal rings or members that can be formed by photolithography, and both are positioned near the opposite corners of the cavity area.

[0060] This fiducial arrangement greatly improves accuracy by eliminating or reducing multiple layers of fiducials and by using the earlier cavity drilling process described above. Specifically, the metallization of at least one layer below the bottom of the cavity will be plated using other fiducials that are used to plate the rest of the dielectric layer, and the metallization does not need to be near the cavity. Once the higher dielectric layers that will be used to form the deep cavity are deposited, only the upper fiducial or fiducial pattern at the uppermost dielectric layer is required, not the fiducials on the other multiple layers. The upper fiducial can be used to align the drill to drill the cavity, and then align the drill with the buried metallization below the bottom of the cavity so that the via hole is drilled at the bottom of the cavity and drilled to the buried metallization. The upper fiducial can then be used to perform the plating of the metallization pattern or RDL at the bottom of the cavity, and can then be used when the cavity is ready for die mounting.

[0061] By another fiducial option, a deep fiducial can be placed on the same horizontal level as the metallization layer or metallization pattern or portion thereof forming the RDL and at the bottom of the cavity. In particular, deep fiducial grinding techniques can be used to align layers above the cavity RDL to the RDL cavity pattern.

[0062] By way of one example form, a deep fiducial is a circular or curved pad with a through hole to generally form a donut shape. A laser can be used to clear the hole through a keep out zone above the fiducial and form a hole below the fiducial and below the through hole to form a continuous hole with the through hole. This allows the location of the metallization layer to be inferred by using a deep down (multi-layer) fiducial to enable direct alignment with the "deep layers". Once the cavity is drilled, the hole to the deep fiducial can be combined with the cavity so that the deep fiducial is within the cavity before being embedded in close proximity to the attached die.

[0063] Reference now Figure 1-2, the IC package 100 has a package substrate 102 having a substrate base (or core) 104 that divides the substrate 102 into a first or front side 106 and a second (or reverse or back) side 108. The back side 108 may have interconnects to mount the IC package 100 on a board 190, such as a motherboard, host board, and / or printed circuit board (PCB), and by way of one example, is mounted on the board 190 via a second level interconnect (SLI) 192. While the SLI 192 is shown as solder balls, it should be understood that the SLI 192 may be any suitable interconnect architecture, including a socket, etc.

[0064] The front side 102 has a dual die bridge arrangement, where the chip or die including the left die 110 is laterally spaced apart from the middle die 111 in this example, and the left die 110 and the middle die 111 are coupled to each other by a bridge die 114 embedded in a dielectric 116. The middle die 111 is also laterally spaced apart from the right die 112, and the middle die 111 and the right die 112 are coupled to each other by a bridge die 115 also embedded in the dielectric 116 on the front side 106. By one form, the die 114 and 115 are below the uppermost dielectric material layer 156 or at least below the uppermost metallization layer 157. This can include the die 114 or 115 extending completely below those layers 156 and 157, or at least partially below those layers. In this example, the upper die 110, 111, and 112 are located above the dielectric 116. By way of example herein, the bridge die 114 electrically and / or physically couples the left die 110 to the middle die 111 , and the bridge die 115 couples the middle die 110 to the right die 112 .

[0065] It should be understood that the term die refers to an integrated circuit (IC) component or chip that is typically singulated from a wafer and has one or more transistors and / or supporting circuitry that routes electrical signals to the transistors, as well as any other IC components. In addition, die 110, 111, 112, 114, and / or 115 can be a monolithic die, an EMIB (as long as the EMIB has metallization at the bottom of the die), an EMIB-T, or a chiplet as explained below, or any combination of these, and alternatively, any of the upper dies 110, 111, and / or 112 can also be a bridge die. Many variations can be envisioned. By other means, die 114 or 115 may not be in a bridge arrangement, as long as it can be partially embedded in dielectric 116 and have bottom metallization to couple to metallization in the bottom of the deep cavity.

[0066] As for when one of the tube die is one or more core particles, the IC industry is constantly striving to produce higher computing performance in smaller packages for various electronic products, such as computer servers, portable computers, electronic tablets, desktop computers and mobile communication phones. High-performance computing products now typically include one or more microelectronic packages, which contain various combinations of semiconductor tiles, chips, core particles and tube dies integrated into one functional unit. These composite or heterogeneous IC device structures can include tiles, chips, core particles or tube dies created using different technologies and materials. Tiles, chips, core particles or tube dies can be stacked vertically, placed horizontally, or both. The connection between different devices can adopt a variety of technologies, including direct bonding. Core particles, rather than monolithic tube dies, decompose the circuit. Therefore, IC package 100 can have multiple core particles including multiple bridges, of which only two bridges in the bridge are shown here. In this case, core particles 114 or 115 can be communicatively coupled to other tube cores 110, 111 and 112 through interconnects (or bridge interconnects), thereby forming an interconnection bridge between tube cores 110 and 111 or 111 and 112. As mentioned above, tube cores 110, 111 and 112 can also be core particles. However, in one form, tube cores 110, 111 and 112 are monolithic IC tube cores.

[0067] The term "chip" is used herein to refer to a die that is part of an IC package 100 having die 110, 111, and 112, and forms a complete IC in terms of application and / or function herein, such as a memory chip, a microprocessor, a microcontroller, a commodity IC (e.g., a chip for repetitive processing routines, simple tasks, application-specific ICs, etc.), and a system on a chip (SoC). In other words, by way of example, a chip 114 or 115 is an individual die (or IC die) that can be connected together with other chips to create the functionality of a monolithic IC. By using independent chips, each individual chip can be optimally arranged and manufactured for a specific function. In this case, die 110, 111, and 112 may also be chips. For example, a processor core containing logic circuits may be targeted for performance and may therefore require a very speed-optimized layout. This has different manufacturing requirements than a USB controller, which is built to meet certain USB standards rather than for processing speed. Therefore, by separating different parts of the overall arrangement into different core-dices, each core-dice is optimized in terms of design and manufacturing, the overall yield and cost of the combined core-dice solution can be improved.

[0068] The connection between these core particles (or core particles and monolithic IC tube cores) can be achieved in many different ways. For example, in a 2.5D packaging solution, silicon inserts and through-silicon vias (TSVs) connect the tube cores at silicon interconnect speeds with minimal footprint. In another example described herein, EMIB or EMIB-T has a silicon bridge or bridge tube core 114 or 115 embedded under the edges of two interconnected tube cores 110 and 111 or 111 and 112, and facilitates electrical coupling between them. In a three-dimensional (3D) architecture, the core particles are stacked one on top of another, creating a smaller overall footprint, and a multi-layer bridge can be formed. Typically, TSVs and fine-pitch solder-based bumps (for example, C2 interconnects can be used) are used to achieve electrical connections and mechanical coupling in such 3D architectures. EMIB or EMIB-T and 3D stacking architectures can also be combined using omnidirectional interconnect (ODI), which allows the top packaged chip to communicate with other chips horizontally using EMIB or EMIB-T, and vertically using through-mold vias (TMVs) that are typically larger than TSVs.

[0069] In some embodiments using core particles, the composite chip can have a fill dielectric layer above the back end of line (BEOL) metallization stack. Here, the fill dielectric layer near the core particle or bridge die (in addition to the main or body dielectric 116) can completely surround the sidewalls of the core particle, embedding the core particle within the dielectric material, and can be a dielectric or can be a separately molded dielectric adjacent to the dielectric 116. The fill dielectric can stabilize and strengthen the package 100, and / or provide a platform for higher BEOL metallization layers. In some embodiments, the fill dielectric layer for the core particle includes an inorganic dielectric material, such as but not limited to amorphous and polycrystalline silicon oxides, which in some cases have a higher k than the interlayer dielectric (ILD) material. In some other embodiments with core particles, the fill dielectric layer includes an organic material, such as but not limited to epoxies and epoxy composites.

[0070] Returning to the details of substrate 102, substrate base or core 104 may be a substrate structure or layer itself, which may be formed of one or more dielectric layers including glass, metal layers, or a combination of both. The stacking direction is outward from substrate layer 104 and opposite on two sides 106 and 108. Substrate base 104 may be referred to herein as a substrate core.

[0071] The package substrate 102 may include a plurality of laminated dielectric layers with conductive metallization or metallization layers embedded therein. In a specific example embodiment herein, the package substrate 100 may be manufactured in a buildup process (e.g., a bumpless dielectric material layer (BBUL) package), whereby the package substrate 102 is formed by the buildup of various levels, each of which is referred to as a buildup or dielectric material layer, and may have a dielectric film and a metallization plane or layer that is integral with the dielectric film (or in other words, embedded in or on the dielectric film). In this example, and in relation hereto, the front side dielectric 116 has dielectric material layers 150, 152, 154, and 156 having metallization layers 151, 153, 155, and 157, respectively. Looking ahead, the dielectric material layers may be referred to herein simply as dielectric layers. The back side dielectric 118 may also have a dielectric layer. In this article, by way of example, the dielectric layer is formed, for example, by a dielectric buildup film. The dielectric 116 material, as mentioned for the core particles, may include organic materials such as, but not limited to, polymers, epoxies and epoxy composites, ceramics, etc., which may be a molded article or molded layer of a molded resin, such as a polymer resin with an intercalated filler. By other forms, the dielectric 116 may be an inorganic dielectric material such as, but not limited to, amorphous and polycrystalline silicon oxides, which in some cases have a higher k than the interlayer dielectric (ILD) material. The package substrate 102 may also include a glass layer or any other material typical to the electronic packaging architecture. The dielectric 116 may be embedded in or cover all of the dies 110, 111, 112, 114, and 115 when desired, not just the bridge dies 114 and 115.

[0072] The metallization 120 may include metallization planes and vertical interconnects with vias and / or pillars that penetrate dielectric layers on the substrate 100, including metallization extending through the substrate core 104 and within dielectric layers of dielectrics 116 and 118 on the front side 106 and back side 108 including metallization layers 151, 153, 155, and 157. Thus, the metallization may include traces, contacts, pads, caps, pillars, and vias, and include, for example, interconnect vias. The metallization, and by one form, all metallization and conductive features may be formed of copper or an alloy of copper. By other forms, some or all of the metallization may be formed of other conductive materials, other metals, or metal alloys. Otherwise, the arrangement of the pattern of the metallization 120 on the substrate 102 is not particularly limited except for providing a metallization layer having a metallization pattern (which may be an RDL) at the bottom of the deep cavity and for coupling to the bottom of at least one of the embedded die 114 or 115.

[0073] Metallization 120 may include conductive features fabricated by electrodeposited copper (semi-additive process (SAP)) and / or etching through a photoresist mask defined by photolithography (subtractive process). As described below, new layers may be added to both sides by building up the package in a cycle of dielectric film lamination and forming new metallization planes on top of the laminated dielectric films.

[0074] With respect to the example bridge arrangement on substrate 100, and by one form, each die 110, 111, and 112 has its own array of core interconnects (122 on the left, 128 in the middle, and 134 on the right) on the left, middle, and right, respectively. The core interconnects 122, 128, and 134 may have one or more metal or conductive features, including one or more vias, pillars, caps, bumps, pads, etc., and whether the interconnects terminate in the front dielectric 116 or pass through the substrate core 104 to couple to the board 190. In either case, such core interconnects may be provided for interconnection to another IC component, such as a die, chip, device, board, substrate, or other such IC component in or on substrate 102. The core interconnects may be considered to be part of metallization 120. The interconnects 122, 128, and 134 may have any desired arrangement of conductive features as described herein, and are not particularly limited as other portions of metallization 120.

[0075] The bridge die 114, whether a die, EMIB-T, or other die, can communicatively couple the left die 110 to the middle die 111 by using a bridge interconnect (or bridge via) 124 from the top of the bridge die 114 to the left die 110 and a bridge interconnect 126 from the top of the bridge die 114 to the middle die 111. Similarly, the bridge die 115, whether a die, EMIB-T, or other die, can communicatively couple the middle die 111 to the right die 112 by using a bridge interconnect (or bridge via) 130 from the top of the bridge die 115 to the middle die 111 and a bridge interconnect 132 from the top of the bridge die 115 to the right die 112.

[0076] Cavity metallization (or RDL) interconnect (or just cavity or cavity bottom interconnect) 136 for cavity 142 and cavity interconnect 138 for cavity 144 may extend from die 114 or 115, respectively, and extend to bump 192 or simply into dielectric 118. Figure 2 Additional details are provided for the cavity interconnect coupled to the bridge die.The term cavity interconnect is used only to distinguish from the bridge interconnect at the top of the die.

[0077] Dies 114 and 115 may be encapsulated in an encapsulation or embedding layer 178. Encapsulation layer 178 may be a laminate material such as a build-up dielectric material, and may be the same material as dielectric layers 150 to 156. In this case, the sidewalls of cavities 142 and 144 may be visible, or may not be visible. Otherwise, encapsulation layer 178 may be formed of a molding resin used as an underfill, where the underfill is used underneath. Figure 2 For explanation. A solder resist layer 180 over the dielectric or encapsulation layer 178 and an upper bottom filler 182 over the solder resist layer 180 can complete the package substrate 102. By one form, the solder resist 180 can be a mixture of epoxy and acrylic components and typically has a filler such as silicon dioxide to improve its mechanical properties. As an example, the solder resist 180 can have a thickness ranging from 5 microns to 30 microns.

[0078] refer to Figure 2 , a close-up of cavity region 200 with die 115 and cavity 144 is shown, however die 114 and cavity 142 have the same or similar structure and unless otherwise noted, the following description applies to both dies. Die 115 can be an example EMIB-T with TSVs 137 extending through the height of die 115 and coupling upper bridge interconnect 130 to lower cavity interconnect 138. The lower end of TSV 137 can be coupled to a conductive feature such as a die contact, a cap or pad 204, or the like.

[0079] The metallization 120 on the lower dielectric layer 150 has a lower metallization layer 151 that is coupled to (or includes) a metallization pattern 140 below the die 115, which can be an RDL. The metallization pattern 140 can include conductive features, such as a cavity cap or pad 202 on the interconnect 138 and located at the bottom 160 of the cavity 144. The solder bump 206 can couple the cavity pad 202 to the die pad 204 in the interconnect 138 and provide electrical signals and / or power to the metallization on the die 115 or the die 111 and / or 112 above the die 115. The RDL 140 can include or be coupled to multiple lower cavity interconnects 138, five in this example, and these lower cavity interconnects can all be coaxial with the upper bridge interconnects 130 and 132, or not all be coaxial with the upper bridge interconnects 130 and 132. In the example of package 100, any of the illustrated core, bridge, and / or cavity bottom interconnects may have configurations other than that shown with any desired arrangement of posts, post ends, caps, pads, vias, traces, and any other conductive features.

[0080] The conductive features of interconnects 122, 124, 126, 128, 130, 132, 136 and 138 can be formed of copper or other alloys or conductive materials, as described above. Solder balls or bumps (or only solder) 206 and any other bumps herein can be formed of Sn, or can include Sn, such as having SnCu, or can include compounds with In, such as SnIn or SnInCu, but can also be any known solder that is sufficient to form connections on IC die and package substrate. As described below, an alternative omits solder and uses hybrid bonding instead. Bridge interconnects 122, 124, 126, 128, 130, 132, 136 and 138 can also have one or more barrier layers, diffusion barrier layers, IMC barrier layers or other types of layers.

[0081] The bottom filler 208 is located between the tube core 115 and the bottom 160 of the cavity 144 to support the tube core 115 and the solder or solder joint 206. A variety of different bottom fillers 208 can be used. In one form, a capillary bottom filler (CUF) is used, and in this case, the remaining portion of the tube core 115 and above the uppermost dielectric layer 156 can be covered with an additional laminated dielectric layer as an encapsulation layer 178, and the additional laminated dielectric layer can be the same material as the dielectric layers 150 to 156. Alternatively, a pressurized molded resin can be used as both a molded bottom filler (MUF) and an encapsulation material 178. As another alternative, a non-conductive film (NCF) bottom filler can be pre-laminated to the bottom of the tube core 114 and 115 before singulation, and can be an epoxy material or other material. As described in one of the following alternatives, when the package substrate has two or more embedded tube cores, each tube core can have a different bottom fill treatment when desired.

[0082] With respect to the use of an excimer laser and the bottom 160 of the cavity 144, the lower dielectric layer 150 and the immediately adjacent upper dielectric layer 152 define a horizontal plane P at the boundary or junction 162 between the two layers 150 and 152. When the pad 202 is plated or otherwise deposited or formed onto the upper surface 164 of the lower dielectric layer 150, the bottom or downward facing surface 210 of the cavity bottom pad 202 is on plane P, and this does not change even after laser drilling.

[0083] However, in this example, the lower dielectric layer 150 has upward-facing surfaces (or upper surfaces) 212, 214, 216, and 218 (thickened for emphasis), and these surfaces are between adjacent cavity pads 202. The excimer laser will roughen and otherwise ablate the dielectric between the original upper surface 164 and the now-drilled surfaces 212, 214, 216, and 218. As shown, the ablation may extend deeper than plane P, as shown by surfaces 212, 214, and 216, or may stop briefly, as shown by surface 218, where the surface is actually above plane P, so that portions 224 of the immediately higher dielectric layer 152 are not ablated down to plane P. By another form, a single surface 216 between adjacent pads 202 may also have an uneven surface with steps, peaks, or depressions. For example, portions 226 and 228 of surface 216 and portions adjacent to pad 202 are both higher or lower than a middle portion 230 of surface 216. This may be caused by variations in cavity depth as the laser drills due to the processing capabilities of the laser and variations in incident film thickness that are not visible to the laser during processing. By some forms, the resulting offset 220 or 222 of surfaces 212, 214, 216, and / or 218 is at least 1 micron to clearly indicate that the drilling was performed by an excimer laser (or other laser with good ablation depth control), rather than etching by photolithography or any other alternative process to remove dielectric material from cavity 144.

[0084] Furthermore, it should be understood that the structures of any embodiment herein, including bridge and cavity structures, may be disposed on the back side of the substrate core instead of or in addition to being disposed on the front side of the substrate core.

[0085] refer to Figure 3 , an example process 300 for manufacturing an IC package according to at least one embodiment of the present invention is provided. The process 300 includes operations 302 to 314, which are generally numbered evenly and, where appropriate, may be referred to herein. Figure 1-2 An electronic system, device, package and / or package substrate 100 is provided.

[0086] Process 300 may include a "receiving IC package substrate core" 302, which may support a stack or a dielectric layer and a metallization layer. Otherwise, the package substrate core is as described above with respect to Figure 1 Just as described.

[0087] Process 300 may include "stacking a plurality of dielectric material layers from a lower dielectric material layer to an uppermost dielectric layer over a substrate core" 304. Here, dielectric layers may be stacked over the core, including an uppermost dielectric layer, from which a laser enters the stack to drill a cavity. By one form, there are four dielectric layers in the package substrate 102, but any number of dielectric layers may be used as desired. By way of example, dielectric layers may be stacked by repeating a cycle of dielectric layer deposition, laser drilling or etching of via holes, metal plating (such as copper plating) over the holes to form vias, and resist patterning and etching to form pads and / or traces over the vias.

[0088] This operation also includes "placing a lower metallization layer on or in the lower dielectric material layer," 306. The lower metallization layer can be or have a metallization pattern that can have many different arrangements, and can be an RDL that routes power into the die as described above. The metallization pattern can be located on the lower dielectric layer at the bottom of the cavity to be formed. The lower dielectric layer and other dielectric layers can have dielectric materials as described above and metallization layers as described above for substrate 102. The metallization pattern can have conductive features, such as caps, traces, or pads for coupling to the die, and can be provided with or without solder caps before drilling the cavity. For example, the solder can be made of tin or other materials as described above.

[0089] Process 300 may include "drilling a cavity through the uppermost dielectric material layer with an excimer laser" 308. This includes using a laser with good ablation depth and rate control as described above. The operation also includes "exposing the lower dielectric material layer with a laser" 310. The excimer drill can be used to grind a deep cavity down to the metallization pattern pad (or other conductive feature) at the bottom of the cavity. The grinding can be from left to right, layer by layer, or some other motion. The metallization pattern pad at the bottom of the cavity can be slightly altered (ablated or melted) by the laser, but such changes should be negligible. The drill can be set to use a certain number of pulses (which can be determined experimentally) to grind down to the upper surface of the lower dielectric layer, and then ideally to the horizontal plane P, although as described above in conjunction with Figure 2 The small offset described should be the result.Other settings of the excimer laser include pulse intensity (fluence), repetition rate, focus offset and overlap ratio, which can be adjusted together to obtain the desired drilling performance.

[0090] The term "exposing" the lower dielectric layer includes laser ablation into the lower dielectric layer as long as the new upward-facing surface of the lower dielectric layer faces the drilled cavity. This means that drilling can be performed without the need to plate a laser stop layer over the metallization pattern, RDL, and the dielectric bottom of the cavity, thereby significantly reducing the number of operations for cavity drilling and die mounting.

[0091] It should be noted that, by alternative form, the lower metallization layer is considered to be at the bottom of the lower dielectric layer, and the method includes drilling a via hole from the bottom of the cavity, through the lower dielectric layer, and to the lower metallization layer. The via hole is then filled and a pad is formed at the bottom of the cavity to couple the die in the cavity to the lower metallization layer. Figure 22-25 to provide additional details.

[0092] Process 300 may include "coupling an integrated circuit (IC) die to a lower metallization layer in the cavity" 312, where a die (which may be a bridge die), EMIB-T, core, or other type of die, may be attached to the metallization pattern, for example, by solder, although non-solder coupling may also be performed. This operation may also include placing an underfill (such as by capillary action), a molding resin, or an NCF between the die and the metallization pattern and between conductive features in the metallization pattern.

[0093] Process 300 may include "covering the die in dielectric material" 314. The cavity may then be filled or at least partially filled with a dielectric, which may be the same material as the dielectric layer and encapsulate the die, but in addition, may be solder resist, molding resin, or NCF, to name a few. An underfill may be placed under the die as described above. Once the cavity is filled and the die is encapsulated or embedded (or at least partially embedded), the package substrate is ready for stacking more layers on the substrate and / or mounting more dies, such as mounting a die to couple to the top of the now embedded bridge die. It should be understood that when the die is shorter than the cavity height, the dielectric may be completely embedded in the die, but when the die is tall and extends above the uppermost dielectric layer, the dielectric material may or may not be the same or similar material as the stacked dielectric layers disclosed herein, and may fill the space in the cavity between the die and the sidewalls of the cavity. In this case as well, another dielectric layer may be placed on top of the die, which may or may not be the same material as the stacked dielectric layers.

[0094] For more details, refer to Figure 4-6 , shows a process for assembling an IC package according to at least one of the embodiments herein, and in particular, a process for assembling an IC package substrate with an embedded die without using a laser stop to drill a cavity and mount the die. Figure 4-6 The process stages numbered 400 to 600 through multiples of 100 are shown in FIG. 1 as only one example process, and it should be understood that many different process flows may be used to provide such an embedded die interconnect layer as described herein. Figure 7-9 is with Figure 4-6 Similar process, except for the different details in stages 700-900.

[0095] refer to Figure 4 , an IC package substrate intermediate manufacturing stage 400 shows a package substrate 402 having a substrate core 404 and a first or positive side 406, the first or positive side 406 having a dielectric 416, the dielectric 416 having a lower dielectric layer 450, and the lower dielectric layer 450 having a lower metallization layer 451. The lower metallization layer 451 can have a metallization pattern or RDL 440, which will be placed at the bottom of the cavity and coupled to the tube core in the cavity. The metallization can be formed of copper or other materials as described above, and can be plated by a semi-adaptive process (SAP) using a seed layer that is etched later or a subtractive process of etching. Therefore, the metallization pattern (or RDL) 440 and other metallizations such as caps, traces, or pads are formed by using a resist (such as a laminated dry film resist (DFR)) and a mask to shape the resist into a desired pattern. Copper plating is then used to form the metallization pattern (or RDL) 440 of the desired pattern. In this example, the metallization pattern 440 has a pad 408 having a lower or bottom surface 412 located at an upper surface 410 of a lower dielectric layer 450 .

[0096] refer to Figure 5 , and for stage 500, the operations explained above for layer 450 may be repeated for each subsequent dielectric layer 502 and 504 shown here, which adds metallization layer 506 to dielectric layer 502, and where layer 504 is the uppermost dielectric layer. As shown, bottom surface 412 of pad 408 is on boundary or junction 508 between layers 450 and 502, which defines horizontal plane P.

[0097] refer to Figure 6 , stage 600 shows a cavity 604 drilled with an excimer laser or other laser with good ablation rate and depth control. After drilling, cavity 604 is formed with sidewalls 606, which, although not shown, can be tapered, and upper surface 410 now becomes the bottom dielectric surface of cavity 604. Although not visible here, surface 410 will deviate from horizontal plane P, as shown in FIG. Figure 2 The bottom 412 of the pad 408 will remain on the horizontal plane P and in contact with the lower dielectric layer 450 .

[0098] It should be noted that the elements of the substrate are, where possible, Figure 1 The components of the package 100 are similarly numbered, and where the components have been fully described on the package 100, the ... Figure 4-25 This description is not repeated at any stage in the description.

[0099] refer to Figure 7, IC package substrate intermediate manufacturing stage 700 shows a package substrate 702 that is similar to package substrates 102 and 402, so that similar or identical components will not be described again. Here, substrate 702 has all dielectric layers stacked up to the topmost layer ready for laser drilling. A cavity keep-out zone or area 760 is maintained to maintain the metallization from being laser drilled and to maintain the metallization layer of dielectric 716 surrounding the cavity area. Also as shown, at least two cavity areas 760 are arranged for two die pads. Once the cavity is drilled, each cavity area 760 has the lower metallization pattern or RDL 740 and 742 located at the position at the bottom of the cavity, and wherein the metallization patterns 740 and 742 are aligned with the horizontal plane P, as described above in conjunction with Figure 2 and Figure 4-6 described.

[0100] refer to Figure 8 In stage 800, laser drilling is used together with milling to drill through dielectric 716, and cavity drilling results in cavities 802 and 804 that are close to each other. Cavity drilling can be performed by using an excimer laser or other laser as described above, without a laser stop or protective layer, thereby reducing the number of operations to install the die. Metallization patterns 740 and 742 are located at the bottom of cavities 802 and 804, respectively, to receive the die. At this point, the bottom surfaces 806 and 808 of the cavities will now have a characteristic offset relative to plane P, such as Figure 2 shown.

[0101] refer to Fig. 9 , in stage 900, dies 914 and 915 are shown here, such as EMIB-T, core particles, bridge dies, etc., and can be attached to metallization patterns 740 and 742 respectively by coupling to cavity interconnects 736 and 738. Specifically, cavity pads or traces 912 are coupled to die conductive features 910, such as contacts, pads, caps or traces 914 or 915, by solder 906, which can be solder or bridge bumps. Combined with the above Figure 2 Solder 906 is described in detail. Here, flux may be applied to remove oxides and clean the pad surface before the solder is placed in place. Dies 914 and 915 are placed completely or at least partially below the uppermost metallization layer ( Figure 1 157) position as shown in FIG.

[0102] Once the dies 914 and 915 are placed and attached in the respective cavities 802 and 804, the underfill 908 may be inserted (if not already in place), and the encapsulation layer 978 may cover the dies 914 and 915, the cavities 802, 804, and the dielectric 716. Although the encapsulation layer 978 may be the same for both dies 914 and 915, the two dies do not always need to have the same underfill treatment. Many different variations may be used. Thus, for this example, both dies 914 and 915 are EMIB-T attached to the RDLs 740 and 742. In the example shown, the die 914 may not have a separate underfill, and the encapsulation layer 978 may be made of a molding resin material that may be used as an underfill. In this case, the molding resin is pressurized to fill the dielectric 716 (or lower dielectric layer 150 or 450 ( Figure 1 or Figure 4 )) of the bottom fill area below the surface 806. On the tube core 915, a non-conductive film (NCF) can be pre-laminated on the bottom of the tube core 915 and is the bottom fill material. Once the solder is in place, a thermal compression bond can be applied. Otherwise, a capillary action or other type of bottom filler 908 can be placed between the tube core 915 and the surface 808. When using an NCF or capillary action bottom filler, the type of material used for the encapsulation layer 978 is not particularly limited and can be a buildup film, molding resin, solder resist, etc. as with the stacked layers.

[0103] refer to Fig.10 , IC package substrate intermediate manufacturing stage 1000 shows a package substrate 1002 with a substrate core 1004, a first or positive side 1006 with a dielectric 1016, and the dielectric 1016 has a lower dielectric layer 1050. Other elements or components numbered similarly to the elements or components of substrate 102, 402 or 702 are not described here. Stage 1000 shows an alternative arrangement to the arrangement of stages 700 to 900. Here, tube core 1014 is EMIB, there is no metallization for the RDL below tube core 1014, and a bridge interconnect can be attached to the top of tube core 1014. Tube core 1015 is still EMIB-T. In this case, the manufacturing operations for EMIB-T are the same and do not need to be explained again. For EMIB 1014, while the metallization pattern 1040 is also being formed for EMIB-T 1015, a laser stop layer 1060 made of a metal such as copper may be plated on an upper surface 1062 of a lower dielectric layer 1050 at the level of a lower metallization layer 1051. A dielectric layer is then stacked over the lower metallization layer 1051, as in other embodiments already described herein.

[0104] Cavities are then drilled for the two dies 1014 and 1015, the EMIB die cavity 1070 may or may not be drilled with an excimer laser drill, and the cavity 1072 for the EMIB-T is drilled with an excimer laser drill. For the EMIB cavity 1070, drilling may expose the laser stop 1060, but then the laser stop 1060 remains in place because no electrical coupling to the die 1014 is required from or under the laser stop 1060.

[0105] The die 1014 may then be attached and may have a die backside film (DBF) 1064 having an adhesive material pressed against the laser stop 1060 to hold the die 1014 in place. The underfill for the die 1015 has been described above. Thereafter, the encapsulation layer 1078 may be deposited and the package substrate 1002 is ready for subsequent operations to complete the package as already described. The substrate 1000 will have a completed package very similar to the substrate 1002, except that for the EMIB 1014, the laser stop 1060 and DBF layer 1064 and accompanying interconnect and cavity structures replace those for the EMIB-T 114.

[0106] refer to Fig.11 , IC package substrate intermediate manufacturing stage 1100 shows a package substrate 1102 having a substrate core 1104, a first or front side 1106, the first or front side 1106 having a dielectric 1116 having a lower dielectric layer 1150. Layer 1150 may have a metallization layer 1151 having a metallization pattern or RDL 1140 or 1142 to engage the bottom of the die 1114 and 1115, respectively. Other elements or components that are numbered similarly to those of substrates 102, 402, 702, or 1002 are not described again herein.

[0107] Stage 1100 shows an alternative arrangement to stage 900, the arrangement being the same or similar except that both dies may be EMIB-T and may or may not have the same underfill treatment. Also here, retaining members (or barriers) 1160 and 1162 may surround dies 1114 and 1115, respectively, and in particular, metallization pattern 1140 or 1142, respectively. As shown in the close-up inset, an inner surface or wall 1164 of retaining member 1162 engages the laterally outwardly expanding underfill material 1108 to retain the underfill material 1108 between die 1015 and a surface 1166 of the lower dielectric layer 1150. This may occur, for example, when an NCF pre-laminated to the bottom of the die is compressed and expands laterally outward during solder bonding. Members or barriers 1060 and 1062 may be formed of copper and may be rectangular or any other convenient or effective shape surrounding dies 1114 and 1115 and metallization patterns 1140 and 1142. Otherwise, the operations are the same or similar to those of stages 700-900.

[0108] refer to Figure 12-16 , shows an IC package according to at least one embodiment of the present invention, and in particular for assembling an IC package substrate with an embedded die without using a laser stop to drill the cavity and install the die. In this alternative process, hybrid bonding is used. Figure 12-16 The process stages numbered 1200 to 1600 in multiples of 100 are shown as an example process only, and it should be understood that many different process flows may be used to provide such an embedded die interconnect layer as described herein. Figure 1-11 Those items with similar numbering above may be the same or similar items previously described and need not be described again.

[0109] refer to Fig.12 In stage 1200, a lower dielectric layer 1250 is deposited on a substrate core 1204 of a substrate 1202. A lower metallization layer 1251 is provided on the lower dielectric layer 1250. However, in this case, a direct bonding film (DBF) or film flash layer 1260 is patterned and laminated into the metallization layer 1251. Chemical mechanical polishing (CMP) may then be performed to ensure that the metallization at least at the metallization patterns 1240 and 1242 is smooth and has reduced thickness variations. The DBF also acts as an adhesive layer in the final product. Such a DBF may be, for example, polyimide.

[0110] refer to Fig.13, in stage 1300, the remaining dielectric layers and metallization layers with interconnects (from left to right) 1222, 1236, 1228, 1238, and 1234 are stacked as shown and over DBF 1260 to complete dielectric 1316. The total front side dielectric 1216 includes the stack 1316, DBF 1260, and lower dielectric layer 1250 below DBF 1260. The stacking also forms cavity regions 1300 and 1302 without metallization as described in other embodiments herein.

[0111] refer to Fig.14 , excimer laser drilling can be performed as described above in earlier embodiments to form cavities 1470 and 1472 here. The excimer laser can change the surface of the dielectric material 1260 that faces upward and enters the cavity, and here as Figure 2 The height offset can be compensated by controlling the thickness of the DBF layer on the die in combination with process optimization.

[0112] refer to Fig.15 In stage 1500, a singulated die 1514 or 1515 is obtained for mounting and may have a bottom die DBF layer 1560 between die conductive features 1502 such as die pads. DBF 1560 may be the same material as DBF 1260.

[0113] refer to Fig.16 , dies 1514 and 1515 are placed in cavities 1470 and 1472, respectively, and on metallization patterns 1240 and 1242. More specifically, each die pad 1502 is placed directly on pad 1602 of metallization pattern 1240 or 1242. The dielectric adhesive on 1260 is placed directly against the dielectric adhesive on 1560 to promote adhesion of the die to the cavity surface and the Cu 1402 to Cu 1602 hybrid bonding joint by a thermocompression bonding process. The embedded dies 1514 and 1515 are then encapsulated by layer 1604 by a lamination or molding process.

[0114] refer to Figure 17-20 , an example process 1700 for manufacturing an IC package is provided according to at least one embodiment of the present invention, and cavity drilling is performed before a metallization pattern is formed on the bottom of the cavity. The process 1700 includes operations 1702 to 1714, which are generally numbered evenly and, where appropriate, may be referred to herein. Figure 1-2 The electronic system, device, package and / or package substrate 100 of the present invention will also be referred to as Figure 18-20 The process 1700 is described with respect to manufacturing stages 1800 to 2000.

[0115] Process 1700 may include receiving an IC package substrate core 1702 and as described using substrate 102 as an example.

[0116] The process 1700 may include stacking a plurality of dielectric material layers from a lower dielectric layer to an uppermost dielectric material layer over the substrate core 1704. Examples of stacking layers are also described above for the substrate 102, the process 300, and other stages described for other embodiments.

[0117] Process 1700 may include “laser drilling a cavity from an uppermost dielectric material layer to a bottom surface of the cavity at a lower dielectric material layer” 1706, and this may or may not be performed by an excimer laser. 2 Laser) the excimer laser will make the bottom of the cavity level.

[0118] Process 1700 may include "laser drilling a via hole into the bottom of the cavity" 1708, and this may or may not be performed by the same type of laser that drilled the cavity. Fig.18 , stage 1800 shows a cavity 1804 on an intermediate stage substrate 1802 that has been drilled, and an operation for positioning a via hole in the bottom of the cavity 1804 is first performed. In particular, the substrate 1802 has a stack of dielectric layers from a lower dielectric layer N-4 to an uppermost dielectric layer N-1, and has a lower metallization layer 1806 within and on the lower dielectric layer N-4. Prior to forming the cavity 1804, the lower metallization layer 1806 has vias and pads aligned with the location of the cavity 1804. Other dielectric layers may also have metallization or metallization layers, such as vias with pads outside the cavity area. Specifically, layer N-3 has a metallization layer 1808 and forms the bottom 1810 of the cavity 1804. Once the metallization layer 1808 is formed, it will have a metallization pattern at the bottom 1810 of the cavity 1804. Layer N-3 may also have metallization 1812 outside the cavity area and this metallization 182 is part of metallization layer 1808. This metallization 1808 may have a cap plated on the upper surface 1814 of layer N-3 patterned by etching or SAP.

[0119] Once cavity 1804 is drilled, a resist layer such as dry film resist (DFR) 1816 may be deposited over cavity 1804 and over the uppermost dielectric layer N-1. DFR 1816 is then patterned using a mask and photolithography to create holes in DFR 1816 where vias and pads are to be plated. This patterning forms a pattern such as Fig.19 Pad hole 1904 is shown.

[0120] refer to Fig.19In stage 1900, a via is drilled and the via may be drilled by an excimer or other laser. It may be a different laser than that used to drill the cavity. As shown, via hole 1902 is drilled and exposes the metallization at the lower metallization layer 1806.

[0121] The process 1700 then includes placing a via in the hole and placing a via pad on the via and on the bottom surface of the cavity 1710. Fig. 20 , stage 2000 fills or plates metal for via 2002 in via hole 1902 and couples pad 2004 to via 2002. Pad 2004 has a bottom or downward facing surface that engages upward facing surface 1814 of lower layer N-3. By one interpretation, layer N-3 can be a lower dielectric layer with metallized pad 1805, where pad 1805 is on layer N-3, as shown.

[0122] Process 1700 may include "attaching die to via pad" 1712, and as shown in stage 2000, and as described above. With this arrangement, pad 2004 in cavity 1804 will have a different thickness than pad 2006 of metallization 1812 outside the cavity area but in the same metallization layer 1808 as pad 2004. This thickness difference is represented by dimension t, and is due to the cavity pad 2004 being formed by a separate patterned resist that is different from the resist used for plating of pad 2006 before cavity formation. Different techniques may also be used, such as SAP outside the cavity area compared to etching inside the cavity, or vice versa.

[0123] Reference again Figure 18-20 , stages 1800 to 2000 also illustrate the fabrication of fiducial pattern 1840. In this example, fiducial pattern 1840 has trenches 1850 and 1852 into the uppermost dielectric layer N-1 as recessed fiducial marks, which may be circular or other shapes in top view, formed by laser, with one trench on each side of cavity 1804. Trenches 1850 and 1852 may be formed in the same drilling operation as cavity 1804. Trenches 1850 and 1852 are covered by DRF 1816 (stage 1800), which is then patterned by photolithography with holes 1950 and 1952 (stage 1900) to form layers or features 2050 and 2052. Features (or raised fiducial features or marks) 2050 and 2052 may be metallic and plated with the same photolithography process used to form pad 2004 in cavity 1804. Thus, in one form, no additional operations are performed to form reference pattern 1840 .

[0124] refer to Fig.21, the fiducial pattern 1840 has grooves 1850 and 1852 near and outside the opposite corners 2100, 2106 of the cavity 1804, while the members 2050 and 2052 are located at the other opposite corners 2102, 2104 of the cavity 1804. In this example, the members 2050 and 2052 can have an outer annular portion 2054 surrounding a middle pillar portion 2056. The grooves 1850 and 1852 and the members 2050 and 2052 can both have an outer diameter of 100-300 microns, for example, such as for a 4×10 mm tube core 2014 in the top view.

[0125] By one approach, the fiducial pattern is placed only on the uppermost dielectric layer N-1 to avoid multiple layers of fiducials that may cause alignment errors due to the use of different fiducials for die mounting alignment. The lithography or SAP for the metallization 1806 below the cavity 1804 and the metallization layer 1808 laterally outside the cavity 1804 can be placed by using fiducials (not shown here) away from the cavity 1804. The alignment of the metallization 2002, 2004 at the bottom of the cavity 1804 can use the fiducial groove 1850 and the deeper metallization 1806 because the metallization 2002, 2004 at the bottom of the cavity 1804 is placed simultaneously with the raised fiducial 2050. Both the raised and groove fiducials can then be used for die mounting.

[0126] refer to Figure 22-25 , an example process 2200 for manufacturing an IC package is provided according to at least one of the embodiments herein, and a metallization pattern is formed at the bottom of a deep cavity after forming the cavity. The process 2200 includes operations 2202 to 2212, which are generally uniformly numbered and, where appropriate, may be referred to herein. Figure 1-2 The electronic system, device, package and / or package substrate 100 of the present invention will also be referred to as Figure 23-25 Process 2200 is described with reference to manufacturing stages 2300 to 2500.

[0127] Process 2200 may include “receive IC package substrate core” 2202 , and this is the same as described above for process 300 or 1700 .

[0128] Process 2200 may include "placing a lower dielectric layer over a substrate core, the lower dielectric layer having a first layer of conductive material over and coupled to a plurality of independent conductive features" 2204, and this may be explained with stage 2300. Thus, the first layer may be a continuous layer or blanket layer of conductive metal such as copper, and may extend over a plurality of vias, traces, or other independent, distinct conductive features, which may be on independent interconnects, for example. Once placed in an area for drilling a deep cavity, the first layer may serve as a laser stop, and may then be divided into a plurality of independent pads for the plurality of vias or conductive features.

[0129] For example, refer to Fig.23 , in stage 2300, IC package substrate intermediate manufacturing stage 2300 shows a package substrate 2302 having a bottom or lowermost dielectric layer N-4 deposited on a substrate core (not shown), and the lowermost dielectric layer N-4 is deposited by the method explained above for stacking or dielectric layers, which is applicable to any dielectric layer that cooperates to form a body or bulk dielectric on the substrate core. Metallization layer 2306 is plated onto dielectric layer N-4, whether by lithography and etching or by SAP process. Metallization layer 2306 has vias and pads below the location of the future cavity and embedded tube core, and forms at least interconnects, and here are three interconnects 2308, 2310 and 2312.

[0130] Next, a lower dielectric layer N-3 is deposited on layer N-4, and the process repeats to plate a lower metallization layer 2314, which includes a continuous or blanket (or first or laser stop) layer 2316 that extends over and couples to a plurality of interconnects and / or other conductive features below the blanket layer 2316. Interconnects 2308, 2310, and 2312 now extend upward through dielectric layer N-3. At this stage, and blanket layer 2316 extends over and couples to interconnects 2308, 2310, and 2312. Lower dielectric layer N-3 has an upper surface 2318 that is the bottom of the target deep cavity, and the lower dielectric layer is plated on surface 2318. The blanket layer 2316 may have outer dimensions that align with the bottom of the deep cavity to be drilled above the blanket layer 2316. By one form, the blanket layer is used to cover the entire bottom of the planned cavity and may serve as a laser stop. Thus, the blanket layer may have a width greater than 500 microns, and instead of connecting to the top of three interconnects, there may be at least one or more than three interconnects.

[0131] Process 2200 may include stacking multiple layers of dielectric material over first layer 2206, where immediately adjacent dielectric layers N-2 and N-1 are stacked over dielectric layer N-3 and blanket layer 2316. In this example, blanket layer 2316 is now embedded within the dielectric of layer N-2.

[0132] Process 2200 may include "Laser drill a cavity from the uppermost dielectric material layer to the first layer" 2208. Here, a laser is used to drill the cavity, and may or may not be excimer laser drilling, as blanket layer 2316 may be used as a laser stop. As shown in stage 2400 ( Fig.24 ), a cavity 2404 is formed, the dielectric material is removed and the blanket layer 2316 within the cavity 2404 is exposed.

[0133] refer to Fig.24 , process 2200 may include "dividing the first layer between conductive features and dividing it into at least two portions, each portion coupled to at least one different conductive feature of the plurality of independent conductive features" 2210. In stage 2400, this operation first includes depositing a resist layer 2402, such as a dry film resist (DFR), on the opening cavity 2404 and above the uppermost dielectric layer N-1. In particular, the resist 2402 is deposited on the cavity sidewalls 2406 and on the blanket layer 2316.

[0134] The resist 240 is then patterned using a mask and photolithography to create a hole 2410 in the resist 2402 and at the bottom of the cavity 2404, the hole 2410 being the blanket layer 2316 to be etched away so that the remaining portion of the blanket layer 2316 forms a pad 2502 on the metallization layer 2314 ( Fig.25 ) of the metallization pattern or RDL. The etching will also form a protrusion 2504 ( Fig.25 ) leaving metal material or copper underneath (the etchant material will not be able to reach underneath the protrusion 2504).

[0135] refer to Fig.25 , process 2200 may include "attaching a die to the portion" 2212. In stage 2500, as shown, pads 2502 have been plated and resist 2302 stripped. A die 2514, such as an EMIB-T or other type of die, is then mounted on pads 2502, and substrate 2502 may be provided for subsequent operations to complete the package, as described above with respect to other embodiments herein. With this arrangement, the process of forming and dividing blanket layer 2316 eliminates a large number of photolithographic manufacturing operations that would be used to form metallization at the bottom of the deep cavity and then form and remove the laser stop.

[0136] Stages 2300-2500 may also form a reference pattern 1850 ( Figure 18-21 ) the same reference pattern 2550, and the reference pattern 2550 is formed in the same manner as described in the above stages 1800-2000, so that the reference does not need to be described again here.

[0137] refer to Fig.26 , IC package 2600 has a package substrate 2602 having a structure similar to that of substrate 102, so that the details of the basic structure need not be repeated here. Substrate 2602 has a substrate base (or core) 2604, a front side 2606 having a dielectric 2616, and a back side 2608 having a dielectric 2618. The back side can be coupled to a board or host, as described with respect to package 100. Substrate 2602 also has a bridge arrangement having a left die 2610, a right die 2612, and a bridge die 2614 coupling the left die 2610 and the right die 2612 to each other. Bridge die 2614 can be an EMIB-T, a core particle, or other die coupled to metallization 2640 on the bottom of die 2614. By one form, like die 114 on substrate 102 , die 2614 is at least partially embedded beneath an uppermost dielectric layer 2656 or at least beneath an uppermost metallization layer 2657 .

[0138] The bridge arrangement may also have core (or non-bridge) interconnects 2622 and 2628 coupled to the dies 2610 and 2612, respectively, and a bridge interconnect 2624 coupling the bridge die 2614 to the left die 26110 and a bridge interconnect 2626 coupling the bridge die 2614 to the right die 2612. The core interconnects and the die 2614 may be embedded within stacked dielectric layers 2650, 2652, 2654, and 2656 forming a dielectric 2616. The die 2614 may also be coupled to a lower bridge interconnect (or cavity bottom interconnect) 2632 including a metallization pattern, which may be an RDL 2640 and part of a lower metallization layer 2651 of the lower dielectric layer 2650. The metallization pattern 2640 may have a plurality of pads 2631 or other conductive features coupled to die conductive features 2638 (such as contacts, pads, or vias) on the die 2614. In one form, pads 2631 and conductive features 2638 are coupled to each other by solder 2636. Underfill 2634 surrounds interconnect 2632 between die 2614 and upper surface 2660 of lower dielectric layer 2650. A protective or encapsulating layer 2678, such as solder resist or other materials mentioned herein, may be placed over dielectric 2616 and die 2614, while an upper underfill layer 2680 is placed under dies 2610 and 2612 and over encapsulating layer 2670. The materials and configurations for these layers and portions of substrate 2602 have been explained above with respect to substrate 102.

[0139] It is relevant here that the lower metallization layer 2651 has a deep reference pattern 2642, which can be used for alignment during lithography, laser drilling and / or die mounting and other assembly operations. Such a deep position provides direct alignment with the deep layer so that more precise alignment is performed with the layer, and here, for example, alignment is performed with the metallization pattern 2640 to couple to the bottom of the embedded die 2614. Alternatively, when desired, the reference pattern 2642 can be placed at many different layers instead of the lower metallization layer, and can be more than one reference on one or more layers, although this should be limited to avoid alignment errors. By way of example, the reference 2642 is laterally spaced from the die 2614 and can contact the lateral edge of the bottom filler 2634. A keep-out zone (KOZ) 2648 without metallization can be maintained above the reference pattern 2642 until the deep cavity is drilled, and in form, is the entire height of the dielectric 2616 above the reference pattern 2642.

[0140] The fiducial pattern, fiducial mark, or just fiducial 2642 has a first donut-shaped fiducial portion 2644 (although other shapes may be used) and a second fiducial portion 2630 which is a deeper hole below the first portion.

[0141] refer to Fig. 27 In this example, the fiducial 2642 may be annular or donut-shaped in a top view, but may be other curved shapes as well, as sharp angles are often difficult to pattern and are often blurred in captured images of the fiducial. The first donut-shaped portion 2644 has a through hole 2744 at or near the middle of the portion 2644. The second portion or deep hole 2630 may be adjacent to or stepped from the through hole 2744, as long as the through hole and the deep hole 2630 cooperate to form a continuous hole or space.

[0142] Via 2744 and deep hole 2630 are used as ideal references for positioning metal layers, and laser drilling can provide very precise circular openings in dielectric materials such as the dielectric build-up materials described above, which can significantly improve readability because it avoids corners that are difficult to pattern and can result in ambiguity.

[0143] By way of example, the donut portion 2644 may have an outer diameter of 40-310 microns, and the via 2744 (and deep hole 2630) may have a diameter of 30-300 microns. The thickness of the donut portion 2644 may be 3-35 microns, and in one form, may be 15 microns or the same thickness as conductive features such as the metallization layer 2651 and the pad 2631 on the metallization pattern 2640.

[0144] The deep hole 2630 should be drilled as deep as is practical or effective. The deeper the hole, the better the contrast with the metallization and other features in the image, and in turn, the easier it is to read by the imaging tool. By an alternative form, when the deep hole 2630 terminates in a metal layer, the metal layer can have a rough surface 2646, which helps to disperse light for better readability.

[0145] refer to Figure 28-31 , shows a process for assembling an IC package 2600, and in particular, a process for assembling a package substrate 2602 with an embedded die and a deep reference IC, according to at least one of the embodiments herein. Figure 28-31 , the process stages numbered 2800 to 3100 in multiples of 100 are shown as one example process only, and it should be understood that many different process flows may be used to provide such an embedded die interconnect layer as described herein.

[0146] refer to Fig.28 , in stage 2800, IC package substrate intermediate manufacturing stage 2800 shows a package substrate 2802 having a substrate core 2804, a first or front side 2806, the first or front side 2806 having a dielectric 2816, the dielectric 2816 having a first or lower dielectric layer 2850 of a dielectric material described herein. The numbered items on substrate 2802 are similar to those on substrate 2602 ( Fig.26 ) and 102( Figure 1 ) and need not be described in detail again here. Stage 2800 shows that the lower dielectric layer 2850 is drilled and then plated with a lower metallization layer 2851.

[0147] For a semi-additive plating process (SAP), this may include depositing a seed layer, patterning a lithographically defined opening in a photoresist mask, and plating through the opening to construct the conductive features of a metallization layer 2851. The metallization layer 2851 may include a metallization pattern or RDL 2840 to be placed under the deep cavity, and other metallization of the layer 2851 outside the region of the cavity yet to be created. The metallization layer 2851 also includes a deep reference pattern 2842 (as described above with respect to the reference portion 2644) having a metal reference portion 2844, and the metal reference portion 2844 is laterally spaced apart from the metallization pattern 2840 and the region reserved for the die, but still within or immediately adjacent to the cavity region. The added plating pattern for SAP may form the reference portion 2844 into a circular shape. As an optional form, the lithography may then include plating a solder 2836, such as tin, on the metallization pattern 2840. The seed may then be etched. As a form, the resist mask may have an annular opening to plate the reference. Otherwise, the etching pattern may include exposing the middle of the reference portion 2844 to provide a circular through hole to form a donut-shaped body for the reference portion 2844 (eg, Fig. 27 2644).

[0148] refer to Fig.29 , in stage 2900, the remaining dielectric layers 2852, 2854 and the uppermost dielectric layer 2856 are stacked on the lower layer 2850. Metallization layers 2853 and 2855 may be placed, but at this point, the metallization of the uppermost dielectric layer 2856 is not in place. The buildup of the higher dielectric layers 2852 and 2854 and their metallization may be performed using the fiducials 2842 for alignment of the photolithography layers.

[0149] Stage 2900 then shows deep milling drilling being performed, resulting in a reference hole 2902 that passes through the uppermost dielectric layer 2856 and down to the reference portion 2844. In this example, the reference hole 2902 is immediately adjacent to the cavity area 2912 reserved for mounting the die, but outside the cavity area. The laser may also mill into the through hole 2829 on the reference portion 2844 to form a deeper hole portion 2830 of the reference pattern 2842. The metallization below the deep hole 2830 will act as a laser stop. The laser need not be an excimer laser, and may be, for example, a CO 2 or other UV laser. A fiducial hole 2902 is drilled that extends down to the fiducial 2842 to facilitate easier imaging of the fiducial during dielectric layer and metallization lithography and plating.

[0150] Also in stage 2900, after the fiducial holes 2902 are in place, the metallization on the uppermost layer 2856 may be plated. This involves depositing a resist 2904 (and 2906 on the back side), such as a dry film resist, which is deposited to cover the fiducial holes 2902 to prevent any metal or other material from contacting or obstructing the view of the fiducial pattern 2842. Thereafter, vias 2908 may be patterned in the resist to provide locations for vias drilled down to the existing interconnects 2822 and 2828 or other metallization.

[0151] refer to Fig.30 , in stage 3000, the vias and metallization layer 2857 are plated, and the resist 2904 is stripped. Next, the deep cavity 3002 can be drilled, and this can be performed by an excimer laser, although other lasers can be used and, for example, with a laser stop in the cavity. The ablation of the laser is set to be wide enough to ablate the dielectric material between the reference hole 2902 and the cavity area 2912, thereby opening the hole 2902 and adding it as part of the cavity 3002. This causes the area of ​​the upper surface 3006 of the lower dielectric layer 2850 adjacent to the reference pattern 2842 to become part of the bottom surface 3004 of the cavity 3002. However, the reference 2842 can be maintained in a separate hole 2902 rather than within the cavity 3002 itself, and / or can be placed in a different convenient or effective location on the package substrate 2802.

[0152] refer to Fig.31 , in stage 3100, a die 3114 is placed in the cavity to couple the die contacts or conductive features 3138 to the metallization pattern 2840 via solder 2836, and coupled as described above for substrate 2602, 102, or other embodiments herein. Alternatively, a non-solder hybrid bond may be used instead. The die 3114 may then be embedded by a further dielectric, and then the solder resist and upper bottom fill layer under the upper die are coupled to the embedded die 3114, resulting in substrate 2600 ( Fig.26 ). The details of these subsequent operations have been explained using substrates 102 and 2602 and other embodiments herein.

[0153] refer to Fig.32, an electronic computing device 3200 according to at least one embodiment of the device disclosed herein may have a package substrate or motherboard 3202 having multiple components, including but not limited to a processor (e.g., an application processor) 3201. The processor 3201 may be physically and / or electrically coupled to the package substrate or board 3202. In some embodiments, the processor 3201 is within a composite IC chip structure, and the processor 3201 may include a first circuit system having a package substrate and an embedded die, the embedded die being such as a bridge die, an EMIB-T, a core particle, or other die such as described herein. The processor 3201 may be implemented with circuit systems in either or both of the host IC chip and the core particle. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be further stored in registers and / or memory.

[0154] In various examples, one or more communication chips 3204 and 3205 may also be physically and / or electrically coupled to the package substrate or board 3202. In further embodiments, the communication chips 3204 and 3205 may be part of the processor 3201. Depending on its application, the computing device 3200 may include other components that may or may not be physically and electrically coupled to the package substrate or board 3202. These other components include, but are not limited to, volatile memory (e.g., DRAM 3207), non-volatile memory (e.g., ROM 3210), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 3208), graphics processor (CPU) 3212, digital signal processor, cryptographic processor, core 3206, antenna 3216, touch screen display 3217, touch screen controller 3211, battery unit 3218, audio codec, video codec, power amplifier 3209, global positioning system (GPS) device 3213, compass 3214, accelerometer, gyroscope, speaker 3215, camera 3203, and mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), etc.), power supply unit 3219, etc. In some exemplary embodiments, any of the IC structures, architectures, or units described on the device 3200 or in any of the above units may have the above interconnection structure. Thus, for example, in addition to being formed by the circuitry of processor 3201 or a composite IC chip of processor 3201, the die bridged by a second die or die as described herein may also or instead be implemented by electronic memory (e.g., MRAM 3208 or DRAM 3207).

[0155] Communication chips 3204 and 3205 may enable wireless communications for transmitting data to and from computing device 3200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may transmit data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments, the device may not contain any wires. The communication chip 3204 can implement any one of a variety of short-range wireless standards or protocols, including but not limited to Wi-Fi (IEEE 3802.11 series), Bluetooth, etc., and the communication chip 3205 can implement long-range wireless standards or protocols such as WiMAX (IEEE 3802.16 series), IEEE 3802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher versions.

[0156] refer to Fig.33 , the mobile computing platform 3305 and the data server machine 3306 employ IC devices included on the package substrate 3360, as described elsewhere herein. For example, the computing device 100, 2600 and any variant or alternative structure mentioned herein can be found inside the platform 3305 or the server machine 3306. The server machine 3306 can be any commercial server, for example, including any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing, which in an exemplary embodiment includes a structure of at least one IC tube core assembly on the substrate 3360 and is used to embed the bridge tube core, for example, as described elsewhere herein, and can include a core grain bonded to a host IC chip and / or a plurality of tube cores on the package substrate 3360. The mobile computing platform 3305 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 3305 can be any one of a tablet computer, a smart phone, a laptop computer, etc., and can include a display screen (e.g., a capacitive, inductive, resistive or optical touch screen), a chip-level or package-level integrated system 3310, and a battery 3315.

[0157] Whether disposed within the integrated system 3310 shown in the enlarged view 3320, or as a standalone package within the server machine 3306, the composite IC chip 3350 can include a package substrate with an embedded die, which can be a bridge die or a core bonded to multiple dies, such as described elsewhere herein. The composite IC chip 3350 can be further coupled to or on the package substrate 3360, and can include one or more of a power management integrated circuit (PMIC) 3330, an RF (wireless) integrated circuit (RFIC) 3325, and a controller 3335, wherein the RF (wireless) integrated circuit 3325 includes a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband, and the analog front end module further includes a power amplifier on the transmit path and a low noise amplifier on the receive path). The PMIC 3330 can perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to the battery 3315, and has an output that provides current supply to other functional modules. As further shown, in an exemplary embodiment, the RFIC 3325 can have an output coupled to an antenna (not shown) to implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDcPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. Any of these IC units or components on the substrate can include a package substrate with an embedded die, which can be a bridge die, core particle and / or EMIB-T with one or more interconnects to other dies, as described herein.

[0158] It should be understood that the subject matter of this specification is not necessarily limited to Figure 1-33 The present subject matter may be applied to other electronic, microelectronic or integrated circuit (IC) device and assembly applications, as well as any suitable electronic application, as will be appreciated by those skilled in the art.

[0159] The following examples relate to further embodiments. The details in the examples may be used anywhere in one or more embodiments.

[0160] In Example 1, an electronic package includes: a substrate core; one or more dielectric material layers above the substrate core and having a lower dielectric material layer and multiple metallization layers including an uppermost metallization layer; an integrated circuit (IC) die embedded in the dielectric material layer and below the uppermost metallization layer; at least one conductive feature below and coupled to the IC die, wherein a downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer, and wherein the lower dielectric material layer has an upwardly facing surface, the upwardly facing surface faces in the direction of the IC die adjacent to the conductive feature, and the upwardly facing surface is vertically offset from the horizontal plane.

[0161] In Example 2, the subject matter of Example 1 wherein the offset is at least 1 micron.

[0162] In Example 3, the subject matter of Examples 1 or 2, wherein the horizontal plane is further defined by a junction between the lower dielectric material layer and an immediately higher dielectric material layer of the one or more dielectric material layers.

[0163] In Example 4, the subject matter of Example 2 or 3, wherein the upward-facing surface includes two portions adjacent to at least two adjacent conductive features and an intermediate portion between the two adjacent portions, wherein the intermediate portion is offset from the horizontal plane differently than the offset of the adjacent portions.

[0164] In Example 5, the subject matter of any of Examples 1-4, wherein the upper surface is between a plurality of adjacent pairs of the conductive features, and wherein the offset is different between each pair of the conductive features.

[0165] In Example 6, the subject matter of any of Examples 1 to 5, wherein the metallization pattern comprises a redistribution layer (RDL).

[0166] In Example 7, the subject matter of any of Examples 1 to 6, wherein the IC die is a first die and the electronic package includes a plurality of embedded dies, the plurality of embedded dies including at least one second die, the at least one second die having a bottom surface physically adhered to a metal base layer, the metal base layer extending at least the width of the bottom surface of the second die, wherein the first die and the second die are within at least one same dielectric material layer.

[0167] In Example 8, the subject matter of any of Examples 1 to 7, wherein the at least one conductive feature comprises a plurality of conductive features of a metallization pattern, and wherein the electronic package comprises a member extending horizontally around the metallization pattern and having an inner surface that laterally engages a bottom fill material between the IC die and the lower dielectric material layer.

[0168] In Example 9, the subject matter of any of Examples 1 to 8 includes at least one hybrid bond interconnect, wherein the at least one conductive feature is directly connected to at least one die conductive feature at a bottom of the IC die.

[0169] In Example 10, the subject matter of any of Examples 1 to 9, wherein the IC die is at least one of a bridge die, an embedded multi-die interconnect bridge with through silicon vias (EMIB-T), or a die.

[0170] In Example 11, a method for manufacturing an electronic package includes: receiving an IC package substrate core; stacking multiple dielectric material layers above the substrate core and from a lower dielectric material layer to an uppermost dielectric material layer, the stacking including placing a lower metallization layer on or within the lower dielectric material layer; drilling a cavity through the uppermost dielectric material layer with an excimer laser, and including exposing the lower dielectric material layer with the laser; coupling an integrated circuit (IC) die to the lower metallization layer in the cavity; and covering the die with a dielectric material.

[0171] In Example 12, the subject matter of Example 11, wherein the drilling includes exposing a separate plurality of conductive pads of the underlying metallization layer.

[0172] In Example 13, the subject matter of Examples 11 or 12, wherein the ones of the dielectric material layers covering the plurality of conductive pads are in direct contact with the plurality of conductive pads before the cavity is drilled.

[0173] In Example 14, the subject matter of Examples 11 or 12 includes drilling a via hole at the bottom of the cavity and adding a conductive feature in the hole extending upward into the cavity, and wherein the coupling includes coupling the IC die to the lower metallization layer through the conductive feature.

[0174] In Example 15, the subject matter of any of Examples 10 to 14 includes: forming a donut-shaped metal datum, the donut-shaped metal datum being on the lower metallization layer and having a through hole, and wherein the stacking includes depositing an adjacent dielectric material layer above the datum; and prior to drilling the cavity, drilling a first hole from the uppermost dielectric material layer with a laser, the first hole being wide enough to expose at least a portion of the datum, the drilling including drilling through the through hole to form a deeper hole below the datum, and wherein the drilling of the cavity combines the first hole with the cavity so that the datum is disposed within the cavity.

[0175] In Example 16, an electronic system includes: a substrate core; one or more dielectric material layers, above the substrate core and having multiple metallization layers, the multiple metallization layers including an uppermost metallization layer and a lower metallization layer; and an integrated circuit (IC) die, having one or more die conductive features and at least partially embedded in the dielectric material below the uppermost metallization layer, wherein the lower metallization layer includes a plurality of pads, the plurality of pads including: at least one first pad below the IC die and coupled to the die conductive feature; and at least one second pad of the lower metallization layer laterally spaced apart from the IC die, and wherein a thickness of the first pad is different from a thickness of the second pad.

[0176] In Example 17, the subject matter of Example 16, wherein the at least one first pad and the at least one second pad include a plurality of first pads and a plurality of second pads, and the plurality of first pads are thicker than the plurality of second pads.

[0177] In Example 18, the subject matter of Example 16 or 17, wherein the one or more dielectric material layers include a lower dielectric material layer that is lower than the IC die, and wherein the at least one first pad includes a downwardly facing surface that engages the lower dielectric material layer and defines a horizontal plane at a junction between the first pad and the lower dielectric material layer, and wherein the lower dielectric material layer has an upper surface that faces in the direction of the IC die adjacent to the first pad and is vertically offset from the horizontal plane.

[0178] In Example 19, the subject matter of any of Examples 16 to 18 includes a fiducial pattern having a groove extending downward from an upper surface of an uppermost dielectric material layer proximate to the embedded die and a raised metal feature on the upper surface and near the hole, wherein the fiducial pattern is only on the uppermost dielectric material layer.

[0179] In Example 20, the subject matter described in any one of Examples 16 to 19 includes: wherein the one or more dielectric material layers include a lower dielectric material layer having the lower metallization layer, and the system includes a reference pattern at the lower metallization layer, the reference pattern including a first portion and a second portion, the first portion having a donut shape and formed of metal, the donut shape having a vertically extending through hole, the second portion being a deeper hole in the lower dielectric material layer and arranged below the through hole, wherein the through hole and the deeper hole cooperate to provide a continuous hole.

[0180] In Example 21, a method of manufacturing an IC package includes: receiving an IC package substrate core; stacking a plurality of dielectric material layers from a lower dielectric layer to an uppermost dielectric material on top of the substrate core; laser drilling a cavity from the uppermost dielectric material to a bottom surface of the cavity at the lower dielectric material layer; placing a via in the hole and placing a via pad on the via and on the bottom surface of the cavity; and attaching a die to the via pad.

[0181] In Example 22, a method for manufacturing an IC package includes: receiving an IC package substrate core; placing a lower dielectric layer over the substrate core, and the lower dielectric layer has a first layer of conductive material over and coupled to a plurality of independent conductive features; stacking a plurality of dielectric material layers over the first layer; laser drilling a cavity from the uppermost dielectric material layer to the first layer; dividing the first layer between the conductive features and into at least two portions, each of the at least two portions being coupled to at least one different conductive feature of the plurality of independent conductive features; and attaching a die to the portions.

[0182] Although certain features presented herein have been described with reference to various embodiments, this description is not intended to be interpreted in a limiting sense. Therefore, various modifications of the embodiments described herein and other embodiments that are obvious to those skilled in the art to which the present disclosure belongs are considered to be within the spirit and scope of the present disclosure.

Claims

1. An electronic package comprising: one or more dielectric material layers and a plurality of metallization layers over the substrate core, the one or more dielectric material layers having a lower dielectric material layer and the plurality of metallization layers having an uppermost metallization layer; an integrated circuit (IC) die embedded within the dielectric material layer and the metallization layer, the IC die being below the uppermost metallization layer; as well as a conductive feature beneath and coupled to the IC die, wherein a downwardly facing surface of the conductive feature is on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer, and The lower dielectric material layer has an upward facing surface, the upward facing surface faces in the direction of the IC die adjacent to the conductive feature, and the upward facing surface is vertically offset from the horizontal plane.

2. The electronic package according to claim 1, wherein: The offset is at least 1 micron.

3. The electronic package according to claim 1, wherein: The horizontal plane is also defined by a junction between the lower dielectric material layer and an immediately higher dielectric material layer of the one or more dielectric material layers.

4. The electronic package according to any one of claims 1 to 3, wherein: The upwardly facing surface includes two portions adjacent to at least two adjacent conductive features and an intermediate portion between the two adjacent portions, the intermediate portion having an offset from the horizontal plane that is different than an offset from the adjacent portions.

5. The electronic package according to any one of claims 1 to 3, wherein: The upward facing surface is between adjacent pairs of the conductive features, and wherein the offset is different between each pair of the conductive features.

6. The electronic package according to any one of claims 1 to 3, wherein: The metallization layer includes a redistribution layer (RDL).

7. The electronic package according to any one of claims 1 to 3, wherein: The IC die is a first IC die, and the electronic package includes a plurality of embedded IC die, the plurality of embedded IC die including at least one second IC die, the at least one second IC die having a bottom surface physically adhered to a metal base layer, the metal base layer extending at least the width of the bottom surface of the second IC die, wherein the first IC die and the second IC die are within at least one same dielectric material layer.

8. The electronic package according to any one of claims 1 to 3, wherein: The conductive features include a plurality of conductive features of a metallization pattern, and wherein the electronic package includes a member extending horizontally around the metallization pattern and having an inner surface that laterally engages an underfill material between the IC die and the lower dielectric material layer.

9. The electronic package according to any one of claims 1 to 3, further comprising at least one hybrid bonding interconnect, wherein: At least one of the conductive features is directly connected to at least one conductive feature at the bottom of the IC die.

10. The electronic package according to any one of claims 1 to 3, wherein: The IC die is at least one of a bridge die, an embedded multi-die interconnect bridge with through silicon vias (EMIB-T), or a die.

11. A method of manufacturing an electronic package, comprising: stacking a plurality of dielectric material layers and a plurality of metallization layers over the IC package substrate core, wherein the stacking forms a lower dielectric material layer to an uppermost dielectric material layer and placing a lower metallization layer on or within the lower dielectric material layer; drilling a cavity through the uppermost dielectric material layer with an excimer laser and exposing the lower dielectric material layer with the laser; coupling an integrated circuit (IC) die to the lower metallization layer in the cavity; and The IC die is covered with a dielectric material.

12. The method according to claim 11, wherein: The drilling includes exposing a separate plurality of conductive pads of the lower metallization layer.

13. The method according to claim 12, wherein: One of the dielectric material layers covering the plurality of conductive pads is in direct contact with the plurality of conductive pads before the cavity is drilled.

14. The method of any one of claims 11 to 13, further comprising drilling a via hole at the bottom of the cavity and forming a conductive feature in the hole extending upwardly into the cavity, and wherein, The coupling includes coupling the IC die to the lower metallization layer through the conductive features.

15. The method according to any one of claims 11 to 13, further comprising: forming a donut-shaped metal fiducial on the lower metallization layer and having a via, and wherein the stacking includes depositing a dielectric material layer immediately above the fiducial; and Prior to drilling the cavity, laser drilling a first hole from the uppermost dielectric material layer, the first hole being wide enough to expose at least a portion of the fiducial, the drilling comprising drilling through the via to form a deeper hole below the fiducial, and wherein the drilling of the cavity combines the first hole with the cavity such that the datum is disposed within the cavity.

16. An electronic system comprising: one or more dielectric material layers and a plurality of metallization layers over the substrate core, the plurality of metallization layers including an uppermost metallization layer and a lower metallization layer; as well as an integrated circuit (IC) die having one or more die conductive features and at least partially embedded within the dielectric material beneath the uppermost metallization layer, Wherein, the lower metallization layer includes a plurality of pads, and the plurality of pads include: at least one first pad below the IC die and coupled to the conductive features of the die; and at least one second pad laterally spaced apart from the IC die, wherein the thickness of the first pad is different from the thickness of the second pad.

17. The system of claim 16, wherein: The at least one first pad and the at least one second pad include a plurality of first pads and a plurality of second pads, and the plurality of first pads are thicker than the plurality of second pads.

18. The system of claim 16, wherein: The one or more dielectric material layers include a lower dielectric material layer lower than the IC die, and wherein the at least one first pad includes a downwardly facing surface that engages the lower dielectric material layer and defines a horizontal plane at a junction between the first pad and the lower dielectric material layer, and The lower dielectric material layer has an upper surface, the upper surface faces the direction of the IC die adjacent to the first pad, and the upper surface is vertically offset from the horizontal plane.

19. The system of any one of claims 16 to 18, further comprising a fiducial pattern having grooves extending downwardly from an upper surface of the uppermost dielectric material layer proximate to the embedded die, and a raised metal feature on the upper surface and proximate to the hole, wherein The reference pattern is only on the uppermost dielectric material layer.

20. The system according to any one of claims 16 to 18, wherein: The one or more dielectric material layers include a lower dielectric material layer including the lower metallization layer, and the system also includes a reference pattern at the lower metallization layer, the reference pattern including a first portion and a second portion, the first portion having a donut shape and formed of metal, the donut shape having a vertically extending through-hole, the second portion being a deeper hole in the lower dielectric material layer and arranged below the through-hole, wherein the through-hole and the deeper hole cooperate to provide a continuous hole.

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