Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to solve the problem of poor dynamic characteristics of the semiconductor device. The semiconductor device includes a substrate, a barrier layer, a cap layer, a first passivation layer, an anti-oxidation layer, and a second passivation layer. The barrier layer is arranged on the substrate. The cap layer is located on the side, away from the substrate, of the barrier layer. The first passivation layer is located on the side, away from the substrate, of the barrier layer. The anti-oxidation layer is located on the side, away from the substrate, of the first passivation layer. And the second passivation layer is located at one side, far away from the substrate, of the anti-oxidation layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride (GaN) materials, as third-generation semiconductor materials, are widely used in various fields due to their wide bandgap, high power density, stable chemical properties, etc. Semiconductor devices, namely gallium nitride high electron-mobility transistors (HEMTs), have the advantages of small chip area, low switching loss, fast operating speed, high conversion efficiency, and high power density. In the field of power electronics, they can further improve the efficiency of power electronic systems, reduce their size, and reduce manufacturing costs.

[0003] Gallium nitride materials in semiconductor devices, such as the barrier layer, have damage and dangling bonds on their surfaces, which lead to the generation of surface states and thus the formation of surface charge traps, affecting the electrical properties of the semiconductor devices. Severe cases may even cause current collapse and other problems. Therefore, during the preparation of semiconductor devices, a passivation layer is often formed on the surface of the semiconductor devices to improve electron mobility, conductivity and suppress surface leakage current.

[0004] However, after the passivation layer is formed, the dynamic characteristics of the semiconductor device deteriorate to a certain extent, such as the dynamic resistance deteriorates. Therefore, an improved semiconductor device is expected to solve the above technical problems. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to solve the problem of poor dynamic characteristics of the semiconductor device.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a semiconductor device is provided, comprising a substrate, a barrier layer, a cap layer, a first passivation layer, an anti-oxidation layer and a second passivation layer. The barrier layer is disposed on the substrate. The cap layer is located on a side of the barrier layer away from the substrate. The first passivation layer is located on a side of the barrier layer away from the substrate. The anti-oxidation layer is located on a side of the first passivation layer away from the substrate. The second passivation layer is located on a side of the anti-oxidation layer away from the substrate.

[0008] During the preparation of the semiconductor device, after the first passivation layer is formed, an anti-oxidation layer is formed on the side of the first passivation layer away from the substrate, which can prevent the first passivation layer from being oxidized during the waiting time to form an oxide film, thereby improving the dynamic characteristics of the semiconductor device while ensuring the passivation effect.

[0009] In a feasible embodiment, the thickness uniformity of the first passivation layer is less than or equal to 1%; the thickness uniformity of the anti-oxidation layer is less than or equal to 1%.

[0010] The first passivation layer and the anti-oxidation layer are formed by the same process, for example, both are formed by atomic layer deposition process, so that both the first passivation layer and the anti-oxidation layer have good thickness uniformity, which can avoid the degradation of electrical performance of the semiconductor device due to uneven thickness of the barrier layer including aluminum gallium nitride.

[0011] Furthermore, the first passivation layer and the anti-oxidation layer are formed by the same process, so that the two can be formed in the same machine, thereby preventing the first passivation layer from being oxidized during the waiting time after the first passivation layer is formed, thereby improving the electrical performance of the semiconductor device, including dynamic characteristics.

[0012] In a feasible embodiment, the material of the anti-oxidation layer includes silicon nitride.

[0013] In a feasible embodiment, the semiconductor device further includes a transition layer, and the transition layer is located between the first passivation layer and the anti-oxidation layer.

[0014] The transition layer can slowly change the stress of each film structure of the semiconductor device to achieve a gradual stress change. The transition layer adjusts the stress of the first passivation layer, the anti-oxidation layer and the second passivation layer to achieve a better passivation effect. At the same time, the adjustment of the stress by the transition layer can also adjust the piezoelectric polarization effect of the heterojunction interface formed by the channel layer and the barrier layer, and change the concentration of the two-dimensional electron gas, thereby improving the current driving capability of the semiconductor device and enhancing the electrical characteristics, stability and reliability of the semiconductor device.

[0015] By adjusting the piezoelectric polarization effect at the heterojunction interface formed by the channel layer and the barrier layer, the threshold voltage of the semiconductor device can be fine-tuned to make it closer to the design target and meet the needs of practical applications.

[0016] In a feasible embodiment, the material of the transition layer includes aluminum silicon nitride.

[0017] In a feasible embodiment, the sum of the thickness of the transition layer and the anti-oxidation layer is greater than or equal to 1 nanometer and less than or equal to 200 nanometers.

[0018] In a feasible embodiment, the sum of the thicknesses of the transition layer and the anti-oxidation layer is greater than or equal to 1 nanometer and less than or equal to 5 nanometers.

[0019] By controlling the sum of the thickness of the transition layer and the anti-oxidation layer within the range of 1 nm to 5 nm, the time required for forming the transition layer and the anti-oxidation layer can be shortened while ensuring the quality of the passivation layer, which is beneficial to improving production efficiency.

[0020] In a feasible embodiment, the material of the anti-oxidation layer includes aluminum silicon nitride.

[0021] In a feasible embodiment, the material of the second passivation layer includes silicon oxide or silicon nitride.

[0022] In a feasible embodiment, the thickness of the anti-oxidation layer is greater than or equal to 1 nanometer and less than or equal to 200 nanometers.

[0023] In a feasible embodiment, the semiconductor device further comprises a buffer layer, a channel layer, a gate, a source and a drain. The buffer layer is located between the substrate and the barrier layer. The channel layer is located between the buffer layer and the barrier layer. The gate is located on the side of the cap layer away from the substrate and penetrates the second passivation layer, the anti-oxidation layer and the first passivation layer. The source and the drain are located on the side of the barrier layer away from the substrate and penetrate the second passivation layer, the anti-oxidation layer and the first passivation layer, and the source and the drain are respectively located on opposite sides of the gate.

[0024] On the other hand, a chip is provided. The chip includes a packaging substrate and the above-mentioned semiconductor device, wherein the packaging substrate is coupled to the semiconductor device.

[0025] On the other hand, an electronic device is provided. The electronic device includes a circuit board and the above chip, wherein the chip is arranged on the circuit board.

[0026] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming a barrier layer and a cap layer in sequence on a substrate; forming a first passivation layer on a side of the barrier layer away from the substrate; forming an anti-oxidation layer on a side of the first passivation layer away from the substrate; forming a second passivation layer on a side of the anti-oxidation layer away from the substrate; wherein the first passivation layer and the anti-oxidation layer are both formed by an atomic layer deposition process.

[0027] After forming the first passivation layer, continuing to form an anti-oxidation layer in the same machine can avoid surface oxidation of the first passivation layer caused by vacuum breaking of the semiconductor structure, improve the quality and passivation effect of the formed first passivation layer, and thus enhance the dynamic characteristics of the semiconductor device.

[0028] In a feasible embodiment, the first passivation layer and the anti-oxidation layer are formed in the same reaction chamber.

[0029] After forming the first passivation layer, continuing to form the anti-oxidation layer in the same chamber of the same machine can shorten the exposure time of the first passivation layer, improve the quality of the formed first passivation layer and the anti-oxidation layer, and thus enhance the dynamic characteristics of the semiconductor device.

[0030] In a feasible embodiment, between forming the first passivation layer on the side of the barrier layer away from the substrate and forming the anti-oxidation layer on the side of the first passivation layer away from the substrate, the method further includes: forming a transition layer on the side of the first passivation layer away from the substrate. The first passivation layer, the transition layer and the anti-oxidation layer are all formed by an atomic layer deposition process.

[0031] After forming the first passivation layer, continuing to form a transition layer and an anti-oxidation layer in the same machine can avoid surface oxidation of the first passivation layer caused by vacuum breaking of the semiconductor structure, improve the quality and passivation effect of the formed first passivation layer, and thus enhance the dynamic characteristics of the semiconductor device.

[0032] In a feasible embodiment, the first passivation layer, the transition layer and the anti-oxidation layer are formed in the same reaction chamber.

[0033] In a feasible embodiment, the second passivation layer is formed by a plasma enhanced chemical vapor deposition process, and is formed in a different reaction chamber from the first passivation layer.

[0034] It can be understood that the beneficial effects that can be achieved by the method for preparing a semiconductor device and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0036] Figure 1 A structural diagram of an electronic device provided according to some embodiments;

[0037] Figure 2 A structural diagram of a chip provided according to some embodiments;

[0038] Figure 3 A structural diagram of a semiconductor device provided according to some embodiments;

[0039] Figure 4 A structural diagram of another semiconductor device provided according to some embodiments;

[0040] Figure 5 A structural diagram of another semiconductor device provided according to some embodiments;

[0041] Figure 6 A flowchart of a method for preparing a semiconductor device according to some embodiments;

[0042] Figure 7A flowchart of another method for preparing a semiconductor device according to some embodiments;

[0043] Figures 8 to 19 A structural diagram of a semiconductor device corresponding to each step in the preparation method;

[0044] Fig. 20 A flowchart of another method for preparing a semiconductor device according to some embodiments;

[0045] Figure 21 to Figure 23 It is a structural diagram of the semiconductor device corresponding to each step in the preparation method. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0047] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0053] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0054] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0055] The technical terms in the embodiments of the present application are described as follows:

[0056] Semiconductor: A semiconductor is a material whose electrical conductivity is between that of a conductor and an insulator at room temperature; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, whose internal electron and hole concentrations are equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or a non-intrinsic semiconductor. Among them, the impurities doped into the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, where the impurity semiconductor doped with impurities that provide electrons (such as 5-valent phosphorus elements) is also called an electron-type semiconductor or an N (negative) type semiconductor, and the impurity semiconductor doped with impurities that provide holes (such as 3-valent boron elements) is also called a hole-type semiconductor or a P (positive) type semiconductor), which can improve the conductivity of the intrinsic semiconductor. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of the present application, this type of impurity semiconductor is also called a conductive semiconductor. For example, the conductive silicon carbide material is doped with impurities such as nitrogen N, boron B, aluminum Al, etc. In addition, when the impurities doped into the impurity semiconductor can compensate for the impurities of the impurity semiconductor, the donor electrons are just enough to fill the acceptor energy level, but cannot provide electrons and holes to the conduction band and the valence band, so that the semiconductor material with a wider bandgap has a resistivity close to that of an insulator. For example, in the embodiment of the present application, the silicon carbide material is doped with a transition metal to achieve impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating properties.

[0057] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0058] Figure 1 FIG. 1 is a structural diagram of an electronic device provided according to some embodiments. Figure 1 As shown, the embodiment of the present disclosure provides an electronic device 1, which can be a product or component with power conversion function such as a power conversion system of an electric vehicle, a charging device of a mobile phone, a power adapter device of a laptop computer, etc. The electronic device 1 can also be different types of user equipment or terminal equipment such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and a vehicle-mounted device, or a power amplification device used in the above electronic equipment. It should be understood that the electronic device 1 can also be a device or component with signal receiving / transmitting function in equipment such as an amplifier, a modulator, a base station, a radar, etc., and the embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1.

[0059] In the following, some embodiments of the present disclosure are schematically described by taking the electronic device 1 as an electronic device having a power conversion function as an example, but the implementation of the present disclosure is not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0060] exist Figure 1 In the embodiment, the electronic device 1 includes, for example, a chip 10 and a circuit board 20. The chip 10 is disposed on the circuit board 20, and the circuit board 20 is configured to supply power to the chip 10 and transmit signals. Figure 2 , Figure 2 FIG. 1 is a structural diagram of a chip according to some embodiments. The chip 10 includes a semiconductor device 100 and a package substrate 300 , and the semiconductor device 100 is coupled to the package substrate 300 .

[0061] Figure 3 The semiconductor device 100 includes a substrate 111 , a buffer layer 112 , a channel layer 113 , a barrier layer 114 , a source 120 , a gate 131 , a cap layer 132 , a drain 140 , a first passivation layer 151 , and a second passivation layer 154 .

[0062] The substrate 111, the buffer layer 112, the channel layer 113 and the barrier layer 114 are stacked in sequence. The gate 131 is located on the side of the barrier layer 114 away from the substrate 111, and the cap layer 132 is located between the gate 131 and the barrier layer 114. The source 120 and the drain 140 are located on the side of the barrier layer 114 away from the substrate 111, and are located on opposite sides of the gate 131 respectively.

[0063] Exemplarily, the substrate 111 may be at least one selected from silicon, silicon carbide, gallium nitride, sapphire, and diamond.

[0064] The buffer layer 112 is located on one side of the substrate 111 . Exemplarily, the buffer layer 112 may be one or more of gallium nitride, aluminum nitride, and aluminum gallium nitride (AlGaN).

[0065] The channel layer 113 is located on a side of the buffer layer 112 away from the substrate 111 . Exemplarily, the material of the channel layer 113 includes a non-intentionally doped gallium nitride layer.

[0066] The barrier layer 114 is located on the side of the channel layer 113 away from the substrate 111. Exemplarily, the material of the barrier layer 114 includes at least one of aluminum nitride and aluminum gallium nitride. In some feasible embodiments, the barrier layer 114 can also be selected from other binary, ternary, and quaternary nitrides.

[0067] The channel layer 113 and the barrier layer 114 contact to form a heterojunction interface. Due to the spontaneous polarization effect and piezoelectric polarization effect of the heterojunction, there is a large potential well at the heterojunction interface. In this structure, electrons are confined at the interface between the channel layer 113 and the barrier layer 114, thereby inducing a high-density two-dimensional electron gas (2DEG) on the side of the channel layer 113 close to the barrier layer 114.

[0068] In some feasible embodiments, the semiconductor device 100 further includes a nucleation layer, which is located between the substrate 111 and the buffer layer 112, and the material of the nucleation layer may include at least one of aluminum nitride, gallium nitride and aluminum gallium nitride. Exemplarily, the nucleation layer buffer layer 112 may be a nitride film.

[0069] In some feasible embodiments, the semiconductor device 100 further includes an insertion layer, which is located between the channel layer 113 and the barrier layer 114 and whose material may be aluminum nitride. The insertion layer can improve the heterojunction interface quality, reduce scattering, and improve electron mobility, and can also improve conduction band discontinuity, thereby increasing the density of the two-dimensional electron gas 301 and improving the performance of the semiconductor device.

[0070] In some feasible embodiments, the gate 131 may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials.

[0071] The first passivation layer 151 is located on a side of the barrier layer 114 away from the substrate 111, the second passivation layer 154 is located on a side of the first passivation layer 151 away from the substrate 111, the source 120 and the drain 140 penetrate the first passivation layer 151 and the second passivation layer 154 respectively to contact the barrier layer 114. The first passivation layer 151 and the second passivation layer 154 partially cover the cap layer 132, and the gate 131 penetrates the first passivation layer 151 and the second passivation layer 154 to contact the cap layer 132.

[0072] Exemplarily, the material of the first passivation layer 151 includes aluminum nitride, and the material of the second passivation layer 154 includes at least one of silicon oxide and silicon nitride.

[0073] The first passivation layer 151 and the second passivation layer 154 can prevent corrosion, mechanical damage, etc. caused by external factors, and can also optimize the electrical performance of the semiconductor device 100, improve leakage current, and increase breakdown voltage, thereby improving the stability and reliability of the semiconductor device 100. However, in the semiconductor device 100 including the first passivation layer 151 and the second passivation layer 154, its dynamic characteristics will deteriorate. The inventors have analyzed and found that in the preparation process of the semiconductor device 100, there is a waiting time Qt ime after the first passivation layer 151 is formed and before the second passivation layer 154 is deposited. During this period of time, the surface of the first passivation layer 151 will be oxidized, generating an oxide film of poor quality, thereby affecting the dynamic characteristics of the semiconductor device 100. In view of this, the present application provides a semiconductor device, such as Figure 4 shown.

[0074] Figure 4 The semiconductor device 100 includes a substrate 111 , a buffer layer 112 , a channel layer 113 , a barrier layer 114 , a source 120 , a gate 131 , a cap layer 132 , a drain 140 , a first passivation layer 151 , an anti-oxidation layer 153 , and a second passivation layer 154 .

[0075] The substrate 111, the buffer layer 112, the channel layer 113 and the barrier layer 114 are stacked in sequence. The gate 131 is located on the side of the barrier layer 114 away from the substrate 111, and the cap layer 132 is located between the gate 131 and the barrier layer 114. The source 120 and the drain 140 are located on the side of the barrier layer 114 away from the substrate 111, and are located on opposite sides of the gate 131 respectively.

[0076] The first passivation layer 151 is located on the side of the barrier layer 114 away from the substrate 111, the anti-oxidation layer 153 is located on the side of the first passivation layer 151 away from the substrate 111, and the second passivation layer 154 is located on the side of the anti-oxidation layer 153 away from the substrate 111. The source 120 and the drain 140 penetrate the first passivation layer 151, the anti-oxidation layer 153 and the second passivation layer 154 respectively to contact the barrier layer 114. The first passivation layer 151, the anti-oxidation layer 153 and the second passivation layer 154 partially cover the cap layer 132, and the gate 131 penetrates the first passivation layer 151, the anti-oxidation layer 153 and the second passivation layer 154 to contact the cap layer 132.

[0077] In some feasible embodiments, the material of the anti-oxidation layer 153 includes silicon nitride.

[0078] In some feasible embodiments, the material of the anti-oxidation layer 153 includes aluminum silicon nitride.

[0079] During the preparation process of the semiconductor device 100, after the first passivation layer 151 is formed, an anti-oxidation layer 153 is formed on the side of the first passivation layer 151 away from the substrate 111, which can prevent the first passivation layer 151 from being oxidized to form an oxide film during the waiting time Qt ime, thereby improving the dynamic characteristics of the semiconductor device 100 while ensuring the passivation effect.

[0080] In some feasible embodiments, the first passivation layer 151 and the anti-oxidation layer 153 are formed by the same process, for example, both are formed by the atomic layer deposition (ALD) process, so that the first passivation layer 151 and the anti-oxidation layer 153 have good thickness uniformity, and the thickness uniformity of the first passivation layer 151 and the anti-oxidation layer 153 is, for example, less than or equal to 1%. The good thickness uniformity of the first passivation layer 151 and the anti-oxidation layer 153 can avoid the degradation of the electrical performance of the semiconductor device 100 due to the uneven thickness of the barrier layer 114 including aluminum gallium nitride. Exemplarily, the thickness uniformity of the first passivation layer 151 and the anti-oxidation layer 153 is less than or equal to 0.5%.

[0081] In some feasible embodiments, the thickness of the anti-oxidation layer 153 is greater than or equal to 1 nm and less than or equal to 200 nm. Exemplarily, the thickness of the anti-oxidation layer 153 is greater than or equal to 1 nm and less than or equal to 5 nm.

[0082] The thickness of the anti-oxidation layer 153 may be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 50 nm, 100 nm, 150 nm, or 200 nm.

[0083] Figure 5 The semiconductor device 100 includes a substrate 111, a buffer layer 112, a channel layer 113, a barrier layer 114, a source 120, a gate 131, a cap layer 132, a drain 140, a first passivation layer 151, a transition layer 152, an anti-oxidation layer 153 and a second passivation layer 154.

[0084] The substrate 111, the buffer layer 112, the channel layer 113 and the barrier layer 114 are stacked in sequence. The gate 131 is located on the side of the barrier layer 114 away from the substrate 111, and the cap layer 132 is located between the gate 131 and the barrier layer 114. The source 120 and the drain 140 are located on the side of the barrier layer 114 away from the substrate 111, and are located on opposite sides of the gate 131 respectively.

[0085] The first passivation layer 151 is located on the side of the barrier layer 114 away from the substrate 111, the transition layer 152 is located on the side of the first passivation layer 151 away from the substrate 111, the anti-oxidation layer 153 is located on the side of the transition layer 152 away from the substrate 111, and the second passivation layer 154 is located on the side of the anti-oxidation layer 153 away from the substrate 111. The source 120 and the drain 140 penetrate the first passivation layer 151, the transition layer 152, the anti-oxidation layer 153 and the second passivation layer 154 respectively to contact the barrier layer 114. The first passivation layer 151, the transition layer 152, the anti-oxidation layer 153 and the second passivation layer 154 partially cover the cap layer 132. The gate 131 penetrates the first passivation layer 151, the transition layer 152, the anti-oxidation layer 153 and the second passivation layer 154 to contact the cap layer 132.

[0086] Exemplarily, the material of the anti-oxidation layer 153 includes silicon nitride, and the material of the transition layer 152 includes aluminum silicon nitride.

[0087] The transition layer 152 can make the stress of each film layer structure of the semiconductor device 100 change slowly, and realize stress gradient. The transition layer 152 adjusts the stress of the first passivation layer 151, the anti-oxidation layer 153 and the second passivation layer 154, and can achieve a better passivation effect. At the same time, the adjustment of the stress by the transition layer 152 can also adjust the piezoelectric polarization effect of the heterojunction interface formed by the channel layer 113 and the barrier layer 114, and change the concentration of the two-dimensional electron gas, thereby improving the current driving capability of the semiconductor device 100, and improving the electrical characteristics, stability and reliability of the semiconductor device 100. The adjustment of the piezoelectric polarization effect of the heterojunction interface formed by the channel layer 113 and the barrier layer 114 can also fine-tune the threshold voltage of the semiconductor device 100, so that it is closer to the design target and meets the needs in practical applications.

[0088] Figure 6 FIG. 1 is a flow chart of a method for preparing a semiconductor device according to some embodiments. Figure 6 The method for preparing the semiconductor device shown includes steps S10 to S40:

[0089] See also Fig. 9 In step S10, a barrier layer 114 and a cap layer 132 are sequentially formed on the substrate 111. Exemplarily, a buffer layer 112, a channel layer 113, a barrier layer 114 and a cap layer 132 are sequentially formed on the substrate 111.

[0090] See also Fig.23 In step S20 , a first passivation layer 151 is formed on a side of the barrier layer 114 away from the substrate 111 .

[0091] In step S30 , an anti-oxidation layer 153 is formed on a side of the first passivation layer 151 away from the substrate 111 .

[0092] See also Fig.11 In step S40 , a second passivation layer 154 is formed on a side of the anti-oxidation layer 153 away from the substrate 111 .

[0093] for Figure 5 The semiconductor device 100 including the transition layer 152 shown in FIG. Figure 7 The preparation method shown. Figure 7 is a flow chart of another method for preparing a semiconductor device according to some embodiments. Figures 8 to 19 It is a structural diagram of the semiconductor device corresponding to each step in the preparation method. Figure 7 The preparation method shown includes:

[0094] In step S11, a buffer layer 112, a channel layer 113, a barrier layer 114 and an initial cap layer 133 are sequentially formed on a substrate 111 to obtain Figure 8 The semiconductor structure shown.

[0095] In step S12, the initial cap layer 133 is etched to form a cap layer 132. Exemplarily, the initial cap layer 133 is etched by a photolithography process to form the cap layer 132 and expose the barrier layer 114 in the etched area, so as to obtain Fig. 9 The semiconductor structure shown.

[0096] In step S21, a first passivation layer 151, a transition layer 152, and an anti-oxidation layer 153 are sequentially formed on the side of the barrier layer 114 away from the substrate 111. For example, the transition layer 152 is formed on the side of the first passivation layer 151 away from the substrate 111, and the anti-oxidation layer 153 is formed on the side of the transition layer 152 away from the substrate 111. The first passivation layer 151, the transition layer 152, and the anti-oxidation layer 153 are formed in the same machine, and the following is obtained: Fig.10 The semiconductor structure shown. Exemplarily, an atomic layer deposition process is used to form a first passivation layer 151 on the side of the barrier layer 114 away from the substrate 111, and the thickness of the first passivation layer 151 is greater than or equal to 10 angstroms and less than or equal to 50 angstroms. In the same machine, an atomic layer deposition process is used to form a transition layer 152 on the side of the first passivation layer 151 away from the substrate 111, and an atomic layer deposition process is used to form an anti-oxidation layer 153 on the side of the transition layer 152 away from the substrate 111.

[0097] The material of the first passivation layer 151 includes, for example, aluminum nitride, the material of the transition layer 152 includes, for example, aluminum silicon nitride, and the material of the anti-oxidation layer 153 includes, for example, any one of silicon oxide and silicon nitride.

[0098] In some feasible embodiments, the process of forming the first passivation layer 151 , the transition layer 152 , and the anti-oxidation layer 153 may be performed in different chambers of the same machine, or may be performed in the same chamber of the same machine.

[0099] After forming the first passivation layer 151 , continuously forming the transition layer 152 and the anti-oxidation layer 153 in the same machine can avoid surface oxidation of the first passivation layer 151 caused by vacuum breaking of the semiconductor structure, thereby improving the quality and passivation effect of the formed first passivation layer 151 and thus enhancing the dynamic characteristics of the semiconductor device 100 .

[0100] After forming the first passivation layer 151, continuing to form the transition layer 152 and the anti-oxidation layer 153 in the same chamber of the same machine can shorten the exposure time of the first passivation layer 151 and improve the quality of the formed first passivation layer 151, transition layer 152 and anti-oxidation layer 153, thereby improving the passivation effect of the passivation layer and enhancing the dynamic characteristics of the semiconductor device 100.

[0101] In some feasible embodiments, the sum of the thicknesses of the transition layer 152 and the anti-oxidation layer 153 is greater than or equal to 1 nm and less than or equal to 200 nm. For example, the sum of the thicknesses of the transition layer 152 and the anti-oxidation layer 153 is greater than or equal to 1 nm and less than or equal to 5 nm.

[0102] By controlling the sum of the thicknesses of the transition layer 152 and the anti-oxidation layer 153 within a range of 1 nm to 5 nm, the time required for forming the transition layer 152 and the anti-oxidation layer 153 can be shortened while ensuring the quality of the passivation layer, which is beneficial to improving production efficiency.

[0103] In step S40, a second passivation layer 154 is formed on the side of the anti-oxidation layer 153 away from the substrate 111, and the Fig.11 The semiconductor structure shown. Exemplarily, PECVD (Plasma-Enhanced Chemical Vapor Deposition) is used to form a second passivation layer 154 on the side of the anti-oxidation layer 153 away from the substrate 111. The material of the second passivation layer 154 includes, for example, silicon oxide, so as to achieve surface passivation of the multi-layer thin film stack of the barrier layer 114. It is easy to know from the different deposition processes that the first passivation layer 151 and the second passivation layer 154 are formed in different machines.

[0104] In step S51, the semiconductor device 100 is isolated by ion implantation to obtain Fig.12 In some feasible embodiments, an ion implantation process is used to Fig.11 An ion implantation region 160 is formed in the semiconductor structure shown to complete the isolation of the semiconductor device 100 .

[0105] Exemplarily, the isolation of the semiconductor device 100 is completed by using an STI (Shallow Trench Isolation) process.

[0106] In step S52, the first passivation layer 151, the transition layer 152, the anti-oxidation layer 153 and the second passivation layer 154 are etched to form the source window 121 and the drain window 141. Fig.13 Exemplarily, the first passivation layer 151 , the transition layer 152 , the anti-oxidation layer 153 and the second passivation layer 154 are etched by photolithography and etching until the surface of the barrier layer 114 away from the substrate 111 is exposed, so as to form the source window 121 and the drain window 141 .

[0107] In some feasible embodiments, after etching to expose the barrier layer 114 , over-etching is performed to form a groove on a side of the barrier layer 114 away from the substrate 111 . The groove is also a component of the source window 121 or the drain window 141 .

[0108] In step S53, a source electrode 120 is formed at the source electrode window 121, and a drain electrode 140 is formed at the drain electrode window 141, so as to obtain Fig.14 As shown in the semiconductor structure. Exemplarily, a process such as metal evaporation or sputtering is used to deposit a source-drain material layer at least at the source window 121 and the drain window 141, the source-drain material layer for example comprising one or more layers of metal, and an etching process such as photolithography is used to etch the source-drain material layer to form a source 120 at the source window 121 and a drain 140 at the drain window 141.

[0109] In step S54, a first protective layer 171 is formed on a side of the second passivation layer 154 away from the substrate 111, and the Fig.15 The semiconductor structure shown.

[0110] In step S55, the first passivation layer 151, the transition layer 152, the anti-oxidation layer 153, the second passivation layer 154 and the first protection layer 171 are etched to form a gate window 134, and the gate window 134 is obtained. Fig.16 Exemplarily, the first passivation layer 151 , the transition layer 152 , the anti-oxidation layer 153 , the second passivation layer 154 and the first protection layer 171 are etched by photolithography and etching until the surface of the cap layer 132 away from the substrate 111 is exposed to form a gate window 134 .

[0111] In step S56, a gate 131 is formed at the gate window 134, and a first field plate 181 is formed on a side of the first protection layer 171 away from the substrate 111, so as to obtain Fig.17As shown in the semiconductor structure. Exemplarily, a gate material layer is deposited at least at the gate window 134 and at a side of the first protective layer 171 away from the substrate 111 by using a process such as metal evaporation or sputtering, and the gate material layer is etched by using an etching process such as photolithography to form a gate 131 at the gate window 134 and a first field plate 181 at a side of the first protective layer 171 away from the substrate 111.

[0112] In step S57, a second protective layer 172 and a second field plate 182 are formed on a side of the first protective layer 171 away from the substrate 111, and the Fig.18 The semiconductor structure shown in FIG. 1 is a semiconductor structure of FIG. 1. Exemplarily, a PECVD process is used to form a second protective layer 172 on a side of the first protective layer 171 away from the substrate 111, and the second protective layer 172 also covers the gate 131. A field plate material layer is formed on a side of the second protective layer 172 away from the substrate 111 by a process such as metal evaporation or sputtering, and the field plate material layer is etched by an etching process such as photolithography to form a second field plate 182.

[0113] In step S58, a third protective layer 173 is formed on the side of the second protective layer 172 away from the substrate 111, and the third protective layer 173 at least covers the second field plate 182, so as to obtain Fig.19 As shown in the semiconductor structure, PECVD is used to form a third protection layer 173 on a side of the second protection layer 172 away from the substrate 111 , and the third protection layer 173 at least covers the second field plate 182 .

[0114] for Figure 4 The semiconductor device 100 shown in FIG. Fig. 20 The preparation method shown, Fig. 20 is a flow chart of another method for preparing a semiconductor device according to some embodiments. Figure 21 to Figure 23 It is a structural diagram of the semiconductor device corresponding to each step in the preparation method. Fig. 20 The preparation method shown includes:

[0115] In step S11, a buffer layer 112, a channel layer 113, a barrier layer 114 and an initial cap layer 133 are sequentially formed on a substrate 111 to obtain Fig.21 The semiconductor structure shown.

[0116] In step S12, the initial cap layer 133 is etched to form a cap layer 132. Exemplarily, the initial cap layer 133 is etched by a photolithography process to form the cap layer 132 and expose the barrier layer 114 in the etched area, so as to obtain Fig. 22 The semiconductor structure shown.

[0117] In step S22, a first passivation layer 151 and an anti-oxidation layer 153 are sequentially formed on a side of the barrier layer 114 away from the substrate 111, a first passivation layer 151 is formed on a side of the barrier layer 114 away from the substrate 111, and a transition layer 152 is formed on a side of the first passivation layer 151 away from the substrate 111. The first passivation layer 151 and the transition layer 152 are formed in the same machine, and the following is obtained: Fig.23 The semiconductor structure shown in FIG. 1 is a semiconductor structure of FIG. 1. Exemplarily, an atomic layer deposition process is used to form a first passivation layer 151 on a side of the barrier layer 114 away from the substrate 111, and the thickness of the first passivation layer 151 is greater than or equal to 10 angstroms and less than or equal to 50 angstroms. In the same machine, an atomic layer deposition process is used to form a transition layer 152 on a side of the first passivation layer 151 away from the substrate 111.

[0118] The material of the first passivation layer 151 includes, for example, aluminum nitride, and the material of the transition layer 152 includes, for example, aluminum silicon nitride or silicon nitride.

[0119] In some feasible embodiments, the thickness of the transition layer 152 is greater than or equal to 1 nm and less than or equal to 200 nm. For example, the thickness of the transition layer 152 is greater than or equal to 1 nm and less than or equal to 5 nm.

[0120] In some feasible embodiments, step S60 is further included between step S12 and step S22.

[0121] In step S60, a solution such as hydrochloric acid (HCl) or ammonia (NH3·H20) is used for cleaning. Fig. 22 The semiconductor structure shown.

[0122] After step S22, Fig. 20 The preparation method shown is Figure 7 S40 and S51 to S58 in the preparation method shown are basically the same, except that Figure 7 The preparation method shown includes the anti-oxidation layer 153, so it is not described again.

[0123] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a barrier layer disposed on the substrate; A cap layer, located on a side of the barrier layer away from the substrate; A first passivation layer, located on a side of the barrier layer away from the substrate; an anti-oxidation layer, located on a side of the first passivation layer away from the substrate; The second passivation layer is located on a side of the anti-oxidation layer away from the substrate.

2. The semiconductor device according to claim 1, wherein: The thickness uniformity of the first passivation layer is less than or equal to 1%; The thickness uniformity of the anti-oxidation layer is less than or equal to 1%.

3. The semiconductor device according to claim 1, wherein: The material of the anti-oxidation layer includes silicon nitride.

4. The semiconductor device according to claim 3, characterized in that Also includes: A transition layer is located between the first passivation layer and the anti-oxidation layer.

5. The semiconductor device according to claim 4, characterized in that The material of the transition layer includes aluminum silicon nitride.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that: The sum of the thickness of the transition layer and the anti-oxidation layer is greater than or equal to 1 nanometer and less than or equal to 200 nanometers.

7. The semiconductor device according to any one of claims 3 to 5, characterized in that: The sum of the thickness of the transition layer and the anti-oxidation layer is greater than or equal to 1 nanometer and less than or equal to 5 nanometers.

8. The semiconductor device according to claim 1, wherein: The material of the anti-oxidation layer includes aluminum silicon nitride.

9. The semiconductor device according to claim 4 or 8, characterized in that: The material of the second passivation layer includes silicon oxide or silicon nitride.

10. The semiconductor device according to claim 8, characterized in that The thickness of the anti-oxidation layer is greater than or equal to 1 nanometer and less than or equal to 200 nanometers.

11. The semiconductor device according to claim 1, wherein: Also includes: a buffer layer, the buffer layer being located between the substrate and the barrier layer; a channel layer, the channel layer being located between the buffer layer and the barrier layer; a gate, located at a side of the cap layer away from the substrate, and penetrating the second passivation layer, the anti-oxidation layer and the first passivation layer; The source electrode and the drain electrode are located on a side of the barrier layer away from the substrate and penetrate the second passivation layer, the anti-oxidation layer and the first passivation layer. The source electrode and the drain electrode are respectively located on two opposite sides of the gate electrode.

12. A chip, characterized in that: The invention comprises a package substrate and the semiconductor device according to any one of claims 1 to 11, wherein the package substrate is coupled to the semiconductor device.

13. An electronic device, characterized in that: It comprises a circuit board and the chip as claimed in claim 12, wherein the chip is arranged on the circuit board.

14. A method for preparing a semiconductor device, characterized in that: include: forming a barrier layer and a cap layer on the substrate in sequence; forming a first passivation layer on a side of the barrier layer away from the substrate; forming an anti-oxidation layer on a side of the first passivation layer away from the substrate; forming a second passivation layer on a side of the anti-oxidation layer away from the substrate; Wherein, the first passivation layer and the anti-oxidation layer are both formed by an atomic layer deposition process.

15. The preparation method according to claim 14, characterized in that: The first passivation layer and the anti-oxidation layer are formed in the same reaction chamber.

16. The preparation method according to claim 14, characterized in that: Between the forming of the first passivation layer on the side of the barrier layer away from the substrate and the forming of the anti-oxidation layer on the side of the first passivation layer away from the substrate, the method further includes: forming a transition layer on a side of the first passivation layer away from the substrate; Wherein, the first passivation layer, the transition layer and the anti-oxidation layer are all formed by an atomic layer deposition process.

17. The preparation method according to claim 15, characterized in that: The first passivation layer, the transition layer and the anti-oxidation layer are formed in the same reaction chamber.

18. The preparation method according to claim 14, characterized in that: The second passivation layer is formed by a plasma enhanced chemical vapor deposition process and is formed in a different reaction chamber from the first passivation layer.

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