Gallium oxide trench MOSFET device based on heterojunction and preparation method thereof

Abstract

The invention provides a gallium oxide trench MOSFET device based on heterojunction and a preparation method thereof, and relates to the technical field of semiconductors. Comprising drain electrode metal, an n-type substrate, an n-type epitaxial drift region, a p-type base region and an n + epitaxial source region which are sequentially arranged from bottom to top, the n-type substrate is made of beta-Ga2O3, and the p-type base region is made of NiO; the p + injection source region is formed in edge regions on two sides of the p-type base region; the gate electrode trench extends downwards from the n + epitaxial source region and penetrates through the n + epitaxial source region and the p-type base region, and the bottom of the gate electrode trench is positioned in the n-type epitaxial drift region; the gate medium is formed on the inner wall of the gate electrode groove and the partial upper surface of the n + epitaxial source region, and the gate electrode is arranged on the gate medium; and the source metal is formed on the p + injection source region and a part of the upper surface of the n + epitaxial source region, and the source metal is in contact with the gate medium. The device application difficulty caused by the fact that gallium oxide lacks effective p-type doping is overcome; the leakage current of the device is small, and the current switching ratio is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a heterojunction-based gallium oxide trench metal-oxide semiconductor field-effect transistor (MOSFET) device and a preparation method thereof. Background Art

[0002] Gallium oxide (β-Ga2O3) has attracted widespread attention due to its excellent performance. It has a bandgap width far exceeding that of SiC and GaN (4.6-4.9eV), an extremely high theoretical breakdown electric field (8MV / cm), and a high electron saturation drift velocity (2×10 7 cm / s), nearly four times that of GaN and ten times that of SiC, Baliga's Figure Of Merit (BFOM) value, many excellent characteristics make β-Ga2O3 devices expected to increase the switching speed of devices, shorten the reverse recovery time of rectifier devices, and have great application potential in high-voltage power and radio frequency fields. In addition, the β-Ga2O3 wafer preparation process is becoming more and more mature, and high-quality large-size single crystals can be prepared by melt growth method (pulling method (CZ), floating zone method (Floating Zone, FZ) and guided mode method (Edge-Defined Film-Fed Growth, EFG)), which is expected to be low-cost and large-scale production. The progress of single crystal β-Ga2O3 substrate synthesis, especially the cost-competitive melt growth method, provides a huge advantage for the development of Ga2O3-based high-voltage power devices with vertical geometric structures.

[0003] In existing technical solutions, unintentionally doped gallium oxide is commonly used as a conductive channel. However, the Ek dispersion relation of the top of the valence band of unintentionally doped gallium oxide is relatively flat, resulting in a large effective mass of holes inside it, and the holes are strongly localized on the O 2p energy level with strong electronegativity. At the same time, the deep energy level acceptors introduced by traditional single doping have extremely low activation efficiency at room temperature, making it difficult to contribute effective free holes to the valence band. Therefore, it is difficult to achieve p-type doping of gallium oxide materials (β-Ga2O3); the insulation performance of unintentionally doped gallium oxide is poor, resulting in a large leakage current of MOSFET devices and a low current switching ratio of MOSFET devices. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a heterojunction-based gallium oxide trench MOSFET device and a preparation method thereof, which overcomes the device application difficulties caused by the lack of effective p-type doping of gallium oxide and solves the problems of large leakage current and low current switching ratio of gallium oxide MOSFET devices.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a heterojunction-based gallium oxide trench MOSFET device, comprising:

[0007] Drain metal;

[0008] An n-type substrate is located on the upper surface of the drain metal, and the material of the n-type substrate is β-Ga2O3 material;

[0009] An n-type epitaxial drift region is formed on the upper surface of the n-type substrate;

[0010] A p-type base region is formed on both side edge regions of the n-type epitaxial drift region, and the material of the p-type base region is NiO material;

[0011] A p+ injection source region is formed in the edge regions on both sides of the p-type base region;

[0012] An n+ epitaxial source region is formed on the upper surface of the p-type base region;

[0013] A gate electrode trench extends downward from the upper surface of the n+ epitaxial source region and penetrates the n+ epitaxial source region and the p-type base region, and the bottom is located in the n-type epitaxial drift region;

[0014] A gate dielectric is formed on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region, and a gate electrode is arranged on the upper surface of the gate dielectric;

[0015] The source metal is formed on the upper surface of the p+ implanted source region and part of the upper surface of the n+ epitaxial source region, and the source metal is in contact with the gate dielectric.

[0016] In some modified embodiments of the first aspect of the present invention, the doping element of the n-type substrate is Sn, and the doping concentration range of the n-type substrate is 3×10 18 ~1×10 19 cm -3 , thickness is 90μm~1500μm.

[0017] In some modified embodiments of the first aspect of the present invention, the thickness of the n-type epitaxial drift region is 10 μm to 500 μm, and the doping concentration ranges from 4×10 15 ~5×10 16 cm -3 .

[0018] In some modified embodiments of the first aspect of the present invention, the thickness of the p-type base region is 300-700 nm, and the hole concentration in NiO is 1×10 17 ~1×10 19 cm -3 .

[0019] In some modified embodiments of the first aspect of the present invention, the thickness of the n+ epitaxial source region is 200 nm to 300 nm, the doping element is Si, and the doping concentration is 3×10 18 cm -3 ~1×10 19 cm -3 .

[0020] In some modified embodiments of the first aspect of the present invention, the junction depth of the p+ injection source region is 100 nm to 200 nm, the doping element is Li, and the doping concentration ranges from 3×10 18 ~1×10 19 cm -3 .

[0021] In some modified implementations of the first aspect of the present invention, the shape of the gate electrode trench is a rounded rectangular shape, and the material of the gate dielectric is SiO2 material with a thickness of 20 to 100 nm.

[0022] In some modified implementations of the first aspect of the present invention, the metal material of the gate electrode is a Ni / Au stacked layer material, the material of the source metal is a Ti / Au stacked layer material, and the material of the drain metal is a Ti / Au stacked layer material.

[0023] A second aspect of the present invention provides a method for preparing a heterojunction-based gallium oxide trench MOSFET device, comprising:

[0024] An n-type epitaxial drift region is formed on the front side of the n-type substrate, and the material of the n-type substrate is β-Ga2O3 material;

[0025] A p-type base region is formed on the n-type epitaxial drift region by using a radio frequency sputtering device, wherein the material of the p-type base region is NiO material;

[0026] forming an n+ epitaxial source region on the p-type base region;

[0027] Etching the edge regions on both sides of the n+ epitaxial source region to form a p+ source region pre-implantation region;

[0028] Using an ion implantation process, ion implantation is performed in a p+ source region pre-implantation area to form a p+ implantation source region;

[0029] Etching is performed in the middle region of the n+ epitaxial source region to form a gate electrode trench, wherein the gate electrode trench penetrates the n+ epitaxial source region and the p-type base region and the bottom of the gate electrode trench is located in the n-type epitaxial drift region;

[0030] forming a gate dielectric on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region;

[0031] forming a gate electrode on the gate dielectric;

[0032] forming a source metal on the p+ implanted source region and the n+ epitaxial source region;

[0033] A drain metal is formed on the back side of the n-type substrate to obtain a heterojunction-based gallium oxide trench MOSFET device.

[0034] In some modified embodiments of the second aspect of the present invention, the target material of the RF sputtering device is 99.99% pure NiO, the sputtering environment is room temperature and Ar / O2 mixture environment, the sputtering chamber pressure is 3mTorr, the RF power is 100-150W, the NiO deposition rate is 0.75nm / min, the thickness of the p-type base region is 300-700nm, and the hole concentration in the sputtered NiO is 1×10 17 ~1×10 19 cm -3 .

[0035] Compared with the prior art, the heterojunction-based gallium oxide trench MOSFET device provided by the present invention and its preparation method include a drain metal; an n-type substrate, located on the upper surface of the drain metal, and the material of the n-type substrate is β-Ga2O3 material; an n-type epitaxial drift region, formed on the upper surface of the n-type substrate; a p-type base region, formed on the edge regions on both sides of the n-type epitaxial drift region, and the material of the p-type base region is NiO material; a p+ injection source region, formed in the edge regions on both sides of the p-type base region; an n+ epitaxial source region, formed on the upper surface of the p-type base region; a gate electrode trench, extending downward from the upper surface of the n+ epitaxial source region, penetrating the n+ epitaxial source region and the p-type base region, and the bottom is located in the n-type epitaxial drift region; a gate dielectric, formed on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region, and a gate electrode is arranged on the upper surface of the gate dielectric; a source metal, formed on the upper surface of the p+ injection source region and a portion of the upper surface of the n+ epitaxial source region, and the source metal is in contact with the gate dielectric. In this way, by constructing a pn heterojunction MOSFET with p-type material NiO and β-Ga2O3, the difficulty in device application caused by the lack of effective p-type doping in gallium oxide can be effectively overcome; the p-type material NiO has good insulation performance, which makes the leakage current of the MOSFET device smaller; the trench gate structure can increase the current switching ratio of the gallium oxide enhancement MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0037] Figure 1 The structure of a heterojunction-based gallium oxide trench MOSFET device is schematically shown;

[0038] Figure 2 The flowchart of the method for preparing a gallium oxide trench MOSFET device based on a heterojunction is schematically shown;

[0039] Figure 3 schematically shows a schematic diagram of forming an n-type epitaxial drift region;

[0040] Figure 4 Schematically shows a schematic diagram of forming a p-type base region;

[0041] Figure 5 Schematically shows a schematic diagram of forming an n+ epitaxial source region;

[0042] Figure 6 The schematic diagram of forming a p+ source region pre-implantation area is schematically shown;

[0043] Figure 7 Schematically shows a schematic diagram of forming a p+ implantation source region;

[0044] Figure 8 Schematically showing a schematic diagram of forming a gate electrode trench;

[0045] Fig. 9 The schematic diagram of forming a gate dielectric is schematically shown;

[0046] Fig.10 schematically shows a schematic diagram of forming a gate electrode;

[0047] Fig.11 schematically shows a schematic diagram of forming a source metal;

[0048] Fig.12 The schematic diagram of forming the drain metal is schematically shown.

[0049] Description of Reference Numerals

[0050] 1. n-type substrate; 2. n-type epitaxial drift region; 3. p-type base region; 4. n+ epitaxial source region; 5. p+ injection source region; 6. gate dielectric; 7. gate electrode; 8. source metal; 9. drain metal. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0052] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0053] The method in the embodiment of the present invention is described in detail below.

[0054] Figure 1 The structure of a gallium oxide trench MOSFET device based on a heterojunction is schematically shown. The gallium oxide trench MOSFET device based on a heterojunction includes:

[0055] Drain metal 9;

[0056] An n-type substrate 1 is located on the upper surface of the drain metal 9, and the material of the n-type substrate 1 is β-Ga2O3 material;

[0057] An n-type epitaxial drift region 2 is formed on the upper surface of the n-type substrate 1;

[0058] A p-type base region 3 is formed on both side edge regions of the n-type epitaxial drift region 2, and the material of the p-type base region 3 is NiO material;

[0059] p+ injection source regions 5 are formed in the edge regions on both sides of the p-type base region 3;

[0060] An n+ epitaxial source region 4 is formed on the upper surface of the p-type base region 3;

[0061] A gate electrode trench extends downward from the upper surface of the n+ epitaxial source region 4 and penetrates the n+ epitaxial source region 4 and the p-type base region 3, and the bottom is located in the n-type epitaxial drift region 2;

[0062] A gate dielectric 6 is formed on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region 4, and a gate electrode 7 is disposed on the upper surface of the gate dielectric 6;

[0063] The source metal 8 is formed on the upper surface of the p+ implanted source region 5 and a portion of the upper surface of the n+ epitaxial source region 4 , and the source metal 8 is in contact with the gate dielectric 6 .

[0064] Specifically, the doping element of the n-type substrate 1 is Sn, and the doping concentration range of the n-type substrate 1 is 3×10 18 ~1×10 19 cm -3 , thickness is 90μm~1500μm.

[0065] Specifically, the thickness of the n-type epitaxial drift region 2 is 10 μm to 500 μm, and the doping concentration ranges from 4×10 15 ~5×10 16 cm -3 .

[0066] Specifically, the thickness of the p-type base region 3 is 300-700 nm, and the hole concentration in NiO is 1×10 17 ~1×10 19 cm -3 .

[0067] Specifically, the thickness of the n+ epitaxial source region 4 is 200 nm to 300 nm, the doping element is Si, and the doping concentration is 3×10 18 cm -3 ~1×10 19 cm -3 .

[0068] Specifically, the junction depth of the p+ implanted source region 5 is 100 nm to 200 nm, the doping element is Li, and the doping concentration range is 3×10 18 ~1×10 19 cm -3 .

[0069] Specifically, the shape of the gate electrode trench is a rounded rectangular shape, and the material of the gate dielectric 6 is SiO2 material with a thickness of 20 to 100 nm.

[0070] Specifically, the shape of the gate electrode trench is a rounded rectangular shape, and the material of the gate dielectric 6 is SiO2 material with a thickness of 20 to 100 nm.

[0071] Specifically, the metal material of the gate electrode 7 is a Ni / Au stacked layer material, the material of the source metal 8 is a Ti / Au stacked layer material, and the material of the drain metal 9 is a Ti / Au stacked layer material.

[0072] The heterojunction-based gallium oxide trench MOSFET device of the present invention is a vertical structure MOSFET with a smaller size and higher power density; the conductive channel of the heterojunction-based gallium oxide trench MOSFET device of the present invention is p-type material nickel oxide, which has good insulation performance and can solve the problems of large leakage current and low current switching ratio; the heterojunction-based gallium oxide trench MOSFET device of the present invention is an enhancement MOSFET, which can be turned off at zero gate voltage and can reduce static power consumption.

[0073] Based on the above Figure 1It can be seen from the implementation method that the heterojunction-based gallium oxide trench MOSFET device of the embodiment of the present invention includes a drain metal 9; an n-type substrate 1, located on the upper surface of the drain metal 9, and the material of the n-type substrate 1 is β-Ga2O3 material; an n-type epitaxial drift region 2, formed on the upper surface of the n-type substrate 1; a p-type base region 3, formed on both side edge regions of the n-type epitaxial drift region 2, and the material of the p-type base region 3 is NiO material; a p+ injection source region 5, formed in both side edge regions of the p-type base region 3 ; n+ epitaxial source region 4, formed on the upper surface of p-type base region 3; gate electrode trench, extending downward from the upper surface of n+ epitaxial source region 4, penetrating n+ epitaxial source region 4 and p-type base region 3, and the bottom is located in n-type epitaxial drift region 2; gate dielectric 6, formed on the inner wall of gate electrode trench and part of the upper surface of n+ epitaxial source region 4, gate electrode 7 is arranged on the upper surface of gate dielectric 6; source metal 8, formed on the upper surface of p+ injection source region 5 and part of the upper surface of n+ epitaxial source region 4, and source metal 8 is in contact with gate dielectric 6. In this way, constructing pn heterojunction MOSFET by p-type material NiO and β-Ga2O3 can effectively overcome the device application difficulties caused by the lack of effective p-type doping of gallium oxide; the p-type material NiO has good insulation performance, so that the leakage current of MOSFET device is small; the trench gate structure can increase the current switching ratio of gallium oxide enhancement MOSFET.

[0074] Figure 2 The method for preparing a heterojunction-based gallium oxide trench MOSFET device in an embodiment of the present invention is schematically shown. Figure 2 As shown, the method for preparing the heterojunction-based gallium oxide trench MOSFET device may include:

[0075] S201 , forming an n-type epitaxial drift region 2 on the front surface of an n-type substrate 1 .

[0076] The material of the n-type substrate 1 is β-Ga2O3 material.

[0077] The doping element of the n-type substrate 1 is Sn, and the doping concentration range is 3×10 18 ~1×10 19 cm -3 , thickness is 90μm~1500μm.

[0078] Figure 3The schematic diagram of forming the n-type epitaxial drift region 2 is schematically shown. When the n-type epitaxial drift region 2 is formed on the front side of the n-type substrate 1, a halide vapor phase epitaxy (HVPE) device is used, high-purity GaCl and O2 gases are used as gallium and oxygen precursors, SiCl4 and N2 are used as doping sources and carrier gases, respectively, the growth temperature is 1000°C, the thickness of the n-type epitaxial drift region 2 is 10μm to 500μm, and the doping concentration ranges from 4×10 15 ~5×10 16 cm -3 .

[0079] The n-type epitaxial drift region 2 may be prepared by metal organic chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition, atomized chemical vapor deposition, etc., and the preparation method of the n-type epitaxial drift region 2 is not specifically limited.

[0080] S202 , forming a p-type base region 3 on the n-type epitaxial drift region 2 using a radio frequency sputtering device.

[0081] The material of the p-type base region 3 is NiO material.

[0082] Specifically, Figure 4 The schematic diagram of forming the p-type base region 3 is schematically shown. When forming the p-type base region 3 on the n-type epitaxial drift region 2, a radio frequency sputtering device is used. The target material of the radio frequency sputtering device is a NiO ceramic with a purity of 99.99%. Before device manufacturing, the sample (including the n-type substrate 1 and the n-type epitaxial drift region 2) is cleaned with acetone and isopropanol, and then rinsed with 4 cycles of deionized water. After cleaning, NiO is sputtered from the NiO target to the front of the sample and patterned using a lift-off process. The sputtering process is carried out at room temperature and in an Ar / O2 mixture environment. The sputtering chamber pressure is 3mTorr, the radio frequency power is 100-150W, the NiO deposition rate is 0.75nm / min, the thickness of the p-type base region 3 is 300-700nm, and the hole concentration in the sputtered NiO is 1×10 17 ~1×10 19 cm -3 .

[0083] S203 , forming an n+ epitaxial source region 4 on the p-type base region 3 .

[0084] Specifically, Figure 5The schematic diagram of forming the n+ epitaxial source region 4 is schematically shown. The n+ epitaxial source region 4 is formed on the p-type base region 3, which can be obtained by evaporating gallium in oxygen plasma. The substrate temperature is maintained at 800°C, the RF power of the oxygen plasma is 100W, the flow rate of oxygen is controlled at 4sccm, the chamber pressure is 0.5mTorr, the thickness of the n+ epitaxial source region 4 is 200nm-300nm, the doping element is Si, and the doping concentration is 3×10 18 cm -3 ~1×10 19 cm -3 , and then annealing is performed to improve the interface quality, and the annealing temperature is 250-350℃.

[0085] There are many alternative ways to prepare the N+ epitaxial source region 4, such as metal organic chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition and atomized chemical vapor deposition, etc. The preparation method of the N+ epitaxial source region 4 is not specifically limited.

[0086] S204 , etching the edge regions on both sides of the n+ epitaxial source region 4 to form a p+ source region pre-implantation region.

[0087] Specifically, Figure 6 The schematic diagram of forming a p+ source region pre-injection area is schematically shown. The p+ source region pre-injection area is formed in the edge areas on both sides of the n+ epitaxial source region 4 using a photolithography process, a mask is used to protect the inner area of ​​the trench, and an inductively coupled plasma (ICP) dry etching process is used to form the p+ source region pre-injection area.

[0088] S205 , using an ion implantation process, ion implantation is performed in the p+ source region pre-implantation area to form a p+ implantation source region 5 .

[0089] Specifically, Figure 7 The schematic diagram of forming the p+ injection source region 5 is schematically shown. The p+ injection source region 5 is formed on the p+ source region pre-injection area using an ion implantation process. The junction depth of the p+ injection source region 5 is 100nm to 200nm, the doping element is Li, and the doping concentration range is 3×10 18 cm -3 ~1×10 19 cm -3 , the implanted Li ions are activated by annealing.

[0090] S206 , etching is performed in the middle area of ​​the n+ epitaxial source region 4 to form a gate electrode trench.

[0091] The gate electrode trench penetrates the n+ epitaxial source region 4 and the p-type base region 3 , and the bottom thereof is located in the n-type epitaxial drift region 2 .

[0092] Specifically, Figure 8 The schematic diagram of forming a gate electrode groove is schematically shown. When the gate electrode groove is formed on the n+ epitaxial source region 4, a photolithography process is used to protect the outer area of ​​the gate electrode groove using a mask, and an inductively coupled plasma ICP dry etching process is used to form the gate electrode groove, and the gate electrode groove is a rounded rectangular shape.

[0093] S207 , forming a gate dielectric 6 on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region 4 .

[0094] Specifically, Fig. 9 A schematic diagram of forming a gate dielectric 6 is schematically shown. When the gate dielectric 6 is formed on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region 4, a mask is used to protect the outer area of ​​the gate electrode trench, and a SiO2 layer is formed on the inner surface of the gate electrode trench using thermal oxidation technology to form a gate dielectric 6 with a thickness of 20 to 100 nm.

[0095] S208 , forming a gate electrode 7 on the gate dielectric 6 .

[0096] Specifically, Fig.10 A schematic diagram of forming a gate electrode 7 is schematically shown. When depositing the gate electrode 7 on the gate dielectric 6, a mask is used to protect the outer area of ​​the gate electrode groove. An electron beam evaporation coating machine is used to deposit the gate electrode 7 on the gate dielectric 6. The metal material of the gate electrode 7 is a Ni / Au stacked layer material.

[0097] S209 , forming a source metal 8 on the p+ implantation source region 5 and the n+ epitaxial source region 4 .

[0098] Specifically, Fig.11 The schematic diagram of forming the source metal 8 is schematically shown. When the source metal 8 is formed on the p+ injection source region 5 and the n+ epitaxial source region 4, an electron beam evaporation coating machine is used to evaporate the source metal 8. The material of the source metal 8 is a Ti / Au stacked layer material.

[0099] S210 , forming a drain metal 9 on the back side of the n-type substrate 1 to obtain a gallium oxide trench MOSFET device based on a heterojunction.

[0100] Specifically, Fig.12 A schematic diagram of forming a drain metal 9 is schematically shown. When the drain metal 9 is formed on the back side of the n-type substrate 1, the drain metal 9 is formed on the back side of the n-type substrate 1 through a thinning process and a back gold process. The material of the drain metal 9 is a Ti / Au stacked layer material, and a Ga2O3 trench MOSFET device based on a heterojunction is finally formed.

[0101] The preparation method of the gallium oxide trench MOSFET device based on the heterojunction of the present invention introduces radio frequency magnetron sputtering and ion implantation technology in the overall process of preparation, thereby improving the reliability of the heterojunction interface and reducing the preparation time of the gallium oxide trench MOSFET based on the heterojunction. Meanwhile, only one ion implantation process is required in the preparation process of the device, thereby reducing the lattice damage to the material and improving the working stability of the device. In addition, the annealing process is used to reduce the interface state at the heterojunction interface.

[0102] Two embodiments of the method for preparing a heterojunction-based gallium oxide trench MOSFET device of the present invention are provided, but the present invention is not limited to these two embodiments.

[0103] Embodiment 1:

[0104] The method for preparing a heterojunction-based gallium oxide trench MOSFET device includes:

[0105] Step 1: prepare an n-type substrate 1 and form an n-type epitaxial drift region 2 on the front of the n-type substrate 1. The material of the n-type substrate 1 is β-Ga2O3 material, the doping element is Sn, and the doping concentration is 5×10 18 cm -3 , with a thickness of 200 μm. When forming the n-type epitaxial drift region 2 on the front side of the n-type substrate 1, HVPE equipment is used, with high-purity GaCl and O2 gases as gallium and oxygen precursors, SiCl4 and N2 as doping sources and carrier gases, respectively. The growth temperature is 1000 °C, the thickness of the n-type epitaxial drift region 2 is 10 μm, and the doping concentration is 1.5×10 16 cm -3 .

[0106] Step 2, forming a p-type base region 3 on the n-type epitaxial drift region 2 obtained in step 1. When forming the p-type base region 3 on the n-type epitaxial drift region 2, a radio frequency sputtering device is used, and the target material is a high-purity (99.99%) NiO ceramic. Before device manufacturing, the sample is cleaned with acetone and isopropanol, and then rinsed with 4 cycles of deionized water. After cleaning, NiO is sputtered from the NiO target to the front of the sample and patterned using a lift-off process. The sputtering process is carried out at room temperature and in an Ar / O2 mixture (30 / 1sccm) environment, with a chamber pressure of 3mTorr and an RF power of 150W. The deposition rate of NiO is 0.75nm / min, the thickness of the p-type epitaxial base region is 300nm, and the hole concentration in the sputtered NiO is 2×10 17 cm -3 , and then annealing is performed to improve the interface quality, and the annealing temperature is 250℃.

[0107] Step 3, forming an n+ epitaxial source region 4 on the p-type base region 3 obtained in step 2. The n+ epitaxial source region 4 can be formed on the p-type base region 3 by evaporating gallium in oxygen plasma, the substrate temperature is maintained at 800°C, the oxygen plasma RF power is 100W, the oxygen flow rate is controlled at 4sccm, the chamber pressure is 0.5mTorr, the thickness of the n+ epitaxial source region 4 is 200nm, the doping element is Si, and the doping concentration is 3×10 18 cm -3 .

[0108] Step 4, forming p+ source region pre-implantation regions on both side edge regions of the n+ epitaxial source region 4 obtained in step 3. The p+ source region pre-implantation regions are formed on the n+ epitaxial source region 4 by using a photolithography process, using a mask to protect the inner regions of the left and right source trenches, and using an inductively coupled plasma ICP dry etching process to form the p+ source region pre-implantation regions.

[0109] Step 5: forming a p+ injection source region 5 on the p+ source region pre-injection region obtained in step 4. The p+ injection source region 5 is formed on the p+ source region pre-injection region using an ion implantation process, with a junction depth of 150nm, a doping element of Li, and a doping concentration of 3×10 18 cm -3 , the implanted Li ions are activated by annealing.

[0110] Step 6: Form a gate electrode groove in the middle region of the n+ epitaxial source region 4 obtained in step 3. When forming the gate electrode groove in the middle region of the n+ epitaxial source region 4, a photolithography process is used, a mask is used to protect the outer region of the gate electrode groove, and an inductively coupled plasma ICP dry etching process is used to form the gate electrode groove. The gate electrode groove is in a rounded rectangular shape, and the groove depth is 2 μm.

[0111] Step 7: Form a gate dielectric 6 on the inner wall of the gate electrode trench obtained in step 6 and on a portion of the upper surface of the n+ epitaxial source region 4. When forming the gate dielectric 6 on the gate electrode trench, a mask is used to protect the outer area of ​​the gate electrode trench, and a SiO2 layer is formed on the inner surface of the gate electrode trench using a thermal oxidation technique to form a gate dielectric 6 with a thickness of 30 nm.

[0112] Step 8, depositing a gate electrode 7 on the gate dielectric 6 obtained in step 7. When depositing the gate electrode 7 on the gate dielectric 6, a mask is used to protect the outer region of the gate electrode groove, and an electron beam evaporation coating machine is used to deposit the gate electrode 7 on the gate dielectric 6. The metal material of the gate electrode 7 is a Ni / Au stacked layer (20 / 100 nm).

[0113] Step 9, forming source metal 8 on the p+ injection source and n+ epitaxial source region 4 obtained in step 5. When forming source metal 8 on the isolation medium, electron beam evaporation coating machine is used to evaporate source metal 8. The material of source metal 8 is Ti / Au stacked layer (20 / 120nm).

[0114] Step 10, forming a drain metal 9 on the back side of the n-type substrate 1 obtained in step 1. When the drain metal 9 is formed on the back side of the n-type substrate 1, a drain metal 9 is formed at the bottom of the n-type substrate 1 through a thinning process and a back gold process. The material of the drain metal 9 is a Ti / Au stacked layer (20 / 120nm), and finally a Ga2O3 trench MOSFET device based on a heterojunction is formed.

[0115] Embodiment 2:

[0116] The method for preparing a heterojunction-based gallium oxide trench MOSFET device includes:

[0117] Step 1: prepare an n-type substrate 1 and form an n-type epitaxial drift region 2 on the front of the n-type substrate 1. The material of the n-type substrate 1 is β-Ga2O3 material, the doping element is Sn, and the doping concentration is 1×10 19 cm -3 , with a thickness of 200 μm. When forming the n-type epitaxial drift region 2 on the front side of the n-type substrate 1, HVPE equipment is used, with high-purity GaCl and O2 gases as gallium and oxygen precursors, SiCl4 and N2 as doping sources and carrier gases, respectively. The growth temperature is 1000 °C, the thickness of the n-type epitaxial drift region 2 is 12 μm, and the doping concentration is 3×10 16 cm -3 .

[0118] Step 2, forming a p-type base region 3 on the n-type epitaxial drift region 2 obtained in step 1. When forming the p-type base region 3 on the n-type epitaxial drift region 2, a radio frequency sputtering device is used, and the target material is a high-purity (99.99%) NiO ceramic. Before device manufacturing, the sample is cleaned with acetone and isopropanol, and then rinsed with 4 cycles of deionized water. After cleaning, NiO is sputtered from the NiO target to the front of the sample and patterned using a lift-off process. The sputtering process is carried out at room temperature and in an Ar / O2 mixture (20 / 1sccm) environment, with a chamber pressure of 3mTorr and an RF power of 150W. The deposition rate of NiO is 0.75nm / min, the thickness of the p-type epitaxial base region is 500nm, and the hole concentration in the sputtered NiO is 5×10 17 cm -3 , and then annealing is performed to improve the interface quality, and the annealing temperature is 300℃.

[0119] Step 3, forming an n+ epitaxial source region 4 on the p-type base region 3 obtained in step 2. The n+ epitaxial source region 4 can be formed on the p-type base region 3 by evaporating gallium in oxygen plasma, the substrate temperature is maintained at 800°C, the oxygen plasma RF power is 100W, the oxygen flow rate is controlled at 4sccm, the chamber pressure is 0.5mTorr, the thickness of the n+ epitaxial source region 4 is 300nm, the doping element is Si, and the doping concentration is 1×10 19 cm -3 .

[0120] Step 4, forming p+ source region pre-implantation regions at both side edge regions of the n+ epitaxial source region 4 obtained in step 3. The p+ source region pre-implantation regions are formed on the p-type epitaxial base region by using a photolithography process, using a mask to protect the inner regions of the left and right source trenches, and using an inductively coupled plasma ICP dry etching process to form the p+ source region pre-implantation regions.

[0121] Step 5: forming a p+ injection source region 5 on the p+ source region pre-injection region obtained in step 4. The p+ injection source region 5 is formed on the p+ source region pre-injection region using an ion implantation process. The junction depth of the p+ injection source region 5 is 200 nm, the doping element is Li, and the doping concentration is 1×10 19 cm -3 , the implanted Li ions are activated by annealing.

[0122] Step 6: Form a gate electrode groove in the middle region of the n+ epitaxial source region 4 obtained in step 3. When forming the gate electrode groove in the middle region of the n+ epitaxial source region 4, a photolithography process is used, a mask is used to protect the outer region of the gate electrode groove, and an inductively coupled plasma ICP dry etching process is used to form the gate electrode groove. The gate electrode groove is in a rounded rectangular shape, and the groove depth is 3 μm.

[0123] Step 7, forming a gate dielectric 6 on the inner wall of the gate electrode trench obtained in step 6 and on a portion of the upper surface of the n+ epitaxial source region 4. When forming the gate dielectric 6 on the inner wall of the gate electrode trench and on a portion of the upper surface of the n+ epitaxial source region 4, a mask is used to protect the outer area of ​​the gate electrode trench, and a SiO2 layer is formed on the inner surface of the gate electrode trench using a thermal oxidation technique to form a gate dielectric 6 with a thickness of 50 nm.

[0124] Step 8, depositing a gate electrode 7 on the gate dielectric 6 obtained in step 7. When depositing the gate electrode 7 on the gate dielectric 6, a mask is used to protect the outer region of the gate electrode groove, and an electron beam evaporation coating machine is used to deposit the gate electrode 7 on the gate dielectric 6. The metal material of the gate electrode 7 is a Ni / Au stacked layer (30 / 120 nm).

[0125] Step 9, forming source metal 8 on the p+ injection source and n+ epitaxial source region 4 obtained in step 5. When forming source metal 8 on the isolation medium, electron beam evaporation coating machine is used to evaporate source metal 8. The material of source metal 8 is Ti / Au stacked layer (30 / 140nm).

[0126] Step 10, forming a drain metal 9 on the back side of the n-type substrate 1 obtained in step 1. When the drain metal 9 is formed on the back side of the n-type substrate 1, a drain metal 9 is formed at the bottom of the n-type substrate 1 through a thinning process and a back gold process. The material of the drain metal 9 is a Ti / Au stacked layer (30 / 140nm), and finally a Ga2O3 trench MOSFET device based on a heterojunction is formed.

[0127] It should be pointed out here that the description of the above embodiment of the method for preparing a gallium oxide trench MOSFET device based on a heterojunction is similar to the description of the above embodiment of the gallium oxide trench MOSFET device based on a heterojunction, and has similar beneficial effects as the embodiment of the gallium oxide trench MOSFET device based on a heterojunction. For technical details not disclosed in the embodiment of the method for preparing a gallium oxide trench MOSFET device based on a heterojunction according to the embodiment of the present invention, please refer to the description of the embodiment of the gallium oxide trench MOSFET device based on a heterojunction according to the present invention for understanding.

[0128] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A gallium oxide trench MOSFET device based on heterojunction, characterized in that: include: Drain metal; An n-type substrate is located on the upper surface of the drain metal, and the material of the n-type substrate is β-Ga2O3 material; An n-type epitaxial drift region formed on the upper surface of the n-type substrate; A p-type base region is formed on both side edge regions of the n-type epitaxial drift region, and the material of the p-type base region is NiO material; A p+ injection source region is formed in the edge regions on both sides of the p-type base region; An n+ epitaxial source region is formed on the upper surface of the p-type base region; A gate electrode trench extending downward from the upper surface of the n+ epitaxial source region and penetrating the n+ epitaxial source region and the p-type base region, with the bottom thereof being located in the n-type epitaxial drift region; A gate dielectric is formed on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region, and a gate electrode is disposed on the upper surface of the gate dielectric; A source metal is formed on the upper surface of the p+ implanted source region and a portion of the upper surface of the n+ epitaxial source region, and the source metal is in contact with the gate dielectric.

2. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The doping element of the n-type substrate is Sn, and the doping concentration range of the n-type substrate is 3×10 18 ~1×10 19 cm -3 , thickness is 90μm~1500μm.

3. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The thickness of the n-type epitaxial drift region is 10 μm to 500 μm, and the doping concentration ranges from 4×10 15 ~5×10 16 cm -3 .

4. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The thickness of the p-type base region is 300-700 nm, and the hole concentration in the NiO is 1×10 17 ~1×10 19 cm -3 .

5. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The thickness of the n+ epitaxial source region is 200nm-300nm, the doping element is Si, and the doping concentration is 3×10 18 cm -3 ~1×10 19 cm -3 .

6. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The junction depth of the p+ injection source region is 100nm-200nm, the doping element is Li, and the doping concentration range is 3×10 18 ~1×10 19 cm -3 .

7. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The gate electrode trench is in a rounded rectangular shape, and the gate dielectric is made of SiO2 material with a thickness of 20 to 100 nm.

8. The heterojunction-based gallium oxide trench MOSFET device according to claim 1, characterized in that: The metal material of the gate electrode is a Ni / Au stacked layer material, the material of the source metal is a Ti / Au stacked layer material, and the material of the drain metal is a Ti / Au stacked layer material.

9. A method for preparing a gallium oxide trench MOSFET device based on a heterojunction, characterized in that: A heterojunction-based gallium oxide trench MOSFET device applicable to any one of claims 1 to 8, comprising: Forming an n-type epitaxial drift region on the front side of an n-type substrate, wherein the material of the n-type substrate is β-Ga2O3 material; Using radio frequency sputtering equipment, forming a p-type base region on the n-type epitaxial drift region, wherein the material of the p-type base region is NiO material; forming an n+ epitaxial source region on the p-type base region; Etching the edge regions on both sides of the n+ epitaxial source region to form a p+ source region pre-implantation region; Using an ion implantation process, ion implantation is performed in the p+ source region pre-implantation area to form a p+ implantation source region; Etching is performed in the middle area of ​​the n+ epitaxial source region to form a gate electrode trench, wherein the gate electrode trench penetrates the n+ epitaxial source region and the p-type base region and has a bottom located in the n-type epitaxial drift region; forming a gate dielectric on the inner wall of the gate electrode trench and a portion of the upper surface of the n+ epitaxial source region; forming a gate electrode on the gate dielectric; forming a source metal on the p+ implantation source region and the n+ epitaxial source region; A drain metal is formed on the back side of the n-type substrate to obtain the heterojunction-based gallium oxide trench MOSFET device.

10. The method for preparing a heterojunction-based gallium oxide trench MOSFET device according to claim 9, characterized in that: The target material of the RF sputtering equipment is 99.99% pure NiO, the sputtering environment is room temperature and Ar / O2 mixture environment, the sputtering chamber pressure is 3mTorr, the RF power is 100-150W, the NiO deposition rate is 0.75nm / min, the thickness of the p-type base region is 300-700nm, and the hole concentration in the sputtered NiO is 1×10 17 ~1×10 19 cm -3 .

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