Semiconductor device structure and forming method thereof

Abstract

Various embodiments of the present disclosure provide a semiconductor device structure including: a source / drain feature disposed over a substrate; a plurality of semiconductor layers vertically stacked over the substrate and in contact with the source / drain features; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers; and a second dielectric spacer in contact with a second side of a topmost semiconductor layer of the plurality of semiconductor layers. The embodiment of the invention also relates to a semiconductor device structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor device structures and methods for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] In pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including nanosheet FETs. In nanosheet FETs, all sides of the channel region are surrounded by gate electrodes, which allows for more complete depletion in the channel region and less short channel effects due to steeper subthreshold current swings (SS) and smaller drain-induced barrier lowering (DIBL). As transistor dimensions continue to shrink, further improvements in nanosheet FETs are needed. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device structure, including: a source / drain component disposed above a substrate; a plurality of semiconductor layers vertically stacked above the substrate and in contact with the source / drain component; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers; and a second dielectric spacer in contact with a second side of the topmost semiconductor layer of the plurality of semiconductor layers.

[0005] Other embodiments of the present application provide a semiconductor device structure, including: a plurality of first semiconductor layers, arranged at a first device region of a substrate; a first source / drain component, contacting each of the plurality of first semiconductor layers; a first dielectric spacer, contacting a first side of a topmost first semiconductor layer of the plurality of semiconductor layers; a plurality of second semiconductor layers, arranged at a second device region of the substrate; and a second source / drain component, contacting each of the plurality of second semiconductor layers, wherein the number of the plurality of first semiconductor layers is different from the number of the plurality of second semiconductor layers.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming an etch stop layer above a substrate, the etch stop layer having a first concentration of a dopant; forming a semiconductor layer stack on the etch stop layer, the semiconductor layer stack comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked, and each of the plurality of second semiconductor layers having a second concentration of the dopant; oxidizing the first semiconductor layer and the second semiconductor layer and a surface portion of the etch stop layer; removing the dopant from the oxidized surface portion of the second semiconductor layer; flowing an etching gas through the oxidized surface portion of the second semiconductor layer to remove each of the plurality of second semiconductor layers; flowing a deposition gas through the oxidized surface portion of the second semiconductor layer to form a channel layer in the region where the second semiconductor layer was removed; and removing the oxidized surface portion of the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 5 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] FIG. 6A to FIG. 16A The various stages of manufacturing a semiconductor device structure according to some embodiments are along Figure 5 A cross-sectional side view taken at section AA.

[0010] FIG. 6B to FIG. 16B The various stages of manufacturing a semiconductor device structure according to some embodiments are along Figure 5 A cross-sectional side view taken along section BB.

[0011] Figure 6C and FIG. 11C to FIG. 16C The various stages of manufacturing a semiconductor device structure according to some embodiments are along Figure 5 Cross-sectional side view taken at section CC.

[0012] Fig.6D and FIG. 11D to FIG. 16D The various stages of manufacturing a semiconductor device structure according to some embodiments are along Figure 5 Cross-sectional side view taken at section DD.

[0013] Fig.17 and Fig.18 is a perspective view of various stages in the manufacture of a semiconductor device structure according to some alternative embodiments.

[0014] Fig.19A and FIG. 19B to FIG. 22A and Fig. 22B The various stages of manufacturing a semiconductor device structure according to some optional embodiments are as follows Fig.18 A cross-sectional side view taken at section AA.

[0015] FIG. 23A to FIG. 23D to FIG. 24A to FIG. 24D The various stages of manufacturing a semiconductor device structure according to some optional embodiments are as follows Fig.18 Cross-sectional side views taken at sections AA, BB, CC and DD.

[0016] Fig.25A and FIG. 25B to FIG. 29A and Fig.29B The various stages of manufacturing a semiconductor device structure according to some optional embodiments are as follows Fig.18 A cross-sectional side view taken at section AA.

[0017] FIG. 30A to FIG. 30D to FIG. 32A to FIG. 32D The various stages of manufacturing a semiconductor device structure according to some optional embodiments are as follows Fig.18 Cross-sectional side views taken at sections AA, BB, CC and DD.

[0018] Fig.33A and FIG. 33B to FIG. 37A and Fig.37B The various stages of manufacturing a semiconductor device structure according to some optional embodiments are as follows Fig.18 A cross-sectional side view taken at section AA.

[0019] FIG. 38A to FIG. 38D to FIG. 40A to FIG. 40D The various stages of manufacturing a semiconductor device structure according to some optional embodiments are as follows Fig.18 Cross-sectional side views taken at sections AA, BB, CC and DD. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "above," "on," "top," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs, implementations of some aspects of embodiments of the present disclosure may be used in other processes and / or other devices, such as planar FETs, Fin-FETs, horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. It will be readily understood by those of ordinary skill in the art that other modifications that may be made are contemplated within the scope of the embodiments of the present disclosure. In instances where a all-around gate (GAA) transistor structure is employed, the GAA transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0023] Figures 1 to 40D FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 40DAdditional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes is not limiting and may be interchanged.

[0024] Figures 1 to 5 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 , semiconductor device structure 100 is shown as including substrate 101, into which dopants have been implanted to form wells. Substrate 101 may be a semiconductor substrate. Substrate 101 may include crystalline semiconductor materials, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), indium phosphide (InP), or combinations thereof. In one embodiment, substrate 101 is made of silicon. Substrate 101 may be doped or undoped. Substrate 101 may be a bulk semiconductor substrate, such as a bulk silicon substrate of a wafer, a silicon on insulator (SOI) substrate, a multilayer or gradient substrate, etc.

[0025] The substrate 101 may include a first device region 103 for forming an N-type device, such as an NMOS device (e.g., an N-type all-around gate transistor), and a second device region 105 for forming a P-type device, such as a PMOS device (e.g., a P-type all-around gate transistor). In order to distinguish between the first device region 103 and the second device region 105, a well may be formed in the substrate 101 using an N-type dopant and a P-type dopant. In order to form the desired well, the N-type dopant and the P-type dopant are implanted into the substrate 101, depending on the device to be formed. For example, an N-type dopant such as phosphorus or arsenic may be implanted to form an N-type well, while a P-type dopant such as boron may be implanted to form a P-type well. The N-type well and the P-type well may be formed using one or more implantation techniques, such as diffusion implantation, ion implantation (e.g., plasma doping, beamline implantation doping), selective implantation, deep well implantation, etc., or a combination thereof. During the first well implantation (e.g., N-type well) process, masking techniques may also be utilized to mask some areas of the substrate 101 (e.g., the second device area 105) while exposing other areas of the substrate 101 (e.g., the first device area 103). Once the first well implantation process has been completed, the mask is removed to expose the previously masked areas (e.g., the second device area 105), and another mask may be placed over the previously exposed areas (e.g., the first device area 103) during the second well implantation (e.g., P-type well) process. Figure 1In one embodiment shown in FIG. 1 , the substrate 101 includes an N-type well 107 and a P-type well 109. Although the first device region 103 is shown as being adjacent to the second device region 105, it should be understood that the first device region 103 may be disposed at a different region of the substrate 101 away from the second device region 105 in the X direction or the Y direction, and the first device region 103 and the second device region 105 belong to a continuous substrate (e.g., the substrate 101).

[0026] Figure 1 Also shown is a semiconductor layer stack 104 formed over the substrate 101 at the first device region 103 and the second device region 105. The semiconductor layer stack 104 includes semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices, such as nanostructure FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108, and the first semiconductor layers 106 and second semiconductor layers 108 are arranged parallel to each other. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some instances, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. In some embodiments, the first semiconductor layer 106 may be made of SiGe having a Ge concentration of about 30 at.% or more (such as about 35 at.% or more). In some embodiments, the first semiconductor layer 106 may be made of SiGe having a first Ge concentration range, and the second semiconductor layer 108 may be made of SiGe having a second Ge concentration range that is lower than or greater than the first Ge concentration range. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0027] The substrate 101 includes an etch stop layer 111 disposed between the semiconductor layer stack 104 and the well (e.g., the first device region 103 and the second device region 105). The etch stop layer 111 serves as a barrier layer during a subsequent etching process for forming recesses for source / drain features. The etch stop layer 111 may be made of SiGe having a Ge concentration of about 30 at.% or less, such as about 10 at.% to about 30 at.%. In instances where the first semiconductor layer 106 or the second semiconductor layer 108 is formed of SiGe, the etch stop layer 111 may have a Ge concentration that is different from (e.g., less than) the Ge concentration of the first semiconductor layer 106 or the second semiconductor layer 108. Figure 1 In one exemplary embodiment shown in , the first semiconductor layer 106 includes SiGe having a Ge concentration of about 35 at. % or more, the second semiconductor layer 108 includes Si, and the etch stop layer 111 includes SiGe having a Ge concentration of about 30 at. % or less.

[0028] The thickness of the first semiconductor layer 106, the second semiconductor layer 108, and the etch stop layer 111 may vary, depending on the application and / or device performance considerations. In some embodiments, each of the first semiconductor layer 106 and the second semiconductor layer 108 has a thickness T1, T2 of about 2nm to about 30nm, respectively, and the etch stop layer 111 has a thickness T3 of about 2nm to about 30nm. In other embodiments, each of the first semiconductor layer 106 and the second semiconductor layer 108 has a thickness T1, T2 of about 10nm to about 20nm, and the etch stop layer 111 has a thickness T3 of about 10nm to about 20nm. The thickness T1 of the first semiconductor layer 106 may be equal to, less than, or greater than the thickness of the thickness T2 of the second semiconductor layer 108. The thickness T3 may be equal to, less than, or greater than the thickness T1, T2. In an exemplary embodiment, the etch stop layer 111 and each of the first semiconductor layers 106 may have a thickness of about 4nm to about 8nm.

[0029] As will be discussed in more detail below, the first semiconductor layer 106 or the second semiconductor layer 108 may be eventually removed and used to define the vertical distance between adjacent channels for the semiconductor device structure 100. If the first semiconductor layer 106 is too thick, the subsequently formed Ge channel layer (e.g., the filling layer 135, Fig. 8A and Figure 8B) may be too thick and reduce the effectiveness of gate control. If the first semiconductor layer 106 is too thin, the process window for forming the subsequent Ge channel layer may be narrow. In addition, if the thickness of the etch stop layer 111 is too thick, there may be lattice mismatch problems, which in turn introduces defects such as dislocations into the channel layer and / or adjacent layers. If the etch stop layer 111 is too thin, it may not be properly used as a stop layer during the subsequent etching process for forming the recess for the source / drain features.

[0030] The first semiconductor layer 106 or the second semiconductor layer 108 or their portions may form a nanostructure channel of the semiconductor device structure 100 in a later manufacturing stage. The term "nanostructure" is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions, and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to an elongated material portion of a circular and substantially circular cross section, and a beam-shaped or strip-shaped material portion including, for example, a cylindrical or substantially rectangular cross section in shape. The nanostructure channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanowire transistor, a nanosheet transistor, a full-ring gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 is further discussed below.

[0031] The first semiconductor layer 106 and the second semiconductor layer 108 and the etch stop layer 111 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 may be implemented by vapor phase epitaxy (VPE), molecular beam epitaxy (MBE) process, metal organic chemical vapor deposition (MOCVD) process and / or other suitable growth processes, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), combinations thereof, etc. Although the three first semiconductor layers 106 and the three second semiconductor layers 108 are arranged alternately, as shown in FIG. Figure 1 , but any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in semiconductor layer stack 104, depending on the predetermined number of nanostructure channels for each FET. For example, the number of first semiconductor layers 106 (which is the number of channels) may be between 2 and 8.

[0032] exist Figure 2In the embodiment, a fin structure 112 is formed by a semiconductor layer stack 104, and an insulating material 118 is formed in a trench 114 between the fin structures 112. Each fin structure 112 has a portion including semiconductor layers 106, 108, a portion of wells 107, 109, and a portion of a mask structure 110. Before forming the fin structure 112, a mask structure 110 is formed over the semiconductor layer stack 104. The mask structure 110 may include a pad layer 110a and a hard mask 110b. The pad layer 110a may be an oxygen-containing layer. The hard mask 110b may be a nitrogen-containing layer. The fin structure 112 may be manufactured using a suitable process including a photolithography and etching process. In some embodiments, the photolithography process may include: forming a photoresist layer (not shown) over the mask structure 110; exposing the photoresist layer to a pattern; performing a post-exposure baking process; and developing the photoresist layer to form a patterned photoresist layer. The patterned photoresist layer can then be used to protect areas of the substrate 101 and the layers formed thereon, while the etching process forms a groove 114 in the unprotected area through the mask structure 110, the semiconductor layer stack 104 and into the wells 107, 109 of the substrate 101, thereby forming an extended fin structure 112. The width W1 of the fin structure 112 along the Y direction at the first device region 103 can be in a range between about 3nm and about 44nm. The width W2 of the fin structure 112 along the Y direction at the second device region 105 can be equal to, less than, or greater than the width W1. The groove 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof. Although two fin structures 112 are shown, the number of fin structures is not limited to two.

[0033] After forming the fin structures 112, an insulating material 118 is formed in the trenches 114 between the fin structures 112. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as LPCVD, plasma enhanced CVD (PECVD), or flowable CVD (FCVD). Next, the insulating material 118 is recessed to form an isolation region 120. Recessing the insulating material 118 exposes a portion of the fin structure 112. The isolation region 120 may be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 in contact with the wells 107 , 109 .

[0034] exist Figure 3 In the embodiment, a cladding layer 117 is formed over the exposed portion of the fin structure 112. The cladding layer 117 is in contact with the semiconductor layer stack 104. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 include the same material. For example, the cladding layer 117 and the second semiconductor layer 108 may be silicon or include silicon. The cladding layer 117 and the second semiconductor layer 108 will then be removed to create a gap for a gate electrode layer to be subsequently formed. A liner 119 is formed on the top surface of the cladding layer 117 and the insulating material 118. The liner 119 may include a material having a k value less than 7, such as SiO2, SiN, SiCN, SiOC, or SiOCN. The liner 119 may be formed by a conformal process, such as an ALD process. Then, in the trench 114 ( Figure 2 ) and a dielectric material 121 is formed on the liner 119. The dielectric material 121 may be an oxygen-containing material, such as an oxide, formed by FCVD. The oxygen-containing material may have a k value less than about 7, for example, less than about 3. A planarization process, such as a CMP process, may be performed to remove the liner 119 and the portion of the dielectric material 121 formed over the fin structure 112. A portion of the cladding layer 117 disposed on the hard mask 110 b is exposed after the planarization process.

[0035] Next, the liner 119 and the dielectric material 121 are recessed to the level of the topmost first semiconductor layer 106. For example, in some embodiments, after the recessing process, the top surface of the liner 119 and the dielectric material 121 may be flush with the top surface of the topmost first semiconductor layer 106. The recessing process may be a selective etching process that does not substantially affect the semiconductor material of the cladding layer 117. Due to the recessing process, the fin structure 112 ( Figure 2 ) form a groove 123 between them.

[0036] exist Figure 4 In the groove 123 ( Figure 3 ) and on the dielectric material 121 and the liner 119. The dielectric material 125 may include SiO, SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO or other suitable dielectric materials. In some embodiments, the dielectric material 125 includes a high-k dielectric material (e.g., a material having a k value greater than 7). The dielectric material 125 may be formed by any suitable process, such as a CVD, PECVD, FCVD or ALD process. A planarization process, such as a CMP process, is performed until the hard mask 110b of the mask structure 110 is exposed. The planarization process removes the dielectric material 125 and the portion of the cladding layer 117 disposed above the mask structure 110. The liner 119, the dielectric material 121, and the dielectric material 125 may be referred to as a dielectric feature 127 or a hybrid fin. The dielectric feature 127 is used to separate subsequently formed source / drain (S / D) epitaxial features from the adjacent gate electrode layer.

[0037] exist Figure 5 The cladding layer 117 is recessed, and the mask structure 110 is removed. The recessing of the cladding layer 117 can be implemented by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process can be controlled so that the remaining cladding layer 117 is substantially located at the same level as the top surface of the uppermost first semiconductor layer 106 in the semiconductor layer stack 104. The etching process can be a selective etching process that does not substantially affect the dielectric material 125. Removing the mask structure 110 can be implemented by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0038] Thereafter, one or more sacrificial gate structures 130 are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over portions of the fin structures 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and subsequent patterning and etching processes. For example, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography), and the photolithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof.

[0039] By patterning the sacrificial gate structure 130, the semiconductor layer stack 104 of the fin structure 112 is partially exposed on opposite sides of the sacrificial gate structure 130. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region for the semiconductor device structure 100. The fin structure 112 partially exposed on opposite sides of the sacrificial gate structure 130 defines a source / drain (S / D) region for the semiconductor device structure 100. Although two sacrificial gate structures 130 are shown, in some embodiments, three or more sacrificial gate structures 130 may be arranged along the X direction.

[0040] Figure 5 Also shown is the formation of gate spacers 138 on the sidewalls of the sacrificial gate structure 130. The gate spacers 138 can be formed by first depositing a conformal layer that is then etched back to form the sidewall gate spacers 138. For example, the spacer material layer can be conformally disposed on the exposed surface of the semiconductor device structure 100 by an ALD process or any suitable conformal deposition technique. Subsequently, the spacer material layer is anisotropically etched using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from horizontal surfaces (such as the top of the fin structure 112, the cladding layer 117, the dielectric material 125), leaving the gate spacers 138 on the vertical surfaces (such as the sidewalls of the sacrificial gate structure 130). The gate spacers 138 can be made of a dielectric material, such as SiO2, Si3N4, SiC, SiON, SiCN, SiOCN, carbon-doped oxides, nitrogen-doped oxides, porous oxides, air gaps, and / or combinations thereof.

[0041] It should be understood that the capping layer 117 and the dielectric member 127 (i.e., the hybrid fin) are optional and may not be required. In some embodiments where the capping layer 117 and the dielectric member 127 are not present, portions of the sacrificial gate structure 130 and the gate spacer 138 are formed on the fin structure 112 and the insulating material 118, and gaps are formed between the exposed portions of the fin structure 112.

[0042] FIG. 6A to FIG. 16A The various stages of manufacturing the semiconductor device structure 100 according to some embodiments are as follows Figure 5 A cross-sectional side view taken at section AA. FIG. 6B to FIG. 16B The various stages of manufacturing the semiconductor device structure 100 according to some embodiments are as follows Figure 5 A cross-sectional side view taken along section BB. Figure 6C and FIG. 11C to FIG. 16C The various stages of manufacturing the semiconductor device structure 100 according to some embodiments are as follows Figure 5 Cross-sectional side view taken at section CC. Fig.6D and FIG. 11D to FIG. 16D The various stages of manufacturing the semiconductor device structure 100 according to some embodiments are as follows Figure 5 The cross-sectional side view is taken from the cross-sectional view DD of FIG. The cross-sectional views AA and BB are located along the X direction at the fin structure 112 ( Figure 4 ). Section CC is located in a plane perpendicular to section AA and is located in the sacrificial gate structure 130. Section DD is located in a plane perpendicular to section AA and is located in the S / D component 146 ( Fig.11A and Fig. 11B )middle.

[0043] exist FIG. 6A to FIG. 6D In the embodiment of the present invention, the exposed portions of the fin structure 112, the cladding layer 117, and the dielectric material 125 at the first device region 103 and the second device region 105 that are not covered by the sacrificial gate structure 130 and the gate spacer 138 are recessed to form a source / drain (S / D) region. The removal process may include one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. The portions of the fin structure 112, the cladding layer 117, and the dielectric material 125 are removed to expose the fin structure 112 ( Figure 4 ). In some embodiments, the removal process is performed so that the sidewalls of the bottom-most second semiconductor layer 108 of each fin structure 112 are completely exposed, and the sidewalls of the etch stop layer 111 are exposed. In some embodiments, the removal process is performed so that the top surface 111t of the etch stop layer 111 is etched to have a curved profile (e.g., concave), such as Fig.16D The embodiment shown in .

[0044] exist Fig. 7A and Figure 7B In the embodiment, oxide layers 129a, 129b, 129c (collectively referred to as oxide layers 129) are formed on the exposed surfaces of the first semiconductor layer 106, the second semiconductor layer 108, and the etch stop layer 111, respectively. The oxide layers 129a, 129b, 129c may be formed due to a cleaning process and a post-treatment process. The cleaning process may be any suitable wet etching process that converts the surface portions of the first semiconductor layer 106, the second semiconductor layer 108, and the etch stop layer 111 into oxide layers. In an example where the first semiconductor layer 106 includes SiGe having a higher Ge atomic concentration (e.g., about 35 at.% or greater), the second semiconductor layer 108 includes Si, and the etch stop layer 111 includes SiGe having a lower Ge atomic concentration (e.g., about 30 at.% or less), respectively, the oxide layer 129a formed on the surface of the first semiconductor layer 106 may include silicon germanium oxide (SiGeO) having a larger Ge amount, and the oxide layer 129b formed on the surface of the second semiconductor layer 108 may include silicon oxide (SiO), and the oxide layer 129c formed on the surface of the etch stop layer 111 may include SiGeO having a smaller Ge amount. The post-treatment process may be any suitable etching process that selectively removes Ge from SiGeO. Removing germanium from the oxide layers 129a and 129c produces oxide layers 129a, 129b, 129c having different film qualities. For example, oxide layer 129a may become more porous SiO than oxide layer 129b, and oxide layer 129c may become slightly more porous SiO than oxide layer 129b. As will be discussed in more detail below, the greater porosity of oxide layer 129a allows for easy replacement of SiGe with Ge at a later stage.

[0045] The oxide layer 129 may have a Peace If the thickness of the oxide layer 129 is about Below 1000 W, the oxide layer 129 may not be thick enough to serve its intended purpose. If the thickness of the oxide layer 129 is greater than about 1000 W, the oxide layer 129 may not be thick enough to serve its intended purpose. Then chemical gases may have difficulty passing through.

[0046] exist Fig. 8A and Figure 8BIn the embodiment of the present invention, the first semiconductor layer 106 is removed, and the filling layer 135 is refilled in the area where the first semiconductor layer 106 was removed. The filling layer 135 is used as a channel layer for PMOS and NMOS devices and can be made of a semiconductor material. In one embodiment, the filling layer 135 is formed of germanium (e.g., pure Ge). Germanium has attracted much attention as the most promising candidate material for next-generation materials because it has a higher carrier mobility than silicon and is larger than silicon in atomic radius. Due to the lattice mismatch between germanium and silicon, the use of germanium as a material for the filling layer 135 will produce strain (i.e., strained germanium) and thus enhance the channel mobility for transistor devices, particularly PMOS devices (e.g., P-type all-around gate transistors). Although germanium is discussed, other semiconductor materials having an atomic radius larger than the atomic radius of the chemical element (e.g., silicon) used for the second semiconductor layer 108 (e.g., about 0.5 times to about 1.5 times) can also be used. Suitable materials for the filling layer 135 may include, but are not limited to, gallium (Ga), indium (In), tin (Sn), selenium (Se), antimony (Sb), and the like.

[0047] Removing the first semiconductor layer 106 can be accomplished by exposing the semiconductor device structure 100 to an etching gas that is suitable for selectively removing SiGe without substantially affecting SiO. Because the oxide layer 129a is porous, the etching gas can easily flow through the oxide layer 129a and remove the first semiconductor layer 106 without removing the oxide layer 129a. Thereafter, the semiconductor device structure 100 is exposed to a deposition gas 142 to epitaxially grow a filling layer 135 in the area formed by removing the first semiconductor layer 106. Because the filling layer 135 is a semiconductor material, the dielectric properties of the oxide layers 129a, 129b, 129c will prevent the filling layer 135 from growing on the oxide layers 129a, 129b, 129c.

[0048] It has been observed that the ability to effectively remove the first semiconductor layer 106 (e.g., SiGe) and form the filling layer 135 (e.g., Ge) is closely related to the porosity of the oxide layer 129a. Therefore, the Ge concentration in the first semiconductor layer 106 should be carefully controlled so that the etching gas and the deposition gas can pass through the oxide layer 129a without affecting the integrity of the oxide layer 129a. If the Geat.% is not high enough (e.g., less than about 30at.%), the porosity of the oxide layer 129a may not be enough to allow the chemical gas to easily pass through the oxide layer 129a, resulting in ineffective removal of the first semiconductor layer 106 (e.g., SiGe) and defective formation of the filling layer 135 (e.g., Ge). On the other hand, if the Geat.% is too high (e.g., greater than about 80at.%), the porosity in the oxide layer 129a may be too large and reduce the mechanical strength of the oxide layer 129a. Therefore, during the removal of the first semiconductor layer 106 and / or the formation of the filling layer 135, the integrity of the oxide layer 129a is weakened.

[0049] Likewise, if the Ge at.% of the etch stop layer 111 is too high (e.g., greater than about 35 at.%), selectivity may not exist between SiGe (e.g., the first semiconductor layer 106) and the etch stop layer 111 when forming the filling layer 135. On the other hand, if the Ge at.% of the etch stop layer 111 is too small (e.g., less than about 10 at.%), selectivity may not exist between SiGe (e.g., the etch stop layer 111) and Si (e.g., the second semiconductor layer 108).

[0050] exist Fig. 9A and Fig. 9B , an edge portion of each second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed along the X direction. During the removal of the second semiconductor layer 108, the oxide layers 129a, 129b, 129c are also removed. In some embodiments, a single extended etching process can be performed to remove the oxide layers 129a, 129b, 129c and the second semiconductor layer 108. Alternatively, a first etching process can be performed to remove the oxide layers 129a, 129b, 129c, and a second etching process can be performed to remove a portion of the second semiconductor layer 108. In either instance, the etching process is selective so that the fill layer 135 is not substantially etched. Removing the edge portion of the second semiconductor layer 108 forms the cavity 131.

[0051] exist Fig. 10A and Fig. 10B In the cavity 131 ( Fig. 9A and Fig. 9B) is filled with dielectric spacers 144. The internal spacers 144 can be formed by conformally forming a dielectric layer on the exposed surfaces of the sacrificial gate structure 130, the filling layer 135, the second semiconductor layer 108 and the etch stop layer 111, and a subsequent anisotropic etching process to remove part of the dielectric layer. The dielectric layer can be made of a dielectric material. Suitable materials for the dielectric layer 144a may include, but are not limited to, SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN and / or other suitable materials. Other materials, such as low-k materials with a k value of less than about 3.5, may also be used. The formation of the dielectric layer can be formed by a conformal deposition process such as ALD. The etching process can use an etchant that selectively removes the dielectric layer without substantially removing the gate spacers 138, the filling layer 135, the second semiconductor layer 108 and the etch stop layer 111. During the anisotropic etching process, the dielectric layer in the cavity 131 is protected by the filling layer 135. The remaining second semiconductor layer 108 covers between the inner spacers 144 along the X direction.

[0052] exist Fig.11A and Fig. 11B In the embodiment of the present invention, epitaxial S / D components 146, 147 are formed in the source / drain (S / D) regions at the first device region 103 and the second device region 105. The epitaxial S / D components 146, 147 can be made of one or more layers of Si, SiP, SiC, SiAs and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-type dopants such as boron (B) can also be included in the epitaxial S / D components 146. For n-channel FETs, n-type dopants such as phosphorus (P) or arsenic (As) can also be included in the epitaxial S / D components 147. The epitaxial S / D components 146, 147 can be formed by epitaxial growth methods using CVD, ALD or MBE. In some embodiments, the epitaxial S / D components 146 for PMOS devices are boron-doped silicon (Si:B), boron-doped germanium (Ge:B) or boron-doped silicon germanium (SiGe:B). In one exemplary embodiment, the epitaxial S / D features 146 are of a thickness of about 1E20 atoms / cm 3 to about 5E21 atoms / cm 3 Boron-rich silicon germanium (SiGeB) having a boron concentration in a range of , wherein the Ge concentration is about 15 at. % to about 80 at. %.

[0053] exist FIG. 12A to FIG. 12DIn the embodiment of the present invention, after forming the S / D features 146, 147, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the S / D features 146, 147, the gate spacer 138, and the dielectric material 125 at the first device region 103 and the second device region 105. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material for the ILD layer 164 may include an oxide formed with tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials including Si, O, C, and / or H. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition technique.

[0054] exist FIG. 13A to FIG. 13D In the embodiment, after the ILD layer 164 has been formed, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 to remove portions of the ILD layer 164 , the CESL 162 , and the mask layer 136 until the sacrificial gate electrode layer 134 is exposed.

[0055] exist FIG. 14A to FIG. 14D , the sacrificial gate structure 130, the cladding layer 117, and the second semiconductor layer 108 are removed from the semiconductor device structure 100 at the first device region 103 and the second device region 105. Removing the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening 166 between the gate spacers 138 and between the filling layer 135. The ILD layer 164 protects the S / D epitaxial components 146, 147 during the removal process. Because the bottom-most second semiconductor layer 108 and the substrate 101 are formed of the same material (e.g., silicon), the use of the etch stop layer 111 creates an etch selectivity relative to the substrate 101, and thus prevents the etchant from over-etching the top portion of the substrate 101, which may otherwise form an oversized gate electrode layer if the etch stop layer 111 is not provided.

[0056] The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 may be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by removal of the sacrificial gate dielectric layer 132, which may also be implemented by any suitable process, such as dry etching, wet etching, or a combination thereof. After removing the sacrificial gate structure 130, the cladding layer 117 and the second semiconductor layer 108 are exposed. Removing the cladding layer 117 and the second semiconductor layer 108 exposes the filling layer 135. The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may use an etchant that selectively removes the cladding layer 117 and the second semiconductor layer 108 without substantially removing the gate spacer 138, the ILD layer 164, the CESL 162, the dielectric material 125, and the filling layer 135. When removing the sacrificial gate structure 130 and the second semiconductor layer 108, a portion of the filling layer 135 is exposed in the opening 166.

[0057] exist FIG. 15A to FIG. 15D , a replacement gate structure 190 is formed in a region provided by removing the capping layer 117 and the second semiconductor layer 108 at the first device region 103 and the second device region 105. The replacement gate structures 190 each include an interface layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182a / 182b. The interface layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106. IL 178 may also be formed on the exposed etch stop layer 111. IL 178 may include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, nitride oxide, hafnium silicate, etc. In one embodiment, IL 178 is silicon oxide. IL 178 may be formed by CVD, ALD, a cleaning process, or any suitable process. Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the gate dielectric layer 180 is formed to wrap around IL 178 and contact IL 178. The gate dielectric layer 180 is also formed on and in contact with the liner 119 and the dielectric material 125 ( Fig. 15C and Fig.15D). The gate dielectric layer 180 may include or be made of a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (Al2O3), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), an oxide of a nitrogen-doped dielectric combined with a metal-content high-k dielectric (having a k value>13), or other suitable dielectrics having a k value ≥9. The gate dielectric layer 180 may be a conformal layer formed by a conformal process such as an ALD process or a CVD process.

[0058] After forming the IL 178 and the gate dielectric layer 180, the gate electrode layer 182a / 182b is formed over the gate dielectric layer 180. The gate electrode layer 182a may be formed to fill the opening 166 ( Fig.14A and Fig. 14B) and completely surrounds each portion of the first semiconductor layer 106 at the second device region 105. The gate electrode layer 182b can be formed to fill the opening 166 and completely surround each portion of the first semiconductor layer 106 at the first device region 103. In some embodiments, the gate electrode layers 182a, 182b can be formed using multiple layers, each layer being deposited sequentially adjacent to each other using a highly conformal deposition process such as ALD. Other deposition techniques such as PVD, CVD or electroplating can also be used. Although not shown, the gate electrode layer 182a may include a capping layer, a barrier layer, an n-metal work function layer, a p-metal work function layer, and a filling material. The capping layer and the barrier layer may be metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations of these, and the like. The barrier layer may be formed of a material different from the capping layer. The n-metal work function layer may be formed of a metal material such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The p-metal work function layer may be formed of a metal material such as W, Al, Cu, TiN, Ti, TiAlN, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, AlCu, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, and the like. Once the n-metal work function layer and the p-metal work function layer are formed, a filling material is deposited to fill the remaining portion of the opening 166. The filling material can be a material such as W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, etc.

[0059] Similarly, gate electrode layer 182b can be formed using multiple layers and materials similar to those of gate electrode layer 182a discussed above. In some embodiments, one or more of the layers within gate electrode layer 182a and gate electrode layer 182b can be formed during the same series of steps. For example, capping layers and barrier layers in gate electrode layer 182a and gate electrode layer 182b can be formed simultaneously, while other layers such as n-metal work function layers and p-metal work function layers can be formed and / or patterned independently of each other. Gate electrode layer 182a and gate electrode layer 182b can be formed using any suitable combination of deposition and removal.

[0060] Once openings 166 have been filled, the material of gate electrode layers 182 a and 182 b may be planarized by a planarization process (eg, CMP) to remove any material outside of the openings left by the removal of sacrificial gate electrode layer 134 .

[0061] exist FIG. 16A to FIG. 16D In the embodiment of the present invention, the gate electrode layers 182a, 182b may be subjected to one or more metal gate etch back (MGEB) processes. The MGEB process is performed so that the top surfaces of the gate electrode layers 182a, 182b and the gate dielectric layer 180 are recessed to a level below the top surface of the gate spacer 138. In some embodiments, the gate spacer 138 is also recessed to a level below the top surface of the ILD layer 164. A self-aligned contact layer 173 is formed above the gate dielectric layer 180 between the gate electrode layers 182a, 182b and the gate spacer 138. The self-aligned contact layer 173 may be a dielectric material having an etch selectivity relative to the ILD layer 164. In some embodiments, the self-aligned contact layer 173 may be a dielectric material, such as silicon nitride or a high-k dielectric layer. Once formed, the self-aligned contact layer 173 may be planarized using a planarization process such as CMP.

[0062] After forming the self-aligned contact layer 173, a contact opening is formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D components 146, 147. A silicide layer 184 is then formed on the S / D epitaxial components 146, 147, and an S / D contact 186 is formed in the contact opening on the silicide layer 184. The contact 186 may include a conductive material such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations of these, and the like. Silicidation may be performed by blanket deposition of an appropriate metal layer and a subsequent annealing step that reacts the metal with the exposed silicon below. The unreacted metal is then removed, such as by a selective etching process. The contact 186 may be formed in the contact opening using sputtering, CVD, electroplating, chemical plating, and the like to fill and / or overfill the contact opening. Any deposited material outside the contact opening may be removed using a planarization process such as CMP.

[0063] The semiconductor device structure 100 may then undergo further complementary metal oxide semiconductor (CMOS) and / or back end of line (BEOL) processes to form various components such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. Fig.16D According to some optional embodiments Fig.16A and Fig. 16B1 is an enlarged view of a portion of the semiconductor device structure 100 shown in FIG. Although the etch stop layer 111 is shown in various figures of the present embodiment as having a substantially flat top surface, it is contemplated that during the removal of a portion of the fin structure 112 ( FIG. 6A to FIG. 6D ), the etch stop layer 111 can be etched to have a curved profile (e.g., concave). The etch stop layer 111 having such a curved profile is suitable for other embodiments of the present disclosure. Therefore, the epitaxial S / D features 146, 147 are formed to have a curved bottom surface 146b / 147b.

[0064] Figures 17 to 24D An exemplary process for fabricating a semiconductor device structure 200 according to another embodiment of the present disclosure is shown. Figures 17 to 24D An embodiment similar to Figures 1 to 16D , except that the semiconductor layer stack 204 includes 4 layers of the first semiconductor layer 206 and 3 layers of the second semiconductor layer 208 alternately arranged above the etch stop layer 111. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 206 can be made of Si, and the second semiconductor layer 208 can be made of SiGe. In some embodiments, the first semiconductor layer 206 can be made of SiGe with a Ge concentration of about 30at.% or more (such as about 35at.% to about 80at.%).

[0065] exist Fig.19A and Fig.19B In the embodiment, the exposed portions of the semiconductor layer stack 204, the cladding layer 117, and the dielectric material 125 at the first device region 103 and the second device region 105 that are not covered by the sacrificial gate structure 130 and the gate spacer 138 are recessed to form a source / drain (S / D) region. The removal process may include one or more suitable etching processes, and may be implemented so that the sidewalls of the bottommost second semiconductor layer 108 of the semiconductor layer stack 204 are completely exposed, and the sidewalls of the etch stop layer 111 are exposed.

[0066] exist Fig. 20A and Fig. 20B In the embodiment, oxide layers 229a, 229b, 229c (collectively referred to as oxide layers 229) are formed on the exposed surfaces of the first semiconductor layer 206, the second semiconductor layer 208, and the etching stop layer 111, respectively. The oxide layers 229a, 229b, 229c may be formed in the same manner as described above. Fig. 7A and Figure 7BThe oxide layers 129a, 129b, 129c discussed are formed in a similar manner due to the cleaning process and the post-treatment process. In an example where the first semiconductor layer 206 includes Si, the second semiconductor layer 208 includes SiGe with a higher Ge atomic concentration (e.g., about 35 at.% or greater), and the etch stop layer 111 includes SiGe with a lower Ge atomic concentration (e.g., about 30 at.% or less), respectively, the oxide layer 229b formed on the surface of the second semiconductor layer 208 may include silicon germanium oxide (SiGeO) with a larger Ge amount, and the oxide layer 229a formed on the surface of the first semiconductor layer 206 may include silicon oxide (SiO), and the oxide layer 229c formed on the surface of the etch stop layer 111 may include SiGeO with a smaller Ge amount. The post-treatment process may be any suitable etching process that selectively removes Ge from SiGeO. Removing germanium from the oxide layers 229b and 229c produces oxide layers 229a, 229b, 229c with different film qualities. For example, oxide layer 229b may become more porous SiO than oxide layer 229a, and oxide layer 229c may become slightly more porous SiO than oxide layer 229a. As previously discussed, the greater porosity of oxide layer 229b allows for easy replacement of SiGe with Ge at a later stage.

[0067] The oxide layer 229 may have a Peace If the thickness of the oxide layer 229 is about Below 1000 W, the oxide layer 129 may not be thick enough to serve its intended purpose. If the thickness of the oxide layer 229 is greater than about 1000 W, the oxide layer 129 may not be thick enough to serve its intended purpose. Then chemical gases may have difficulty passing through.

[0068] exist Fig.21A and Fig. 21B In the embodiment of the present invention, the second semiconductor layer 208 is removed, and a filling layer 235, such as the filling layer 135, is refilled in the area where the second semiconductor layer 208 was removed. The filling layer 235 serves as a channel layer for PMOS and NMOS devices and can be made of a semiconductor material. In one embodiment, the filling layer 235 is formed of germanium (e.g., pure Ge). Due to the lattice mismatch between germanium and silicon, the use of germanium as a material for the filling layer 235 will produce strain (i.e., strained germanium) and thus enhance the channel mobility for transistor devices, particularly PMOS devices (e.g., P-type all-around gate transistors). Similarly, although germanium is discussed, other semiconductor materials having an atomic radius larger than the atomic radius of the chemical element (e.g., silicon) used for the first semiconductor layer 206 (e.g., about 0.5 times to about 1.5 times) can also be used. The filling layer 235 can be formed in the same manner as described above with respect to Fig. 8Aand Figure 8B The fill layer 135 discussed above is formed in a similar manner. Because the oxide layer 229b is porous, the etching gas can easily flow through the oxide layer 229b and remove the second semiconductor layer 208 without removing the oxide layer 229b. Thereafter, the semiconductor device structure 200 is exposed to the deposition gas 242 to epitaxially grow the fill layer 235 in the area formed by removing the second semiconductor layer 208. Likewise, the Ge concentration in the second semiconductor layer 208 should be carefully controlled (e.g., about 35 at.% to about 80 at.%) so that the chemical gas can pass through the oxide layer 229b without affecting the integrity of the oxide layer 229b.

[0069] exist Fig.22A and Fig. 22B , the oxide layers 229a, 229b, 229c are removed, and the edge portions of each first semiconductor layer 206 of the semiconductor layer stack 204 are horizontally removed along the X direction. The etching process is selective so that the filling layer 235 is substantially not etched. The edge portions of the first semiconductor layer 206 are removed to form a cavity, which is then filled with a dielectric material to form an internal spacer 144. Thereafter, epitaxial S / D components 146, 147 are formed in the source / drain (S / D) regions of the first device region 103 and the second device region 105. The epitaxial S / D components 146, 147 may grow laterally from the sidewalls of the filling layer 235 and form facets corresponding to the crystal planes of the material of the filling layer 235. In some embodiments, the top surfaces of the epitaxial S / D components 146, 147 are located at substantially the same height as the top surface of the topmost filling layer 235. As described above with respect to FIG. 9A to FIG. 9B to FIG. 12A to FIG. 12B A contact etch stop layer (CESL) 162 and an interlayer dielectric (ILD) layer 164 are sequentially formed over the semiconductor device structure 200 in a manner similar to that discussed above.

[0070] In some embodiments, the topmost dielectric spacer 144 at the first device region 103 may have a thickness T9 in a range of about 3 nm to about 8 nm, and the topmost dielectric spacer 144 at the second device region 105 may have a thickness T10 in a range of about 2 nm to about 9 nm. If the thickness T9 and the thickness T10 of the topmost dielectric spacer 144 at the first device region 103 and the second device region 105 are greater than about 9 nm, the resistance may increase. On the other hand, if the thickness T9 and the thickness T10 of the topmost dielectric spacer 144 at the first device region 103 and the second device region 105 are less than about 2 nm, the gate-to-source / drain parasitic capacitance may increase.

[0071] exist FIG. 23A to FIG. 23DIn the embodiment, after the ILD layer 164 has been formed, a planarization operation, such as CMP, is performed on the semiconductor device structure 200 to remove portions of the ILD layer 164, the CESL 162, and the mask layer 136 until the sacrificial gate electrode layer 134 is exposed. Then, the sacrificial gate structure 130, the cladding layer 117, and the first semiconductor layer 206 are removed from the semiconductor device structure 200 at the first device region 103 and the second device region 105. When the sacrificial gate structure 130 and the first semiconductor layer 206 are removed, portions of the fill layer 235 are exposed.

[0072] In some embodiments, when first semiconductor layer 206 is removed for replacement of gate structure, filler layer 235 may be consumed. In such an example, each filler layer 235 at first device region 103 and second device region 105 may have a thickness T11 less than thickness T10 of topmost dielectric spacer 144.

[0073] exist FIG. 24A to FIG. 24D In the embodiment, replacement gate structures 190 are formed in the regions provided by removing the cladding layer 117 and the second semiconductor layer 108 at the first device region 103 and the second device region 105. The replacement gate structures 190 each include an interfacial layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182a / 182b, and may be formed in the same manner as described above with respect to FIG. 15A to FIG. 15D Thereafter, the gate electrode layer 182a and the gate electrode layer 182b are planarized by a planarization process, and an MGEB process is performed so that the top surfaces of the gate electrode layers 182a, 182b and the gate dielectric layer 180 are recessed to a level below the top surface of the gate spacer 138. Then, a self-aligned contact layer 173 is formed over the gate dielectric layer 180 between the gate electrode layers 182a, 182b and the gate spacer 138.

[0074] After forming the self-aligned contact layer 173, contact openings are formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D features 146, 147. A silicide layer 184 is then formed on the S / D epitaxial features 146, 147, and an S / D contact 186 is formed in the contact opening on the silicide layer 184. Any deposited material outside the contact opening may be removed using a planarization process such as CMP.

[0075] like Fig.24A and Fig. 24B, two opposite ends or edge portions of the topmost Ge channel layer (i.e., fill layer 235) at the first device region 103 and the second device region 105 are disposed between and in contact with the inner spacers 144 in a symmetrical manner. Because the first semiconductor layer 206 has been previously removed, the topmost dielectric spacer 144 is now disposed between the gate electrode layer 182a / 182b and the S / D contact 186. Therefore, the gate-to-source / drain parasitic capacitance of the NMOS and PMOS devices is minimized due to the added dielectric (represented by distances S1 and S2, respectively) in combination with the topmost dielectric spacer 144 and the CESL 162.

[0076] FIG. 25A to FIG. 25B to FIG. 32A to FIG. 32D An exemplary process for fabricating a semiconductor device structure 300 according to yet another embodiment of the present disclosure is shown. FIG. 25A to FIG. 25B to FIG. 32A to FIG. 32D An embodiment similar to Figures 17 to 24D The embodiment shown in FIG. 1 is different in that the NMOS and PMOS devices in the first device region 103 and the second device region 105 use different numbers / materials of channel layers. Fig.25A and Fig.25B 1 shows a stage of the semiconductor device structure 300 after forming source / drain (S / D) regions, such as Fig.19A and Fig.19B . After forming the S / D regions, a hard mask layer 137 is deposited on the exposed surface of the semiconductor device structure 300 at the first device region 103 and the second device region 105. The hard mask layer 137 will be patterned into a subsequent processing area for one type of device, such as an N-type device in the first device region 103 or a P-type device at the second device region 105. In some embodiments, the hard mask layer 137 is an oxide, such as aluminum oxide (AlO x ). Thereafter, a photolithography process is performed to pattern the hard mask layer 137 to expose a processing area for one type of device, such as an N-type device area or a P-type device area. The first device area 103 remains protected by the hard mask layer 137. In an exemplary embodiment, the hard mask layer 137 at the second device area 105 is patterned to expose an area above the N-type well 107 where a P-type device will be formed.

[0077] After the photolithography process, oxide layers 329a, 329b, 329c (collectively referred to as oxide layers 329) are formed on the exposed surfaces of the first semiconductor layer 206, the second semiconductor layer 208, and the etch stop layer 111, respectively. The oxide layers 329a, 329b, 329c may be formed in the same manner as described above. Fig. 7A and Figure 7BThe oxide layers 129a, 129b, 129c discussed are formed in a similar manner due to the cleaning process and the post-treatment process. In an example where the first semiconductor layer 206 includes Si, the second semiconductor layer 208 includes SiGe with a higher Ge atomic concentration (e.g., about 35 at.% or greater), and the etch stop layer 111 includes SiGe with a lower Ge atomic concentration (e.g., about 30 at.% or less), respectively, the oxide layer 329b formed on the surface of the second semiconductor layer 208 may include silicon germanium oxide (SiGeO) with a larger Ge amount, and the oxide layer 329a formed on the surface of the first semiconductor layer 206 may include silicon oxide (SiO), and the oxide layer 329c formed on the surface of the etch stop layer 111 may include SiGeO with a smaller Ge amount. The post-treatment process may be any suitable etching process that selectively removes Ge from SiGeO. Removing germanium from the oxide layers 329b and 329c produces oxide layers 329a, 329b, 329c with different film qualities. For example, oxide layer 329b may become more porous SiO than oxide layer 329a, and oxide layer 329c may become slightly more porous SiO than oxide layer 329a. As previously discussed, the greater porosity of oxide layer 329b allows for easy replacement of SiGe with Ge at a later stage.

[0078] exist Fig.26A and Fig.26B In the embodiment of the present invention, the second semiconductor layer 208 is removed, and a filling layer 335, such as the filling layer 135, is refilled in the area where the second semiconductor layer 208 was removed. The filling layer 335 serves as a channel layer for the PMOS device at the second device region 105, and can be made of a semiconductor material. In one embodiment, the filling layer 335 is formed of germanium (e.g., pure Ge). Due to the lattice mismatch between germanium and silicon, the use of germanium as a material for the filling layer 335 will produce strain (i.e., strained germanium) and thus enhance the channel mobility for transistor devices, particularly PMOS devices (e.g., P-type all-around gate transistors). Similarly, although germanium is discussed, other semiconductor materials having an atomic radius larger than the atomic radius of the chemical element (e.g., silicon) used for the first semiconductor layer 206 (e.g., about 0.5 times to about 1.5 times) can also be used. The filling layer 335 can be formed in the same manner as described above with respect to Fig. 8A and Figure 8BThe fill layer 135 discussed above is formed in a similar manner. Because the oxide layer 329b is porous, the etching gas can easily flow through the oxide layer 329b and remove the second semiconductor layer 208 without removing the oxide layer 329b. Thereafter, the semiconductor device structure 300 is exposed to the deposition gas 342 to epitaxially grow the fill layer 335 in the area formed by removing the second semiconductor layer 208. Likewise, the Ge concentration in the second semiconductor layer 208 should be carefully controlled (e.g., about 35 at.% to about 80 at.%) so that the chemical gas can pass through the oxide layer 329b without affecting the integrity of the oxide layer 329b.

[0079] exist Fig.27A and Fig.27B In the embodiment, the oxide layers 329a, 329b, 329c are removed, and the edge portion of each first semiconductor layer 206 of the semiconductor layer stack 204 at the second device region 105 is removed horizontally along the X direction. The etching process is selective so that the filling layer 335 is not substantially etched. The edge portion of the first semiconductor layer 206 is removed to be consistent with the above description of Fig.22A and Fig. 22B The cavity is formed in a similar manner as discussed above and then filled with a dielectric material to form the internal spacer 144 .

[0080] exist Fig.28A and Fig.28B In the embodiment, after forming the inner spacer 144 at the second device region 105, a hard mask layer 139, such as the hard mask layer 137, is deposited on the exposed surface of the semiconductor device structure 300 at the second device region 105. Thereafter, a photolithography process is performed to pattern the hard mask layer 139 to expose the processing area at the first device region 103. Then, the edge portion of each second semiconductor layer 208 of the semiconductor layer stack 204 at the first device region 103 is horizontally removed along the X direction. The edge portion of the second semiconductor layer 208 is removed to be consistent with the above description of Fig.22A and Fig. 22B The cavity is formed in a similar manner as discussed above and then filled with a dielectric material to form the internal spacer 144 .

[0081] exist Fig.29A and Fig.29BIn the embodiment of the present invention, epitaxial S / D features 146, 147 are formed in source / drain (S / D) regions of the first device region 103 and the second device region 105. The epitaxial S / D features 146, 147 can be laterally grown from the fill layer 335 and the first semiconductor layer 206, respectively. The epitaxial S / D features 146, 147 can form facets corresponding to crystal planes of the materials of the fill layer 335 and the first semiconductor layer 206. Due to different growth rates on different materials and the fact that the first semiconductor layer 206 at the first device region 103 and the fill layer 335 at the second device region 105 are arranged at different heights (due to the patterning process ( FIG. 25B to FIG. 27B ), the epitaxial S / D components 146, 147 are grown to have different heights. In an exemplary embodiment, the epitaxial S / D component 147 at the first device region 103 may have a first height H1, and the epitaxial S / D component 146 at the second device region 105 may have a second height H2 shorter than the first height H1. FIG. 9A to FIG. 9B to FIG. 12A to FIG. 12B A contact etch stop layer (CESL) 162 and an inter-layer dielectric (ILD) layer 164 are formed over the semiconductor device structure 300 in a similar manner as discussed above.

[0082] exist FIG. 30A to FIG. 30D In the embodiment of the present invention, after the ILD layer 164 has been formed, a planarization operation such as CMP is performed on the semiconductor device structure 300 to remove portions of the ILD layer 164, the CESL 162, and the mask layer 136 until the sacrificial gate electrode layer 134 is exposed. The sacrificial gate electrode layer 134 at the first device region 103 has a first height, and the sacrificial gate electrode layer 134 at the second device region 105 has a second height greater than the first height. Then, the sacrificial gate structure 130, the cladding layer 117, the first semiconductor layer 206, and the second semiconductor layer 208 are removed from the semiconductor device structure 300 at the first device region 103 and the second device region 105, respectively. The etchant is selective so that the etch stop layer 111 is substantially not etched during the removal of the first semiconductor layer 206 and the second semiconductor layer 208. When the sacrificial gate structure 130 and the first semiconductor layer 206 are removed, portions of the filling layer 335 at the second device region 105 are exposed. Likewise, after removing the sacrificial gate structure 130 and the second semiconductor layer 208 , a portion of the first semiconductor layer 206 at the first device region 103 is exposed.

[0083] exist FIG. 31A to FIG. 31DIn the embodiment, replacement gate structures 190 are formed in the regions provided by removing the cladding layer 117 and the second semiconductor layer 208 at the first device region 103 and the second device region 105. The replacement gate structures 190 each include an interfacial layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182a / 182b, and may be formed in the same manner as described above with respect to FIG. 15A to FIG. 15D Thereafter, the gate electrode layer 182a and the gate electrode layer 182b are planarized by a planarization process.

[0084] exist FIG. 32A to FIG. 32D In the embodiment of the present invention, the gate electrode layers 182a, 182b may be subjected to one or more metal gate etch back (MGEB) processes such that the top surfaces of the gate electrode layers 182a, 182b and the gate dielectric layer 180 are recessed to a level below the top surface of the gate spacer 138. A self-aligned contact layer 173 is then formed over the gate dielectric layer 180 between the gate electrode layers 182a, 182b and the gate spacer 138. After the self-aligned contact layer 173 is formed, a contact opening is formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D features 146, 147. A silicide layer 184 is then formed on the S / D epitaxial features 146, 147, and an S / D contact 186 is formed in the contact opening on the silicide layer 184. Any deposited material outside the contact opening may be removed using a planarization process such as CMP.

[0085] like Fig.32A and Fig.32B As can be seen in FIG. 1 , the NFET at the first device region 103 and the PFET at the second device region 105 are formed with staggered channels and different S / D contact heights, which is partly due to the patterning process used for the NFET (i.e., FIG. 25B to FIG. 27B ) and the fact that different semiconductor layers have been removed for the channel layer (i.e., Fig. 30A and Fig. 30B ). The channel layers of the NFET at the first device region 103 and the PFET at the second device region 105 are not aligned. In particular, the topmost channel layer at the first device region 103 (i.e., the topmost first semiconductor layer 206 ( Fig.25B )) is located at a first height, and the topmost channel layer at the second device region 105 (ie, the topmost filling layer 335 ( Fig.29A)) is located at a second height different from (e.g., lower than) the first height, resulting in different metal gate heights on the topmost channel layer at the first device region 103 and the second device region 105. In other words, the bottom surface 182b-1 of the gate electrode layer 182b at the first device region 103 is located at a different height than (e.g., higher than) the bottom surface 182a-1 of the gate electrode layer 182a at the second device region 105.

[0086] Two opposite ends or edge portions of the topmost channel layer (i.e., the first semiconductor layer 206) at the first device region 103 have a first side in contact with the dielectric spacers 144 and a second side in contact with the gate spacers 138. Two opposite ends or edge portions of the topmost channel layer (i.e., the filling layer 335) at the second device region 105 are disposed between and in contact with the dielectric spacers 144. Therefore, the gate-to-source / drain parasitic capacitance of the PMOS device is minimized due to the added dielectric body (represented by the distance S3) in combination with the topmost dielectric spacer 144 and the CESL 162.

[0087] The epitaxial S / D feature 147 at the first device region 103 has a first height H1, and the epitaxial S / D feature 146 at the second device region 105 has a second height H2 less than the first height H1. Correspondingly, the S / D contact 186 at the first device region 103 has a third height H3, and the S / D contact 186 at the second device region 105 has a fourth height H4 greater than the third height H3. Although the etch stop layer 111 at the first device region 103 and the second device region 105 is located at the same height, the channel layer (i.e., the first semiconductor layer 206) above the etch stop layer 111 at the first device region 103 has a first number, and the channel layer (i.e., the filling layer 335) above the etch stop layer 111 at the second device region 105 has a second number different from (e.g., greater than) the first number. Therefore, the channel mobility for the PMOS device is enhanced due to the use of strained Ge as the channel layer, and the channel mobility for the NMOS device is also enhanced due to the increased number of the channel layer.

[0088] In some embodiments, the dielectric spacer 144 at the first device region 103 may have a thickness T4, and each first semiconductor layer 206 at the first device region 103 may have a thickness T5 substantially the same as the thickness T1. The dielectric spacer 144 at the second device region 105 may have a thickness T6, and each filling layer 335 at the second device region 105 may have a thickness T7 less than the thickness T6.

[0089] In some embodiments, thickness T4 is about 0.1 nm to about 3 nm greater than thickness T5. If thickness T4 is greater than about 3 nm, the thickness of the channel layer (ie, first semiconductor layer 206) may be reduced, resulting in increased gate-to-source / drain parasitic capacitance for the NMOS device.

[0090] In some embodiments, when the second semiconductor layer 208 is removed for replacing the gate structure, the first semiconductor layer 206 may be consumed. In such an example, the gate electrode layer 182b at the first device region 103 may have a thickness T8 that is substantially the same as the thickness T5.

[0091] FIG. 33A to FIG. 33B to FIG. 40A to FIG. 40D An exemplary process for fabricating a semiconductor device structure 400 according to another embodiment of the present disclosure is shown. FIG. 33A to FIG. 33B to FIG. 40A to FIG. 40D An embodiment similar to FIG. 25A to FIG. 25B to FIG. 32A to FIG. 32D The embodiment shown in , differs in that the NFET channel is strained silicon. Fig.33A and Fig.33B 4 shows a stage of the semiconductor device structure 400 after an oxide layer 229 is formed on the exposed surfaces of the first semiconductor layer 206, the second semiconductor layer 208, and the etch stop layer 111, respectively. Fig. 20A and Fig. 20B The semiconductor device structure 200 is shown in FIG.

[0092] exist Fig.34A and Fig.34B In the embodiment, the second semiconductor layer 208 is removed, and the Fig.21A and Fig. 21B In a similar manner as discussed above, a filling layer 235 is refilled in the region where the second semiconductor layer 208 was removed, such as the filling layer 135. Due to the lattice mismatch between germanium and silicon, the first semiconductor layer 206 at the first device region 103 is formed to have strain (i.e., strained silicon). Therefore, the channel mobility for the NMOS transistor device (e.g., N-type all-around gate transistor) is improved.

[0093] exist Fig.35A and Fig.35B In the embodiment of the present invention, a hard mask layer 157, such as the hard mask layer 137 discussed above, is deposited on the exposed surface of the semiconductor device structure 400 at the first device region 103 and the second device region 105. The hard mask layer 157 at the first device region 103 is patterned to expose the area above the P-type well 109 where the N-type device will be formed. The hard mask layer 157 can be patterned in the same manner as described above with respect to Fig.25B The oxide layer 229 at the first device region 103 is removed and the device is formed in the same manner as discussed above. Fig.22Aand Fig. 22B The inner spacer 144 is formed in a similar manner as discussed above by replacing the edge portion of the fill layer 235 with a dielectric layer.

[0094] exist Fig.36A and Fig.36B , after forming the inner spacer 144 at the first device region 103, a hard mask layer 159, such as the hard mask layer 137, is deposited on the exposed surface of the semiconductor device structure 400 at the first device region 103. Thereafter, a photolithography process is performed to pattern the hard mask layer 157 to expose the processing area at the second device region 105. Then, the oxide layer 229 at the second device region 105 is removed, and the edge portion of each first semiconductor layer 206 of the semiconductor layer stack 204 at the second device region 105 is horizontally removed along the X direction. The edge portion of the first semiconductor layer 206 is removed to form a cavity in a manner similar to that discussed above, and then the cavity is filled with a dielectric material to form the inner spacer 144.

[0095] exist Fig.37A and Fig.37B , the hard mask layer 159 is removed, and epitaxial S / D features 146, 147 are formed in source / drain (S / D) regions at the first device region 103 and the second device region 105. The epitaxial S / D features 146, 147 may be laterally grown from the fill layer 235 and the first semiconductor layer 206, respectively. The epitaxial S / D features 146, 147 may form facets corresponding to crystal planes of the materials of the fill layer 235 and the first semiconductor layer 206. Due to different growth rates on different materials and the fact that the first semiconductor layer 206 at the first device region 103 and the fill layer 335 at the second device region 105 are arranged at different heights, the epitaxial S / D features 146, 147 grow to have different heights. In an exemplary embodiment, the epitaxial S / D feature 147 at the first device region 103 may have a first height H3, and the epitaxial S / D feature 146 at the second device region 105 may have a second height H4 that is shorter than the first height H3. Thereafter, in the same manner as described above with respect to FIG. 9A to FIG. 9B to FIG. 12A to FIG. 12B A contact etch stop layer (CESL) 162 and an interlayer dielectric (ILD) layer 164 are sequentially formed over the semiconductor device structure 400 in a manner similar to that discussed above.

[0096] exist FIG. 38A to FIG. 38DIn the embodiment, after the ILD layer 164 has been formed, a planarization operation, such as CMP, is performed on the semiconductor device structure 400 to remove portions of the ILD layer 164, the CESL 162, and the mask layer 136 until the sacrificial gate electrode layer 134 is exposed. Then, the sacrificial gate structure 130, the cladding layer 117, the first semiconductor layer 206, and the second semiconductor layer 208 are removed from the semiconductor device structure 400 at the first device region 103 and the second device region 105, respectively. The etchant is selective so that the etch stop layer 111 is not substantially etched during the removal of the first semiconductor layer 206 and the second semiconductor layer 208. When the sacrificial gate structure 130 and the first semiconductor layer 206 are removed, portions of the filling layer 335 at the second device region 105 are exposed. Likewise, after the sacrificial gate structure 130 and the second semiconductor layer 208 are removed, portions of the first semiconductor layer 206 at the first device region 103 are exposed.

[0097] exist FIG. 39A to FIG. 39D In the embodiment, replacement gate structures 190 are formed in the regions provided by removing the cladding layer 117 and the second semiconductor layer 208 at the first device region 103 and the second device region 105. The replacement gate structures 190 each include an interfacial layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182a / 182b, and may be formed in the same manner as described above with respect to FIG. 15A to FIG. 15D Thereafter, the gate electrode layer 182a and the gate electrode layer 182b are planarized by a planarization process.

[0098] exist FIG. 40A to FIG. 40D In the embodiment of the present invention, the gate electrode layers 182a, 182b may be subjected to one or more metal gate etch back (MGEB) processes such that the top surfaces of the gate electrode layers 182a, 182b and the gate dielectric layer 180 are recessed to a level below the top surface of the gate spacer 138. A self-aligned contact layer 173 is then formed over the gate dielectric layer 180 between the gate electrode layers 182a, 182b and the gate spacer 138. After the self-aligned contact layer 173 is formed, a contact opening is formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D features 146, 147. A silicide layer 184 is then formed on the S / D epitaxial features 146, 147, and an S / D contact 186 is formed in the contact opening on the silicide layer 184. Any deposited material outside the contact opening may be removed using a planarization process such as CMP.

[0099] The semiconductor device structure 400 may then undergo further complementary metal oxide semiconductor (CMOS) and / or back end of line (BEOL) processes to form various components such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0100] Various embodiments or examples described herein provide improved semiconductor device structures that use strained germanium materials as channel layers to enhance channel mobility for PFETs, and use germanium materials, ordinary silicon or strained silicon materials as channel layers to enhance channel mobility for NFETs. In some embodiments, the topmost channel layer (e.g., strained Ge layer) of the NFET and / or PFET has both sides thereof in contact with the internal spacer, such that the topmost internal spacer is disposed between the gate electrode layer and the S / D contacts. Thus, the gate to source / drain parasitic capacitance is minimized due to the added dielectric in combination with the topmost internal spacer and the immediately adjacent layer (e.g., contact etch stop layer).

[0101] The embodiment is a semiconductor device structure. The semiconductor device structure includes: a source / drain component disposed above a substrate; a plurality of semiconductor layers vertically stacked above the substrate and in contact with the source / drain component; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers; and a second dielectric spacer in contact with a second side of the topmost semiconductor layer of the plurality of semiconductor layers.

[0102] Another embodiment is a semiconductor device structure. The semiconductor device structure includes: a plurality of first semiconductor layers disposed at a first device region of a substrate; a first source / drain feature in contact with each of the plurality of first semiconductor layers; a first dielectric spacer in contact with a first side of a topmost first semiconductor layer of the plurality of semiconductor layers; a plurality of second semiconductor layers disposed at a second device region of the substrate; and a second source / drain feature in contact with each of the plurality of second semiconductor layers, wherein the number of the plurality of first semiconductor layers and the number of the plurality of second semiconductor layers are different.

[0103] A further embodiment is a method for forming a semiconductor device structure. The method includes: forming an etch stop layer above a substrate, the etch stop layer having a first concentration of a dopant; forming a semiconductor layer stack on the etch stop layer, the semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, and each of the plurality of second semiconductor layers having a second concentration of a dopant. The method also includes: oxidizing a surface portion of the first semiconductor layer and the second semiconductor layer and the etch stop layer; removing the dopant from the oxidized surface portion of the second semiconductor layer; flowing an etching gas through the oxidized surface portion of the second semiconductor layer to remove each of the plurality of second semiconductor layers; flowing a deposition gas through the oxidized surface portion of the second semiconductor layer to form a channel layer in an area where the second semiconductor layer was removed; and removing the oxidized surface portion of the second semiconductor layer.

[0104] Some embodiments of the present application provide a semiconductor device structure, including: a source / drain component disposed above a substrate; a plurality of semiconductor layers vertically stacked above the substrate and in contact with the source / drain component; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers; and a second dielectric spacer in contact with a second side of the topmost semiconductor layer of the plurality of semiconductor layers.

[0105] In some embodiments, the first dielectric spacer and the second dielectric spacer are in contact with the gate spacer. In some embodiments, the plurality of semiconductor layers are formed of germanium. In some embodiments, each of the semiconductor layers is formed of strained germanium. In some embodiments, the semiconductor device structure further comprises: a contact etch stop layer (CESL) in contact with the source / drain component and the first dielectric spacer. In some embodiments, the first dielectric spacer is disposed between the gate electrode layer and the contact etch stop layer. In some embodiments, the topmost semiconductor layer of the plurality of semiconductor layers has a first thickness, and the first dielectric spacer has a second thickness greater than the first thickness. In some embodiments, the semiconductor device structure further comprises: an etch stop layer disposed between the bottommost semiconductor layer of the plurality of semiconductor layers and the substrate, wherein the etch stop layer has a first germanium concentration. In some embodiments, each of the plurality of semiconductor layers has a second germanium concentration greater than the first germanium concentration.

[0106] Other embodiments of the present application provide a semiconductor device structure, including: a plurality of first semiconductor layers, arranged at a first device region of a substrate; a first source / drain component, contacting each of the plurality of first semiconductor layers; a first dielectric spacer, contacting a first side of a topmost first semiconductor layer of the plurality of semiconductor layers; a plurality of second semiconductor layers, arranged at a second device region of the substrate; and a second source / drain component, contacting each of the plurality of second semiconductor layers, wherein the number of the plurality of first semiconductor layers is different from the number of the plurality of second semiconductor layers.

[0107] In some embodiments, the first source / drain feature has a first height, and the second source / drain feature has a second height different from the first height. In some embodiments, the plurality of first semiconductor layers include strained germanium, and the plurality of second semiconductor layers include silicon. In some embodiments, the semiconductor device structure further includes: an etch stop layer disposed between a bottommost first semiconductor layer of the plurality of first semiconductor layers and the substrate, wherein the etch stop layer has a germanium concentration less than a germanium concentration of the first semiconductor layer. In some embodiments, the semiconductor device structure further includes: a second dielectric spacer contacting the first source / drain feature and a second side of the topmost first semiconductor layer of the plurality of semiconductor layers. In some embodiments, the first dielectric spacer also contacts a first gate spacer. In some embodiments, the topmost second semiconductor layer of the plurality of second semiconductor layers has a first side contacting a second gate spacer. In some embodiments, the semiconductor device structure further includes: a third dielectric spacer contacting the second source / drain feature and a second side of the topmost second semiconductor layer of the plurality of second semiconductor layers.

[0108] Some other embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming an etch stop layer above a substrate, the etch stop layer having a first concentration of a dopant; forming a semiconductor layer stack on the etch stop layer, the semiconductor layer stack comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked, and each of the plurality of second semiconductor layers having a second concentration of the dopant; oxidizing the first semiconductor layer and the second semiconductor layer and a surface portion of the etch stop layer; removing the dopant from the oxidized surface portion of the second semiconductor layer; flowing an etching gas through the oxidized surface portion of the second semiconductor layer to remove each of the plurality of second semiconductor layers; flowing a deposition gas through the oxidized surface portion of the second semiconductor layer to form a channel layer in the region where the second semiconductor layer was removed; and removing the oxidized surface portion of the second semiconductor layer.

[0109] In some embodiments, the second concentration of the dopant is greater than the first concentration of the dopant. In some embodiments, the channel layer is formed of strained germanium.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and in examples that do not deviate from the spirit and scope of the embodiments of the present disclosure, they can make various changes, substitutions and modifications herein.

Claims

1. A semiconductor device structure, comprising: a source / drain component disposed above the substrate; a plurality of semiconductor layers vertically stacked above the substrate and in contact with the source / drain features; a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers; a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers; as well as A second dielectric spacer contacts a second side of the topmost semiconductor layer of the plurality of semiconductor layers.

2. The semiconductor device structure according to claim 1, wherein: The first dielectric spacer and the second dielectric spacer are in contact with the gate spacer.

3. The semiconductor device structure according to claim 1, wherein: The plurality of semiconductor layers are formed of germanium.

4. The semiconductor device structure according to claim 3, wherein: Each of the semiconductor layers is formed of strained germanium.

5. The semiconductor device structure according to claim 2, further comprising: A contact etch stop layer (CESL) contacts the source / drain features and the first dielectric spacer.

6. The semiconductor device structure according to claim 5, wherein: The first dielectric spacer is disposed between the gate electrode layer and the contact etch stop layer.

7. The semiconductor device structure according to claim 1, wherein: The topmost semiconductor layer of the plurality of semiconductor layers has a first thickness, and the first dielectric spacer has a second thickness greater than the first thickness.

8. The semiconductor device structure according to claim 1, further comprising: An etch stop layer is disposed between a bottommost semiconductor layer of the plurality of semiconductor layers and the substrate, wherein the etch stop layer has a first germanium concentration.

9. A semiconductor device structure, comprising: A plurality of first semiconductor layers are disposed at a first device region of the substrate; a first source / drain feature in contact with each of the plurality of first semiconductor layers; a first dielectric spacer contacting a first side of a topmost first semiconductor layer of the plurality of semiconductor layers; A plurality of second semiconductor layers are arranged at a second device region of the substrate; as well as a second source / drain feature in contact with each of the plurality of second semiconductor layers, The number of the plurality of first semiconductor layers is different from the number of the plurality of second semiconductor layers.

10. A method for forming a semiconductor device structure, comprising: forming an etch stop layer over the substrate, the etch stop layer having a first concentration of a dopant; forming a semiconductor layer stack on the etch stop layer, the semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked, and each of the plurality of second semiconductor layers having a second concentration of the dopant; oxidizing surface portions of the first semiconductor layer and the second semiconductor layer and the etch stop layer; removing the dopant from the oxidized surface portion of the second semiconductor layer; flowing an etching gas through the oxidized surface portion of the second semiconductor layer to remove each of the plurality of second semiconductor layers; flowing a deposition gas over the oxidized surface portion of the second semiconductor layer to form a channel layer in the region where the second semiconductor layer was removed; as well as The oxidized surface portion of the second semiconductor layer is removed.

Images