Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. A semiconductor device includes a substrate having a front side and a rear side, a source / drain structure disposed on the front side of the substrate, a backside via including a trench filled with a conductive material, the trench exposed at the backside of the substrate, extending through the substrate, and electrically coupled to the source / drain structure, and an isolation layer including a dielectric material disposed between the substrate and the backside via and separating the substrate from the backside via, where the isolation layer selectively covers a first portion of a plurality of sidewalls of the trench between the substrate and the backside via, and does not cover a second portion of the plurality of sidewalls of the trench.

Description

Technical Field

[0001] The invention relates to a semiconductor device and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has continued to grow rapidly in recent years. Technological advances in IC materials and design have led to continuous improvements in multiple generations of ICs. In each new generation, circuits become smaller and more complex than the previous generation, achieving higher performance density (i.e., the number of interconnected devices per chip area) and smaller geometry (i.e., the smallest component or line that can be created using a manufacturing process). This scaled-down process is conducive to improving production efficiency and reducing associated costs. However, as feature sizes continue to shrink, the manufacturing process becomes more challenging, and it becomes increasingly difficult to ensure the reliability of semiconductor devices. Therefore, the industry faces the continuous challenge of developing processes that can manufacture smaller and more reliable ICs. Summary of the invention

[0003] According to an embodiment, a semiconductor device is provided including a substrate having a front side and a back side, a source / drain structure disposed on the front side of the substrate, a backside via including a trench filled with a conductive material, the trench being exposed at the back side of the substrate, extending through the substrate, and electrically coupled to the source / drain structure, and an isolation layer including a dielectric material disposed between the substrate and the backside via and separating the substrate from the backside via, wherein the isolation layer selectively covers a first portion of multiple sidewalls of the trench between the substrate and the backside via, and does not cover a second portion of the multiple sidewalls of the trench.

[0004] According to another embodiment, a method for forming a semiconductor device is provided. The method includes forming a trench through the back side of a substrate of the semiconductor device, having a trench opening on the back side of the substrate, wherein a first portion of a plurality of sidewalls of the trench is formed of a first material, at least a second portion of the plurality of sidewalls of the trench is formed of a second material different from the first material, and a base of the trench is formed of a third material different from the first material and the second material; flowing a fluid into the trench to form a uniform isolation layer on the first portion of the plurality of sidewalls of the trench and on the base of the trench without forming the isolation layer on the second portion of the plurality of sidewalls of the trench; removing a portion of the isolation layer covering the base of the trench to expose a portion of a source / drain structure; and forming a backside via including a conductive material in the trench, the backside via being exposed at the back side of the substrate, extending through the substrate, and electrically coupled to the source / drain structure of the semiconductor device.

[0005] According to another embodiment, a method for forming a semiconductor device is provided. The method includes forming a trench through the back side of a substrate of the semiconductor device, having a trench opening on the back side of the substrate, wherein a first portion of a plurality of sidewalls of the trench is formed of a first material, at least a second portion of the plurality of sidewalls of the trench is formed of a second material different from the first material, and a base of the trench is formed of a third material different from the first material and the second material; flowing a fluid into the trench to form a uniform isolation layer on the first portion of the plurality of sidewalls of the trench and on the base of the trench without forming the isolation layer on the second portion of the plurality of sidewalls of the trench; removing a portion of the isolation layer covering the base of the trench to expose a portion of a source / drain structure; and forming a backside via including a conductive material in the trench, the backside via being exposed at the back side of the substrate, extending through the substrate, and electrically coupled to the source / drain structure of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with the attached Figure 1 When read together, the drawings or the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the size of various features can be increased or decreased arbitrarily for the clarity of discussion.

[0007] Figure 1 A flowchart is shown of an exemplary method for forming a semiconductor device or structure according to some embodiments;

[0008] Figures 2 to 8includes cross-sectional views of a portion of a semiconductor device at various stages in an integrated circuit fabrication process according to some embodiments;

[0009] Fig. 9 is a cross-sectional view of a sample fabricated during experimental studies leading to certain aspects of the embodiments, and a graph showing material measurements of the sample along a scan line; and

[0010] Fig.10 and Fig.11 Included are cross-sectional views of a portion of a semiconductor device at various stages in an integrated circuit fabrication process in accordance with some embodiments.

[0011] Description of Reference Numerals

[0012] 100: Method

[0013] 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132: Operation

[0014] 200:Semiconductor devices

[0015] 201:Front

[0016] 202: Dorsal

[0017] 210: Substrate

[0018] 212: Source / drain structure

[0019] 216: Channel layer

[0020] 218: Gate structure

[0021] 220: Interlayer dielectric layer

[0022] 222: Metal drain structure

[0023] 226: Oxide

[0024] 228: Isolation layer

[0025] 230: Insulation layer

[0026] 310: first mask layer

[0027] 312: second mask layer

[0028] 410: Groove

[0029] 412: Matrix

[0030] 414: Side wall

[0031] 510: Isolation layer

[0032] 610: Conductive deposit

[0033] 710: Back side through hole

[0034] 810: Shallow Trench Isolation

[0035] 900:Semiconductor devices

[0036] 910: Substrate

[0037] 912: Isolation layer

[0038] 914: Groove

[0039] 916: first mask layer

[0040] 918: Second mask layer

[0041] 920: Arrow

[0042] 922: The Front Line

[0043] 924: Second Line

[0044] 926: The Third Line DETAILED DESCRIPTION

[0045] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. The following describes specific examples of elements and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0046] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or portions, but these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms may only be used to distinguish one component, element, region, layer, or portion from another element, component, region, layer, or portion. Terms such as "first," "second," and "third" when used herein do not imply a sequence or order unless the context clearly indicates.

[0047] In addition, spatially related terms, such as "over", "overlying", "above", "upper", "top", "under", "underlying", "below", "lower", "bottom", for the convenience of description, as shown in the figure, this article may use terms such as the accompanying drawings to describe the relationship between one element or feature and another element or feature. In addition to the orientation depicted in the figure, spatially related terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article can also be interpreted accordingly. When spatially relative terms such as those listed above are used to describe a first element relative to a second element, the first element can be directly on the other element, or there can be an intermediate element or layer. When an element or layer is referred to as "on" another element or layer, it is directly on the other element or layer and in contact with the other element or layer.

[0048] Please note that references in the specification to "one embodiment", "embodiment", "example embodiment", "exemplary", "example", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it would be within the knowledge of a person of ordinary skill in the art to affect such feature, structure, or characteristic in conjunction with other embodiments.

[0049] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals are generally used to refer to the same components throughout the text. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it is apparent that the claimed subject matter can be practiced without these specific details. In other cases, structures and devices are shown in block diagram form to facilitate description of the subject matter.

[0050] Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the semiconductor device structure. For different embodiments, some of the features described below may be replaced or deleted. Although some embodiments are discussed by operations performed in a particular order, these operations may be performed in another logical order.

[0051] As used herein, a "layer" is a region, such as a region that includes any boundaries and does not necessarily include a uniform thickness. For example, a layer can be a region that includes at least some thickness variation.

[0052] Disclosed herein is a method for manufacturing a semiconductor device having an isolation layer selectively formed adjacent to a backside via. For the sake of brevity, conventional techniques associated with conventional semiconductor device manufacturing are not described in detail herein. In addition, the various tasks and processes described herein may be incorporated into a more comprehensive process or process having additional functions not described in detail herein. Specifically, the various processes in semiconductor device manufacturing are well known, and therefore, for the sake of brevity, many conventional processes will only be briefly mentioned herein or will be omitted entirely without providing well-known process details. A person of ordinary skill in the art will readily understand, after reading this disclosure in its entirety, that the structures disclosed herein may be used with a variety of techniques and may be incorporated into a variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes a varying number of components, and that a single component shown in the figure may represent multiple components.

[0053] In certain semiconductor device applications, a source power connection is provided on the back side of the semiconductor device to facilitate reducing overall size and power consumption. In such applications, a source / drain structure disposed on the front side of the semiconductor device can be electrically coupled to a power rail disposed on the back side of the semiconductor device via a back side via. Preferably, the back side via is configured to provide low resistance, low capacitance, and low leakage current.

[0054] Typically, a backside via includes a trench extending through a substrate and electrically coupling a source / drain structure and a power rail, the trench being filled with a conductive material exposed on the back side of the semiconductor device. In order to reduce the possibility of current leakage from the backside via to the substrate, an isolation layer formed of a dielectric material may be deposited in the trench before the trench is filled with a conductive material, the isolation layer covering the entire sidewall and base of the trench. However, due to the reduced size of the conductive material, this may increase the resistance of the backside via. In addition, an additional process step is required to remove a portion of the isolation layer from the base of the trench, thereby exposing the source / drain structure.

[0055] In various embodiments disclosed herein, a trench may be formed through the back side of a semiconductor device such that the trench leads to the back side of the semiconductor device. In some embodiments, a first portion of the plurality of sidewalls of the trench is formed of a first material, a second portion of the plurality of sidewalls of the trench is formed of a second material different from the first material, and a base of the trench is formed of a third material different from one or both of the first material and the second material. In various embodiments, a uniform isolation layer is selectively formed over the first portion of the plurality of sidewalls of the trench by flowing a fluid into the trench, the fluid reacting with the first material of the first portion of the plurality of sidewalls of the trench, but not reacting with the second material of the second portion of the plurality of sidewalls of the trench, and may or may not react with the third material of the base of the trench, depending on the specific embodiment. A backside via may be formed in the trench, extending through the substrate, and electrically coupled to a source / drain structure of the semiconductor device, the backside via comprising a conductive material exposed at the back side of the semiconductor device.

[0056] Multiple semiconductor devices and multiple methods disclosed herein provide a selectively formed isolation layer between the substrate and the backside via as an alternative to depositing the isolation layer to promote ease of manufacturing, reduce manufacturing costs, reduce the resistance of the backside via, and access the substrate to the trench for subsequent process steps.

[0057] Please refer to Figure 1 According to one or more embodiments of the present disclosure, exemplary method 100 represents forming a semiconductor device or structure, such as a non-planar transistor device. For example, at least some operations (or steps) of method 100 can be used to form a Fin Field-Effect Transistor (FinFET) device, a Gate-all-around Field-Effect Transistor (GAA FET) device, a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, etc. Please note that method 100 is only an example and is not intended to limit the present invention. Therefore, please understand that it can be used in Figure 1 Additional operations are provided before, during, and after the method 100, and some other operations may only be briefly described herein. For convenience, certain operations of the method 100 are described with reference to a cross-sectional view of an exemplary gate-all-around field effect transistor device 200 (also referred to as semiconductor device 200). The various manufacturing stages of the integrated circuit manufacturing process are as follows: Figures 2 to 8 However, it should be understood that the semiconductor device and method disclosed herein are not limited to method 100 or Figures 2 to 8 Example shown. Figures 2 to 7 The multiple cross-sectional views are in a direction perpendicular to the length direction of the active gate structure 218 of the semiconductor device 200, and Figure 8 The cross-sectional view is taken in a direction parallel to the length direction of the active gate structure 218 of the semiconductor device 200 .

[0058] The method 100 may begin at operation 110. At operation 112, the method 100 may include providing a semiconductor device 200. The semiconductor device 200 may include a substrate 210 having a front side 201 and a back side 202. The substrate 210 may have circuits formed therein and / or thereon, for example to define a transistor structure disposed on its front side 201. The transistor structure may include a plurality of source / drain structures 212 disposed on the front side 201 of the substrate 210, a plurality of channel layers 216 vertically separated from each other between the plurality of source / drain structures 212, and a gate structure 218 located above and around each of the plurality of channel layers 216. In the present disclosure, source and drain may be used interchangeably and their structures are substantially the same. Various methods that may be used to produce the semiconductor device 200 are known in the art, and therefore such processes are not discussed in detail herein.

[0059] The multiple components of the semiconductor device 200 can be formed of various materials, including those commonly used in the manufacture of semiconductor integrated circuits. In some embodiments, the substrate 210 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (for example, with a p-type or n-type dopant) or undoped. The substrate 210 can be a wafer, such as a silicon wafer. Typically, a silicon-on-insulator substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 210 may include silicon, germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0060] In various embodiments, the channel layer 216 may include, for example, a compound semiconductor material (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor material (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or a combination thereof). In one embodiment, each channel layer 216 is silicon that may be undoped or substantially free of dopants (i.e., having a dopant concentration from about 0 cm-3 to about 1×1017 cm-3), where, for example, no intentional doping is performed when forming the channel layer 216 (e.g., of silicon).

[0061] In various embodiments, the channel layer 216 may be intentionally doped. For example, when the semiconductor device 200 is configured as n-type (and operates in enhancement mode), each channel layer 216 may be silicon doped with a p-type dopant such as boron, aluminum, indium, gallium, etc.; when the semiconductor device 200 is configured as p-type (and operates in enhancement mode), each channel layer 216 may be silicon doped with an n-type dopant such as phosphorus, arsenic, antimony, etc. In another example, when the semiconductor device 200 is configured as n-type (and operates in depletion mode), each channel layer 216 may be silicon doped with an n-type dopant; when the semiconductor device 200 is configured as p-type (and operates in depletion mode), each channel layer 216 may be silicon doped with a p-type dopant. In some embodiments, each channel layer 216 may include different compositions.

[0062] In various embodiments, the channel layers 216 may have the same or different thicknesses from one layer to another. The thickness of each channel layer 216 may range, for example, from a few nanometers to tens of nanometers. In an embodiment, the thickness of each channel layer 216 ranges from about 5 nanometers to about 20 nanometers. It should be understood that the semiconductor device 200 may include any number of channel layers 216 while remaining within the scope of the present disclosure.

[0063] A plurality of internal spacers may be disposed along respective etched ends of the plurality of channel layers 216. The internal spacers may be formed from, for example, silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon carbon nitride, or any other type of dielectric material suitable for forming the role of insulating gate sidewall spacers of transistors (e.g., a dielectric material having a dielectric constant k less than about 5).

[0064] In various embodiments, a plurality of gate spacers may be provided to surround portions of the gate structure 218. The gate spacers may include a single conformal layer or a combination of two or more conformal layers. It should be understood that any gate spacer formed as a combination of any number of conformal layers may be formed while still being within the scope of the present disclosure. In some embodiments, each conformal layer may include a dielectric material selected from silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, and the like, or combinations thereof. Each conformal layer may have a thickness ranging from about 2 angstroms (A) to about 500 angstroms.

[0065] In various embodiments, the gate structure 218 includes a gate dielectric and a gate metal. In such embodiments, the gate dielectric and the gate metal can be formed in one or more layers. In some embodiments where the gate dielectric and the gate metal each include a single layer, the gate dielectric can wrap each channel layer 216, for example, the top surface and the bottom surface and some sidewalls. The gate dielectric can be formed of different high dielectric materials or similar high dielectric materials. Exemplary high dielectric materials include metal oxides, nitrides or silicates of hafnium, aluminum, zirconium, tantalum, lanthanum, magnesium, barium, titanium, lead and combinations thereof. The gate dielectric can include a stack of multiple high dielectric materials.

[0066] The gate metal may encapsulate each channel layer 216, and the gate dielectric is disposed between the gate metal and the channel layer 216. Specifically, the gate metal may include a plurality of gate metal segments adjacent to each other. Each gate metal segment may extend not only along a horizontal plane, but also along a vertical direction. In this way, two adjacent gate metal segments in the gate metal segment may be adjacent to each other to encapsulate a corresponding one of the plurality of channel layers 216, and the gate dielectric is disposed therebetween.

[0067] The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary p-type work function metals may include TiN, TAN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals may include Ti, Ag, TaAl, TaAIC, TiAlN, TAC, TACN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0068] Multiple source / drain structures 212 are electrically coupled to respective channel layers 216. In various embodiments, multiple channel layers 216 can collectively function as a conductive channel for a gate-all-around transistor. In-situ doping (ISD) can be applied to form multiple doped source / drain structures 212, thereby producing multiple junctions for multiple gate-all-around transistors. N-type and p-type field effect transistors are formed by implanting different types of dopants into multiple selected regions of the device to form (multiple) junctions. N-type devices can be formed by implanting arsenic or phosphorus, and p-type devices can be formed by implanting boron.

[0069] Interlayer dielectric layer 220 may be disposed between gate structure 218 and front side 201 of semiconductor device 200. Interlayer dielectric layer 220 may include or be formed from a dielectric material such as silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or combinations thereof.

[0070] A metal drain structure 222 may be disposed between the source / drain structure 212 and the front side 201 of the substrate 210. An oxide 226 may be disposed between the source / drain structure 212 and the back side 202 of the substrate 210.

[0071] Source / drain isolation layer 228 may be disposed adjacent to and contacting the plurality of source / drain structures 212. Source / drain isolation layer 228 may include or be formed from insulating materials such as silicon dioxide, silicon nitride, high dielectric materials (eg, hafnium oxide or aluminum oxide), and polysilicon.

[0072] The front side 201 of the substrate 210 may be covered with a third insulating layer 230 formed from or including a third dielectric material. The third insulating layer 230 may include or be formed from various dielectric materials such as silicon nitride.

[0073] At operation 114, method 100 may include preparing substrate 210 of semiconductor device 200 for deposition of additional layers thereon. Substrate 210 may be prepared by, for example, thinning and / or planarizing backside 202 of substrate 210, such as Figure 2 In some embodiments, a chemical mechanical polishing (CMP) process may be performed on the back side 202 of the substrate 210. In some embodiments, the substrate 210 may be thinned and / or planarized to have a thickness of about 10 to 50 nanometers from the back side 202 to the portion of the gate structure 218 closest to the back side 202.

[0074] At operation 116, the method 100 may include forming a first mask layer 310 of a first dielectric material on the back side 202 of the substrate 210; and at operation 118, the method 100 may include forming a second mask layer 312 of a second dielectric material on the first mask layer 310, such as Figure 3 As shown. The first mask layer 310 and the second mask layer 312 may include or be formed from various dielectric materials. In one embodiment, the first mask layer 31 is formed from silicon nitride and the second mask layer 312 is formed from silicon dioxide. In some embodiments, the first mask layer 310 may have a thickness of about 5 to 15 nanometers, and the second mask layer 312 may have a thickness of about 15 to 45 nanometers. Various processes may be used to form the first mask layer 310 and the second mask layer 312. In some embodiments, the first mask layer 310 and the second mask layer 312 may both be formed by a thin film deposition process.

[0075] At operation 120, the method 100 may include forming a trench 410 through the second mask layer 312, the first mask layer 310, and the back side 202 of the substrate 210, such that the trench 410 leads to the back side 202 of the substrate 210, as shown in FIG. Figure 4 As shown. Various processes may be used to form the trench 410. In some embodiments, the trench 410 may be formed by one or more photolithography and etching processes. In some embodiments, the trench 410 may have a depth of about 30 to 110 nanometers and a width of about 5 to 30 nanometers. In some embodiments, the ratio of the width of the trench 410 to the thickness of the isolation layer may be in a range between 6 and 12. In some embodiments, the trench 410 may be formed to a sufficient depth so that the base 412 of the trench 410 is defined by the isolation layer 228 (if present) or a portion of the source / drain structure 212.

[0076] A first portion of the plurality of sidewalls 414 of the trench 410 may be formed from a first material, a second portion of the plurality of sidewalls 414 of the trench 410 may be formed from a second material different from the first material, and a body 412 of the trench 410 may be formed from a third material different from the first material and the second material. For example, the plurality of sidewalls 414 of the trench 410 may include a plurality of exposed surfaces of the first mask layer 310, the second mask layer 312, the substrate 210, the isolation layer 228, the source / drain structure 212, the shallow trench isolation layer, and / or various other components of the semiconductor device 200.

[0077] At operation 122, the method 100 may include forming a uniform isolation layer 510 over a first portion of the plurality of sidewalls 414 of the trench 410, such as Figure 5As shown, by flowing a fluid into the trench 410, the fluid reacts with the material of at least one of the plurality of sidewalls 414 defining the trench 410; various processes can be used to form the isolation layer 510. In some embodiments, the isolation layer 510 can be formed by a physical vapor deposition (PVD) process. In one embodiment, the formation of the isolation layer 510 includes flowing a fluid containing nitrogen or oxygen into the trench 410 at a flow rate in the range of 1 standard cubic centimeter per minute (sccm) to 20 standard cubic centimeters per minute, a power in the range of 500 to 2000 W, a pressure in the range of 10 to 100 Torr, and a time in the range of 60 to 360 seconds.

[0078] In various embodiments, the fluid reacts with a first material of a first portion of the plurality of sidewalls 414 of the trench 410, does not react with a second material of a second portion of the plurality of sidewalls 414 of the trench 410, or otherwise does not react with the isolation layer 510 formed thereon. And depending on the embodiment, the trench 410 reacts or does not react with a third material of the substrate 412. For example, Figure 4 and Figure 5 4 represents the trench 410 base 412 defined by the isolation layer 228, and no isolation layer 510 is formed thereon. In contrast, Fig.10 and Fig.11 The body 412 of the trench 410 is represented as being defined by the exposed portions of the source / drain structure 212 and the isolation layer 510 is formed thereon.

[0079] For example, the first portion of the plurality of sidewalls 414 may be a plurality of exposed surfaces of the substrate 210, while the second material and the third material may be a plurality of exposed surfaces of other components (e.g., the first mask layer 310, the second mask layer 312, the isolation layer 228, the source / drain structure 212, the shallow trench isolation layer, and / or various other components of the semiconductor device 200). In some embodiments, the third material may be an exposed portion of the source / drain structure 212. And the fluid may react with the exposed surface of the source / drain structure 212 to form a dielectric material. In various embodiments, the fluid may be a gaseous compound configured to react with the first material to form a dielectric material.

[0080] In one embodiment, the first material is silicon and the fluid is gaseous nitrogen, oxygen, or a compound containing nitrogen or oxygen, which is configured to react with silicon to form silicon nitride or silicon oxide. In various embodiments, the reaction between the first material and the fluid consumes a portion of the first material at its exposed surface, so that the reaction product (e.g., SiNx or SiOx) barely protrudes from the plurality of sidewalls 414 of the trench 410. Therefore, the formation of the isolation layer 510 has little or no effect on the shape and size of the trench 410.

[0081] At operation 124, method 100 may include removing material at base 412 of trench 410 to expose source / drain structure 212. In some embodiments, the removed material includes a portion of isolation layer 228 (eg, Figure 4 and Figure 5 In some embodiments, the removed material includes a portion of isolation layer 510 (eg, Fig.10 and Fig.11 ). Various processes may be used to remove material at the base 412 of the trench 410. In one embodiment, the material at the base 412 of the trench 410 is removed by one or more selective etching processes.

[0082] At operation 126 , method 100 may include forming a conductive deposit 610 disposed at body 412 of trench 410 that is electrically coupled to source / drain structure 212 , such as Figure 6 As shown. Conductive deposit 610 is configured to facilitate electrical connection with source / drain structure 212. Conductive deposit 610 can be formed from or include various silicide materials, such as titanium silicide, nickel silicide, cobalt silicide, etc. Forming conductive deposit 610 can be performed by various deposition processes. Conductive deposit 610 can have a thickness in the range of 5 to 10 nanometers.

[0083] At operation 128, method 100 may include forming a backside via 710 in trench 410, such as Figure 7 As shown. The backside via 710 can be formed by various processes. The backside via 710 may include a conductive material exposed at the back side 202 of the semiconductor device 200, extending through the substrate 210 and electrically coupled to the source / drain structure 212 of the semiconductor device 200. The backside via 710 is configured to provide an electrical connection between the source / drain structure 212 on the back side 202 of the semiconductor device 200 and the power rail. The conductive material of the backside via 710 can be formed from or include various conductive materials. Non-limiting examples include various metal materials, such as titanium-titanium nitride-tungsten alloy, tungsten, cobalt, ruthenium, molybdenum, etc.

[0084] At operation 130, the method 100 may include removing the second mask layer 312 and any other excess material (eg, portions of the backside vias 710), such as Figure 7 As shown. Various processes can be used to remove the second mask layer 312. In an embodiment, the second mask layer 312 is removed by a chemical mechanical polishing process. A person of ordinary skill in the art can select various parameters of the chemical mechanical polishing process. In some embodiments, the entire second mask layer 312 adjacent to the first mask layer 310 is removed. In some embodiments, the entire first mask layer 310 is removed.

[0085] Method 100 may end at operation 132 . Figure 7 and Figure 8 A plurality of cross-sectional views of a semiconductor device 200 after the method 100 is completed according to various embodiments are presented, wherein Figure 8 The cross-section is perpendicular to Figure 7 A cross-sectional view of Figure 7 As shown, the isolation layer 510 is limited to only cover certain portions of the plurality of sidewalls 414 of the trench 410. Figure 7 , the isolation layer 510 defines portions of the plurality of sidewalls 414 initially defined by the exposed surface of the substrate 210, but does not define other portions defined by the first mask layer 310. Figure 8 As shown, portions of the plurality of sidewalls 414 are partially defined by shallow trench isolation 810. Figure 8 The isolation layer 510 is not visible in the view shown. The isolation layer 510 barely protrudes into the cavity of the trench 410, other than defining only selected portions of the plurality of sidewalls 414. Thus, the presence of the isolation layer 510 has little effect on the size of the trench 410, and thus has little effect on the size and performance of the backside via 710.

[0086] Fig. 9 A cross-sectional image of an example semiconductor device 900 is presented that includes an empty trench 914 formed therein to extend through a substrate 910 , a first mask layer 916 , and a second mask layer 918 .

[0087] An isolation layer 912 is formed from a substrate 910 through a process similar to operations 112 to 122 of the method 100 to provide a resistive barrier along a plurality of sidewalls of the trench 914. The substrate 910 is formed of silicon, the first mask layer 916 is formed of silicon nitride, and the second mask layer 918 is formed of silicon oxide. The isolation layer 912 is formed by reacting with the substrate 910 to define a portion of a plurality of sidewalls of the trench 914, and the isolation layer 912 is formed of silicon nitride.

[0088] The provided graph shows the presence of certain compounds, namely silicon, silicon nitride, and silicon oxide, along a scan line (indicated by arrow 920) through a portion of the substrate 910 and the isolation layer 912. This graph indicates the material content (y-axis) relative to the position (x-axis). More specifically, the graph includes a first line 922 indicating the relative silicon content, a second line 924 indicating the relative silicon nitride content, and a third line 926 indicating the relative silicon oxide content. As the position transitions from the substrate 910 to the isolation layer 912 and into the trench 914, the relative content changes from being primarily silicon (e.g., about 0.91 for the first line 922) to a significant decrease in silicon and an increase in silicon nitride followed by silicon oxide.

[0089] Therefore, the present disclosure provides a method for forming a semiconductor device or structure that can significantly improve the resistance characteristics of a backside via. In some embodiments, the backside via includes an isolation layer selectively formed on multiple portions of multiple sidewalls of the backside via defined by multiple exposed portions of the substrate of the semiconductor device.

[0090] According to an embodiment, a semiconductor device is provided including a substrate having a front side and a back side, a source / drain structure disposed on the front side of the substrate, a backside via including a trench filled with a conductive material, the trench being exposed at the back side of the substrate, extending through the substrate, and electrically coupled to the source / drain structure, and an isolation layer including a dielectric material disposed between the substrate and the backside via and separating the substrate from the backside via, wherein the isolation layer selectively covers a first portion of a plurality of sidewalls of the trench between the substrate and the backside via, and does not cover a second portion of the plurality of sidewalls of the trench. In other embodiments, the semiconductor device further includes at least one additional layer formed on the back side of the substrate, wherein the backside via extends through the substrate and the at least one additional layer. In other embodiments, the substrate is formed of silicon, and the isolation layer is formed of silicon oxide (SiOx) or silicon nitride (SiNx). In other embodiments, the isolation layer has a thickness in a range between 2 nanometers and 4 nanometers. In other embodiments, the trench has a thickness in a range between 5 nanometers and 30 nanometers. In other embodiments, the ratio of the width of the trench to the thickness of the isolation layer is in a range between 6 and 12. In other embodiments, the second portion of the plurality of sidewalls of the trench is defined as a plurality of exposed portions of shallow trench isolation. In other embodiments, the semiconductor device further includes a second source / drain structure disposed on the front side of the substrate, a plurality of semiconductor layers vertically isolated from each other, and a gate structure disposed on each of the plurality of semiconductor layers and wrapping each of the plurality of semiconductor layers, wherein a plurality of portions of the gate structure disposed between each of the plurality of semiconductor layers are in contact with the first source / drain structure and the second source / drain structure.

[0091] According to another embodiment, a method for forming a semiconductor device is provided. The method includes forming a trench through the back side of a substrate of the semiconductor device and having a trench opening on the back side of the substrate, wherein a first portion of a plurality of sidewalls of the trench is formed of a first material, a second portion of the plurality of sidewalls of the trench is formed of a second material different from the first material, and a base of the trench is formed of a third material different from the first material and the second material; forming a uniform isolation layer on the first portion of the plurality of sidewalls of the trench by flowing a fluid into the trench, forming the isolation layer on the first portion of the plurality of sidewalls of the trench, and not forming the isolation layer on the second portion of the trench or the base; and forming a backside via including a conductive material in the trench, the backside via being exposed at the back side of the substrate, extending through the substrate, and electrically coupled to a source / drain structure of the semiconductor device. In other embodiments, the first material is silicon, and the isolation layer is formed of a dielectric material including silicon oxide (SiOx) or silicon nitride (SiNx). In other embodiments, the isolation layer has a thickness in a range between 2 nanometers and 4 nanometers. In other embodiments, the trench has a width in a range between 5 nanometers and 30 nanometers. In other embodiments, forming the isolation layer includes flowing the fluid at a flow rate in a range between 1 standard cubic centimeter per minute (sccm) and 20 standard cubic centimeters per minute, while providing a pressure in a range between 10 Torr and 100 Torr at a power in a range between 500 Watts and 2000 Watts, for a time in a range between 60 seconds and 360 seconds. In other embodiments, the method further includes: planarizing the back side of the substrate; forming a first mask layer on the back side of the substrate; forming a second mask layer on the first mask layer, wherein forming the groove includes performing a photolithography process and an etching process to form the groove passing through the first mask layer and the second mask layer; after forming the isolation layer, etching the third material at the base of the groove to expose a portion of the source / drain structure; forming a silicide deposit at the base of the groove electrically coupled to the source / drain structure; and after forming the back side through hole, removing the second mask layer by a chemical mechanical polishing process.

[0092] According to another embodiment, a method for forming a semiconductor device is provided. The method includes forming a trench through the back side of a substrate of the semiconductor device, having a trench opening on the back side of the substrate, wherein a first portion of a plurality of sidewalls of the trench is formed of a first material, at least a second portion of the plurality of sidewalls of the trench is formed of a second material different from the first material, and a base of the trench is formed of a third material different from the first material and the second material; flowing a fluid into the trench to form a uniform isolation layer on the first portion of the plurality of sidewalls of the trench and on the base of the trench without forming the isolation layer on the second portion of the plurality of sidewalls of the trench; removing a portion of the isolation layer covering the base of the trench to expose a portion of a source / drain structure; and forming a backside via including a conductive material in the trench, the backside via being exposed at the back side of the substrate, extending through the substrate, and electrically coupled to the source / drain structure of the semiconductor device. In other embodiments, the first material is silicon, and the isolation layer is formed of a dielectric material including silicon oxide (SiOx) or silicon nitride (SiNx). In other embodiments, the isolation layer has a thickness in a range between 2 nanometers and 4 nanometers. In other embodiments, the trench has a width in a range between 5 nanometers and 30 nanometers. In other embodiments, forming the isolation layer includes flowing the fluid at a flow rate in a range of 1 standard cubic centimeter per minute (sccm) to 20 standard cubic centimeters per minute, while providing a pressure in a range of 10 torr to 100 torr at a power in a range of 500 watts to 2000 watts for a time in a range of 60 seconds to 360 seconds. In other embodiments, the method further includes: planarizing the back side of the substrate; forming a first mask layer on the back side of the substrate; forming a second mask layer on the first mask layer, wherein forming the groove includes performing a photolithography process and an etching process to form the groove passing through the first mask layer and the second mask layer; after removing the portion of the isolation layer covering the base of the groove, forming a silicide deposit disposed at the base of the groove, the silicide deposit being electrically coupled to the source / drain structure; and after forming the back side through hole, removing the second mask layer by a chemical mechanical polishing process.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a front side and a back side; a first source / drain structure disposed on the front side of the substrate; a backside via comprising a trench filled with a conductive material, the trench being exposed at a backside of the substrate, extending through the substrate, and electrically coupled to the first source / drain structure; as well as an isolation layer comprising a dielectric material disposed between the substrate and the backside via and separating the substrate from the backside via, wherein the isolation layer selectively covers a first portion of a plurality of sidewalls of the trench between the substrate and the backside via and does not cover a second portion of the plurality of sidewalls of the trench.

2. The semiconductor device according to claim 1, wherein: Further included is at least one additional layer formed on the back side of the substrate, wherein the back side via extends through the substrate and the at least one additional layer.

3. The semiconductor device according to claim 1, wherein: The second portions of the sidewalls of the trench are defined as exposed portions of shallow trench isolation.

4. The semiconductor device according to claim 1, wherein: It further includes a second source / drain structure disposed on the front side of the substrate, a plurality of semiconductor layers vertically isolated from each other, and a gate structure disposed on each of the plurality of semiconductor layers and wrapping each of the plurality of semiconductor layers, wherein a plurality of portions of the gate structure disposed between each of the plurality of semiconductor layers are in contact with the first source / drain structure and the second source / drain structure.

5. A method for forming a semiconductor device, characterized in that: The method comprises: forming a trench through a back side of a substrate of the semiconductor device and having a trench opening on the back side of the substrate, wherein a first portion of a plurality of sidewalls of the trench is formed of a first material, a second portion of the plurality of sidewalls of the trench is formed of a second material different from the first material, and a body of the trench is formed of a third material different from the first material and the second material; forming a uniform isolation layer on the first portion of the plurality of sidewalls of the trench by flowing a fluid into the trench, forming the isolation layer on the first portion of the plurality of sidewalls of the trench without forming the isolation layer on the second portion of the trench or the substrate; and A backside via including a conductive material is formed in the trench, the backside via being exposed at the backside of the substrate, extending through the substrate, and electrically coupled to a source / drain structure of the semiconductor device.

6. The method according to claim 5, characterized in that The isolation layer has a thickness ranging from 2 nanometers to 4 nanometers.

7. The method according to claim 5, characterized in that Wherein the trench has a width in the range between 5 nanometers and 30 nanometers.

8. The method according to claim 5, characterized in that Wherein forming the isolation layer comprises flowing the fluid at a flow rate in a range of 1 standard cubic centimeter per minute (sccm) to 20 standard cubic centimeters per minute, while providing a pressure in a range of 10 Torr to 100 Torr at a power in a range of 500 Watts to 2000 Watts, for a time in a range of 60 seconds to 360 seconds.

9. A method for forming a semiconductor device, characterized in that: The method comprises: forming a trench through a back side of a substrate of the semiconductor device, having a trench opening on the back side of the substrate, wherein a first portion of a plurality of sidewalls of the trench are formed of a first material, at least a second portion of the plurality of sidewalls of the trench are formed of a second material different from the first material, and a body of the trench is formed of a third material different from the first material and the second material; Allowing a fluid to flow into the trench to form a uniform isolation layer on the first portions of the plurality of sidewalls of the trench and on the base of the trench, while not forming the isolation layer on the second portions of the plurality of sidewalls of the trench; removing a portion of the isolation layer of the substrate covering the trench to expose a portion of the source / drain structure; and A backside via including a conductive material is formed in the trench, the backside via being exposed at the backside of the substrate, extending through the substrate, and electrically coupled to the source / drain structure of the semiconductor device.

10. The method according to claim 9, characterized in that Also includes: planarizing the back side of the substrate; forming a first mask layer on the back side of the substrate; forming a second mask layer on the first mask layer, wherein forming the groove comprises performing a photolithography process and an etching process to form the groove passing through the first mask layer and the second mask layer; After removing the portion of the isolation layer covering the base of the trench, forming a silicide deposit disposed at the base of the trench, the silicide deposit being electrically coupled to the source / drain structure; as well as After forming the backside through hole, the second mask layer is removed by a chemical mechanical polishing process.

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