A back-contact battery, its manufacturing method, and a photovoltaic module

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a back contact battery, a manufacturing method thereof, and a photovoltaic module, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, a front passivation layer and an antireflection layer sequentially arranged on the front surface of the silicon wafer. The front passivation layer includes a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer. The film thickness of the hydrogenated amorphous silicon oxide layer is 0.5 - 2 nm. When preparing the hydrogenated amorphous silicon oxide layer, the oxygen doping amount is controlled at 5% - 15% by mass percentage. The thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12. The present invention is beneficial to effectively inhibiting the epitaxial and twin crystal growth at the crystal silicon interface of the silicon wafer, can enhance the passivation effect on the crystal silicon surface, is beneficial to improving the open circuit voltage, fill factor, and short circuit current of the battery, and further improves the conversion efficiency of the battery.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery, a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] The existing back-contact battery includes an N-type monocrystalline silicon wafer, a pyramid texture, an intrinsic amorphous silicon layer, and an antireflection layer sequentially arranged on the front surface of the silicon wafer, a first passivation layer (such as an intrinsic amorphous silicon layer), a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid line layer sequentially arranged on the surface of the P region on the back surface of the silicon wafer, a second passivation layer (such as an intrinsic amorphous silicon layer), an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid line layer sequentially arranged on the surface of the N region on the back surface of the silicon wafer.

[0003] In the prior art, the intrinsic amorphous silicon passivation layer on the front surface of the back-contact battery usually uses hydrogenated amorphous silicon (a-Si:H). However, when growing a-Si:H on the surface of crystalline silicon (c-Si) of N-type monocrystalline silicon, epitaxial growth and twins are likely to occur, resulting in a decrease in passivation quality and a reduction in the open-circuit voltage of the battery; at the same time, when light passes through the amorphous silicon thin film, parasitic absorption is likely to occur, resulting in energy loss of some light and affecting the short-circuit current of the battery.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of poor passivation effect and low short-circuit current of the intrinsic amorphous silicon passivation layer on the front surface of the back-contact battery in the prior art, and to provide a back-contact battery, a manufacturing method thereof, and a photovoltaic module, which are beneficial to effectively suppressing epitaxial and twin growth at the crystalline silicon interface of the silicon wafer, enhancing the passivation effect on the crystalline silicon surface, being beneficial to improving the open-circuit voltage, fill factor, and short-circuit current of the battery, and further improving the conversion efficiency of the battery.

[0006] To achieve the above purpose, in a first aspect, the present invention provides a back-contact battery, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, a front passivation layer and an antireflection layer sequentially arranged on the front surface of the silicon wafer, the front passivation layer including a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer, the film thickness of the hydrogenated amorphous silicon oxide layer being 0.5 - 2 nm, controlling the oxygen doping amount in mass percentage to be 5% - 15% when preparing the hydrogenated amorphous silicon oxide layer, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer being 1:2 - 12.

[0007] In some preferred embodiments of the present invention, the conductivity of the hydrogenated amorphous silicon oxide layer is 1.0×10 -7 S / cm - 1.0×10 -6S / cm, and its average transmittance in the visible light band is 80% - 90%; the conductivity of the hydrogenated amorphous silicon layer is 1.0×10 -6 S / cm - 1.0×10 -4 S / cm, and its average transmittance in the visible light band is 70% - 80%.

[0008] In some preferred embodiments of the present invention, the film thickness of the hydrogenated amorphous silicon layer is 4 - 6 nm.

[0009] In some preferred embodiments of the present invention, the volume flow ratio of hydrogen to silane introduced during the preparation of the hydrogenated amorphous silicon oxide layer is 2.5 - 10:1, and the volume flow ratio of hydrogen to silane introduced during the preparation of the hydrogenated amorphous silicon layer is 4 - 16:1.

[0010] In some preferred embodiments of the present invention, the hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon oxide layer is less than the hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon layer.

[0011] In some preferred embodiments of the present invention, the front passivation layer further includes a microcrystalline silicon oxide layer provided on the outer surface of the hydrogenated amorphous silicon layer, the antireflection layer is provided on the outer surface of the microcrystalline silicon oxide layer, and the thickness of the microcrystalline silicon oxide layer is 6 - 20 nm.

[0012] In some preferred embodiments of the present invention, the thickness ratio of the hydrogenated amorphous silicon oxide layer, the hydrogenated amorphous silicon layer, and the microcrystalline silicon oxide layer is 1:2 - 12:10 - 56.

[0013] In some preferred embodiments of the present invention, the oxygen doping amount is controlled to be 20% - 80% by mass percentage during the preparation of the microcrystalline silicon oxide layer.

[0014] In some preferred embodiments of the present invention, the ratio of the oxygen doping amounts by mass percentage of the hydrogenated amorphous silicon oxide layer and the microcrystalline silicon oxide layer in the corresponding preparations is 1:1 - 8.5.

[0015] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0016] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, and the thickness ratio of the hydrogenated amorphous silicon oxide layer, the hydrogenated amorphous silicon layer, the intrinsic amorphous silicon layer, and the tunneling oxide layer is 1:2 - 12:2 - 16:0.5 - 2.

[0017] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outwardly to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the region between them is an interval region; in the interval region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer.

[0018] In some preferred embodiments of the present invention, the back-contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on a part of the conductive film layer located in the interval region; the metal electrode is provided on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening region and the first semiconductor opening region respectively.

[0019] Second, the present invention provides a method for manufacturing a back-contact battery, including the following steps:

[0020] S01. Provide a double-sided polished silicon wafer;

[0021] S02. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0022] S03. Perform a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0023] S04. Through texturing and cleaning, form a textured surface on the front surface of the silicon wafer and the second semiconductor opening region, and then perform a step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer or not perform the step of removing the mask layer;

[0024] S05. Deposit a second passivation layer on the back surface obtained in S04;

[0025] S06. Sequentially form a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on the front surface of the silicon wafer obtained in S05; control the film thickness of the hydrogenated amorphous silicon oxide layer to be 0.5 - 2 nm, control the oxygen doping amount of the hydrogenated amorphous silicon oxide layer in terms of mass percentage to be 5% - 15% during preparation, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12;

[0026] Among them, the deposition process of the hydrogenated amorphous silicon layer includes: first, high-speed short-time deposition is carried out under the condition of introducing silane, then medium-speed deposition is carried out under the condition of introducing silane to form a thin film intermediate, then hydrogen plasma treatment is carried out, and then it is deposited to the target thickness under the condition of introducing silane and hydrogen (preferably at a deposition rate of 0.5-2 Å / s); among them, the conditions for high-speed short-time deposition include: the deposition rate is 4-10 Å / s, and the deposition duration is 1-5 s; the conditions for medium-speed deposition include: the deposition rate is 0.5-2 Å / s, and the deposition duration is 10-40 s; the conditions for hydrogen plasma treatment are: the temperature is 180-230 °C, the reaction pressure is 20-150 Pa, and the treatment duration is 10-40 s;

[0027] S08. Deposit a second doped silicon layer on the back surface, and the second passivation layer and the second doped silicon layer form a second semiconductor layer;

[0028] S09. Deposit an antireflection layer on the front surface obtained in S08.

[0029] In some preferred embodiments of the present invention, the temperature during the deposition process of the hydrogenated amorphous silicon layer is controlled at 180-230 °C.

[0030] Preferably, the pressures for high-speed short-time deposition and medium-speed deposition are each independently 30-100 Pa.

[0031] In some preferred embodiments of the present invention, the conditions for depositing the hydrogenated amorphous silicon layer to the target thickness under the condition of introducing silane and hydrogen include: the volume flow ratio of hydrogen to silane is 4-16:1, and the pressure is 30-250 Pa.

[0032] In a third aspect, the present invention provides a method for manufacturing a back-contact battery, including the following steps:

[0033] S01. Provide a double-sided polished silicon wafer;

[0034] S02. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0035] S03. Perform a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0036] S04. Through texturing and cleaning, form a textured surface on the front surface of the silicon wafer and the second semiconductor opening region, and then perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer after cleaning or do not perform the step of removing the mask layer;

[0037] S05. Deposit a second passivation layer on the back surface obtained in S04;

[0038] S06. A hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer are sequentially formed on the front side of the silicon wafer obtained in S05; the thickness of the hydrogenated amorphous silicon oxide layer is controlled to be 0.5 - 2 nm, the oxygen doping amount of the hydrogenated amorphous silicon oxide layer is controlled to be 5% - 15% by mass percentage during preparation, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12;

[0039] Among them, the deposition process of the hydrogenated amorphous silicon layer includes: first, a first deposition is carried out under the condition of introducing silane to form an amorphous silicon thin film intermediate; then, a second deposition is carried out to the target thickness under the condition of introducing silane and hydrogen; the conditions of the first deposition include: the deposition rate is 1 - 2 Å / s, and the deposition duration is 10 - 40 s; the conditions of the second deposition include: the volume flow ratio of hydrogen to silane is 4 - 16, and the deposition rate is 0.5 - 2 Å / s;

[0040] S08. A second doped silicon layer is deposited on the back side, and the second passivation layer and the second doped silicon layer form a second semiconductor layer;

[0041] S09. An antireflection layer is deposited on the front side obtained in S08.

[0042] In some preferred embodiments of the present invention, the temperature during the deposition process of the hydrogenated amorphous silicon layer is controlled at 180 - 230 °C.

[0043] In some preferred embodiments of the present invention, the pressure of the first deposition is 30 - 100 Pa, and the pressure of the second deposition is 30 - 250 Pa.

[0044] In some preferred embodiments of the present invention, the deposition conditions of the hydrogenated amorphous silicon oxide layer include: the temperature is 180 - 230 °C, the process gas includes: silane, carbon dioxide and hydrogen, where carbon dioxide is 5% - 50% of the volume flow rate of silane, the volume flow ratio of hydrogen to silane is 2.5 - 10:1, the pressure is 20 - 100 Pa, and the deposition rate is 0.3 Å / s - 1 Å / s.

[0045] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes performing between S06 and S08: S07. A microcrystalline silicon oxide layer is deposited on the front side obtained in S06.

[0046] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes:

[0047] S10. A second etching opening is performed on a part of the second semiconductor layer on the back side to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0048] S11. A conductive film layer is deposited on the back side obtained in S10;

[0049] S12. Perform a third etching opening on the partial conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0050] S13. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0051] Fourthly, the present invention provides a back-contact battery, which is obtained by the manufacturing method of the back-contact battery described in the second aspect or the third aspect.

[0052] Fifthly, the present invention provides a photovoltaic module, which includes the back-contact battery described in the first aspect, or includes the back-contact battery described in the fourth aspect.

[0053] Beneficial effects:

[0054] Through the above technical solutions, especially by using a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer to replace the existing hydrogenated amorphous silicon passivation layer, the present invention improves the microstructure factor of the thin film. Cooperating with a hydrogenated amorphous silicon oxide layer with an appropriate oxygen doping amount and an appropriate thickness, it is beneficial to effectively inhibit the epitaxial and twin growth at the crystal silicon interface of the silicon wafer and reduce the adverse effects on electrical properties. Then, cooperating with a hydrogenated amorphous silicon layer with an appropriate thickness ratio, it can enhance the passivation effect on the crystal silicon surface, improve the passivation quality, reduce the recombination of photo-generated carriers, and is beneficial to improving the open-circuit voltage and fill factor of the battery; it also cooperates with a hydrogenated amorphous silicon oxide layer with an appropriate oxygen doping amount. Appropriate oxygen doping can inhibit the epitaxial growth on the surface of the silicon wafer, but as the oxygen doping amount increases, the conductivity of the film layer decreases. Therefore, controlling the oxygen doping amount within a small range can not only improve the passivation effect but also reduce its impact on electrical properties; at the same time, an appropriate oxygen doping amount makes the refractive index of the hydrogenated amorphous silicon oxide layer slightly smaller than that of the hydrogenated amorphous silicon layer and has high transmittance, which is beneficial to reducing the parasitic absorption of light, increasing the light transmittance, improving the light utilization rate, and contributing to the improvement of the short-circuit current of the battery. Under the same conditions, if the film thickness of the hydrogenated amorphous silicon oxide layer is too large, it will lead to a relatively high resistivity and a large impact on the electrical properties of the passivation layer. If it is too small or the oxygen doping amount is inappropriate, it will lead to a poor effect of inhibiting the epitaxial and twin growth at the crystal silicon interface of the silicon wafer, and an inappropriate oxygen doping amount will lead to a decrease in electrical properties; under the same conditions, if the thickness ratio of the hydrogenated amorphous silicon layer is inappropriate, it will lead to a poor passivation effect on the crystal silicon surface, a large amount of recombination, and a low conductivity.

[0055] In the preferred embodiment of the present invention, by controlling the appropriate flow ratio of hydrogen silane introduced when preparing the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer respectively, the hydrogen content of the corresponding film layer can be controlled within an appropriate range, thereby promoting orderly arrangement of the amorphous silicon film, reducing internal stress, stabilizing the structure, and reducing the microcrystalline silicon factor, making the film denser, improving the passivation quality, and optimizing the passivation effect while enhancing the photoelectric properties of the film layer itself, increasing the optical band gap, increasing transmittance, and reducing optical absorption.

[0056] In a preferred embodiment of the present invention, the hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon oxide layer is less than the hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon layer. The hydrogen-rich hydrogenated amorphous silicon layer has a higher degree of hydrogenation, which is more conducive to improving the passivation effect of the film layer and reducing surface defects and recombination. At the same time, hydrogen doping can also reduce the microstructure factor of the thin film and improve the density of the film layer, which is conducive to obtaining a front passivation layer with both excellent passivation effect and high conductivity.

[0057] In a manufacturing method of the present invention, a specific process is used to deposit a hydrogenated amorphous silicon layer: first, high-speed short-time deposition is performed to form an amorphous disordered structure as quickly as possible to prevent epitaxial growth; then, medium-speed deposition is performed under the condition of introducing silane to supplement the thickness, improve the film passivation effect, and form a thin film intermediate; then, hydrogen plasma treatment is performed and deposition is continued to the target thickness. While increasing the thickness, H is doped to optimize the microstructure factor of the film and improve the uniformity of the film layer; thereby improving battery performance such as open circuit voltage and short circuit current.

[0058] In another manufacturing method of the present invention, there is no need for high-speed short-time deposition of a hydrogen-rich buffer layer and a hydrogen plasma treatment step, and the purpose of inhibiting epitaxial growth at the crystalline silicon interface and increasing transmittance can be achieved, and the deposition steps and duration of the thin film are reduced, which is beneficial to saving production costs and improving production capacity. However, compared with the preparation method, the present invention adopts a manufacturing method of high-speed short-time deposition of a hydrogen-rich buffer layer and a hydrogen plasma treatment step. The high-speed deposition of a relatively disordered amorphous silicon film layer can further improve the passivation effect, and the hydrogen plasma treatment is beneficial to improving the light transmittance of the film layer, while optimizing the uniformity of the film and reducing defects, thereby being more beneficial to improving battery performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 It is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0061] Description of Reference Numerals

[0062] 101-N-type silicon wafer; 201-tunneling oxide layer; 202-N-type polysilicon layer; 401-first intrinsic amorphous silicon layer; 501-second intrinsic amorphous silicon layer; 502-microcrystalline silicon oxide layer; 601-P-type amorphous silicon layer; 701-anti-reflection layer; 801-transparent conductive film; 901-metal electrode. DETAILED DESCRIPTION

[0063] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0065] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0066] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0067] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0068] The electrical conductivity in the present invention is obtained by measuring the resistivity σ using a four-probe resistivity tester and calculating according to the electrical conductivity ρ=1 / σ.

[0069] In the present invention, the average transmittance in the visible light band is obtained by testing with an ultraviolet-visible spectrophotometer.

[0070] In the present invention, the hydrogen dilution ratio refers to the flow ratio of hydrogen and silane introduced during the preparation of the corresponding film layer.

[0071] In a first aspect, the present invention provides a back-contact battery, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, and a front passivation layer and an antireflection layer sequentially arranged on the front surface of the silicon wafer. The front passivation layer includes a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer. The film thickness of the hydrogenated amorphous silicon oxide layer is 0.5 - 2 nm. When preparing the hydrogenated amorphous silicon oxide layer, the oxygen doping amount is controlled at 5% - 15% by mass percentage, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12.

[0072] The oxygen doping amount is 5% - 15%, for example, specifically it can be 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, etc. and the range between any two point values.

[0073] The thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12, for example, specifically it can be 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, 1:11, 1:12, etc. and the range between any two point values.

[0074] In some preferred embodiments of the present invention, the conductivity of the hydrogenated amorphous silicon oxide layer is 1.0×10 -7 S / cm - 1.0×10 -6 S / cm, and its average transmittance in the visible light band is 80% - 90%; the conductivity of the hydrogenated amorphous silicon layer is 1.0×10 -6 S / cm - 1.0×10 -4 S / cm, and its average transmittance in the visible light band is 70% - 80%. The hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer of the present invention respectively have appropriate conductivity and their average transmittance in the visible light band, which is more conducive to increasing the light transmittance, improving the passivation quality, reducing the parasitic absorption, while reducing the influence on the carrier transport, further increasing the short-circuit current of the battery, and thus improving the battery conversion efficiency.

[0075] In some preferred embodiments of the present invention, the film thickness of the hydrogenated amorphous silicon layer is 4 - 6 nm, for example, specifically it can be 4 nm, 4.3 nm, 4.5 nm, 4.8 nm, 5 nm, 5.5 nm, 5.7 nm, 6 nm, etc., and the range between any two point values. Using a hydrogenated amorphous silicon layer with an appropriate film thickness is more conducive to improving the passivation quality of the interface, reducing carrier recombination, increasing the open-circuit voltage of the battery, and thus enhancing the conversion efficiency of the battery. Under the same conditions, if the film thickness of the hydrogenated amorphous silicon layer is too large, it will lead to a decrease in the transmittance and conductivity of the thin film, affecting the optical and electrical properties; if the film thickness is too small, the passivation effect will be poor.

[0076] In some preferred embodiments of the present invention, the volume flow ratio of hydrogen to silane introduced during the preparation of the hydrogenated amorphous silicon oxide layer is 2.5 - 10:1, and the volume flow ratio of hydrogen to silane introduced during the preparation of the hydrogenated amorphous silicon layer is 4 - 16:1. Using hydrogenated amorphous silicon oxide layers and hydrogenated amorphous silicon layers with appropriate hydrogen contents is more conducive to improving the passivation quality, increasing the transmittance of the film layer, and increasing the short-circuit current of the battery.

[0077] In some preferred embodiments of the present invention, the hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon oxide layer is less than that during the preparation of the hydrogenated amorphous silicon layer, which is more conducive to inhibiting the epitaxial growth of silicon at the interface and improving the passivation effect. Stacking a hydrogenated amorphous silicon layer with a higher hydrogen dilution ratio is beneficial to increasing the conductivity, thereby obtaining a front passivation layer that takes into account excellent passivation effects and high conductivity.

[0078] In some preferred embodiments of the present invention, the front passivation layer further includes a microcrystalline silicon oxide layer provided on the outer surface of the hydrogenated amorphous silicon layer, and the antireflection layer is provided on the outer surface of the microcrystalline silicon oxide layer. Using the microcrystalline silicon oxide layer in combination with the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer is more conducive to exerting the field passivation effect, reducing the carrier recombination loss, and improving the passivation effect.

[0079] Further preferably, the thickness of the microcrystalline silicon oxide layer is 6 - 20 nm, which is more conducive to increasing the light transmittance.

[0080] In some preferred embodiments of the present invention, the thickness ratio of the hydrogenated amorphous silicon oxide layer, the hydrogenated amorphous silicon layer, and the microcrystalline silicon oxide layer is 1:2 - 12:10 - 56, preferably 1:5 - 12:10 - 14. With this preferred scheme, the first hydrogenated amorphous silicon oxide layer has good passivation performance but poor electrical performance, so it is set extremely thin to inhibit epitaxial growth. To further improve the passivation effect, adding a hydrogenated amorphous silicon layer with an appropriate thickness is beneficial to increasing the open-circuit voltage of the battery, while the microcrystalline silicon oxide layer is conducive to enhancing the field passivation effect and reducing carrier recombination. It forms an enhanced field passivation effect with the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon; at the same time, it has good light transmittance performance, which is more conducive to increasing the open-circuit voltage and short-circuit current of the battery, and thus enhancing the conversion efficiency of the battery.

[0081] In some preferred embodiments of the present invention, when preparing the microcrystalline silicon oxide layer, the oxygen doping amount is controlled to be 20%-80% by mass, preferably 20%-70%.

[0082] Preferably, the ratio of the oxygen doping amounts by mass of the hydrogenated amorphous silicon oxide layer and the microcrystalline silicon oxide layer in the corresponding preparations is 1:1-8.5, more preferably 1:1-5, and further preferably 1:1.6-5. Using a microcrystalline silicon oxide layer with an appropriate oxygen doping amount, in combination with a hydrogenated amorphous silicon oxide layer with an appropriate oxygen doping amount, is more conducive to improving the front transmittance of the battery, thereby increasing the short-circuit current of the battery.

[0083] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0084] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer. Using a combined passivation structure, in combination with a specific front passivation structure, is more conducive to improving the passivation quality, increasing the light transmittance, enhancing the field passivation effect, and improving the open-circuit voltage and short-circuit current of the battery.

[0085] Further preferably, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 100-200 nm, and the effective doping concentration is 5e19 cm -3 -5e20 cm -3 , the thickness of the intrinsic amorphous silicon layer is 5-12 nm, the film thickness of the second doped silicon layer is 5-25 nm, and the effective doping concentration is 1e19 cm -3 -5e20 cm -3 . One of the first doped polysilicon layer and the second doped silicon layer is N-type, and the other is P-type.

[0086] Further preferably, the thickness ratio of the hydrogenated amorphous silicon oxide layer, the hydrogenated amorphous silicon layer, the intrinsic amorphous silicon layer, and the tunneling oxide layer is 1:2-12:2-16:0.5-2, which is more conducive to balancing the matching between the emitter and the front surface field of the battery and is beneficial to improving the conversion efficiency of the battery.

[0087] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outward to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening area is formed between adjacent first semiconductor layers. The second semiconductor opening area and the first semiconductor opening area are arranged at intervals, and the area between them is the interval area.

[0088] Further preferably, in the spacer region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer. The thickness of the mask layer can be, for example, 60 - 80 nm.

[0089] In some preferred embodiments of the present invention, the back-contact cell further includes a metal electrode and a conductive film layer disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed in a portion of the conductive film layer located in the spacer region; the metal electrode is disposed on the outer surface of the respective conductive film layer corresponding to the second semiconductor opening region and the first semiconductor opening region. The conductive film layer is preferably a transparent conductive film layer, such as an indium oxide-based transparent conductive film or a tin oxide-based transparent conductive film. The thickness of the conductive film layer can be, for example, 50 - 150 nm.

[0090] In the present invention, the types and corresponding thickness ranges of the antireflection layer, the conductive film layer, and the mask layer can be referred to the corresponding ranges in the prior art, respectively, and can all be used in the present invention, which will not be elaborated here.

[0091] Preferably, a portion of the silicon wafer at the position of the second semiconductor opening region is a textured surface, and a portion of the silicon wafer at the position corresponding to the first semiconductor layer is a polished surface.

[0092] In a second aspect, the present invention provides a method for manufacturing a back-contact cell, including the following steps:

[0093] S01. Provide a double-sided polished silicon wafer;

[0094] S02. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0095] S03. Perform a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0096] S04. Through texturing cleaning, form a textured surface on the front surface of the silicon wafer and the second semiconductor opening region, and then perform a step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer or do not perform the step of removing the mask layer;

[0097] S05. Deposit a second passivation layer on the back surface obtained in S04;

[0098] S06. Sequentially form a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on the front surface of the silicon wafer obtained in S05; control the film thickness of the hydrogenated amorphous silicon oxide layer to be 0.5 - 2 nm, control the oxygen doping amount in mass percentage to be 5% - 15% when preparing the hydrogenated amorphous silicon oxide layer, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12;

[0099] Among them, the deposition process of the hydrogenated amorphous silicon layer includes: first, high-speed short-time deposition is carried out under the condition of introducing silane, then medium-speed deposition is carried out under the condition of introducing silane to form a thin-film intermediate, then hydrogen plasma treatment is carried out, and then it is deposited to the target thickness under the condition of introducing silane and hydrogen (preferably at a deposition rate of 0.5-2 Å / s); among them, the conditions for high-speed short-time deposition include: the deposition rate is 4-10 Å / s, and the deposition duration is 1-5 s; the conditions for medium-speed deposition include: the deposition rate is 0.5-2 Å / s, and the deposition duration is 10-40 s; the conditions for hydrogen plasma treatment are: the temperature is 180-230 °C, the reaction pressure is 20-150 Pa, and the treatment duration is 10-40 s;

[0100] S08. Deposit a second doped silicon layer on the back surface, and the second passivation layer and the second doped silicon layer form a second semiconductor layer;

[0101] S09. Deposit an antireflection layer on the front surface obtained in S08.

[0102] In some preferred embodiments of the second aspect of the present invention, the temperature during the deposition process of the hydrogenated amorphous silicon layer is controlled at 180-230 °C. And the temperatures of each stage such as high-speed short-time deposition and medium-speed deposition can be the same or different, and can be adjusted according to actual needs.

[0103] Preferably, the pressures of high-speed short-time deposition and medium-speed deposition are each independently 30-100 Pa.

[0104] Preferably in the present invention, the flow rates of silane in each stage during the deposition process of the hydrogenated amorphous silicon layer are each independently 200-3000 sccm.

[0105] During the deposition process of the hydrogenated amorphous silicon layer, the deposition rate can be adjusted by adjusting process parameters such as the silane flow rate, deposition pressure, and deposition power.

[0106] In some preferred embodiments of the second aspect of the present invention, the conditions for depositing the hydrogenated amorphous silicon layer to the target thickness under the condition of introducing silane and hydrogen include: the volume flow ratio of hydrogen to silane is 4-16:1, and the pressure is 30-250 Pa.

[0107] Adopting the suitable deposition conditions of the present invention to form the hydrogenated amorphous silicon layer is more conducive to maintaining a good passivation effect while shortening the process cycle and improving production capacity.

[0108] In the third aspect, the present invention provides a method for manufacturing a back-contact battery, including the following steps:

[0109] S01. Provide a double-sided polished silicon wafer;

[0110] S02. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0111] S03. Perform the first etching opening on the back obtained in S02 to form a second semiconductor opening region;

[0112] S04. Through texturing cleaning, form a textured surface on the front of the silicon wafer and the second semiconductor opening region, and then perform the step of removing the mask layer outside the second semiconductor opening region on the back of the silicon wafer through cleaning or do not perform the step of removing the mask layer;

[0113] S05. Deposit a second passivation layer on the back obtained in S04;

[0114] S06. Sequentially form a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer on the front of the silicon wafer obtained in S05; control the film thickness of the hydrogenated amorphous silicon oxide layer to be 0.5 - 2 nm, control the oxygen doping amount of the hydrogenated amorphous silicon oxide layer in mass percentage during preparation to be 5% - 15%, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2 - 12;

[0115] Among them, the deposition process of the hydrogenated amorphous silicon layer includes: first perform the first deposition under the condition of introducing silane to form an amorphous silicon thin film intermediate; then perform the second deposition to the target thickness under the conditions of introducing silane and hydrogen; the conditions of the first deposition include: the deposition rate is 1 - 2 Å / s, and the deposition duration is 10 - 40 s; the conditions of the second deposition include: the volume flow ratio of hydrogen to silane is 4 - 16, and the deposition rate is 0.5 - 2 Å / s;

[0116] S08. Deposit a second doped silicon layer on the back, and the second passivation layer and the second doped silicon layer form a second semiconductor layer;

[0117] S09. Deposit an antireflection layer on the front obtained in S08.

[0118] In some preferred embodiments of the present invention, the temperature is controlled at 180 - 230 °C during the deposition process of the hydrogenated amorphous silicon layer.

[0119] In some preferred embodiments of the present invention, the pressure of the first deposition is 30 - 100 Pa, and the pressure of the second deposition is 30 - 250 Pa.

[0120] Among them, in the first deposition process, since the silane molecular formula is SiH4, there will be various hydrogen atom-containing radicals such as SiH3, SiH2, and SiH during the thin film deposition process, so the formed is a hydrogenated amorphous silicon thin film intermediate, which has a high degree of hydrogenation, but its film layer structure is relatively disordered; cooperating with the subsequent second deposition under the conditions of introducing silane and hydrogen can improve the orderliness of the film layer structure and further increase the degree of hydrogenation.

[0121] In some preferred embodiments of the second or third aspect of the present invention, the deposition conditions of the hydrogenated amorphous silicon oxide layer include: the temperature is 180 - 230 °C, the pressure is 20 - 100 Pa, and the deposition rate is 0.3 Å / s - 1 Å / s.

[0122] In some preferred embodiments of the second or third aspect of the present invention, the deposition conditions of the hydrogenated amorphous silicon oxide layer further include: the process gas contains silane, carbon dioxide, and hydrogen, where carbon dioxide is 5% - 50% of the volume flow rate of silane, and the volume flow rate ratio of hydrogen to silane is 2.5 - 10:1. Further preferably, the silane flow rate is 200 - 800 sccm.

[0123] Forming a hydrogenated amorphous silicon oxide layer by using the present invention under the above deposition conditions is more conducive to suppressing epitaxial growth on the surface of crystalline silicon, improving the passivation effect, and increasing the open-circuit voltage of the battery.

[0124] In the second or third aspect of the present invention, the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer are respectively formed by PECVD.

[0125] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes performing between S06 and S08: S07, depositing a microcrystalline silicon oxide layer on the front surface obtained in S06.

[0126] The texturing and cleaning of the present invention is used to remove the residual mask layer and the first semiconductor layer in the second semiconductor opening area, and at the same time form a textured surface on the exposed part of the silicon wafer.

[0127] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes:

[0128] S10, performing a second etching opening on a part of the second semiconductor layer on the back surface to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0129] S11, depositing a conductive film layer on the back surface obtained in S10;

[0130] S12, performing a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0131] S13, respectively forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0132] In a fourth aspect, the present invention provides a back contact battery obtained by the manufacturing method of the back contact battery described in the second or third aspect.

[0133] In a fifth aspect, the present invention provides a photovoltaic module, which includes the back-contact battery described in the first aspect or the back-contact battery described in the fourth aspect.

[0134] Embodiments of the present invention will be described in detail below. These embodiments are exemplary and are only used to explain the present invention, and should not be construed as a limitation to the present invention.

[0135] Embodiment 1

[0136] A back-contact battery is prepared by the following method:

[0137] S01, providing a polished and cleaned N-type silicon wafer 101; the N-type silicon wafer 101 removes the damaged layer on the surface of the silicon wafer by polishing and cleaning, and remains clean; the N-type silicon wafer 101 is a single-crystalline silicon wafer.

[0138] S02, forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer; the first semiconductor layer includes a tunneling oxide layer 201 and an N-type polysilicon layer 202; the thickness of the tunneling oxide layer 201 is 1.5 nm; the thickness of the N-type polysilicon layer 202 is 150 nm and the effective doping concentration is 1e20 cm -3 ; the mask layer is silicon nitride with a thickness of 60 nm;

[0139] S03, opening on the back surface of the silicon wafer obtained in S02 by laser etching, removing the mask layer, the N-type polysilicon layer 202 and the tunneling oxide layer 201 in the second semiconductor opening area;

[0140] S04, performing texturing cleaning on the silicon wafer obtained in S03, removing all mask layers, the remaining N-type polysilicon layer 202 and the tunneling oxide layer 201; and forming a textured surface on the exposed surface of the silicon wafer;

[0141] S05, depositing a first intrinsic amorphous silicon layer 401 of the second semiconductor layer on the back surface obtained in S04; the first intrinsic amorphous silicon layer 401 is formed by plate-type PECVD with a thickness of 9 nm;

[0142] S06, forming a second intrinsic amorphous silicon layer 501 on the front surface obtained in S05 by PECVD; the second intrinsic amorphous silicon layer 501 includes a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer.

[0143] The process of forming the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer specifically includes:

[0144] First, a hydrogenated amorphous silicon oxide layer is deposited under the following conditions: temperature is 200 °C, process gases are silane, carbon dioxide, and hydrogen, the flow rate of silane is 300 sccm, the ratio of the flow rate of carbon dioxide to that of silane is 20%, the ratio of the flow rate of hydrogen to that of silane is 6:1, the pressure is 60 Pa, the deposition rate is 0.6 Å / s, the thickness is 1 nm, and the oxygen doping content in terms of mass percentage after conversion is 13%, and the conductivity is 5×10 -7 S / cm, and its average transmittance in the visible light band is 85%.

[0145] Subsequently, a hydrogenated amorphous silicon layer is deposited. Specifically, a step-by-step deposition method is adopted. The conditions for the first step are: temperature is 200 °C, process gas is silane with a flow rate of 3000 sccm, pressure is 60 Pa, deposition rate is 5 Å / s, deposition duration is 5 s, to form an intermediate a of a hydrogenated amorphous silicon thin film; the conditions for the second step are: temperature is 200 °C, process gas is silane with a flow rate of 1000 sccm, pressure is 50 Pa, deposition rate is 2 Å / s, deposition duration is 10 s, to form an intermediate b of a hydrogenated amorphous silicon thin film; in the third step, the intermediate b of the hydrogenated amorphous silicon thin film is treated with hydrogen plasma under the conditions: temperature is 200 °C, reaction pressure is 100 Pa, treatment duration is about 20 s; the conditions for the fourth step are: temperature is 200 °C, process gases are silane and hydrogen, the flow rate of silane is 900 sccm, the ratio of the flow rate of hydrogen to that of silane is 10:1, pressure is 100 Pa, deposition rate is 1 Å / s, and the finally formed hydrogenated amorphous silicon layer has a film thickness of 6 nm, conductivity is 3×10 -5 S / cm, and its average transmittance in the visible light band is 78%.

[0146] S07. Deposit a microcrystalline silicon oxide layer 502 with a thickness of 10 nm and an oxygen doping content of 50% on the front side of the silicon wafer obtained in S06;

[0147] S08. Deposit a P-type amorphous silicon layer 601 of the second semiconductor layer on the back side of the silicon wafer obtained in S07; the film thickness of the P-type amorphous silicon layer 601 is 20 nm, and the effective doping concentration is 5e20 cm -3 ;

[0148] S09. Deposit an antireflection layer 701 on the front side of the silicon wafer obtained in S08;

[0149] S10. Open an opening on the back side of the silicon wafer obtained in S09 by laser etching to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area, and then perform cleaning;

[0150] S11. Deposit a transparent conductive thin film 801 on the back side of the silicon wafer obtained in S10; the thickness of the transparent conductive thin film 801 is 100 nm;

[0151] S12. Etch an opening on the surface of the spacer region between the second semiconductor opening region and the first semiconductor opening region on the back surface of the silicon wafer obtained in S11 to form an isolation groove between the second semiconductor opening region and the first semiconductor opening region, isolating the first semiconductor and the second semiconductor to avoid short circuit;

[0152] S13. Form metal electrodes 901 on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back surface of the silicon wafer obtained in S12, as Figure 1 shown.

[0153] Example 2

[0154] Refer to Example 1, the difference is that the step of depositing the hydrogenated amorphous silicon layer is different. Specifically, the step-by-step deposition method is adopted. The conditions for the first step are: temperature 200 °C, process gas: silane flow rate 1500 sccm, pressure 50 Pa, deposition rate 1.5 Å / s, deposition duration 20 s, to form an intermediate hydrogenated amorphous silicon thin film; the conditions for the second step are: temperature 200 °C, process gas: silane and hydrogen, silane flow rate 1000 sccm, flow rate ratio of hydrogen to silane 12:1; pressure 100 Pa, deposition rate 1 Å / s, finally forming a hydrogenated amorphous silicon layer with a film thickness of 6 nm, the conductivity is 3×10 -6 S / cm, and its average transmittance in the visible light band is 77%.

[0155] Example 3

[0156] Refer to the method of Example 1, the difference is that the film thickness of the hydrogenated amorphous silicon layer is adjusted to 4 nm, and the corresponding preparation process parameters are adjusted accordingly: the deposition duration in the first step of hydrogenated amorphous silicon deposition is reduced by 20%, and the calculated thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:4. The conductivity of the hydrogenated amorphous silicon layer is 4×10 - 5 S / cm.

[0157] Example 4

[0158] Refer to the method of Example 1, the difference is that the hydrogen introduced during the preparation of the hydrogenated amorphous silicon oxide layer is adjusted so that the volume flow rate ratio of hydrogen to silane is 10:1. The conductivity of the hydrogenated amorphous silicon oxide layer is 1×10 -6 S / cm, and its average transmittance in the visible light band is 80%.

[0159] Example 5

[0160] Refer to the method of Example 1, the difference is that the microcrystalline silicon oxide layer is not provided.

[0161] Example 6

[0162] It was carried out according to the method of Example 1, except that the thickness of the microcrystalline silicon oxide layer was adjusted to 15 nm, so that the thickness ratio of the hydrogenated amorphous silicon oxide layer, the hydrogenated amorphous silicon layer, and the microcrystalline silicon oxide layer was 1:6:15.

[0163] Example 7

[0164] It was carried out according to the method of Example 1, except that the oxygen doping amount of the microcrystalline silicon oxide layer was controlled at 80% and the thickness remained unchanged.

[0165] Comparative Example 1

[0166] It was carried out according to the method of Example 1, except that the hydrogenated amorphous silicon oxide layer was not provided.

[0167] Comparative Example 2

[0168] It was carried out according to the method of Example 1, except that the hydrogenated amorphous silicon layer was not provided.

[0169] Comparative Example 3

[0170] It was carried out according to the method of Example 1, except that when preparing the hydrogenated amorphous silicon oxide layer, the oxygen doping amount was controlled at 17% by mass content, and the carbon dioxide flow rate during the preparation of the hydrogenated amorphous silicon oxide layer was correspondingly increased by 60% to meet this condition. The conductivity of this hydrogenated amorphous silicon oxide layer was 2×10 -7 S / cm, and its average transmittance in the visible light band was 86%.

[0171] Comparative Example 4

[0172] It was carried out according to the method of Example 1, except that the thickness of the hydrogenated amorphous silicon oxide layer was adjusted to 4 nm. Correspondingly, the process parameters of the hydrogenated amorphous silicon oxide layer were changed: the deposition duration was increased by 200%. The conductivity of this hydrogenated amorphous silicon oxide layer was 2×10 -10 S / cm, and its average transmittance in the visible light band was 84%.

[0173] Test Example

[0174] The back-contact batteries obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. Each performance index of each example and comparative example was respectively converted with Comparative Example 1 as the reference benchmark. The data of Comparative Example 1 was the normalization benchmark 1.000, and other examples were converted based on Comparative Example 1. For example, the open-circuit voltage of Example 1 / the open-circuit voltage of Comparative Example 1 was 1.004. Among them, when converting, the unit of the open-circuit voltage was V, the unit of the fill factor was %, and the unit of the battery conversion efficiency was %.

[0175] Table 1

[0176]

[0177] As can be seen from the above results, compared with the comparative example, adopting the embodiment scheme of the present invention is beneficial to effectively suppressing the epitaxial and twin growth at the crystal silicon interface of the silicon wafer, can enhance the passivation effect on the crystal silicon surface, is beneficial to improving the open-circuit voltage, fill factor, and short-circuit current of the battery, and further improves the battery conversion efficiency.

[0178] Furthermore, according to Embodiment 1 and Embodiments 3-7, it can be known that adopting the preferred scheme of the present invention is more beneficial to improving the open-circuit voltage, fill factor, and short-circuit current of the battery, and further improving the battery conversion efficiency.

[0179] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a back contact battery, characterized in that: The steps include: S01. Provide double-sided polished silicon wafers; S02, sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S03, performing a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region; S04, forming a textured surface on the front side of the silicon wafer and the second semiconductor opening region by texturing and cleaning, and then performing a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer by cleaning, or not performing a step of removing the mask layer; S05, depositing a second passivation layer on the back surface obtained in S04; S06, forming a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer in sequence on the front side of the silicon wafer obtained in S05; controlling the film thickness of the hydrogenated amorphous silicon oxide layer to be 0.5-2 nm, controlling the oxygen doping amount of the hydrogenated amorphous silicon oxide layer to be 5%-15% by mass during preparation, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer to be 1:2-12; The deposition process of the hydrogenated amorphous silicon layer includes: firstly, high-speed short-time deposition under the condition of introducing silane, then medium-speed deposition under the condition of introducing silane to form a thin film intermediate, then hydrogen plasma treatment, and then deposition to the target thickness at a deposition rate of 0.5-2Å / s under the condition of introducing silane and hydrogen; wherein, the conditions of high-speed short-time deposition include: deposition rate of 4-10Å / s, deposition time of 1-5s; the conditions of medium-speed deposition include: deposition rate of 0.5-2Å / s, deposition time of 10-40s; the conditions of hydrogen plasma treatment are: temperature of 180-230°C, reaction pressure of 20-150Pa, and treatment time of 10-40s; S08, depositing a second doped silicon layer on the back side, and the second passivation layer and the second doped silicon layer form a second semiconductor layer; S09, depositing an anti-reflection layer on the front surface obtained in S08.

2. The method for manufacturing a back contact battery according to claim 1, characterized in that: During the deposition of the hydrogenated amorphous silicon layer, the temperature is controlled at 180-230°C, and the pressures of the high-speed short-time deposition and the medium-speed deposition are independently 30-100 Pa; And / or, the conditions for depositing the hydrogenated amorphous silicon layer to a target thickness under the conditions of introducing silane and hydrogen include: a volume flow ratio of hydrogen to silane of 4-16:1 and a pressure of 30-250Pa.

3. The method for manufacturing a back contact battery according to claim 1 or 2, characterized in that: The deposition conditions of the hydrogenated amorphous silicon oxide layer include: a temperature of 180-230°C, process gases comprising: silane, carbon dioxide and hydrogen, wherein carbon dioxide is 5%-50% of the volume flow of silane, the volume flow ratio of hydrogen to silane is 2.5-10:1, the pressure is 20-100Pa, and the deposition rate is 0.3Å / s-1Å / s.

4. The method for manufacturing a back contact battery according to claim 1 or 2, characterized in that: The method for manufacturing the back contact cell further includes, between S06 and S08, performing: S07, depositing a microcrystalline silicon oxide layer on the front surface obtained in S06.

5. The method for manufacturing a back contact battery according to claim 1 or 2, characterized in that: The method for manufacturing the back contact battery further includes: S10, performing a second etching opening on a portion of the second semiconductor layer on the back side to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S11, depositing a conductive film layer on the back surface obtained in S10; S12, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S13, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

6. A back contact battery, characterized in that: It is prepared based on the preparation method according to any one of claims 1 to 5.

7. The back contact cell according to claim 6, characterized in that: The invention comprises a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, and a front passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, wherein the two ends of the second semiconductor layer respectively extend outward to cover the part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening area is formed between adjacent first semiconductor layers, the second semiconductor opening area is arranged at intervals from the first semiconductor opening area, and the area between them is the interval area; the front passivation layer comprises a hydrogenated amorphous silicon oxide layer and a hydrogenated amorphous silicon layer sequentially arranged on the front side of the silicon wafer, the film thickness of the hydrogenated amorphous silicon oxide layer is 0.5-2nm, the oxygen doping amount of the hydrogenated amorphous silicon oxide layer is controlled to be 5%-15% in terms of mass percentage during preparation, and the thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer is 1:2-12.

8. The back contact battery according to claim 7, characterized in that: The conductivity of hydrogenated amorphous silicon oxide layer is 1.0×10 -7 S / cm-1.0×10 -6 S / cm, its average transmittance in the visible light band is 80%-90%; the conductivity of the hydrogenated amorphous silicon layer is 1.0×10 -6 S / cm-1.0×10 -4 S / cm, and its average transmittance in the visible light band is 70%-80%.

9. The back contact cell according to claim 7, characterized in that: The thickness of the hydrogenated amorphous silicon layer is 4-6 nm.

10. The back contact cell according to claim 7, characterized in that: The volume flow ratio of hydrogen and silane introduced during the preparation of the hydrogenated amorphous silicon oxide layer is 2.5-10:1, and the volume flow ratio of hydrogen and silane introduced during the preparation of the hydrogenated amorphous silicon layer is 4-16:

1.

11. The back contact cell according to claim 7 or 10, characterized in that: The hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon oxide layer is smaller than the hydrogen dilution ratio during the preparation of the hydrogenated amorphous silicon layer.

12. The back contact cell according to claim 7, characterized in that: The front passivation layer also includes a microcrystalline silicon oxide layer arranged on the outer surface of the hydrogenated amorphous silicon layer, and the anti-reflection layer is arranged on the outer surface of the microcrystalline silicon oxide layer. The thickness of the microcrystalline silicon oxide layer is 6-20nm. When preparing the microcrystalline silicon oxide layer, the oxygen doping amount is controlled to be 20%-80% by mass percentage.

13. The back contact cell according to claim 12, characterized in that: The thickness ratio of the hydrogenated amorphous silicon oxide layer to the hydrogenated amorphous silicon layer and the microcrystalline silicon oxide layer is 1:2-12:10-56, and / or the oxygen doping ratio of the hydrogenated amorphous silicon oxide layer and the microcrystalline silicon oxide layer in the corresponding preparation in terms of mass percentage is 1:1-8.

5.

14. The back contact cell according to claim 7, characterized in that: The first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

15. The back contact cell according to claim 14, characterized in that The first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, and the thickness ratio of the hydrogenated amorphous silicon oxide layer and the hydrogenated amorphous silicon layer, the intrinsic amorphous silicon layer, and the tunneling oxide layer is 1:2-12:2-16:0.5-2.

16. The back contact cell according to claim 7, characterized in that: In the spacing area, a mask layer is set between the first semiconductor layer and the second semiconductor layer, or no mask layer is set; the back contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is opened on the part of the conductive film layer located in the spacing area; the metal electrode is set on the outer surface of the conductive film layer corresponding to the second semiconductor opening area and the first semiconductor opening area.

17. A photovoltaic module, characterized in that: It comprises a back contact cell as claimed in any one of claims 6 to 16.

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