Display device

Abstract

The invention provides a display device. The reliability of the display device is improved. The display device includes a light emitting element, a first transistor, and a second transistor, the first transistor including: a first gate electrode provided on a substrate; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping the first gate electrode; a second insulating film provided on the first oxide semiconductor layer; and a first conductive layer provided on the second insulating film, the second transistor including: a first insulating film provided on the substrate; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer, the second insulating film having a film thickness smaller than a film thickness of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping the second oxide semiconductor layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel. Another embodiment of the present invention relates to a display device using the semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices using oxide semiconductor films as channels has been progressing in place of silicon semiconductors such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon (for example, see Patent Documents 1 to 6). Semiconductor devices including such oxide semiconductor films can be formed with a simple structure and a low-temperature process, similarly to semiconductor devices including amorphous silicon films. In addition, it is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] In addition, the use of oxide semiconductors as semiconductor layers constituting organic EL display devices has attracted much attention. Transistors using oxide semiconductor layers have low off-leakage current and can be driven at low frequencies, so they are expected to be used in low-power display devices. In particular, when transistors using oxide semiconductor layers are used in self-luminous organic EL display devices, the effect of reducing power consumption is great.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0007] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0008] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0009] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0010] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0011] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0012] Problems to be solved by the invention

[0013] A problem with transistors using an oxide semiconductor layer is that the threshold voltage varies over time, etc., and reliability is low. When a transistor using an oxide semiconductor layer is formed with a bottom gate structure or a double gate structure, it is difficult to ensure sufficient reliability.

[0014] In view of the above problems, one object of an embodiment of the present invention is to improve the reliability of a display device.

[0015] Means for solving problems

[0016] A display device according to one embodiment of the present invention includes: a light-emitting element; a first transistor that controls a current value flowing from a driving power supply line to the light-emitting element; and a second transistor that writes a voltage corresponding to the light-emitting brightness of the light-emitting element into a first gate electrode of the first transistor, wherein the first transistor includes: a first gate electrode; a first insulating film that is disposed on the first gate electrode; a first oxide semiconductor layer that is disposed on the first insulating film and has a region overlapping with the first gate electrode; a second insulating film that is disposed on the first oxide semiconductor layer; and a first conductive layer that is disposed on the second insulating film, wherein the second transistor includes: a first insulating film; a second oxide semiconductor layer that is disposed on the first insulating film; and a second conductive layer that is disposed on the second insulating film. A gate electrode is provided on the first oxide semiconductor layer and the second oxide semiconductor layer and has a film thickness smaller than that of the first insulating film; and a second gate electrode is provided on the second insulating film and has a region overlapping with the second oxide semiconductor layer, the first oxide semiconductor layer has a first channel region and a first high-concentration impurity region provided in a manner sandwiching the first channel region, the second oxide semiconductor layer has a second channel region and a second high-concentration impurity region provided in a manner sandwiching the second channel region, the first conductive layer is electrically connected to the light-emitting element, and an etching rate of less than 3 nm / min when the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component.

[0017] A display device according to one embodiment of the present invention includes: a light-emitting element; a first transistor that controls a current value flowing from a driving power supply line to the light-emitting element; and a second transistor that writes a voltage corresponding to the light-emitting brightness of the light-emitting element into a first gate electrode of the first transistor, wherein the first transistor includes: a first gate electrode; a first insulating film that is disposed on the first gate electrode; and a first oxide semiconductor layer that is disposed on the first insulating film and has a region overlapping with the first gate electrode, wherein the second transistor includes: a first insulating film; a second oxide semiconductor layer that is disposed on the first insulating film; and a second insulating film that is disposed on the first oxide semiconductor layer and the second oxide semiconductor layer. , and having a film thickness smaller than that of the first insulating film; and a second gate electrode, which is arranged on the second insulating film and has a region overlapping with the second oxide semiconductor layer, the first oxide semiconductor layer has a first channel region, a low-concentration impurity region arranged in a manner sandwiching the first channel region, and a first high-concentration impurity region arranged adjacent to the low-concentration impurity region, the second oxide semiconductor layer has a second channel region and a second high-concentration impurity region arranged in a manner sandwiching the second channel region, and an etching rate of less than 3 nm / min when the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a plan view illustrating the structure of a display device according to one embodiment of the present invention.

[0019] Figure 2 This is an equivalent circuit diagram of a pixel included in a display device according to one embodiment of the present invention.

[0020] Figure 3 It is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention.

[0021] Figure 4 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0022] Figure 5 It is a cross-sectional view explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0023] Figure 6 It is a cross-sectional view explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0024] Figure 7 It is a cross-sectional view explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0025] Figure 8 It is a cross-sectional view explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0026] Fig. 9 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0027] Fig.10 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0028] Fig.11 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0029] Fig.12 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0030] Fig.13 It is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention.

[0031] Fig.14 This is an equivalent circuit diagram of a pixel included in a display device according to one embodiment of the present invention.

[0032] Fig.15 It is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention.

[0033] Fig.16 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0034] Fig.17 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0035] Fig.18 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0036] Fig.19 It is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention.

[0037] Fig. 20 It is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention.

[0038] Fig.21 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0039] Fig. 22 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0040] Fig.23It is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention.

[0041] Fig.24 This is an equivalent circuit diagram of a pixel included in a display device according to one embodiment of the present invention.

[0042] Fig.25 yes Fig.24 The timing diagram of the pixel circuit is shown.

[0043] Fig.26 This is an equivalent circuit diagram of a pixel included in a display device according to one embodiment of the present invention.

[0044] Fig. 27 yes Fig.26 The timing diagram of the pixel circuit is shown.

[0045] Description of Reference Numerals

[0046] 100: display device, 101: substrate, 102: display area, 103: pixel, 103A to 103G: pixel, 104_1, 104_2: gate drive circuit, 105: driver IC, 106: terminal, 107: terminal portion, 108: flexible printed circuit, 109: peripheral area, 110: touch sensor, 202: base film, 204_1, 204_2: conductive layer, 205: metal oxide film, 206: insulating film, 207_1, 207_2: oxide semiconductor layer, 208_1, 208_2: oxide semiconductor layer, 208a: channel region, 208b: high concentration impurities region, 208c: high concentration impurity region, 208d: low concentration impurity region, 208e: low concentration impurity region, 208f: channel region, 208g: high concentration impurity region, 208h: high concentration impurity region, 208i: channel region, 208j: high concentration impurity region, 208k: high concentration impurity region, 210, 210A: transistor, 212: insulating film, 213: metal oxide film, 214: conductive layer, 215: resist mask, 216: insulating film, 218: drain electrode, 220, 220A: transistor, 222: planarization film, 226: pixel electrode, 228: insulating film, 230: Light-emitting element, 232: organic layer, 233: inorganic insulating film, 234: common electrode, 236: inorganic insulating film, 238: organic insulating film, 240: sealing film, 242: inorganic insulating film, 250: transistor, 301: substrate, 302: base film, 304: conductive layer, 306: insulating film, 308: oxide semiconductor layer, 310: transistor, 312: insulating film, 314: conductive layer, 316: insulating film, 318: drain electrode, 320: transistor, 350: transistor, BCT: output transistor, BG: control signal, Cad: additional capacitance, Cel: parasitic capacitance, DRT: drive transistor ,IST: initialization transistor,OLED: light emitting element,Pvdd: high potential power supply,Pvss: low potential power supply,RG: control signal,RST: reset transistor,Sg: write control scan line,SG: control signal,Sga: light emitting control scan line,Sgb: write control scan line,Sgc: reset control scan line,Sgd: initialization control scan line,Sgr: reset control scan line,SLa: high potential power supply,SLb: low potential power supply electrode,SLc: reset power supply line,SST: write transistor,Vini: initialization potential,VL: image signal line,Vrst: reset potential,Vsig: image signal DETAILED DESCRIPTION

[0047] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings, etc. However, the present invention can be implemented in various ways within the scope of the main purpose thereof, and should not be construed as being limited to the contents of the embodiments illustrated below. In addition, with respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method, but these schematic drawings are examples and do not limit the interpretation of the present invention. In addition, in this specification and the drawings, the same or similar elements as those described in the drawings that have appeared are marked with the same figure numbers, and repeated descriptions are sometimes omitted.

[0048] In this specification, when a certain film is processed to form multiple films, these multiple films sometimes have different functions and effects. However, these multiple films are films formed as the same layer in the same process, have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.

[0049] It should be noted that in this specification, etc., expressions such as "upper" and "lower" when describing the accompanying drawings indicate the relative positional relationship between the structure of interest and other structures. In this specification, etc., when observed from the side, the direction from the first substrate described later toward the pixel electrode is defined as "upper", and the opposite direction is defined as "lower". In this specification and technical solution, when expressing the manner of configuring other structures on a certain structure, when it is only expressed as "upper", unless otherwise specified, it includes both the case where other structures are configured just above a certain structure in a manner of being connected to a certain structure, and the case where other structures are further configured above a certain structure separated by other structures.

[0050] (First embodiment)

[0051] Reference Figures 1 to 12 A display device 100 according to one embodiment of the present invention will be described.

[0052] FIG. 1 is a top view illustrating the structure of a display device 100 according to an embodiment of the present invention. Figure 1 As shown, the display device 100 includes a display area 102 and a peripheral area 109 disposed on a substrate 101 .

[0053] The display region 102 includes a plurality of pixels 103 arranged in a matrix. Each of the plurality of pixels 103 includes a plurality of transistors and a light-emitting element.

[0054] The peripheral area 109 is arranged in a manner to surround the display area 102. It should be noted that the peripheral area 109 refers to the area in the substrate 101 from the display area 102 to the end of the substrate 101. In other words, the peripheral area 109 refers to the area outside the display area 102 (i.e., the area outside the display area 102) provided on the substrate 101. The peripheral area 109 has gate drive circuits 104_1, 104_2 and a terminal portion 106 including a plurality of terminals 107. The gate drive circuits 104_1, 104_2 are arranged in a manner to sandwich the display area 102. The plurality of terminals 107 are connected to the flexible printed circuit 108. Although in Figure 1 105 is shown as an example in which a source driving circuit is incorporated in the driver IC 105, but the present invention is not limited to this method, and a source driving circuit may be provided separately from the driver IC 105 on the substrate 101. In addition, an example in which the driver IC 105 is arranged on the flexible printed circuit 108 is shown, but the driver IC 105 may be arranged on the substrate 101 in a manner similar to an IC chip.

[0055] The driver IC 105 is connected to the gate drive circuits 104_1 and 104_2 and a plurality of image signal lines VL. The gate drive circuit 104_1 or the gate drive circuit 104_2 is connected to the pixel 103 via the write control scan line Sg. Among the plurality of write control scan lines Sg, for example, the write control scan lines Sg of the odd rows are connected to the gate drive circuit 104_1, and the write control scan lines Sg of the even rows are connected to the gate drive circuit 104_2. The image signal line VL is connected to the pixel 103. A control signal SG for selecting each pixel 103 is given from the driver IC 105 to the display area 102 via the gate drive circuits 104_1 and 104_2 and the write control scan line Sg. In addition, an image signal Vsig is given from the driver IC 105 to the display area 102 via the image signal line VL. The transistors of the pixels 103 are driven by these signals, and an image corresponding to the image signal Vsig is displayed in the display area 102. It should be noted that the high potential power source SLa and the low potential power source electrode SLb connected to the pixel 103 are connected to different terminals 107 , respectively.

[0056] A glass substrate or a flexible plastic substrate is used as the substrate 101. When a flexible plastic substrate is used as the substrate 101, the area between the display area 102 and the terminal portion 106 can be folded. This allows the display device 100 to have a narrow frame.

[0057] <Equivalent circuit diagram>

[0058] Figure 21 is an equivalent circuit diagram of a pixel 103 included in a display device 100 according to an embodiment of the present invention. The display device 100 includes a high potential power supply SLa, a low potential power supply electrode SLb, a write control scan line Sg, and an image signal line VL. The high potential power supply SLa is provided with a high potential power supply Pvdd, and the low potential power supply electrode SLb is provided with a low potential power supply Pvss. The write control scan line Sg is connected to gate drive circuits 104_1 and 104_2, and the image signal line VL is connected to a driver IC 105.

[0059] Each pixel 103 has at least a driving transistor DRT, a writing transistor SST and a light emitting element OLED. A high potential power supply Pvdd is given to the anode (also called pixel electrode) of the light emitting element OLED via the driving transistor DRT, and a low potential power supply Pvss is given to the cathode (also called common electrode). The driving transistor DRT is connected in series with the light emitting element OLED between the high potential power supply SLa and the low potential power supply electrode SLb. The driving transistor DRT functions as a current control element that controls the current value flowing through the light emitting element OLED according to the gate-source voltage. The writing transistor SST functions as a switching element that selects conduction or non-conduction between two nodes, and writes a voltage corresponding to the luminous brightness of the light emitting element OLED. A holding capacitor Cs can be set between the gate and source of the driving transistor DRT. The holding capacitor Cs maintains the gate-source voltage of the driving transistor DRT for a certain period of time.

[0060] The write transistor SST has a first terminal, a second terminal, and a control terminal. The drive transistor DRT has a first terminal, a second terminal, a first control terminal, and a second control terminal. In this embodiment, the first terminal is set as a source electrode, the second terminal is set as a drain electrode, the first control terminal is set as a first gate electrode, and the second control terminal is set as a second gate electrode for description.

[0061] As for the write transistor SST, the first gate electrode and the second gate electrode are connected to the write control scan line Sg, the source electrode is connected to the image signal line VL, and the drain electrode is connected to the first gate electrode of the drive transistor DRT. In the drive transistor DRT, the drain electrode is connected to the high potential power supply SLa, and the source electrode is connected to the second gate electrode and one electrode (here, the anode) of the light-emitting element OLED. The other electrode (here, the cathode) in the light-emitting element OLED is connected to the low potential power supply electrode SLb. The drive transistor DRT outputs a drive current of a current amount corresponding to the image signal Vsig to the light-emitting element OLED.

[0062] As a semiconductor layer of a transistor constituting the display device 100, for example, amorphous silicon, low-temperature polysilicon, or an oxide semiconductor is used. Here, since the transistor using the oxide semiconductor layer has a low off-leakage current and can be driven at a low frequency, a low-power display device 100 can be realized. In addition, compared with a transistor having a low-temperature polysilicon layer, a transistor using an oxide semiconductor layer does not have a kink effect, so the saturation characteristics are good. In this embodiment, a case where an oxide semiconductor layer is used as a semiconductor layer of a transistor constituting the display device 100 is described.

[0063] Transistors using oxide semiconductor layers have problems such as low reliability due to changes in threshold voltage over time. For example, when a write transistor and a drive transistor are formed in a dual-gate structure in order to increase the on-current of a transistor using an oxide semiconductor layer, the voltage applied to the oxide semiconductor layer is easily applied to the drive transistor, causing a large amount of current to flow through the drive transistor. As a result, thermal degradation occurs in the oxide semiconductor layer, and the reliability of the drive transistor is reduced.

[0064] In the case of a transistor using an oxide semiconductor layer formed by a top gate structure, by forming the gate insulating film with a relatively thin film thickness of more than 100nm and less than 200nm, the on-current can be increased and the subthreshold swing value (hereinafter referred to as the S value) can be reduced. Therefore, in the case of using a transistor with a top gate structure as a write transistor, since the S value is small, the effect of good switching characteristics can be obtained. On the other hand, in the case of using a transistor with a top gate structure as a driving transistor, since it is current driven, the problem of a larger current change due to the small S value will arise. In particular, in a low grayscale area that needs to be controlled with a small current, the current change of the driving transistor becomes larger, and the grayscale cannot be finely controlled. As a result, the problem of uneven display is easily generated in the display area 102.

[0065] In addition, in the case of a transistor using an oxide semiconductor layer formed by a bottom gate structure, by making the thickness of the gate insulating film thicker, it is not easy to apply the voltage to be applied to the oxide semiconductor layer, so the amount of current flowing through the transistor can be reduced. Therefore, in the case of a transistor with a bottom gate structure having a thicker gate insulating film as a driving transistor, thermal degradation of the oxide semiconductor layer is suppressed and the reliability of the transistor is improved. On the other hand, in the case of a transistor with a bottom gate structure having a thicker gate insulating film as a write transistor, there is a tendency for the on-current Ion of the write transistor to decrease due to the thicker gate insulating film.

[0066] Therefore, when a transistor using an oxide semiconductor layer is used in a display device, it is preferable to set transistors having different characteristics and structures according to the required functions. For example, it is preferable to set a transistor with good switching characteristics and high on-current for the write transistor, and to set a transistor with lower switching characteristics than the write transistor, suppressed thermal degradation, and high reliability for the drive transistor.

[0067] Therefore, for the display device 100 of one embodiment of the present invention, the write transistor SST having a switching function and the transistors constituting the gate drive circuits 104_1 and 104_2 are set to top gate drive or dual gate drive, and the drive transistor having a current control function is set to bottom gate drive. It should be noted that in this specification, etc., top gate drive refers to a drive that controls on and off by a gate electrode arranged above the oxide semiconductor layer. As a top gate driven transistor, it can be a top gate structure composed of a gate electrode arranged above the oxide semiconductor layer, or it can be a dual gate structure composed of respective gate electrodes arranged above and below the oxide semiconductor layer. In addition, in this specification, etc., bottom gate drive refers to a drive that controls on and off by a gate electrode arranged below the oxide semiconductor layer. As a bottom gate driven transistor, it can be a bottom gate structure composed of a gate electrode arranged below the oxide semiconductor layer, or it can be a dual gate structure composed of respective gate electrodes arranged above and below the oxide semiconductor layer. In addition, in this specification, dual gate drive refers to a drive that controls on and off by inputting the same control signal to the gate electrodes arranged above and below the oxide semiconductor layer.

[0068] <Cross-sectional structure of a pixel>

[0069] Figure 3 1 is a diagram illustrating a cross-sectional structure of a pixel 103 of a display device 100 according to an embodiment of the present invention. Figure 3 As shown, a transistor 210 and a transistor 220 are provided on a substrate 101 via a base film 202. The transistor 210 is connected to a light emitting element 230. Here, the transistor 210 corresponds to a driving transistor DRT, the transistor 220 corresponds to a writing transistor SST, and the light emitting element 230 corresponds to a light emitting element OLED.

[0070] The transistor 210 that functions as the driving transistor DRT has a dual-gate structure. The transistor 210 has at least a conductive layer 204_1, an insulating film 206 disposed on the conductive layer 204_1, an oxide semiconductor layer 208_1 disposed on the insulating film 206, an insulating film 212 disposed on the oxide semiconductor layer 208_1, and a conductive layer 214_1 disposed on the insulating film 212. Here, the first control terminal for controlling the switch of the transistor 210 is the conductive layer 204_1. Therefore, the transistor 210 is bottom-gate driven. In addition, the conductive layer 204_1 also functions as a light shielding layer for suppressing light from irradiating the back side of the oxide semiconductor layer 208. The second control terminal is the conductive layer 214_1. Here, the oxide semiconductor layer 208_1 has a channel region 208a and high-concentration impurity regions 208b and 208c. The high-concentration impurity regions 208b and 208c are disposed in a manner that sandwiches the channel region 208a. Here, the channel region 208 a overlaps with the conductive layer 204_1 . The insulating film 206 functions as a gate insulating film of the transistor 210 .

[0071] The channel region 208a has the properties of a semiconductor. Therefore, if a voltage is applied to the conductive layer 204_1, a channel that serves as a current path is formed in the channel region 208a. The high-concentration impurity region 208b and the high-concentration impurity region 208c each have the properties of a conductor by adding an impurity element. Therefore, the carrier concentration of the high-concentration impurity region 208b and the high-concentration impurity region 208c is greater than the carrier concentration of the channel region 208a. In other words, the channel region 208a has a higher resistivity (or lower conductivity) than each of the high-concentration impurity region 208b and the high-concentration impurity region 208c. When measured by SIMS analysis, at 1×10 18 cm -3 Above 1×10 21 cm -3 When an impurity element is added to the oxide semiconductor layers 208_1 and 208_2 at a concentration of 100 Ω / sq. or less, the sheet resistance can be reduced. For example, the sheet resistance of the high-concentration impurity region 208 b and the high-concentration impurity region 208 c is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. Hereinafter, for convenience of description, a region having a higher resistivity than the high-concentration impurity region 208 b and the high-concentration impurity region 208 c, such as the channel region 208 a, is referred to as a “high resistance region”.

[0072] An insulating film 216 is provided on the oxide semiconductor layer 208_1. The insulating film 216 functions as an interlayer insulating film. Source or drain electrodes 218_1 and 218_2 are provided on the insulating film 216. The source or drain electrode 218_1 is connected to the high-concentration impurity region 208b via a contact hole provided in the insulating films 212 and 216. The source or drain electrode 218_2 is connected to the high-concentration impurity region 208c and the conductive layer 214_1. The conductive layer 214_1 is connected to the pixel electrode 226 of the light-emitting element OLED via the source or drain electrode 218_2. Although not shown in the figure, the conductive layer 204_1 is electrically connected to any one of the source or drain electrodes 218_3 and 218_4. In addition Figure 3 In addition to the above-described embodiment, the conductive layer 214_1 may be connected to a fixed potential, for example. An example of the fixed potential is a high potential power source Pvdd or a low potential power source Pvss, which is a driving power source for the light emitting element OLED.

[0073] The transistor 220 that functions as a write transistor SST has a dual-gate structure. The transistor 220 has at least a conductive layer 204_2, an insulating film 206 disposed on the conductive layer 204_2, an oxide semiconductor layer 208_2 disposed on the insulating film 206, an insulating film 212 disposed on the oxide semiconductor layer 208_2, and a conductive layer 214_2 disposed on the insulating film 212. Here, the first control terminal for controlling the switch of the transistor 220 is the conductive layer 204_2 and the conductive layer 214_2. Therefore, the transistor 220 is dual-gate driven. In addition, the conductive layer 204_1 also functions as a light shielding layer for suppressing light from irradiating the back side of the oxide semiconductor layer 208. The insulating film 206 and the insulating film 212 function as gate insulating films. The oxide semiconductor layer 208_2 has a channel region 208f and high-concentration impurity regions 208g and 208h. The high-concentration impurity regions 208g and 208h are disposed in a manner that sandwiches the channel region 208f. Here, the channel region 208f overlaps with the conductive layer 214_2.

[0074] The channel region 208f has the properties of a semiconductor. Therefore, if a voltage is applied to the conductive layer 204_2 and the conductive layer 214_2, a channel that becomes a current path is formed in the channel region 208f. The high-concentration impurity region 208g and the high-concentration impurity region 208h each have the properties of a conductor. Therefore, the carrier concentration of the high-concentration impurity region 208g and the high-concentration impurity region 208h is greater than the carrier concentration of the channel region 208f. In other words, the channel region 208f has a higher resistivity (or lower conductivity) than each of the high-concentration impurity region 208g and the high-concentration impurity region 208h. For example, the sheet resistance of the high-concentration impurity region 208g and the high-concentration impurity region 208h is 1000Ω / sq. or less, preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less. The channel region 208f is called a high resistance region.

[0075] An insulating film 216 is provided on the conductive layer 214_2. Source or drain electrodes 218_3 and 218_4 are provided on the insulating film 216. The source or drain electrodes 218_3 and 218_4 are connected to the high-concentration impurity regions 208g and 208h via contact holes provided in the insulating films 212 and 216.

[0076] In this embodiment, in the display device 100, a dual-gate driven transistor having a dual-gate structure is provided as a write transistor SST on the same substrate, and a bottom-gate driven transistor having a dual-gate structure is provided as a drive transistor DRT. At this time, among the insulating films 206 and 212 sandwiching the oxide semiconductor layers 208_1 and 208_2 above and below, in the write transistor SST, both the insulating film 212 and the insulating film 206 function as gate insulating films, and in the drive transistor DRT, the insulating film 206 functions as a gate insulating film. The film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. Therefore, the thickness of the gate insulating film can be different by using the write transistor SST and the drive transistor DRT. The write transistor SST is configured as a dual-gate drive, but the threshold voltage is dominated by the applied voltage from the conductive layer 214_2 provided across the thin insulating film 212.

[0077] Since the gate insulating film of the write transistor SST can be thinner than the gate insulating film of the drive transistor DRT, it is easy to apply an electric field to the oxide semiconductor layer 208_2, and the on-current can be increased. In addition, in the write transistor SST and the drive transistor DRT, the conductive layers 214_1 and 214_2 are used as masks to add impurity elements to the oxide semiconductor layer 208_2, so that the channel length L can be shortened. In one embodiment of the present invention, the channel length L of the write transistor SST and the drive transistor DRT can be set to, for example, 2.0 μm or more and 4.0 μm or less. Thus, the S value of the write transistor SST can be reduced, so the switching characteristics of the write transistor SST are improved. On the other hand, since the gate insulating film of the drive transistor DRT can be thicker than the gate insulating film of the write transistor SST, it is not easy to apply an electric field to the oxide semiconductor layer 208_1, and the on-current of the drive transistor DRT can be reduced. In addition, since the S value of the drive transistor DRT can be increased, the current change can be reduced in the low grayscale area controlled by a small current, and the grayscale can be finely controlled. This can suppress the occurrence of display unevenness in the display region 102. In addition, it can suppress a large amount of current from continuously flowing through the drive transistor DRT, thereby suppressing a decrease in reliability due to thermal degradation.

[0078] In the driving transistor DRT, the conductive layer 214_1 and the high-concentration impurity region 208c are connected via the source electrode or the drain electrode 218_2. The conductive layer 214_1 is connected to the pixel electrode 226 of the light-emitting element OLED via the source electrode or the drain electrode 218_2. Thus, the signal on the source side of the driving transistor DRT can be stabilized. Therefore, the display unevenness in the display area 102 can be suppressed.

[0079] It should be noted that by using the transistor 220 having the same structure as the write transistor SST as the transistor constituting the gate drive circuits 104_1 and 104_2, the gate drive circuits 104_1 and 104_2 can be driven at high speed.

[0080] A planarization film 222 is provided on the source electrode or the drain electrode 218_1 to 218_4. As the planarization film 222, an organic resin material such as polyimide, polyamide, acrylic acid, epoxy resin, etc. can be used. These materials can be formed into a film by a solution coating method, and have the characteristic of a high planarization effect. It should be noted that the planarization film 222 is not provided in the peripheral area 109.

[0081] The transistor 210 is connected to the light emitting element 230. The light emitting element 230 has a pixel electrode 226, an organic layer 232, and a common electrode 234. In one embodiment of the present invention, the display device 100 may be a top emission type or a bottom emission type. In this embodiment, the case where the display device 100 is a top emission structure is described. In the case of the top emission structure, the pixel electrode 226 becomes an anode and the common electrode 234 becomes a cathode.

[0082] A pixel electrode 226 is provided on the planarization film 222. The pixel electrode 226 is provided for each pixel 103. The pixel electrode 226 is connected to the source electrode or the drain electrode 218_2 of the transistor 210 via a contact hole provided in the planarization film 222. A metal film with high reflectivity is used as the pixel electrode 226. Alternatively, as the pixel electrode 226, a laminated structure of a transparent conductive layer with a high work function such as an indium oxide-based transparent conductive layer (e.g., ITO) or a zinc oxide-based transparent conductive layer (e.g., IZO, ZnO) and a metal film can be used.

[0083] An insulating film 228 is provided to cover the end of the pixel electrode 226. The insulating film 228 is also called a partition wall or a cofferdam. As the insulating film 228, a photosensitive acrylic is used in the same manner as the planarization film 222. The insulating film 228 is preferably opened so that the pixel electrode 226 is exposed, and the end of the opening is in a gentle tapered shape. If the end of the opening is in a steep shape, poor coverage of the organic layer 232 formed later occurs.

[0084] A plurality of organic materials constituting the organic layer 232 are stacked on the pixel electrode 226 and the insulating film 228. In the organic layer 232, a hole transport layer, a light emitting layer, and an electron transport layer are stacked in order from the pixel electrode 226 side. These layers can be formed by evaporation or by coating after being dispersed in a solvent. In addition, the hole transport layer and the electron transport layer can be selectively formed for each sub-pixel or formed on the entire surface of the display area 102.

[0085] A common electrode 234 is provided on the organic layer 232. In this embodiment, since it is a top emission structure, the common electrode 234 needs to be light-transmissive. When MgAg is used as the common electrode 234, it is formed as a thin film to the extent that the emitted light from the organic layer 232 is transmitted. The common electrode 234 is connected to the wiring layer at the cathode contact portion provided in the peripheral area 109 and is electrically connected to the terminal 107.

[0086] A sealing film 240 is provided on the common electrode 234. The sealing film 240 is provided to suppress the intrusion of moisture from the outside into the organic layer 232. In the present embodiment, as the sealing film 240, an example of a three-layer structure formed by an inorganic insulating film 236, an organic insulating film 238 and an inorganic insulating film 242 is shown. As the inorganic insulating films 236 and 233, silicon nitride with high gas barrier properties is preferably used, and as the organic insulating film 238, an organic resin material with high flexibility is preferably used. It should be noted that a silicon oxide film or an amorphous silicon film can be provided between the silicon nitride and the organic resin material. Thereby, the adhesion between the silicon nitride and the organic resin material can be improved. On the inorganic insulating film 242, for example, an outer coating can be provided while taking into account planarization.

[0087] The touch sensor 110 is provided on the sealing film 240. The touch sensor 110 may be directly formed on the sealing film 240. Alternatively, a cover glass on which the touch sensor 110 is formed may be provided on the sealing film 240.

[0088] <Characteristics of Oxide Semiconductor Layers 208_1 and 208_2>

[0089] In one embodiment of the present invention, the oxide semiconductor layers 208_1 and 208_2 have properties different from those of conventional oxide semiconductors having a polycrystalline structure. Therefore, in order to distinguish the oxide semiconductors contained in the oxide semiconductor layers 208_1 and 208_2 from conventional oxide semiconductors having a polycrystalline structure, the oxide semiconductors contained in the oxide semiconductor layers 208_1 and 208_2 are referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) for description below.

[0090] In Poly-OS, a plurality of crystal grains may have one crystal structure or multiple crystal structures. The crystal structure of Poly-OS may be determined by electron beam diffraction or XRD. That is, the crystal structure of the oxide semiconductor layers 208_1 and 208_2 may be determined by electron beam diffraction or XRD.

[0091] The oxide semiconductor layers 208_1 and 208_2 including Poly-OS have excellent etching resistance. Specifically, the etching rate when the oxide semiconductor layers 208_1 and 208_2 are etched using an etchant for wet etching is very low. This means that the oxide semiconductor layers 208_1 and 208_2 are hardly etched by the etchant.

[0092] Specifically, in a temperature range of 35°C to 45°C (for example, including an error range of ±5°C at a set temperature of 40°C), the etching rate when etching the oxide semiconductor layers 208_1 and 208_2 of this embodiment using an etching solution containing phosphoric acid as a main component (for example, a mixed acid etching solution, etc.) is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The proportion of phosphoric acid in the etching solution is greater than 50%, greater than 60%, or greater than 70%. In addition to phosphoric acid, the etching solution may also contain nitric acid and acetic acid. In contrast, in an oxide semiconductor layer having an amorphous structure (oxide semiconductor layer before OS annealing), the etching rate when etching is performed using the above-mentioned etching solution in a temperature range of 35°C to 45°C is greater than 100nm / min.

[0093] In addition, when the oxide semiconductor layers 208_1 and 208_2 of this embodiment are etched using an etching solution containing hydrogen fluoride (for example, a hydrofluoric acid solution) at room temperature (here, "25°C ± 5°C"), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. The proportion of hydrogen fluoride in the etching solution is 0.5%. In contrast, in the oxide semiconductor layer having an amorphous structure, the etching rate when etching is performed using the above etching solution at room temperature is 15 nm / min or more.

[0094] Here, the etching rates of various oxide semiconductor layers are shown in Table 1. Table 1 shows the etching rates of each sample produced relative to the mixed acid etching solution and the 0.5% hydrofluoric acid solution. As the mixed acid etching solution, "Mixed Acid AT-2F (product name)" manufactured by RASA Industries, LTD. was used. The proportion of phosphoric acid in the mixed acid etching solution was about 65%. In addition, the temperature of the mixed acid etching solution was set to 40°C, and the temperature of the 0.5% hydrofluoric acid solution was set to 22°C when etching each sample. In Table 1, Sample 1 is an oxide semiconductor layer having a polycrystalline structure of the present embodiment, Sample 2 is an oxide semiconductor layer having an amorphous structure of the present embodiment, and Sample 3 is an oxide semiconductor layer of indium gallium zinc oxide (IGZO) containing an indium ratio of less than 50%.

[0095] [Table 1]

[0096] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0097] As shown in Table 1, sample 1 is hardly etched even when using a mixed acid etching solution, and is only etched at most by about 2 nm / min even when using a 0.5% hydrofluoric acid solution. Compared with the etching rate of sample 2, the etching rate of sample 1 is less than 1 / 100 in a mixed acid etching solution, and less than about 1 / 10 in a 0.5% hydrofluoric acid solution. In addition, compared with the etching rate of sample 3, the etching rate of sample 1 is less than 1 / 100 in a mixed acid etching solution. Thus, it can be seen that sample 1 has significantly superior etching resistance compared to samples 2 and 3.

[0098] The excellent etching resistance of the oxide semiconductor layers 208_1 and 208_2 of this embodiment is a characteristic that cannot be obtained in the conventional oxide semiconductor layers having a polycrystalline structure manufactured by a process below 500° C. Although the detailed mechanism is not clear, it can be said that the excellent etching resistance is evidence that the oxide semiconductor layers 208_1 and 208_2 of this embodiment have a polycrystalline structure different from the conventional ones. In addition, the oxide semiconductor layers having a polycrystalline structure described in the modified examples and embodiments described later also have the same characteristics.

[0099] As described above, the etching rate of the oxide semiconductor layers 208_1 and 208_2 including Poly-OS in the etching solution is very low. Therefore, it is very difficult to pattern the oxide semiconductor layers 208_1 and 208_2. Therefore, in the case of forming the island-shaped oxide semiconductor layers 208_1 and 208_2, the oxide semiconductor film having an amorphous structure before the heat treatment is patterned into an island shape, and then the heat treatment is performed to crystallize. Thus, the island-shaped oxide semiconductor layers 208_1 and 208_2 including Poly-OS can be formed.

[0100] In the display device 100 of this embodiment, the transistor is formed using the oxide semiconductor layers 208_1 and 208_2 having a good polycrystalline structure. In the transistor including the oxide semiconductor layers 208_1 and 208_2, when the channel length L of the channel regions 208a and 208f is 2 μm or more and 4 μm or less, and the channel width of the channel regions 208a and 208f is 2 μm or more and 25 μm or less, a mobility of 30 cm-1 can be obtained. 2 / Vs or above, 35cm 2 / Vs or above, or 40cm 2 The mobility in this embodiment is the field effect mobility in the saturation region of the transistor, and refers to the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage (Vg) supplied to the gate electrode.

[0101] <Method for manufacturing display device>

[0102] Next, refer to Figures 4 to 12 A method for manufacturing the display device 100 according to one embodiment of the present invention will be described.

[0103] Figure 4 This is a diagram for explaining the process of forming from base film 202 to insulating film 206 on substrate 101. As substrate 101, a glass substrate, a quartz substrate, a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose, cyclic olefin copolymer, cyclic olefin polymer, other flexible resin substrates) can be used.

[0104] A base film 202 is formed on the substrate 101. As the base film 202, silicon oxide or silicon nitride can be used as a single layer, or a combination of silicon oxide and silicon nitride can be used. Conductive layers 204_1 and 204_2 are formed on the base film 202. The conductive layers 204_1 and 204_2 are formed by forming a conductive film on the base film 202 and processing it using a photolithography method. As the conductive layers 204_1 and 204_2, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), copper (Cu), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi), etc. can be used. In addition, alloys of these metals can also be used.

[0105] Next, an insulating film 206 is formed on the conductive layers 204_1 and 204_2. As the insulating film 206, silicon oxide or silicon nitride may be used as a single layer, or a combination of silicon oxide and silicon nitride may be used. In addition, the film thickness of the insulating film 206 is preferably greater than the film thickness of the insulating film 212 described later. The film thickness of the insulating film 206 is, for example, not less than 100 nm and not more than 500 nm, preferably not less than 150 nm and not more than 300 nm.

[0106] Figure 5 The diagram illustrates a step of forming the oxide semiconductor film 207 over the insulating film 206 .

[0107] The oxide semiconductor film 207 is formed by sputtering or atomic layer deposition (ALD) and has a thickness of, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0108] As the oxide semiconductor film 207, a metal oxide having semiconductor properties can be used. As the oxide semiconductor film 207, for example, an oxide semiconductor containing two or more metals including indium (In) can be used. In addition, the ratio of indium in the two or more metals is 50% or more. As the oxide semiconductor film 207, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanide elements are used in addition to indium. As the oxide semiconductor film 207, elements other than the above may also be used. In this embodiment, as the oxide semiconductor film 207, a metal oxide containing indium (In) and gallium (Ga) can be used.

[0109] When the oxide semiconductor film 207 is crystallized by the OS annealing treatment described later, the oxide semiconductor film 207 after film formation and before the OS annealing treatment is preferably amorphous (a state in which the crystalline component of the oxide semiconductor is small). That is, the film formation method of the oxide semiconductor film 207 is preferably performed under conditions that do not crystallize the oxide semiconductor film 207 immediately after film formation as much as possible. For example, when the oxide semiconductor film 207 is formed by sputtering, the oxide semiconductor film 207 is formed while controlling the temperature of the object to be formed (the substrate SUB1 and the structure formed thereon).

[0110] If a film is formed on a film-forming object by sputtering, the ions generated in the plasma and the atoms recoiled by the sputtering target collide with the film-forming object, so the temperature of the film-forming object rises along with the film-forming process. If the temperature of the film-forming object rises during the film-forming process, the oxide semiconductor film 207 contains microcrystals in the state just after the film is formed, and the crystallization based on the subsequent OS annealing process is hindered. In order to control the temperature of the film-forming object as described above, for example, the film can be formed while the film is cooled. For example, the film-forming object can also be cooled from the surface opposite to the film-forming surface in a manner such that the temperature of the film-forming surface of the film-forming object (hereinafter referred to as the "film-forming temperature") is below 100°C, below 70°C, below 50°C, or below 30°C. As described above, by forming the oxide semiconductor film 207 while cooling the film-forming object, an oxide semiconductor film 207 with a small crystalline component can be formed in the state just after the film is formed.

[0111] Figure 62 is a diagram for explaining a process of forming patterns of oxide semiconductor layers 207_1 and 207_2 from an oxide semiconductor film 207. A resist mask is formed on the oxide semiconductor film 207, and the oxide semiconductor film 207 is etched using the resist mask. The oxide semiconductor film 207 may be etched by wet etching or dry etching. As wet etching, an acidic etchant may be used for etching. As an etchant, oxalic acid or hydrofluoric acid may be used, for example.

[0112] In the oxide semiconductor film 207, it is preferred that the patterns of the oxide semiconductor layers 207_1 and 207_2 are formed before the OS annealing treatment. As described above, if the oxide semiconductor film 207 is crystallized by the OS annealing treatment, the etching resistance is improved, so there is a tendency that etching is difficult. In addition, even if the oxide semiconductor film 207 is damaged by etching, the damage can be repaired by the OS annealing treatment, so it is preferred.

[0113] Figure 7 2 is a diagram illustrating a process of heat treating the oxide semiconductor layers 207_1 and 207_2 (also referred to as OS annealing). In the OS annealing, the oxide semiconductor layers 207_1 and 207_2 are maintained at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300°C to 500°C, preferably 350°C to 450°C. In addition, the holding time at the reaching temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing the OS annealing, the oxide semiconductor layers 207_1 and 207_2 are crystallized to form oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure. Thus, oxide semiconductor layers 208_1 and 208_2 with high etching resistance can be formed.

[0114] Next, the insulating film 212 is formed over the oxide semiconductor layers 208_1 and 208_2 .

[0115] The film formation method and insulating material of the insulating film 212 may refer to the description of the insulating film 206. The insulating film 212 has a film thickness of, for example, 30 nm to 150 nm.

[0116] As the insulating film 212, an insulating material containing oxygen is preferably used. In addition, as the insulating film 212, an insulating film with few defects is preferably used. For example, when the composition ratio of oxygen in the insulating film 212 is compared with the composition ratio of oxygen in an insulating film having the same composition as the base film 202 (hereinafter referred to as "other insulating film"), the composition ratio of oxygen in the insulating film 212 is closer to the stoichiometric ratio for the insulating film than the composition ratio of oxygen in the other insulating film. For example, when silicon oxide (SiO x) is used for each of the insulating film 212 and the base film 202, the oxygen composition ratio in the silicon oxide used as the insulating film 212 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the base film 202. For example, as the insulating film 212, a layer in which no defects are observed when evaluated by an electron spin resonance method (ESR) may be used.

[0117] In order to form an insulating film with few defects as the insulating film 212, the insulating film 212 may be formed at a film forming temperature of 350° C. or higher. In addition, after the insulating film 212 is formed, a process of injecting oxygen into a part of the insulating film 212 may be performed. In this embodiment, silicon oxide is formed at a film forming temperature of 350° C. or higher in order to form an insulating film with few defects as the insulating film 212.

[0118] Figure 8 The figure is a diagram for explaining the step of forming a metal oxide film 213 mainly composed of aluminum on the insulating film 212 .

[0119] The metal oxide film 213 is a metal oxide containing aluminum as a main component. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating materials. x N y It is an aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). AlN x O y An aluminum compound containing oxygen at a ratio smaller than nitrogen (x>y).

[0120] “A metal oxide film mainly composed of aluminum” means that the ratio of aluminum contained in the metal oxide film 213 is greater than 1% of the entire metal oxide film 213. The ratio of aluminum contained in the metal oxide film 213 may be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide film 213. The above ratio may be a mass ratio or a weight ratio.

[0121] The metal oxide film 213 is formed by, for example, sputtering and has a thickness of, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm.

[0122] For example, when the metal oxide film 213 is formed by sputtering, oxygen is injected into the insulating film 212 due to the formation of the metal oxide film 213. Therefore, the process gas used in sputtering remains in the film of the insulating film 212. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the insulating film 212. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the insulating film 212.

[0123] In this embodiment, aluminum oxide is used as the metal oxide film 213. Aluminum oxide has a high barrier property to gases. In this embodiment, by using aluminum oxide as the metal oxide film 213, it is possible to suppress the outdiffusion of oxygen injected into the insulating film 212 during the formation of the metal oxide film 213.

[0124] In a state where the insulating film 212 is formed over the oxide semiconductor layers 208_1 and 208_2 and the metal oxide film 213 is formed over the insulating film 212 , heat treatment (oxidation annealing treatment) for supplying oxygen to the oxide semiconductor layers 208_1 and 208_2 is performed.

[0125] In the process from forming the oxide semiconductor layers 208_1 and 208_2 to forming the insulating film 212 on the oxide semiconductor layers 208_1 and 208_2, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Therefore, the oxygen defects formed near the upper surface of the oxide semiconductor layers 208_1 and 208_2 are more than the oxygen defects formed near the lower surface of the oxide semiconductor layers 208_1 and 208_2. That is, the oxygen defects in the oxide semiconductor layers 208_1 and 208_2 are not uniformly present in the thickness direction of the oxide semiconductor layers 208_1 and 208_2, but are present in a non-uniform distribution in the thickness direction of the oxide semiconductor layers 208_1 and 208_2. Specifically, the oxygen vacancies in the oxide semiconductor layers 208_1 and 208_2 decrease toward the bottom surface of the oxide semiconductor layers 208_1 and 208_2 and increase toward the top surface of the oxide semiconductor layers 208_1 and 208_2.

[0126] In this embodiment, oxidation annealing is performed in a state where the metal oxide film 213 is provided on the oxide semiconductor layers 208_1 and 208_2. Thus, in the above-mentioned oxidation annealing process, the oxygen injected into the insulating film 212 is blocked by the metal oxide film 213, and thus the situation where it is released into the atmosphere is suppressed. In addition, the oxygen released from the insulating film 206 is supplied to the upper surface and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Thus, the oxygen is efficiently supplied to the oxide semiconductor layers 208_1 and 208_2, and oxygen defects can be repaired.

[0127] Next, after the oxidation annealing treatment, the metal oxide film 213 is etched (removed). As the etching of the metal oxide film 213, wet etching can be used, or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) can be used. Through this etching, the metal oxide film 213 formed on the entire surface is removed. In other words, the metal oxide film 213 is removed without using a mask. In other words, through this etching, all the metal oxide films 213 in the area overlapping with the oxide semiconductor layers 208_1 and 208_2 formed into a certain pattern are removed at least when viewed from above.

[0128] Fig. 9 2 is a diagram for explaining a process of forming conductive layers 214_1 and 214_2 on the insulating film 212. The conductive layers 214_1 and 214_2 are formed by forming a conductive film on the insulating film 212 and processing it by photolithography. For example, the same material as the conductive layers 204_1 and 204_2 can be used as the conductive layers 214_1 and 214_2. The conductive layer 214_1 is formed in a region overlapping the conductive layer 204_1 and the oxide semiconductor layer 208_1, and the conductive layer 214_2 is formed in a region overlapping the conductive layer 204_2 and the oxide semiconductor layer 208_2.

[0129] Fig.10 This diagram illustrates a step of adding an impurity element to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. In this embodiment, the case where impurities are added by ion implantation is described, but addition may also be performed by an ion doping method.

[0130] Specifically, by ion implantation, impurity elements are added to the oxide semiconductor layers 208_1 and 208_2 through the insulating film 212, thereby forming high-concentration impurity regions 208b, 208c, 208g, and 208h. In addition, in the oxide semiconductor layers 208_1 and 208_2, the regions overlapping with the gate wiring GL1 become channel regions 208a and 208f. As the impurity element, argon (Ar), phosphorus (P), or boron (B) can be used, for example. In addition, when boron (B) is added by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 14 cm -2 Above 1×10 16 cm -2 The following will do.

[0131] When the concentration of the impurity element contained in the high-concentration impurity regions 208b, 208c, 208g, and 208h is measured by SIMS analysis (secondary ion mass spectrometry), it is preferably 1×10 18 cm -3 Above 1×10 21 cm -3 In addition, the high-concentration impurity regions 208b, 208c, 208g, and 208h contain 1×10 18 cm -3 Above 1×10 21 cm -3 In the following cases, it is presumed that the impurity element is intentionally added by an ion implantation method or a doping method.

[0132] Fig.11 2 is a diagram illustrating a process of forming an insulating film 216 on the oxide semiconductor layers 208_1 and 208_2 to the source electrode or drain electrode 218_1 to 218_4. First, an insulating film 216 is formed on the oxide semiconductor layers 208_1 and 208_2. As the insulating film 216, silicon oxide or silicon nitride can be used as a single layer, or silicon oxide and silicon nitride can be stacked in combination. In addition, the film thickness of the insulating film 216 is preferably greater than the film thickness of the insulating film 212. The film thickness of the insulating film 216 is preferably formed to be greater than 250 nm and less than 600 nm, for example. By using silicon nitride as the insulating film 216, hydrogen contained in the silicon nitride is introduced into the oxygen vacancies formed in the oxide semiconductor layers 208_1 and 208_2 by ion implantation. As a result, the high-concentration impurity regions 208b, 208c, 208g, and 208h can be further reduced in resistance.

[0133] Next, contact holes are formed in the insulating film 212 and the insulating film 216 so as to reach the oxide semiconductor layers 208_1 and 208_2 and the conductive layer 214_1. Next, source or drain electrodes 218_1 to 218_4 are formed on the insulating film 216. The source or drain electrodes 218_1 to 218_4 are formed by forming a conductive film on the insulating film 216 and processing the conductive film using a photolithography method. Thus, the source or drain electrode 218_1 is connected to the high-concentration impurity region 208b, and the source or drain electrode 218_2 is connected to the high-concentration impurity region 208c and the conductive layer 214_1. The source or drain electrode 218_3 is connected to the high-concentration impurity region 208g, and the source or drain electrode 218_4 is connected to the high-concentration impurity region 208h. As the source or drain electrodes 218_1 to 218_4, the same material as that of the conductive layers 204_1 and 204_2 can be used. Although not shown, in this process, a contact hole reaching the conductive layer 204_1 may be formed in the insulating films 206, 212, and 216. This allows the conductive layer 204_1 to be connected to the source electrode or the drain electrode 218_3. Through the processes up to this point, the transistors 210 and 220 can be formed.

[0134] Fig.12 2 is a diagram for explaining the process of forming a planarization film 222 and a pixel electrode 226. The planarization film 222 is formed on the source or drain electrodes 218_1 to 218_4. As the planarization film 222, an organic resin material such as polyimide, acrylic, or epoxy resin can be used. These materials can be formed into a film by a solution coating method and have a high planarization effect.

[0135] The light emitting element 230 is formed by forming a pixel electrode 226, an organic layer 232, and a common electrode 234. First, a contact hole that reaches the source electrode or the drain electrode 218_2 is formed in the planarization film 222. Next, a pixel electrode 226 is formed on the planarization film 222. The pixel electrode 226 is formed by forming a conductive film on the planarization film 222 and processing the conductive film using a photolithography method. An insulating film 228 is formed with an opening in such a way that the pixel electrode 226 is exposed. Next, a plurality of organic materials constituting the organic layer 232 are formed on the pixel electrode 226 and the insulating film 228. Next, a common electrode 234 is formed on the organic layer 232.

[0136] Then, the sealing film 240 is formed by forming an inorganic insulating film 236, an organic insulating film 238, and an inorganic insulating film 242 on the common electrode 234. First, the inorganic insulating film 236 is formed on the common electrode 234. Next, the organic insulating film 238 is formed on the inorganic insulating film 236. Next, the inorganic insulating film 242 is formed on the organic insulating film 238. At this time, it is preferable to seal the organic insulating film 238 by contacting the end of the inorganic insulating film 236 with the end of the inorganic insulating film 242. Thus, it is possible to suppress the degradation of the light emitting element 230 due to the intrusion of moisture from the outside of the sealing film 240.

[0137] Through the above process, it is possible to manufacture Figure 3 A display device 100 having a structure of a pixel 103 shown in FIG.

[0138] According to the method for manufacturing the display device 100 according to one embodiment of the present invention, even in a small area such as within one pixel, two types of transistors having different characteristics and structures can be formed more simply without increasing the number of processes.

[0139] (Variation Example)

[0140] Next, refer to Fig.13 With Figure 3 A pixel 103A having a partially different configuration of the pixel 103 will be described.

[0141] Fig.13 1 is a diagram illustrating a cross-sectional structure of a pixel 103A of a display device 100 according to an embodiment of the present invention. Fig.13 As shown in FIG. 1 , a transistor 210 and a transistor 250 are provided on a substrate 101 via a base film 202. Here, the transistor 210 corresponds to Figure 3 The driving transistor DRT shown, transistor 250 corresponds to Figure 3 It should be noted that due to the structure of the transistor 210 and the Figure 3 The transistor 210 shown is the same, so the description is omitted.

[0142] The transistor 250 that functions as a write transistor SST has a top gate structure. The transistor 250 has at least an oxide semiconductor layer 208_3 provided on the insulating film 206, an insulating film 212 provided on the oxide semiconductor layer 208_3, and a conductive layer 214_3 provided on the insulating film 212. Here, the control terminal that controls the switch of the transistor 250 is the conductive layer 214_3. The insulating film 212 functions as a gate insulating film. The oxide semiconductor layer 208 has a channel region 208i and high-concentration impurity regions 208j and 208k. An insulating film 212 is provided on the conductive layer 214_3. A source electrode or a drain electrode 218_5 and 218_6 are provided on the insulating film 212. The source electrode or the drain electrode 218_5 and 218_6 are connected to the high-concentration impurity regions 208j and 208k via contact holes provided in the insulating films 212 and 216.

[0143] Since the gate insulating film of the write transistor SST can be thinner than the gate insulating film of the drive transistor DRT, it is easy to apply an electric field to the oxide semiconductor layer 208_3, which can increase the on-current. In addition, since the channel length L can be shortened, the switching characteristics become good. On the other hand, since the gate insulating film of the drive transistor DRT can be thicker than the gate insulating film of the write transistor SST, it is not easy to apply an electric field to the oxide semiconductor layer 208_1, which can reduce the on-current. In particular, since the current change of the drive transistor DRT can be reduced in a low grayscale area controlled by a tiny current, the grayscale can be finely controlled. Thus, the display unevenness in the display area 102 can be suppressed. In addition, since a large amount of current can be suppressed from continuously flowing through the drive transistor DRT, the reduction in reliability associated with thermal degradation can be suppressed.

[0144] In addition, since the crystallized oxide semiconductor layers 208_1 and 208_2 have high etching resistance, the film thickness reduction between the oxide semiconductor film 207 and the crystallized oxide semiconductor layers 208_1 and 208_2 can be suppressed. Therefore, the film thickness of the formed oxide semiconductor film 207 can be reduced, and the film thickness of the crystallized oxide semiconductor layers 208_1 and 208_2 can be reduced. Thus, when the gate voltage is applied, the field effect mobility can be improved by increasing the current density within the range of the electric field strength. In addition, the film thickness of the crystallized oxide semiconductor layers 208_1 and 208_2 can be suppressed by etching, thereby suppressing the uneven film thickness within the substrate surface. Thus, the uneven characteristics of the transistors within the substrate surface can also be suppressed, so the display unevenness of the display area 102 can be suppressed.

[0145] (Second embodiment)

[0146] In this embodiment, refer to Fig.14 and Fig.15 The structure of the pixel 103B having a structure partially different from the structure of the pixel 103 described in the first embodiment is described. It should be noted that regarding the structure of the pixel 103B, the same reference numerals are given to the same parts as the pixel 103 or parts having the same functions, and repeated descriptions are omitted.

[0147] <Equivalent circuit diagram>

[0148] Fig.14 FIG. 1 is an equivalent circuit diagram of a pixel 103B included in the display device 100 according to one embodiment of the present invention. Fig.14 In the equivalent circuit diagram shown in Figure 2 The equivalent circuit diagram shown is different in the configuration of the drive transistor DRT. Fig.14 In the embodiment, the driving transistor DRT is bottom gate driven and the writing transistor SST is top gate driven.

[0149] <Cross-sectional structure of a pixel>

[0150] Fig.15 1 is a diagram illustrating a cross-sectional structure of a pixel 103B of a display device 100 according to an embodiment of the present invention. Fig.15 As shown, a transistor 210A and a transistor 250 are provided on a substrate 101 via a base film 202. Here, the transistor 250 corresponds to Fig.14 The write transistor SST shown in FIG. 210A corresponds to the transistor Fig.14 It should be noted that due to the structure of the transistor 250 and Fig.13 The structure of the transistor 250 shown is the same, so the detailed description is omitted.

[0151] The transistor 210A that functions as the driving transistor DRT has a bottom gate structure. The transistor 210A has at least a conductive layer 204_1, an insulating film 206 disposed on the conductive layer 204_1, and an oxide semiconductor layer 208_1 disposed on the insulating film 206. Here, the oxide semiconductor layer 208_1 has a channel region 208a, high-concentration impurity regions 208b, 208c, and low-concentration impurity regions 208d, 208e. The low-concentration impurity regions 208d, 208e are disposed in a manner sandwiching the channel region 208a. The high-concentration impurity regions 208b, 208c are disposed in a manner adjacent to the low-concentration impurity regions 208d, 208e. Here, the channel region 208a and the low-concentration impurity regions 208d, 208e overlap with the conductive layer 204_1. The insulating film 206 functions as a gate insulating film of the transistor 210. An insulating film 212 is provided on the oxide semiconductor layer 208_1, and an insulating film 216 is further provided on the insulating film 212. The film thickness of the insulating film 206 is preferably greater than the film thickness of the insulating film 212. The film thickness of the insulating film 206 is greater than 100 nm and less than 400 nm, preferably greater than 150 nm and less than 300 nm. The film thickness of the insulating film 212 is greater than 30 nm and less than 150 nm. Source electrodes or drain electrodes 218_1 and 218_2 are provided on the insulating film 216. The source electrodes or drain electrodes 218_1 and 218_2 are connected to the high-concentration impurity regions 208b and 208c via contact holes provided in the insulating films 212 and 216. Although not shown in the figure, the conductive layer 204_1 is electrically connected to any one of the source electrodes or drain electrodes 218_3 and 218_4.

[0152] about Fig.15 In the transistor 210A shown, low-concentration impurity regions 208d and 208e are provided between the channel region 208a and the high-concentration impurity regions 208b and 208c in the oxide semiconductor layer 208_1. As a result, the electric field applied near the end of the channel region 208a is reduced, so that the source-drain resistance can be improved. By overlapping the low-concentration impurity regions 208d and 208e with the conductive layer 204_1, the source-drain resistance can be further improved.

[0153] like Fig.15As shown, in the display device 100, a transistor with a top gate structure as a write transistor SST is provided on the same substrate, and a transistor with a bottom gate structure as a drive transistor DRT is provided. At this time, among the insulating films 206 and 212 sandwiching the oxide semiconductor layers 208_1 and 208_2 above and below, the insulating film 212 is made to function as a gate insulating film in the write transistor SST, and the insulating film 206 is made to function as a gate insulating film in the drive transistor DRT. At this time, the film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. Therefore, by using the write transistor SST and the drive transistor DRT, the thickness of the gate insulating film can be different. That is, a thin gate insulating film can be applied to the top-gate driven SST, and a thick gate insulating film can be applied to the bottom-gate driven drive transistor DRT.

[0154] Since the gate insulating film of the write transistor SST can be thinner than the gate insulating film of the drive transistor DRT, it is easy to apply an electric field to the oxide semiconductor layer 208_2, and the on-current can be increased. In addition, in the write transistor SST, since impurity elements are added to the oxide semiconductor layer 208_2 via the conductive layer 214_2, the channel length L can be shortened. Thus, the S value of the write transistor SST can be reduced. On the other hand, since the gate insulating film of the drive transistor DRT can be thicker than the gate insulating film of the write transistor SST, it is not easy to apply an electric field to the oxide semiconductor layer 208_1, and the on-current can be reduced. In particular, since the current change of the drive transistor DRT can be reduced in the low grayscale area controlled by a tiny current, the grayscale can be finely controlled. Thus, the display unevenness in the display area 102 can be suppressed. In addition, since a large amount of current can be suppressed from continuously flowing through the drive transistor DRT, the reliability reduction associated with thermal degradation can be suppressed. In addition, as described in the first embodiment, in the case of dual-gate driving in the write transistor SST, the BT stress of the gate becomes larger than that of the case of single-side gate driving. Therefore, although there is an advantage that the on-off characteristics of the transistor become sharper, reliability may be slightly sacrificed. Therefore, when the driving capability is sufficient with top gate driving and backside light shielding is not required, reliability can be improved by omitting the bottom gate electrode.

[0155] <Method for manufacturing display device>

[0156] Next, refer to Figure 16 to Figure 18 A method for manufacturing the display device 100 according to one embodiment of the present invention will be described. It should be noted that the steps from forming the base film 202 on the substrate 101 to performing the oxidation annealing step are described in detail below. Figures 4 to 8 The description is enough.

[0157] Fig.162 is a diagram for explaining the process of forming a conductive layer 214_2 and a resist mask 215 on an insulating film 212. First, a conductive layer 214_2 is formed on the insulating film 212. The conductive layer 214_4 is formed by forming a conductive film on the insulating film 212 and processing it using a photolithography method. The conductive layer 214_2 is formed in a region overlapping with the oxide semiconductor layer 208_2. Next, a resist mask 215 is formed in a portion of a region overlapping with the oxide semiconductor layer 208_1 provided on the insulating film 212. Here, the resist mask 215 is formed in a manner such that the end portion becomes a tapered shape. The resist mask 215 is not limited to a tapered shape as long as its film thickness decreases as it approaches the end portion.

[0158] Fig.17 2 is a diagram for explaining a process of adding an impurity element to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. The impurity element is added to the oxide semiconductor layers 208_1 and 208_2 by ion implantation using the conductive layer 214_2 and the resist mask 215 as masks. As a result, in the oxide semiconductor layer 208_2, high-concentration impurity regions 208g and 208h are formed in regions that do not overlap with the conductive layer 214_2, and a channel region 208f is formed in a region that overlaps with the conductive layer 214_2. The concentration of the impurity element in the high-concentration impurity regions 208g and 208h is preferably 1×10 18 cm -3 Above 1×10 21 cm -3 At the same time, in the oxide semiconductor layer 208_1, high-concentration impurity regions 208b and 208c are formed in the region not overlapping with the resist mask 215. In addition, low-concentration impurity regions 208d and 208e are formed by adding impurity elements to the region overlapping with the tapered shape in the region overlapping with the resist mask 215 through the resist mask 215. In addition, a channel region 208a is formed in the region overlapping with the portion other than the tapered shape in the resist mask 215. The concentration of the impurity elements in the high-concentration impurity regions 208b and 208c is preferably 1×10 18 cm -3 Above 1×10 21 cm -3In addition, impurity elements are added to the low-concentration impurity regions 208d and 208e through the resist mask 215. Therefore, the concentration of impurities added to the low-concentration impurity regions 208d and 208e is relatively lower than the concentration of impurities added to the high-concentration impurity regions 208b and 208c. For example, if the inclination of the side surface of the resist mask 215 is properly controlled, the concentration of impurities added to the low-concentration impurity regions 208d and 208e can be made one order of magnitude or more lower than the concentration of impurities added to the high-concentration impurity regions 208b and 208c. Therefore, the concentration of impurity elements in the low-concentration impurity regions 208d and 208e is less than 1×10 18 cm -3 . The concentration of impurities added to the low-concentration impurity regions 208d and 208e can be made lower than the concentration of impurities added to the high-concentration impurity regions 208b and 208c by more than one order of magnitude. As a result, the conductivity of the low-concentration impurity regions 208d and 208e is lower than the conductivity of the high-concentration impurity regions 208b and 208c. In other words, the resistivity of the low-concentration impurity regions 208d and 208e is higher than the resistivity of the high-concentration impurity regions 208b and 208c. In other words, the sheet resistance of the low-concentration impurity regions 208d and 208e is greater than the sheet resistance of the high-concentration impurity regions 208b and 208c. It should be noted that the area where the thickest area in the resist mask 215 overlaps with the oxide semiconductor layer 208_1 determines the channel area of ​​the transistor 210A. In the case where the thickest area in the resist mask 215 is greater than 2μm and less than 4μm, the channel length L can also be greater than 2μm and less than 4μm. However, the channel length L of the transistor 210A and the channel length L of the transistor 250 may be within a range of 2 μm to 4 μm, and may be the same or different.

[0159] By adding impurity elements to the oxide semiconductor layers 208_1 and 208_2, defects are generated in the crystals of the oxide semiconductor layers 208_1 and 208_2, and thus the resistance of the region is reduced. Depending on the concentration of the impurity elements added, the resistance of the oxide semiconductor layers 208_1 and 208_2 can be reduced. Therefore, the resistance of the high-concentration impurity regions 208b, 208c, 208g, and 208h can be made lower than the resistance of the low-concentration impurity regions 208d and 208e. In addition, by using the resist mask 215 having a tapered shape and the conductive layer 214_2 as a mask, a structure having low-concentration impurity regions 208d and 208e can be formed in the oxide semiconductor layer 208_1 through a single impurity element addition process, and a structure having no low-concentration impurity regions can be formed in the oxide semiconductor layer 208_2. On the other hand, the channel regions 208a and 208f have few crystal defects and low hydrogen concentration, so the resistance is kept high. In this way, different oxide semiconductor layers 208_1 and 208_2 can be formed in the same process. Note that the resist mask 215 is removed after the impurity element is added.

[0160] Fig.18 2 is a diagram for explaining the process from the step of forming the insulating film 216 to the step of forming the pixel electrode 226. Fig.12 Note that, from the step of forming the insulating film 228 to the step of forming the inorganic insulating film 242 , the manufacturing method described in the first embodiment may be applied.

[0161] Through the above process, it is possible to manufacture Fig.15 The display device 100 has a structure of a pixel 103B shown in FIG.

[0162] According to the manufacturing method of the display device 100 of one embodiment of the present invention, even in such a small area as within one pixel, two transistors with different characteristics and structures can be simply formed without increasing the process. In particular, the oxide semiconductor layer 208_1 including the high-concentration impurity regions 208b and 208c and the low-concentration impurity regions 208d and 208e and the oxide semiconductor layer 208_2 including the high-concentration impurity regions 208g and 208h can be formed at the same time.

[0163] (Variant 2)

[0164] Fig.19 1 is a diagram illustrating a cross-sectional structure of a pixel 103C of a display device 100 according to an embodiment of the present invention. Fig.19 As shown, a transistor 210B and a transistor 250 are provided on the substrate 101 via a base film 202. Here, the transistor 250 corresponds to Fig.13The write transistor SST shown in FIG. 210B corresponds to the transistor Fig.13 The driving transistor DRT is shown.

[0165] Regarding the transistor 210B, in the configuration of the transistor 210A, the conductive layer 214_1 and the high-concentration impurity region 208b are connected via the source electrode or the drain electrode 218_2. When forming the transistor 210B, after forming the conductive layers 214_1 and 214_2, a 5×10 12 atoms / cm 2 ~1×10 14 atoms / cm 2 Then, after forming a resist mask so as to cover the conductive layer 214_1 and the low-concentration impurity regions 208d and 208e, 1×10 14 atoms / cm 2 ~5×10 13 atoms / cm 2 Thus, a channel region 208a, high-concentration impurity regions 208b and 208c, and low-concentration impurity regions 208d and 208e can be formed in the oxide semiconductor layer 208_1 included in the driving transistor DRT.

[0166] (Third embodiment)

[0167] In this embodiment, refer to Figure 20 to Figure 22 The structure of the pixel 103D having a structure partially different from the structure of the pixel 103 described in the first embodiment and the second embodiment is described. It should be noted that in the pixel 103D, the same reference numerals are attached to the same parts as the pixel 103 or the parts having the same functions, and repeated descriptions are omitted.

[0168] Fig. 20 1 is a diagram illustrating a cross-sectional structure of a pixel 103D of a display device according to an embodiment of the present invention. Fig. 20 As shown in the figure, the case where the metal oxide layers 205_1 and 205_2 are provided between the insulating film 206 and the oxide semiconductor layers 208_1 and 208_2 will be described.

[0169] The metal oxide layers 205_1 and 205_2 are metal oxides containing aluminum as a main component. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y), aluminum nitride (AlN x ) or other inorganic insulating materials. The ratio of aluminum contained in the metal oxide layers 205_1 and 205_2 may be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide layers 205_1 and 205_2. The above ratio may be a mass ratio or a weight ratio.

[0170] The thickness of the metal oxide layers 205_1 and 205_2 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, aluminum oxide is used as the metal oxide layers 205_1 and 205_2. Aluminum oxide has high barrier properties against gases.

[0171] <Method for manufacturing display device>

[0172] Next, refer to Fig.21 and Fig. 22 A method for manufacturing the display device 100 according to one embodiment of the present invention will be described. It should be noted that the steps from forming the base film 202 on the substrate 101 to forming the insulating film 206 are similar to those of FIG. Figure 4 The description is enough.

[0173] Fig.21 2 is a diagram for explaining a process of forming a metal oxide film 205 mainly composed of aluminum and an oxide semiconductor film 207 on an insulating film 206. The metal oxide film 205 is formed by sputtering. The thickness of the metal oxide film 205 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm.

[0174] Next, an oxide semiconductor film 207 is formed on the metal oxide film 205. For a method of forming the oxide semiconductor film 207, refer to Figure 5 The description of the formation of the oxide semiconductor film 207 will suffice.

[0175] Next, the oxide semiconductor layers 207_1 and 207_2 are patterned from the oxide semiconductor film 207. For the patterning of the oxide semiconductor film 207, refer to Figure 6 The description of the pattern formation of the oxide semiconductor film 207 will suffice.

[0176] Next, the oxide semiconductor layer is subjected to an OS annealing treatment. Figure 7 The description of the OS annealing treatment in hereinafter will suffice. By performing the OS annealing treatment, the oxide semiconductor layers 207_1 and 207_2 are crystallized, thereby forming oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure.

[0177] In the case where the oxygen supply treatment is uniformly performed on the oxide semiconductor layers 208_1 and 208_2 having the above-described oxygen defect distribution, if the amount of oxygen required to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layers 208_1 and 208_2 is supplied, oxygen is excessively supplied to the lower surface side of the oxide semiconductor layers 208_1 and 208_2. As a result, defect energy levels different from those of the oxygen defects are formed on the lower surface side of the oxide semiconductor layers 208_1 and 208_2 due to the excess oxygen. As a result, phenomena such as characteristic changes in reliability tests or reductions in field effect mobility occur. Therefore, in order to suppress this phenomenon, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layers 208_1 and 208_2 while suppressing the oxygen supply to the lower surface side of the oxide semiconductor layers 208_1 and 208_2.

[0178] The oxidation annealing is performed in a state where the metal oxide layers 205_1 and 205_2 are provided under the oxide semiconductor layers 208_1 and 208_2, and the metal oxide film 213 is provided on the oxide semiconductor layers 208_1 and 208_2. Thus, in the above-mentioned oxidation annealing process, the oxygen injected into the insulating film 212 is blocked by the metal oxide film 213, and thus the situation where it is released into the atmosphere is suppressed. In addition, the oxygen released from the insulating film 206 is supplied to the upper surface and side surfaces of the oxide semiconductor layers 208_1 and 208_2. In addition, the metal oxide layers 205_1 and 205_2 can suppress the excessive supply of oxygen to the bottom of the oxide semiconductor layers 208_1 and 208_2. Thus, the oxygen can be efficiently supplied to the oxide semiconductor layers 208_1 and 208_2 to repair oxygen defects.

[0179] Fig. 22This is a diagram for explaining a process of using oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure and forming patterns of metal oxide layers 205_1 and 205_2 from a metal oxide film 205. The metal oxide layers 205_1 and 205_2 are etched using the oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure as masks. As the etching of the metal oxide layers 205_1 and 205_2, wet etching or dry etching can be used. As wet etching, for example, a mixed acid etching solution or a 0.5% hydrofluoric acid solution can be used. As described in the first embodiment, the oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure have etching resistance to a mixed acid etching solution or a 0.5% hydrofluoric acid solution compared to the amorphous oxide semiconductor layers 207_1 and 207_2. The oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure have almost no film reduction due to etching and are excellent in etching resistance. Therefore, the metal oxide layers 205_1 and 205_2 can be etched using the oxide semiconductor layers 208_1 and 208_2 as masks. Thus, a photolithography step can be omitted.

[0180] Next, an insulating film 212 is formed on the oxide semiconductor layers 208_1 and 208_2, and a metal oxide film 213 is formed on the insulating film 212. For the materials and film formation methods of the insulating film 212 and the metal oxide film 213, see Figure 8 The description of the insulating film 121 in FIG.

[0181] In the process from forming the oxide semiconductor layers 208_1 and 208_2 to forming the insulating film 212 on the oxide semiconductor layers 208_1 and 208_2, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layers 208_1 and 208_2. Therefore, the oxygen defects formed near the upper surface of the oxide semiconductor layers 208_1 and 208_2 are more than the oxygen defects formed near the lower surface of the oxide semiconductor layers 208_1 and 208_2. That is, the oxygen defects in the oxide semiconductor layers 208_1 and 208_2 are not uniformly present in the thickness direction of the oxide semiconductor layers 208_1 and 208_2, but are present in a non-uniform distribution in the thickness direction of the oxide semiconductor layers 208_1 and 208_2. Specifically, the oxygen vacancies in the oxide semiconductor layers 208_1 and 208_2 decrease toward the bottom surface of the oxide semiconductor layers 208_1 and 208_2 and increase toward the top surface of the oxide semiconductor layers 208_1 and 208_2.

[0182] In the case where the oxide semiconductor layers 208_1 and 208_2 having the above-described oxygen defect distribution are uniformly subjected to oxygen supply treatment, if the amount of oxygen required to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layers 208_1 and 208_2 is supplied, oxygen is excessively supplied to the lower surface side of the oxide semiconductor layers 208_1 and 208_2. As a result, defect energy levels different from those of the oxygen defects are formed on the lower side due to the excess oxygen. As a result, phenomena such as characteristic changes in reliability tests or a decrease in field effect mobility occur. Therefore, in order to suppress this phenomenon, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layers 208_1 and 208_2 while suppressing the oxygen supply to the lower surface side of the oxide semiconductor layers 208_1 and 208_2.

[0183] The oxidation annealing is performed in a state where the metal oxide layers 205_1 and 205_2 are provided under the oxide semiconductor layers 208_1 and 208_2, and the metal oxide film 213 is provided on the oxide semiconductor layers 208_1 and 208_2. Thus, in the above-mentioned oxidation annealing process, the oxygen injected into the insulating film 212 is blocked by the metal oxide film 213, and thus the situation where it is released into the atmosphere is suppressed. In addition, the oxygen released from the insulating film 206 is supplied to the upper surface and side surfaces of the oxide semiconductor layers 208_1 and 208_2. In addition, the metal oxide layers 205_1 and 205_2 can suppress the excessive supply of oxygen to the bottom of the oxide semiconductor layers 208_1 and 208_2. Thus, the oxygen can be efficiently supplied to the oxide semiconductor layers 208_1 and 208_2 to repair oxygen defects.

[0184] After the oxidation annealing, the metal oxide film 213 is removed. Figures 9 to 12 The description is enough.

[0185] In the transistor including the oxide semiconductor layers 208_1 and 208_2 manufactured by the above manufacturing method, a mobility of 50 cm-1 can be obtained when the channel length L of the channel regions 208a and 208f is in the range of 2 μm to 4 μm and the channel width of the channel regions 208a and 208f is in the range of 2 μm to 25 μm. 2 / Vs or above, 55cm 2 / Vs or above, or 60cm 2 / Vs and above electrical characteristics.

[0186] (Variant 3)

[0187] Fig.23 A diagram illustrating a cross-sectional structure of a pixel 103E of a display device 100 according to an embodiment of the present invention. Fig.23The cross-sectional structure of the pixel 103E of the display device 100 shown in FIG. 1 is similar to that of FIG. 1 except that the metal oxide layers 205_1 and 205_2 are provided between the insulating film 206 and the oxide semiconductor layers 208_1 and 208_2. Fig.15 The cross-sectional structure of the pixel 103B shown is the same. Fig.23 The method for forming the metal oxide layers 205_1 and 205_2 shown in FIG. Fig.21 and Fig. 22 The description is enough.

[0188] In the transistor including the oxide semiconductor layers 208_1 and 208_2 manufactured by the above manufacturing method, a mobility of 50 cm-1 can be obtained when the channel length L of the channel regions 208a and 208i is in the range of 2 μm to 4 μm and the channel width W of the channel regions 208a and 208i is in the range of 2 μm to 25 μm. 2 / Vs or above, 55cm 2 / Vs or above, or 60cm 2 / Vs and above electrical characteristics.

[0189] (Variant 4)

[0190] In this embodiment, the case where the oxidation annealing is performed in a state where the metal oxide layers 205_1 and 205_2 and the metal oxide film 213 are formed is described, but one embodiment of the present invention is not limited to this. Fig. 22 After the oxide semiconductor layers 208_1 and 208_2 having a polycrystalline structure described in the above, oxidation annealing is performed in such a way that the insulating film 212 is formed but the metal oxide film 213 is not formed. In this case, the structure of the pixel is similar to Fig. 20 The pixel 103D and Fig.23 The pixel 103E shown is the same and therefore is omitted from illustration in this variation.

[0191] In the display device 100 of this embodiment, the transistor is formed using the oxide semiconductor layers 208_1 and 208_2 having a good polycrystalline structure. In the transistor Tr including the oxide semiconductor layers 208_1 and 208_2, when the channel length L of the channel regions 208a and 208i is 2 μm or more and 4 μm or less, and the channel width of the channel regions 208a and 208i is 2 μm or more and 25 μm or less, a mobility of 30 cm 2 / Vs or above, 35cm 2 / Vs or above, or 40cm 2 / Vs and above electrical characteristics.

[0192] (Fourth embodiment)

[0193] In this embodiment, refer to Fig.24 and Fig.25 The circuit configuration and operation method of the pixel included in the display device 100 will be described.

[0194] <Equivalent circuit diagram>

[0195] Fig.24 1 is an equivalent circuit diagram of a pixel 103F included in a display device 100 according to an embodiment of the present invention. The display device 100 includes a high potential power supply SLa, a low potential power supply electrode SLb, a light emission control scanning line Sga, a write control scanning line Sgb, a reset control scanning line Sgc, and an image signal line VL. The high potential power supply SLa is provided with a high potential power supply Pvdd, and the low potential power supply electrode SLb is provided with a low potential power supply Pvss. The light emission control scanning line Sga, the write control scanning line Sgb, and the reset control scanning line Sgc are connected to gate drive circuits 104_1 and 104_2. In addition, the image signal line VL is connected to a driver IC 105.

[0196] The pixel 103F has a write transistor SST, a drive transistor DRT, a holding capacitor Cs and an additional capacitor Cad. The holding capacitor Cs and the additional capacitor Cad are capacitors. The additional capacitor Cad is a component provided to adjust the amount of light-emitting current, and the additional capacitor Cad is sometimes not required depending on the situation. The parasitic capacitor Cel is the capacitance of the light-emitting element itself (the parasitic capacitance of the light-emitting element OLED). The light-emitting element OLED also functions as a capacitor.

[0197] Each pixel 103F has an output transistor BCT. In this embodiment, four pixels 103F adjacent to each other in the row direction X and the column direction Y share one output transistor BCT. In addition, a plurality of reset transistors RST are provided in the gate drive circuits 104_1 and 104_2. The reset transistors RST and the reset control scanning lines Sgr are connected one to one.

[0198] The driving transistor DRT has the structure of the transistor 210 described in the first embodiment, and the write transistor SST, the output transistor BCT, and the reset transistor RST have the structure of the transistor 220 described in the first embodiment. Alternatively, the driving transistor DRT may have the structure of the transistor 210A or the transistor 210B described in the second embodiment, and the write transistor SST, the output transistor BCT, and the reset transistor RST may have the structure of the transistor 220 or the transistor 250 described in the second embodiment. In the display device 100 of this embodiment, all transistors constituting each driving transistor and each switch are formed in the same process.

[0199] The write transistor SST, the drive transistor DRT, the output transistor BCT, and the reset transistor RST each have a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is a source electrode, the second terminal is a drain electrode, and the control terminal is a gate electrode.

[0200] In the pixel circuit of the pixel, the driving transistor DRT is connected in series with the light emitting element OLED between the high potential power source SLa and the low potential power source electrode SLb.

[0201] In the output transistor BCT, the drain electrode is connected to the high potential power supply SLa, the source electrode is connected to the drain electrode of the driving transistor DRT, and the gate electrode is connected to the light emission control scanning line Sga. Thus, the output transistor BCT is controlled to be turned on (conductive state) and off (non-conductive state) by the control signal BG (1 to m / 2) from the light emission control scanning line Sga. The output transistor BCT controls the light emission time of the light emitting element OLED in response to the control signal BG.

[0202] In the driving transistor DRT, the drain electrode is connected to the source electrode of the output transistor BCT and the reset control scanning line Sgr, and the source electrode is connected to one electrode (here, the anode) of the light emitting element OLED. The other electrode (here, the cathode) of the light emitting element OLED is connected to the low potential power supply electrode SLb. The driving transistor DRT outputs a driving current of a current amount corresponding to the image signal Vsig to the light emitting element OLED.

[0203] In the write transistor SST, the source electrode is connected to the image signal line VL (1 to n), the drain electrode is connected to the gate electrode of the drive transistor DRT, and the gate electrode is connected to the write control scan line Sgb (1 to m) which functions as a gate wiring for signal write control. The write transistor SST is turned on and off by the control signal SG (1 to m) supplied from the write control scan line Sgb. In addition, the write transistor SST controls the connection and disconnection between the pixel circuit and the image signal line VL (1 to n) in response to the control signal SG (1 to m), and takes the image signal Vsig from the corresponding image signal line VL (1 to n) into the pixel circuit.

[0204] The reset transistor RST is provided in the gate drive circuits 104_1 and 104_2 in every two rows. The reset transistor RST is connected between the drain electrode of the drive transistor DRT and the reset power supply. In the reset transistor RST, the source electrode is connected to the reset power supply line SLc, which is connected to the reset power supply, the drain electrode is connected to the reset control scanning line Sgr, and the gate electrode is connected to the reset control scanning line Sgc which functions as a reset control gate wiring. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed at the reset potential Vrst which is a constant potential.

[0205] The reset transistor RST switches the reset power supply line SLc and the reset control scanning line Sgr to a conducting state (on) or a non-conducting state (off) according to the control signal RG (1-m / 2) given by the reset control scanning line Sgc. By switching the reset transistor RST to a conducting state, the potential of the source electrode of the driving transistor DRT is initialized.

[0206] The gate drive circuits 104_1 and 104_2 include shift registers and output buffers (not shown), which sequentially transmit the horizontal scan start pulse supplied from the outside to the next stage, and supply three control signals, namely, control signal BG (1 to m / 2), control signal SG (1 to m), and control signal RG (1 to m / 2), to the pixels 103F of each row via the output buffers. It should be noted that the control signal RG is not directly supplied to the pixel 103F, but a predetermined voltage is supplied from the reset power supply line SLc fixed to the reset potential Vrst at a predetermined timing corresponding to the control signal RG. Thus, the light emission control scan line Sga, the write control scan line Sgb, and the reset control scan line Sgc are driven by the control signals BG, SG, and RG, respectively.

[0207] <Timing diagram>

[0208] Fig.25 Is used to drive Fig.24 The timing diagram of the pixel gate drive circuit 104_1 and 104_2 is shown in FIG. Fig.25 In FIG. 1 , control signals RGk, BGk, and SGk for row k, and control signals RGk+1, BGk+1, and SGk+1 for row k+1 are shown. Each interval shown in G1 to G4 is a horizontal period, which is then omitted but continues to the last row. Fig.24 The period indicated by T0 to T1 is described in detail below.

[0209] <T0. Previous frame lights up>

[0210] During the period until the processing of a certain frame period starts, the pixel continues the light emitting state of the previous frame.

[0211] <T1. DRT source initialization operation>

[0212] During this period, first, the control signal BG becomes L level, the control signal RG becomes H level, the control signal SG becomes L level, the output transistor BCT is turned off, the reset transistor RST is turned on, and the write transistor SST is turned off. Here, the "voltage corresponding to the image signal written in the previous frame" is maintained in the holding capacitor Cs. If the image signal Vsig is greater than the reset potential Vrst, the source side is also close to the reset potential Vrst through the driving transistor DRT. In addition, the reset potential Vrst becomes substantially the same potential as the low potential power supply Pvss, so the current supply to the light-emitting element OLED is stopped. As a result, the potential on the source side of the driving transistor DRT becomes the lowest state in the pixel system.

[0213] <T2. DRT gate initialization>

[0214] During this period, the control signal BG becomes L level, the control signal RG becomes H level, the control signal SG becomes H level, the image signal line VL becomes the initialization potential Vini, the output transistor BCT is turned off, the reset transistor RST is turned on, and the write transistor SST is turned on. In each pixel 103F of each row, the gate of the driving transistor DRT is fixed to the initialization potential Vini via the write transistor SST. The initialization potential Vini is set to a potential greater than the threshold of the driving transistor DRT relative to the reset potential Vrst. That is, the driving transistor DRT is turned on by this operation. However, since the output transistor BCT is in the off state, the current has not yet flowed through the driving transistor DRT. It should be noted that even if the image signal Vsig is not greater than the reset potential Vrst in the T1.DRT source initialization action, the source of the driving transistor DRT can be initialized during this period.

[0215] <T3. Adjustment elimination (Japanese: オフセットキャンセル) action>

[0216] During this period, the control signal BG becomes an H level, the control signal RG becomes an L level, the control signal SG becomes an H level, the image signal line VL becomes an initialization potential Vini, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned on. Since the driving transistor DRT is in an on state due to the previous action, a current is supplied to the driving transistor DRT from the high potential power supply Pvdd through the output transistor BCT. At this stage, the voltage between the anode and cathode of the light-emitting element OLED does not exceed the light-emitting start voltage, so the current does not flow. Therefore, the source of the driving transistor DRT is charged by the current supplied from the high potential power supply Pvdd, and its potential rises. At this time, the gate potential of the driving transistor DRT becomes Vini, so at the stage where the source of the driving transistor DRT becomes (Vini-Vth), the driving transistor DRT is turned off and the rise of the potential stops. The so-called Vth refers to the threshold voltage of the driving transistor DRT, and there is a deviation depending on the pixel 103F, so the potential of the source of the driving transistor DRT when the rise of the potential stops varies from pixel to pixel. That is, through this operation, a voltage equivalent to the threshold voltage of the driving transistor DRT is obtained in each pixel 103F. At this time, a voltage of {(Vini-Vth)-Pvss} is applied between the anode and cathode of the light-emitting element OLED, but since this voltage still does not exceed the light-emitting start voltage, no current flows in the light-emitting element OLED.

[0217] It should be noted that according to Fig.25 In the timing diagram, the actions 1. to 3. are performed in parallel for 2 rows, but the present invention is not limited thereto. The actions may be performed sequentially for each row, or may be performed in parallel for 3 or more rows.

[0218] <T4. Mobility elimination and image signal writing operation>

[0219] The control signal BG becomes an H level, the control signal RG becomes an L level, the control signal SG becomes an H level, the image signal line VL becomes an image signal Vsig, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned on. In each pixel 103F of the row, the image signal Vsig is input to the gate of the drive transistor DRT, and the gate potential of the drive transistor DRT changes from the initialization potential Vini to the image signal Vsig. On the other hand, the source potential of the drive transistor DRT is still (Vini-Vth), and as a result, the gate-source voltage of the drive transistor DRT becomes {Vsig-(Vini-Vth)}, reflecting the deviation of the threshold value between the pixels 103F.

[0220] Since the video signal line VL sharing the video signal Vsig is shared by a plurality of rows of pixels 103F belonging to the same column, the video signal writing operation is sequentially performed for each row.

[0221] <T5. Luminous action>

[0222] The control signal BG becomes an H level, the control signal RG becomes an L level, the control signal SG becomes an L level, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned off. Current is supplied from the high potential power supply Pvdd to the drive transistor DRT through the output transistor BCT. The drive transistor DRT causes a current corresponding to the gate-source voltage set up to the previous stage to flow through the light-emitting element OLED, and the light-emitting element OLED emits light at a brightness corresponding to the current. At this time, the anode-cathode voltage of the light-emitting element OLED becomes a voltage corresponding to the current, so the potential on the anode side rises, but since the gate-source voltage of the drive transistor DRT is maintained by the holding capacitor Cs, as the potential on the anode side rises, the gate potential of the drive transistor DRT also rises through the coupling of the holding capacitor Cs. In fact, the gate of the driving transistor DRT is provided with not only a holding capacitor Cs but also an additional capacitor Cad and other parasitic capacitors. Therefore, the rise in the gate potential of the driving transistor DRT is slightly smaller than the rise in the potential on the anode side, but this value is known. Therefore, it is sufficient to determine the potential of the image signal Vsig in such a way that the desired current value becomes the final gate-source voltage of the driving transistor DRT.

[0223] Thus, a series of pixel operations are completed. If the operation is completed from the first row to the last row, one screen is displayed within one frame period. After that, the operation is repeated to display an image.

[0224] Any of the bottom-gate driven transistors 210, 210A, and 210B described in the first and second embodiments is applied to the driving transistor DRT. In addition, any of the top-gate driven transistors 220 and 250 described in the first and second embodiments is applied to the write transistor SST, the reset transistor RST, and the initialization transistor IST. Thus, since the S value of the driving transistor DRT is large, the current change of the driving transistor DRT can be reduced in a low grayscale area that needs to be controlled by a small current, and the grayscale can be finely controlled. Thus, the display unevenness can be suppressed in the display area 102.

[0225] (Fifth embodiment)

[0226] In this embodiment, refer to Fig.26 and Fig. 27 The circuit structure and operation method of the pixel 103G included in the display device 100 will be described.

[0227] <Circuit Diagram>

[0228] Fig.26 1 is an equivalent circuit diagram of the pixel circuit of pixel 103G. The light emitting control scanning line Sga, the writing control scanning line Sgb, the reset control scanning line Sgc, and the initialization control scanning line Sgd are respectively connected to the gate driving circuits 104_1 and 104_2 arranged outside the display area 102. An output transistor BCT, an initialization transistor IST, a writing transistor SST, and a driving transistor DRT are provided in each pixel 103G. A part of the transistors can be shared between a plurality of adjacent pixels 103G. The reset transistor RST is provided outside the display area, for example, one in each row. A holding capacitor Cs can be provided between the gate and the source of the driving transistor DRT. The parasitic capacitor Cel is a parasitic capacitance between the anode and the cathode of the light emitting element OLED. A high potential power supply Pvdd is given to the anode of the light emitting element OLED via the output transistor BCT and the driving transistor DRT, and a low potential power supply Pvss is given to the cathode. The output transistor BCT, the initialization transistor IST, and the write transistor SST function as switch elements for selecting conduction or non-conduction between two nodes, and the drive transistor DRT functions as a current control element for controlling the current value flowing through the OLED according to the voltage between its gate and source. In this embodiment, the transistor 210 is used as the drive transistor DRT, and the structure of the transistor 220 is used as the output transistor BCT, the initialization transistor IST, and the write transistor SST.

[0229] <Timing diagram>

[0230] Fig. 27 Is used to drive Fig.26 The timing diagram of the pixel gate drive circuits 104_1 and 104_2 shown in FIG. Each interval shown in G1 to G3 is a horizontal period and lasts until the last row. Fig. 27 The period shown in FIG. 1 is T0 to T6.

[0231] <T0. Previous frame lights up>

[0232] During the period until the processing of a certain frame period starts, the pixel continues the light emitting state of the previous frame.

[0233] <T1. Source initialization operation of driving transistor DRT>

[0234] During this period, first, the control signal BG becomes L level, the control signal RG becomes H level, the control signal IG becomes L level, the control signal SG becomes L level, the output transistor BCT is turned off, the reset transistor RST is turned on, the initialization transistor IST is turned off, and the write transistor SST is turned off. Here, the "voltage corresponding to the image signal written in the previous frame" is maintained in the holding capacitor Cs. If the image signal Vsig is greater than the reset potential Vrst, the source side is also close to the reset potential Vrst through the driving transistor DRT. In addition, the reset potential Vrst becomes substantially the same potential as the low potential power supply Pvss, so the current supply to the light-emitting element OLED stops. As a result, the potential on the source side of the driving transistor DRT becomes the lowest state in the pixel system.

[0235] <T2. Gate initialization of drive transistor DRT>

[0236] The control signal IG becomes H level, and the initialization transistor IST is turned on. In each pixel of the row, the gate of the driving transistor DRT is fixed to the initialization potential Vini via the initialization transistor IST. The initialization potential Vini is set to a potential greater than the threshold of the driving transistor DRT relative to the reset potential Vrst. That is, the driving transistor DRT is turned on by this operation. However, since the output transistor BCT is turned off, the current has not yet flowed through the driving transistor DRT.

[0237] <T3. Disturbance elimination action>

[0238] The control signal BG becomes an H level, the control signal RG becomes an L level, the control signal IG becomes an H level, the output transistor BCT is turned on, the reset transistor RST is turned off, and the initialization transistor IST is turned on. Since the driving transistor DRT is in an on state due to the previous action, current is supplied from the output transistor BCT to the driving transistor DRT through Pvdd. At this stage, the voltage between the anode and cathode of the light-emitting element OLED does not exceed the light-emitting start voltage, so the current does not flow. Therefore, the source of the driving transistor DRT is charged by the current supplied from the high potential power supply Pvdd, and its potential rises. At this time, the gate potential of the driving transistor DRT becomes the initialization potential Vini, so at the stage where the source of the driving transistor DRT becomes (Vini-Vth), the driving transistor DRT is turned off and the rise of the potential stops. The so-called Vth refers to the threshold voltage of the driving transistor DRT, and there is a deviation depending on the pixel 103G, so the potential of the source of DRT when the rise of the potential stops is different from pixel to pixel. That is, through this action, a voltage equivalent to the threshold voltage of the driving transistor DRT is obtained in each pixel. At this time, a voltage of {(Vini-Vth)-Pvss} is applied between the anode and cathode of the light-emitting element OLED, but since this voltage still does not exceed the emission start voltage, no current flows through the light-emitting element OLED.

[0239] It should be noted that according to Fig. 27 In the timing diagram, the actions of T1. to T3. are performed in parallel for two rows, but the present invention is not limited thereto. The actions may be performed sequentially for each row, or may be performed in parallel for three or more rows.

[0240] <T4.T5. Image signal writing operation>

[0241] The control signal BG becomes an H level, the control signal RG becomes an L level, the control signal IG becomes an L level, the control signal SG becomes an H level, the output transistor BCT is turned on, the reset transistor RST is turned off, the initialization transistor IST is turned off, and the write transistor SST is turned on. In each pixel of the row, the image signal Vsig is input to the gate of the drive transistor DRT, and the gate potential of the drive transistor DRT changes from Vini to Vsig. On the other hand, the source potential of the drive transistor DRT is still (Vini-Vth). As a result, the gate-source voltage of the drive transistor DRT becomes {Vsig-(Vini-Vth)}, reflecting the deviation of the threshold value between pixels.

[0242] Since the video signal line VL sharing Vsig is commonly used by a plurality of rows of pixels belonging to the same column, the writing operation of the video signal VSig is sequentially performed for each row.

[0243] <T6. Luminous action>

[0244] The control signal BG becomes an H level, the control signal RG becomes an L level, the control signal IG becomes an L level, the control signal SG becomes an L level, the output transistor BCT is turned on, the reset transistor RST is turned off, the initialization transistor IST is turned off, and the write transistor SST is turned off. Current is supplied from the high potential power supply Pvdd to the driving transistor DRT through the output transistor BCT. The driving transistor DRT causes a current corresponding to the gate-source voltage set in the previous stage to flow through the light-emitting element OLED, and the light-emitting element OLED emits light with a brightness corresponding to the current. At this time, the anode-cathode voltage of the light-emitting element OLED becomes a voltage corresponding to the current, so the potential on the anode side rises, but since the gate-source voltage of the driving transistor DRT is maintained by the holding capacitor Cs, as the potential on the anode side rises, the gate potential of the driving transistor DRT also rises through the coupling of the holding capacitor Cs. In fact, the gate of the driving transistor DRT is provided with not only a holding capacitor Cs but also an additional capacitor Cad and other parasitic capacitors Cel. Therefore, the rise in the gate potential of the driving transistor DRT is slightly smaller than the rise in the potential on the anode side, but this value is known. Therefore, it is sufficient to determine the potential of the image signal Vsig in such a way that the desired current value becomes the final gate-source voltage of the driving transistor DRT.

[0245] Thus, a series of operations of the pixel 103G are completed. When the operations from the first row to the last row are completed, one screen is displayed within one frame period. Thereafter, the operations are repeated to display an image.

[0246] Any of the bottom-gate driven transistors 210, 210A, and 210B described in the first and second embodiments is applied to the driving transistor DRT. In addition, any of the top-gate driven transistors 220 and 250 described in the first and second embodiments is applied to the write transistor SST, the reset transistor RST, and the initialization transistor IST. Thus, since the S value of the driving transistor DRT is large, the current change of the driving transistor DRT can be reduced in a low grayscale area that needs to be controlled by a small current, and the grayscale can be finely controlled. Thus, the display unevenness can be suppressed in the display area 102.

[0247] Based on the display device described as the embodiment and example of the present invention, the solution obtained by adding, deleting or changing the design of the components, or the solution obtained by adding, omitting or changing the conditions of the processes appropriately by the skilled person in the art, as long as it has the gist of the present invention, is included in the scope of the present invention. In addition, the above-mentioned embodiments can be combined with each other within the scope that no technical contradiction occurs.

[0248] Furthermore, even if there are other effects different from the effects brought about by the above-mentioned embodiments, the effects that are clearly described in this specification or that can be easily predicted by those skilled in the art can of course be understood to be brought about by the present invention.

[0249] Within the scope of the present invention, those skilled in the art can obtain schemes equivalent to various variations and modifications, and these variations and modifications should also be understood to belong to the scope of the present invention. For example, embodiments obtained by adding, deleting or designing the above-mentioned embodiments by those skilled in the art, or embodiments obtained by adding, omitting or changing the conditions of the processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

Claims

1. A display device, comprising: Light emitting element; a first transistor for controlling a current value flowing from a driving power line to the light emitting element; and a second transistor that writes a voltage corresponding to the light emission brightness of the light emitting element into the first gate electrode of the first transistor, The first transistor comprises: the first gate electrode; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode; a second insulating film provided on the first oxide semiconductor layer; and a first conductive layer provided on the second insulating film, The second transistor comprises: the first insulating film; a second oxide semiconductor layer provided on the first insulating film; the second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer, The first oxide semiconductor layer includes a first channel region and a first high-concentration impurity region disposed so as to sandwich the first channel region. The second oxide semiconductor layer includes a second channel region and a second high-concentration impurity region disposed so as to sandwich the second channel region. The first conductive layer is electrically connected to the light emitting element. When the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate is less than 3 nm / min.

2. The display device according to claim 1, wherein: The first insulating film has a thickness of not less than 100 nm and not more than 500 nm. The second insulating film has a thickness of not less than 30 nm and not more than 150 nm.

3. The display device according to claim 1, wherein: The impurity element contained in the first high-concentration impurity region and the impurity element contained in the second high-concentration impurity region are the same element, The concentration of the impurity element contained in the first high-concentration impurity region and the second high-concentration impurity region is 1×10 18 cm -3 Above 1×10 21 cm -3 the following.

4. The display device according to claim 3, wherein: The sheet resistance in the first high-concentration impurity region and the second high-concentration impurity region is 1000 Ω / sq. or less.

5. The display device according to claim 1, further comprising: a first metal oxide layer provided between the first insulating film and the first oxide semiconductor layer; and a second metal oxide layer provided between the first insulating film and the second oxide semiconductor layer, The film thickness of the first metal oxide layer and the film thickness of the second metal oxide layer are not less than 1 nm and not more than 10 nm.

6. The display device according to claim 1, wherein: The etching solution includes nitric acid and acetic acid.

7. The display device according to claim 1, wherein: When the first oxide semiconductor layer and the second oxide semiconductor layer are etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate is less than 5 nm / min.

8. The display device according to claim 1, wherein: The first oxide semiconductor layer and the second oxide semiconductor layer are formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate is 100 nm / min or more.

9. The display device according to claim 1, wherein: The first oxide semiconductor layer and the second oxide semiconductor layer contain a plurality of metal elements. One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

10. A display device comprising: Light emitting element; a first transistor for controlling a current value flowing from a driving power line to the light emitting element; and a second transistor that writes a voltage corresponding to the light emission brightness of the light emitting element into the first gate electrode of the first transistor, The first transistor comprises: a first gate electrode; a first insulating film provided on the first gate electrode; and a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode, The second transistor comprises: the first insulating film; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer, The first oxide semiconductor layer includes a first channel region, a low-concentration impurity region disposed so as to sandwich the first channel region, and a first high-concentration impurity region disposed adjacent to the low-concentration impurity region. The second oxide semiconductor layer includes a second channel region and a second high-concentration impurity region disposed so as to sandwich the second channel region. When the first oxide semiconductor layer and the second oxide semiconductor layer are etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate is less than 3 nm / min.

11. The display device according to claim 10, wherein: The low-impurity concentration region overlaps with the first gate electrode.

12. The display device according to claim 10, wherein: The first insulating film has a thickness of not less than 100 nm and not more than 500 nm. The second insulating film has a thickness of not less than 30 nm and not more than 150 nm.

13. The display device according to claim 10, wherein: An impurity element contained in the first high-concentration impurity region and an impurity element contained in the second high-concentration impurity region are the same element.

14. The display device according to claim 10, wherein: The concentration of the impurity element contained in the first high-concentration impurity region and the second high-concentration impurity region is 1×10 18 cm -3 Above 1×10 21 cm -3 the following, The concentration of the impurity element contained in the low-concentration impurity region is less than 1×10 18 cm -3 .

15. The display device according to claim 14, wherein: The sheet resistance in the first high-concentration impurity region and the second high-concentration impurity region is 1000 Ω / sq. or less.

16. The display device according to claim 10, further comprising: a first metal oxide layer provided between the first insulating film and the first oxide semiconductor layer; and a second metal oxide layer provided between the first insulating film and the second oxide semiconductor layer, The film thickness of the first metal oxide layer and the film thickness of the second metal oxide layer are not less than 1 nm and not more than 10 nm.

17. The display device according to claim 10, wherein: The etching solution includes nitric acid and acetic acid.

18. The display device according to claim 10, wherein: When the first oxide semiconductor layer and the second oxide semiconductor layer are etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate is less than 5 nm / min.

19. The display device according to claim 10, wherein: The first oxide semiconductor layer and the second oxide semiconductor layer are formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate is 100 nm / min or more.

20. The display device according to claim 10, wherein: The first oxide semiconductor layer and the second oxide semiconductor layer contain a plurality of metal elements. One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

Images