MEMS device with ultra-thick structure and ultra-small structure gap and processing method

Abstract

The invention belongs to the technical field of micro-electro-mechanical systems, and particularly relates to an MEMS device with an ultra-thick structure and an ultra-small structure gap and a processing method. The MEMS device comprises a cover plate (333), a silicon structure layer (201) and a silicon through hole sheet (111) which are formed by bonding, a second cavity (28) is manufactured to change the thickness of a movable structure by means of photoetching and etching on the back surfaces of areas of a thin movable structure (24) and a small structure gap (23) of the silicon structure layer (201), a large structure gap (27) and the small structure gap (23) are simultaneously realized by photoetching and etching on a non-pattern surface of the silicon structure layer (201), and the thickness of the large structure gap (27) and the small structure gap (23) is changed by means of photoetching and etching on the back surfaces of areas of the thin movable structure (24) and the small structure gap (23). And the influence of the lag effect is effectively eliminated. By changing the thickness of the local structure layer and simultaneously solving the problems that the etching depth-to-width ratio is difficult to increase and the structure gap is limited by the etching depth-to-width ratio in the processing process of the super-thick structure, the size of the minimum structure gap in the super-thick structure is further reduced, and the driving and detecting capabilities of the capacitive MEMS device are remarkably improved.

Description

Technical Field

[0001] The invention belongs to the technical field of micro-electronic machinery, and in particular relates to a MEMS device with an ultra-thick structure and an ultra-small structure gap and a processing method thereof. Background Art

[0002] Micro Electro-Mechanical Systems (MEMS) can achieve the advantages of large-scale and low-cost manufacturing. At the same time, the device is small in size and low in power consumption, and is increasingly being used in the fields of biology, gas, and inertial sensing.

[0003] The structural processing of MEMS devices can generally be divided into surface micromachining technology and bulk silicon processing technology. The bulk silicon processing technology realizes the bonding of wafers or the sealing of devices by wafer bonding. The structural layer can use single-crystal silicon wafers. Compared with deposited polycrystalline silicon, single-crystal silicon materials have better mechanical and electrical properties and are widely used in high-precision inertial sensing MEMS gyroscopes, accelerometers and other devices. MEMS gyroscopes and accelerometers can effectively increase the sensing quality and improve device performance by increasing the thickness of the movable structure. For capacitive MEMS devices, the capacitor gap is also a key parameter that affects the signal-to-noise ratio of the device. Reducing the capacitor gap can significantly increase the capacitor driving capability or significantly improve the capacitor detection sensitivity.

[0004] Compared with surface micromachining technology, bulk silicon technology can achieve thicker MEMS device core structure processing through photolithography combined with anisotropic dry etching and isotropic wet etching. However, due to the limitations of MEMS processing capabilities, especially the DRIE etching depth-to-width ratio, the ratio of structure thickness to minimum structure gap is limited. Generally, the thickness of MEMS movable structures is 50um to 70um, and the minimum gap of capacitors is generally 2um to 5um. For the processing of ultra-thick structures, on the one hand, as the etching depth increases, the etching efficiency decreases significantly, the etching time is significantly prolonged, the photoresist mask is more lost, and the DRIE etching depth-to-width ratio is more difficult to improve. On the other hand, during the etching process, the etching rate in the area with a small structure gap is significantly lower than that in the area with a large structure gap, that is, the lag effect causes a significant decrease in the processing uniformity of MEMS devices. In order to improve the etching uniformity, a Dummy filling structure is generally added to the structure to ensure that the etched structure gap is consistent. However, the structure gap of this method is limited by the dry etching depth-to-width ratio, and the structure gap becomes larger as the structure thickness increases. Summary of the invention

[0005] Purpose of the invention: To provide a MEMS device with ultra-thick structure and ultra-small structure gap and processing method, solve the problem that it is difficult to improve the etching depth-to-width ratio during the processing of ultra-thick silicon structure, and the structure gap is limited by the etching depth-to-width ratio, effectively eliminate the influence of lag effect, and realize the etching of large structure gap and small structure gap at the same time. This method breaks the limitation of DRIE etching depth-to-width ratio of ultra-thick structure and further reduces the size of the smallest structure gap in ultra-thick structure.

[0006] Technical solution:

[0007] A MEMS device with an ultra-thick structure and an ultra-small structure gap comprises: a cover plate 333, a silicon structure layer 201 and a through silicon via sheet 111, which are bonded together.

[0008] The through silicon via sheet 111 comprises: a first cavity 6, a first supporting structure 7, a through silicon via 5, an oxide layer 4 and a conductive metal 9, wherein the first cavity 6 is a square shallow cavity located in the sheet, the side wall of the first cavity 6 is the first supporting structure 7, the through silicon via 5 comprises a dry-etched hole 8 and a trapezoidal hole formed by wet etching corresponding to the position of the dry-etched hole 8, the dry-etched hole 8 is circular, square or polygonal, and the conductive metal 9 is located on the inner wall surface of the through silicon via 5;

[0009] The silicon structure layer 201 includes: a thin movable structure 24, a thick movable structure 26, a first anchor point 25, a filling structure anchor point 29, an electrode 22 and a first sealing ring 21 of the MEMS device; a small structure gap 23 is a gap between the thin movable structure 24 and the electrode 22; a gap between the thick movable structure 26 and the first anchor point 25, a gap between the thick movable structure 26 and the filling structure anchor point 29, and a gap between the thick movable structures 26 are all large structure gaps 27; the back area of ​​the thin movable structure 24 and the small structure gap 23 in the chip has a second Cavity 28, the second cavity 28 is a square shallow cavity made by dry etching or a trapezoidal shallow cavity made by wet etching, the silicon structure layer 201 and the through silicon via sheet 111 are connected by silicon-silicon bonding, the first anchor point 25 is located inside the sheet and corresponds to the support structure 7 of the through silicon via sheet 111, the first sealing ring 21 is located outside the sheet and also corresponds to the support structure 7 of the through silicon via sheet 111, the silicon structure layer electrode 22 corresponds to the dry etching hole 8 of the through silicon via 5 on the through silicon via sheet 111, and the signal is directly led out through the conductive metal 9 of the through silicon via 5 on the through silicon via sheet 111;

[0010] The SOI sheet used for the cover plate 333 includes a top silicon layer 31 bonded to the silicon structure layer 201, an intermediate buffer layer 32 and a support layer 33. The top silicon layer 31 structure of the cover plate 333 includes a second sealing ring 36 corresponding to the position of the first sealing ring 21 of the silicon structure layer 201, and a second anchor point 37 corresponding to the anchor point of the silicon structure layer 201. The cover plate 333 and the silicon structure layer 201 are sealed by bonding through an intermediate metal layer 35.

[0011] Furthermore, the SOI top silicon 31 structure of the cover plate 333 also includes: a silicon conduction band 38, which connects the second anchor point 37 to the electrode 22. The silicon conduction band 38 is formed by etching twice on the SOI top silicon 31. The silicon conduction band 38 is used to reduce the number and arrangement of silicon through vias 5. The top silicon 31 is low-resistance silicon with a resistivity of 0.001Ω·cm to 0.1Ω·cm.

[0012] Furthermore, the cover plate 333 is a silicon wafer 666, and the cover plate 333 structure includes a third anchor point 63, an oxide layer 61 and a third sealing ring 62. The third anchor point 63 and the third sealing ring 62 are etched from the silicon wafer 666, and then the oxide layer 61 is formed on the surface by thermal oxidation, and finally, an intermediate metal layer 35 for bonding is made to bond and seal with the silicon structure layer 201.

[0013] Further, the through silicon via sheet 111 includes: a first cavity 6, a through silicon via 5, an oxide layer 4, and a conductive metal 9. The through silicon via 5 includes a dry-etched hole 8 and a trapezoidal hole formed by wet etching corresponding to the position of the dry-etched hole 8. The silicon structure layer 444 includes a fourth sealing ring 41, a fourth anchor point 46, a fourth filling structure anchor point 50, a fourth cavity 47, a fifth cavity 45, a fourth thin movable structure 44, and a fourth thick movable structure 48, wherein:

[0014] The fourth cavity 47 is a shallow cavity formed by etching around the fourth anchor point 46 in the chip, and is a square shallow cavity formed by dry etching or a trapezoidal shallow cavity formed by wet etching. The fifth cavity 45 is located in the corresponding area on the back side of the fourth thin movable structure 44 and the fourth small structure gap 43, wherein the depth of the fourth cavity 47 is less than the depth of the fifth cavity 45;

[0015] The fourth small structural gap 43 is the gap between the fourth electrode 42 and the fourth thin movable structure 44 , and the fourth large structural gap 43 is the gap between the fourth thick movable structures 44 , between the fourth thick movable structure 44 and the fourth filling structure anchor point 50 , and between the fourth thick movable structure 44 and the fourth anchor point 46 .

[0016] Furthermore, the SOI top silicon used for the silicon structure layer 444 is etched into a fourth cavity 47, a fourth anchor point 46 and a fifth cavity 45 through two photolithography and etching processes; then the silicon structure layer 444 is bonded to the silicon through-hole sheet 111 by silicon-silicon bonding; then, the top silicon 401 is photolithographically etched on the non-patterned surface to produce a fourth small structure gap 43 and a fourth large structure gap 49, to form a fourth sealing ring 41, a fourth anchor point 46, a fourth thin movable structure 44, a fourth filling structure anchor point 50 and a fourth thick movable structure 48, and finally bonded and sealed with the cover plate 333.

[0017] A method for the above-mentioned MEMS device comprises the following steps:

[0018] a. manufacturing a through silicon via sheet 111, manufacturing a support structure 7 and a dry-etched hole 8 by dry etching, manufacturing a through silicon via 5 by wet etching, and then oxidizing the through silicon via sheet 111;

[0019] b. Making a silicon structure layer 201, depositing silicon oxide 13 on a SOI wafer with a certain thickness of top silicon 201, spin-coating photoresist 14 on the back area of ​​the thin movable structure 24 and the small structure gap 23, etching silicon oxide by photolithography and RIE, making a second cavity 28 by dry etching or wet etching silicon, removing silicon oxide on the surface of the top silicon 201, cleaning, silicon-silicon bonding of the top silicon 201 of the SOI wafer with the through silicon via wafer 111, removing the SOI wafer support layer 203 and the buffer layer 202; making a small structure gap 23 and a large structure gap 27 by photolithography and etching on the top silicon 201 bonded with the through silicon via wafer 111, forming a thin movable structure 24, a thick movable structure 26, a bonding anchor 29, a filling structure anchor 29 and an electrode 22;

[0020] c. Make a second sealing ring 36 and a second anchor point 37 structure on the top silicon 31 of the cover plate 333 SOI, deposit a bonding intermediate metal layer 35, photolithograph and etch the intermediate metal layer 35, and use gold-silicon bonding or gold-gold bonding to achieve connection and sealing between the cover plate 333 and the silicon structure layer 201. Use a hard mask to plate a conductive metal 9 in the silicon through hole 5 of the silicon through hole sheet 111 to achieve electrode lead-out.

[0021] Furthermore, the silicon structure layer 201 uses a double-polished silicon wafer 666, and the double-polished silicon wafer 666 is temporarily bonded to a support sheet. After photolithography and etching to form the second cavity 28, the silicon structure layer 201 is silicon-silicon bonded to the through silicon via sheet 111, and then the temporary support sheet and temporary bonding glue are removed.

[0022] Furthermore, the silicon structure layer 201 is a double-polished silicon wafer, which is bonded to the through silicon via sheet 111 after the second cavity 28 is made on the first side of the silicon wafer. After bonding, the silicon wafer is thinned to obtain a silicon wafer of appropriate thickness, and then the second side is made.

[0023] Beneficial effects:

[0024] The all-silicon MEMS structure device of the present invention has good temperature characteristics, uses silicon through holes to directly lead out electrodes, and uses an SOI cover plate to simultaneously realize the interconnection between electrodes in the cavity, the rearrangement and sealing of the silicon through hole electrodes, and the electrical signal is convenient to lead out, and the design flexibility is high. By back-aligning etching in the small structure gap area of ​​the structural layer to reduce the thickness of the high aspect ratio area, the influence of the lag effect is effectively eliminated, and the etching of large structure gaps and small structure gaps is realized at the same time. This method breaks the limitation of the DRIE etching aspect ratio of ultra-thick structures, further reduces the size of the smallest structure gap in the ultra-thick structure, and significantly improves the driving and detection capabilities of capacitive MEMS devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A MEMS device with an ultra-thick structure and an ultra-small structure gap according to an embodiment of the present invention is shown;

[0026] Figure 2(a) to Figure 2(i) A method for processing a MEMS device with an ultra-thick structure and an ultra-small structure gap according to an embodiment of the present invention is shown; wherein,

[0027] FIG2(a) shows a first cavity 6, a support structure 7 and a dry-etched hole 8 formed by dry etching;

[0028] FIG2( b ) shows the formation of through silicon via 5 by wet etching;

[0029] FIG. 2( c ) is a silicon oxide through-hole sheet 111 ;

[0030] FIG. 2( d ) shows a second cavity 10 formed on the silicon structure layer 201 using an SOI wafer 222 ;

[0031] FIG. 2( e ) shows the silicon-silicon bonding between the SOI wafer 222 with the silicon structure layer 201 and the through silicon via 111 ;

[0032] FIG2(f) deposits a Si3N4 film 12, and removes the support layer 203 and the intermediate buffer layer 202 on the SOI wafer 222 with the silicon structure layer 201;

[0033] FIG2(g) Back-aligned photolithography is used to etch the silicon structure layer 201 to fabricate the device structure;

[0034] FIG2(h) Photolithography and etching are used to manufacture the cover plate 333 structure including the second sealing ring 36 and the second anchor point 37 structure, and to manufacture the bonding intermediate metal layer 35;

[0035] FIG2(i) bonding the cover plate 333 and the silicon structure layer 201, plating the through silicon via 5 with conductive metal, and making electrodes;

[0036] Figure 3 Another embodiment of the present invention shows a MEMS device with an ultra-thick structure and an ultra-small structure gap, wherein the top silicon layer of the cover SOI is made with a silicon conduction band;

[0037] Figure 4 A MEMS device with an ultra-thick structure and an ultra-small structure gap according to another embodiment of the present invention is shown, wherein the silicon structure layer is a MEMS device structure with a self-supporting anchor point;

[0038] Figure 5 A MEMS device with an ultra-thick structure and an ultra-small structure gap according to another embodiment of the present invention is shown, wherein the cover plate is a silicon wafer with support anchor points and a sealing ring and an oxidized surface. DETAILED DESCRIPTION

[0039] A MEMS device with an ultra-thick structure and an ultra-small structure gap that is easy to process is composed of a cover plate 333, a silicon structure layer 201 and a through silicon via sheet 111 that are bonded together.

[0040] The through silicon via sheet 111 includes: a first cavity 6, a first supporting structure 7, a through silicon via 5, an oxide layer 4 and a conductive metal 9, wherein the first cavity 6 is a square shallow cavity located in the sheet, and the side wall of the first cavity 6 is the first supporting structure 7. The through silicon via 5 includes a dry-etched hole 8 and a trapezoidal hole formed by wet etching corresponding to the position of the dry-etched hole 8. The dry-etched hole 8 is circular, square or polygonal, and the conductive metal 9 is located on the inner wall surface of the through silicon via 5.

[0041] The silicon structure layer 201 includes a thin movable structure 24, a thick movable structure 26, a first anchor point 25, a filling structure anchor point 29, an electrode 22 and a first sealing ring 21 of the MEMS device. The silicon structure layer 201 structure includes a large structure gap 27 and a small structure gap 23. The small structure gap 23 is the gap between the thin movable structure 24 and the electrode 22, and the large structure gap 27 includes the gap between the thick movable structure 26 and the first anchor point 25, the gap between the thick movable structure 26 and the filling structure anchor point 29, and the gap between the thick movable structure 26. There is a second cavity 28 in the back area of ​​the thin movable structure 24 and the small structure gap 23 in the chip. The second cavity 28 can be a square shallow cavity made by dry etching or a trapezoidal shallow cavity made by wet etching. The silicon structure layer 201 and the silicon through hole sheet 111 are connected by silicon-silicon bonding. The first anchor point 25 is located in the sheet and corresponds to the silicon through hole sheet support structure 7. The first sealing ring 21 is located at the periphery of the sheet and also corresponds to the silicon through hole sheet support structure 7. The silicon structure layer electrode 22 corresponds to the dry-etched hole 8 of the through silicon via 5 on the through silicon via sheet 111 , and the signal is directly led out through the conductive metal 9 of the through silicon via 5 on the through silicon via sheet 111 .

[0042] The SOI sheet used in the cover plate 333 includes a top silicon layer 31 bonded to the silicon structure layer 201, an intermediate buffer layer 32 and a support layer 33. The top silicon layer 31 structure of the cover plate 333 includes a second sealing ring 36 corresponding to the position of the first sealing ring 21 of the silicon structure layer 201, and a second anchor point 37 corresponding to the anchor point of the silicon structure layer 201, and is sealed by an intermediate metal layer 35 such as gold-silicon or gold-gold bonding.

[0043] In one embodiment of the present invention, the cover plate 333 SOI top silicon 31 structure optionally includes a silicon conduction band 38, a second anchor point 37 and a second sealing ring 36. The rearrangement of the through silicon vias 5 is achieved by etching the silicon conduction band 38 twice on the SOI top silicon 31. The top silicon 31 is low-resistance silicon, and generally has a resistivity of 0.001Ω·cm to 0.1Ω·cm.

[0044] In one embodiment of the present invention, the cover plate 333 may be a silicon wafer 666, and the structure includes a third anchor point 63, an oxide layer 61, and a third sealing ring 62. The third anchor point 63 and the third sealing ring 62 are etched on the silicon wafer 666, and then the oxide layer 61 is formed on the surface by thermal oxidation, and finally the intermediate metal layer 35 for bonding is made to bond and seal with the silicon structure layer 201.

[0045] The back-etched capacitor thickness is reduced, the capacitor area is reduced, but the reduced capacitor gap can bring greater driving force or capacitor detection capability.

[0046] In one embodiment of the present invention, the through silicon via sheet 111 includes a first cavity 6, a dry etching hole 8, a through silicon via 5, an oxide layer 4, a conductive metal 9, but no supporting structure 7. The silicon structure layer 444 includes a fourth small structure gap 43, a fourth large structure gap 49, a fourth sealing ring 41, a fourth anchor point 46, a fourth filling structure anchor point 50, a fourth cavity 47, a fifth cavity 45, a fourth thin movable structure 44, and a fourth thick movable structure 48.

[0047] The fourth cavity 47 is a shallow cavity formed by etching around the fourth anchor point 46 in the chip, which can be a square shallow cavity formed by dry etching or a trapezoidal shallow cavity formed by wet etching. The fifth cavity 45 is located in the corresponding area on the back of the fourth thin movable structure 44 and the fourth small structure gap 43, wherein the depth of the fourth cavity 47 is less than the depth of the fifth cavity 45.

[0048] The fourth small structure gap 43 is the gap between the fourth electrode 42 and the fourth thin movable structure 44. The fourth large structure gap 43 is the gap between the fourth thick movable structures 44, between the fourth thick movable structure 44 and the fourth filling structure anchor point 50, and between the fourth thick movable structure 44 and the fourth anchor point 46.

[0049] The SOI top silicon used for the silicon structure layer 444 is etched into the fourth cavity 47, the fourth anchor point 46 and the fifth cavity 45 through two photolithography and etching. Then, the silicon structure layer 444 is bonded to the silicon through-hole sheet 111. Then, the top silicon 401 is photolithographically etched on the non-patterned surface to make the fourth small structure gap 43 and the fourth large structure gap 49, and form the fourth sealing ring 41, the fourth anchor point 46, the fourth thin movable structure 44, the fourth filling structure anchor point 50 and the fourth thick movable structure 48. Finally, it is bonded and sealed with the cover plate 333.

[0050] A method for manufacturing the above-mentioned MEMS device structure, the method comprising the following steps:

[0051] a: Fabricating a through silicon via sheet 111. Fabricating a support structure 7 and a dry-etched hole 8 by dry etching, fabricating a through silicon via 5 by wet etching, and oxidizing the through silicon via sheet 111.

[0052] b: Make silicon structure layer 201. Deposit silicon oxide 13 on the SOI wafer with a certain thickness of top silicon 201, spin-coat photoresist 14 on the back area of ​​thin movable structure 24 and small structure gap 23, etch silicon oxide by photolithography and RIE, dry-etch or wet-etch silicon to make second cavity 28, remove silicon oxide on the surface of top silicon 201, clean, silicon-silicon bond top silicon 201 of SOI wafer to through silicon via wafer 111, remove SOI wafer support layer 203 and buffer layer 202. Make small structure gap 23 and large structure gap 27 by photolithography and etching on top silicon 201 bonded to through silicon via wafer 111, form thin movable structure 24, thick movable structure 26, bonding anchor 29, filling structure anchor 29 and electrode 22;

[0053] c: A second sealing ring 36, a second anchor point 37 and other structures are manufactured on the top silicon 31 of the cover plate 333SOI, a bonding intermediate metal layer 35 is deposited, the intermediate metal layer 35 is photolithographically etched, and the cover plate 333 and the silicon structure layer 201 are connected and sealed by intermediate metal layer bonding methods such as gold-silicon bonding and gold-gold bonding. A conductive metal 9 is plated in the through silicon hole 5 of the through silicon via sheet 111 through a hard mask to realize the lead-out of the electrode.

[0054] The silicon structure layer 201 can be made of a double-polished silicon wafer 666 of a specific thickness and temporarily bonded to a support sheet. After the second cavity 28 is fabricated by photolithography and etching, the silicon structure layer 201 is bonded to the through silicon via sheet 111 and the temporary support sheet and temporary bonding adhesive are removed.

[0055] The silicon structure layer 201 may also be a double-polished silicon wafer, which is bonded to the through silicon via sheet 111 after the second cavity 28 is made on the first side of the silicon wafer, and a silicon wafer of appropriate thickness may be obtained by thinning the silicon wafer after bonding. In this case, the surface of the silicon wafer after bonding needs to be polished to achieve a surface roughness that can achieve subsequent bonding.

[0056] The structure and method of the present invention are applicable to ultra-thick structures with a thickness ranging from 150 microns to 500 microns; and ultra-small structures with a gap ranging from 3 microns to 15 microns.

[0057] Refer to Figure 2 below and combine Figure 1 , the manufacturing method of the above-mentioned MEMS device structure is described in detail with examples.

[0058] Embodiment 1:

[0059] The fabrication of the through silicon via sheet 111 is shown in FIGS. 2( a ) to ( c ).

[0060] First, an oxide layer 11 is oxidized on a double-sided polished silicon wafer. According to the design of the MEMS device, a first cavity 6, a support structure 7 and a dry-etched hole 8 are made on one side of the silicon wafer by dry etching (see FIG. 2(a)). After that, a wet etching is performed on the other side of the silicon wafer at a position corresponding to the electrode hole 8 to form a through silicon via 5 (see FIG. 2(b)). Etching from the other side to form a through silicon via 5 has the advantages of simple process and convenience. Finally, after removing the oxide layer, the entire silicon wafer is re-oxidized to form a new oxide layer 4, and a through silicon via sheet 111 is obtained (see FIG. 2(c)).

[0061] The fabrication of the silicon structure layer 201 is shown in FIGS. 2( d ) to ( g ).

[0062] First, silicon oxide 13 is deposited on the surface of the SOI wafer with a top layer of silicon of a specific thickness by PECVD (plasma enhanced chemical vapor deposition), and then photoresist 14 is spin-coated thereon for photolithography, and the surface silicon oxide 13 is etched by RIE (reactive ion etching), and a certain thickness of silicon is dry-etched in the back area of ​​the thin movable structure 24 and the small structure gap 23 to make the second cavity 28 (see Figure 2 (d)). The surface photoresist 14 is cleaned and the deposited silicon oxide 14 is removed. The oxidized silicon through-hole wafer 111 and the SOI wafer 222 are bonded to silicon (see Figure 2 (e)), the SOI support layer is removed by dry etching, and the Si3N4 film 12 is deposited by LPCVD (low pressure chemical vapor deposition). The Si3N4 film 12 on the surface of the buffer layer 202 is etched by RIE, and the SOI wafer buffer layer 202 is wet-etched (see Figure 2 (f)). A layer of silicon oxide 13 is deposited by PECVD, a photoresist 14 is spin-coated for back-alignment lithography, and the small structure gap 23 and the large structure gap 27 are dry-etched to form a thin movable structure 24, a thick movable structure 26, a first anchor point 25, a filling structure anchor point 29, a first sealing ring 21 and an electrode 22 (see Figure 2(g)).

[0063] The silicon structure layer 201 may also be a double-polished silicon wafer, which is bonded to the through silicon via sheet 111 after the second cavity 28 is made on the first surface, and a silicon structure layer 201 of appropriate thickness may be obtained by thinning the double-polished silicon wafer after bonding. In this case, the surface of the silicon wafer needs to be polished to achieve a surface roughness that can achieve subsequent bonding.

[0064] The cover plate 333 is manufactured as shown in FIG2(h);

[0065] First, a layer of silicon oxide 13 is grown on the surface of the SOI wafer, and the top silicon 31 of the SOI wafer is photolithographically dry-etched to the buffer layer 32 of the SOI wafer to make the second sealing ring 36 and the second anchor point 37 structure, and the surface silicon oxide 13 is wet-etched to form the SOI cover plate 333. Of course, wet etching can also be selected to make electrode bonding anchor points and sealing rings on the top silicon 31 of the SOI wafer. Bonding metal is deposited, and the bonding intermediate metal layer 35 is made by photolithographic wet etching.

[0066] Bonding and in-hole metallization, as shown in Figure 2(i);

[0067] The cover plate 333 is bonded to the silicon structure layer 201, and the first sealing ring 21 of the silicon structure layer 201 is bonded to the second sealing ring 36 of the cover plate 333. Then, the Si3N4 film 12 in the through silicon via 5 is dry-etched through a hard mask. Finally, a conductive metal 9, preferably aluminum, is plated in the through silicon via 5 through a hard mask and annealed, so that the electrode of the silicon structure layer 201 is led out through the through silicon via 5.

[0068] As described above, the manufacturing of the above-mentioned MEMS device structure is completed.

[0069] Embodiment 2:

[0070] The difference between Example 2 and Example 1 is that: Figure 3 As shown, the SOI top silicon 31 structure of the cover plate 333 includes a silicon conduction band 38, a second anchor point 37 and a second sealing ring 36. The rearrangement of the through silicon vias 5 is achieved by etching the silicon conduction band 38 twice on the SOI top silicon 31. The top silicon 31 is low-resistance silicon, and generally has a resistivity of 0.001Ω·cm to 0.1Ω·cm.

[0071] Embodiment 3:

[0072] The difference between Example 3 and Example 1 is that: Figure 4 As shown, the through silicon via sheet 111 includes a first cavity 6, a dry etching hole 8, a through silicon via 5, an oxide layer 4, a conductive metal 9, but no supporting structure 7. The silicon structure layer 444 includes a fourth small structure gap 43, a fourth large structure gap 49, a fourth sealing ring 41, a fourth anchor point 46, a fourth filling structure anchor point 50, a fourth cavity 47, a fifth cavity 45, a fourth thin movable structure 44, and a fourth thick movable structure 48.

[0073] The fourth cavity 47 is a shallow cavity formed by etching around the fourth anchor point 46 in the chip, which can be a square shallow cavity formed by dry etching or a trapezoidal shallow cavity formed by wet etching. The fifth cavity 45 is located in the corresponding area on the back of the fourth thin movable structure 44 and the fourth small structure gap 43, wherein the depth of the fourth cavity 47 is less than the depth of the fifth cavity 45.

[0074] The fourth small structure gap 43 is the gap between the fourth electrode 42 and the fourth thin movable structure 44. The fourth large structure gap 43 is the gap between the fourth thick movable structures 44, between the fourth thick movable structure 44 and the fourth filling structure anchor point 50, and between the fourth thick movable structure 44 and the fourth anchor point 46.

[0075] The SOI top silicon used for the silicon structure layer 444 is etched into the fourth cavity 47, the fourth anchor point 46 and the fifth cavity 45 through two photolithography and etching. Then, the silicon structure layer 444 is bonded to the silicon through-hole sheet 111. Then, the top silicon 401 is photolithographically etched on the non-patterned surface to make the fourth small structure gap 43 and the fourth large structure gap 49, and form the fourth sealing ring 41, the fourth anchor point 46, the fourth thin movable structure 44, the fourth filling structure anchor point 50 and the fourth thick movable structure 48. Finally, it is bonded and sealed with the cover plate 333.

[0076] Embodiment 4:

[0077] The difference between Example 4 and Example 1 is that: Figure 5 As shown, the cover plate 333 may be a silicon wafer 666, and the structure includes a third anchor point 63, an oxide layer 61, and a third sealing ring 62. The third anchor point 63 and the third sealing ring 62 are etched on the silicon wafer 666, and then the oxide layer 61 is formed on the surface by thermal oxidation, and finally the intermediate metal layer 35 for bonding is made to bond and seal with the silicon structure layer 201.

[0078] The all-silicon MEMS structure device of the present invention has good temperature characteristics, uses silicon through vias to directly lead out electrodes, and uses an SOI cover plate to simultaneously realize the interconnection between electrodes in the cavity, the rearrangement and sealing of the silicon through via electrodes, and the electrical signal is convenient to lead out, and the design flexibility is high. By back-aligned etching in the small structural gap area of ​​the structural layer to reduce the thickness of the high aspect ratio area, the influence of the lag effect is effectively eliminated, and the etching of large structural gaps and small structural gaps is achieved at the same time. The all-silicon MEMS structure device has good temperature characteristics. By changing the thickness of the local structural layer, the difficulty in improving the etching aspect ratio during the processing of ultra-thick structures is solved, and the problem that the structural gap is limited by the etching aspect ratio is solved, and the size of the minimum structural gap in the ultra-thick structure is further reduced, which significantly improves the driving and detection capabilities of capacitive MEMS devices.

[0079] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims. The parts of the invention that are not described in detail belong to the common knowledge of those skilled in the art.

Claims

1. A MEMS device with ultra-thick structure and ultra-small structure gap, characterized in that: include: The cover plate (333), the silicon structure layer (201) and the through silicon via sheet (111) are formed by bonding. The through silicon via sheet (111) comprises: a first cavity (6), a first supporting structure (7), a through silicon via (5), an oxide layer (4) and a conductive metal (9), wherein the first cavity (6) is a square shallow cavity located in the sheet, the side wall of the first cavity (6) is the first supporting structure (7), the through silicon via (5) comprises a dry etching hole (8) and a trapezoidal hole formed by wet etching corresponding to the position of the dry etching hole (8), the dry etching hole (8) is circular, square or polygonal, and the conductive metal (9) is located on the inner wall surface of the through silicon via (5); The silicon structure layer (201) comprises: a thin movable structure (24), a thick movable structure (26), a first anchor point (25), a filling structure anchor point (29), an electrode (22) and a first sealing ring (21) of a MEMS device; the small structure gap (23) is the gap between the thin movable structure (24) and the electrode (22); the gap between the thick movable structure (26) and the first anchor point (25), the gap between the thick movable structure (26) and the filling structure anchor point (29) and the gap between the thick movable structures (26) are all large structure gaps (27); the back area of ​​the thin movable structure (24) and the small structure gap (23) in the chip has a first anchor point (25), a filling structure anchor point (29), an electrode (22) and a first sealing ring (21); the small structure gap (23) is the gap between the thin movable structure (24) and the electrode (22); the gap between the thick movable structure (26) and the first anchor point (25), the gap between the thick movable structure (26) and the filling structure anchor point (29) and the gap between the thick movable structures (26) are all large structure gaps (27); the back area of ​​the thin movable structure (24) and the small structure gap (23) in the chip has a first anchor point (25), a filling structure anchor point (29) and a filling structure anchor point (29) Two cavities (28), the second cavity (28) is a square shallow cavity made by dry etching or a trapezoidal shallow cavity made by wet etching, the silicon structure layer (201) and the through silicon via sheet (111) are connected by silicon-silicon bonding, the first anchor point (25) is located inside the sheet and corresponds to the support structure (7) of the through silicon via sheet (111), the first sealing ring (21) is located outside the sheet and also corresponds to the support structure (7) of the through silicon via sheet (111), the silicon structure layer electrode (22) corresponds to the dry etching hole (8) of the through silicon via (5) on the through silicon via sheet (111), and the signal is directly led out through the conductive metal (9) of the through silicon via (5) on the through silicon via sheet (111); The SOI sheet used for the cover plate (333) comprises a top silicon layer (31) bonded to the silicon structure layer (201), an intermediate buffer layer (32) and a support layer (33); the top silicon layer (31) structure of the cover plate (333) comprises a second sealing ring (36) corresponding to the position of the first sealing ring (21) of the silicon structure layer (201), and a second anchor point (37) corresponding to the anchor point of the silicon structure layer (201); the cover plate (333) and the silicon structure layer (201) are sealed by bonding via an intermediate metal layer (35).

2. The MEMS device with ultra-thick structure and ultra-small structure gap according to claim 1, characterized in that: The SOI top silicon (31) structure of the cover plate (333) further includes: a silicon conduction band (38), the silicon conduction band (38) connects the second anchor point (37) to the electrode (22), the silicon conduction band (38) is formed by etching twice on the SOI top silicon (31), the silicon conduction band (38) is used to reduce the number and arrangement of silicon through vias (5), and the top silicon (31) is low-resistance silicon with a resistivity of 0.001Ω·cm to 0.1Ω·cm.

3. The MEMS device with ultra-thick structure and ultra-small structure gap according to claim 1, characterized in that: The cover plate (333) is a silicon wafer (666). The structure of the cover plate (333) includes a third anchor point (63), an oxide layer (61) and a third sealing ring (62). The third anchor point (63) and the third sealing ring (62) are etched from the silicon wafer (666), and then the oxide layer (61) is formed on the surface by thermal oxidation. Finally, an intermediate metal layer (35) for bonding is made to bond and seal with the silicon structure layer (201).

4. The MEMS device with ultra-thick structure and ultra-small structure gap according to claim 2, characterized in that: The through silicon via sheet (111) comprises: a first cavity (6), a through silicon via (5), an oxide layer (4), and a conductive metal (9); the through silicon via (5) comprises a dry etching hole (8) and a trapezoidal hole formed by wet etching corresponding to the position of the dry etching hole (8); the silicon structure layer (444) comprises a fourth sealing ring (41), a fourth anchor point (46), a fourth filling structure anchor point (50), a fourth cavity (47), a fifth cavity (45), a fourth thin movable structure (44), and a fourth thick movable structure (48), wherein: The fourth cavity (47) is a shallow cavity formed by etching around the fourth anchor point (46) in the chip, and is a square shallow cavity formed by dry etching or a trapezoidal shallow cavity formed by wet etching. The fifth cavity (45) is located in the corresponding area on the back side of the fourth thin movable structure (44) and the fourth small structure gap (43), wherein the depth of the fourth cavity (47) is less than the depth of the fifth cavity (45); The fourth small structural gap (43) is the gap between the fourth electrode (42) and the fourth thin movable structure (44), and the fourth large structural gap (43) is the gap between the fourth thick movable structure (44), between the fourth thick movable structure (44) and the fourth filling structure anchor point (50), and between the fourth thick movable structure (44) and the fourth anchor point (46).

5. The MEMS device with ultra-thick structure and ultra-small structure gap according to claim 4, characterized in that: The SOI top silicon used for the silicon structure layer (444) is etched into a fourth cavity (47), a fourth anchor point (46) and a fifth cavity (45) through two times of photolithography and etching; then the silicon structure layer (444) is silicon-silicon bonded to the through silicon via sheet (111); Then, the non-patterned surface of the top silicon (401) is photolithographically etched to form a fourth small structure gap (43) and a fourth large structure gap (49), to form a fourth sealing ring (41), a fourth anchor point (46), a fourth thin movable structure (44), a fourth filling structure anchor point (50) and a fourth thick movable structure (48), and finally bonded and sealed with the cover plate (333).

6. A method for manufacturing the MEMS device according to claim 1, characterized in that: The following steps are involved: (a) manufacturing a through silicon via sheet (111), manufacturing a support structure (7) and a dry etching hole (8) by dry etching, manufacturing a through silicon via (5) by wet etching, and then oxidizing the through silicon via sheet (111); (b) manufacturing a silicon structure layer (201), depositing silicon oxide (13) on a SOI wafer with a top silicon layer (201) of a certain thickness, spin-coating a photoresist (14) on the back area of ​​the thin movable structure (24) and the small structure gap (23), etching the silicon oxide by photolithography and RIE, dry etching or wet etching silicon to manufacture a second cavity (28), removing the silicon oxide on the surface of the top silicon layer (201), cleaning, silicon-silicon bonding the top silicon layer (201) of the SOI wafer to the through silicon via wafer (111), removing the SOI wafer support layer (203) and the buffer layer (202); photolithography and etching on the top silicon layer (201) bonded to the through silicon via wafer (111) to manufacture a small structure gap (23) and a large structure gap (27), forming a thin movable structure (24), a thick movable structure (26), a bonding anchor point (29), a filling structure anchor point (29) and an electrode (22); (c) manufacturing a second sealing ring (36) and a second anchor point (37) structure on the top silicon layer (31) of the cover plate (333) SOI, depositing a bonding intermediate metal layer (35), photolithography and etching the intermediate metal layer (35), using a gold-silicon bonding or gold-gold bonding intermediate metal layer bonding method to achieve connection and sealing between the cover plate (333) and the silicon structure layer (201), and plating a conductive metal (9) in the silicon through hole (5) of the silicon through hole sheet (111) through a hard mask to achieve electrode extraction.

7. The method according to claim 6, characterized in that The silicon structure layer (201) uses a double-polished silicon wafer (666), and the double-polished silicon wafer (666) is temporarily bonded to a support sheet. After the second cavity (28) is produced by photolithography and etching, the silicon structure layer (201) is silicon-silicon bonded to a through silicon via sheet (111), and then the temporary support sheet and the temporary bonding adhesive are removed.

8. The method according to claim 6, characterized in that The silicon structural layer (201) is a double-polished silicon wafer. After the second cavity (28) is fabricated on the first side of the silicon wafer, it is bonded to the through silicon via sheet (111). After bonding, the silicon wafer is thinned to obtain a silicon wafer of appropriate thickness, and then the second side is fabricated.

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