MEMS Optimized Process for a Wide Temperature Range Silicon Pressure Sensor Chip

Abstract

This invention discloses a MEMS optimized process for a wide-temperature-range silicon pressure sensor chip, comprising forming a honeycomb-shaped stress buffer cavity on a double-sided polished silicon wafer, generating a bilayer composite film on the surface of the top silicon layer of the SOI wafer, and then bonding them to form a heterostructure; on the surface of the top silicon layer of the SOI wafer, a depth-direction doping concentration gradient is formed by a three-stage variable-angle ion implantation process, and a temperature compensation electrode is fabricated by electron beam lithography to construct a gradient-doped piezoresistive network, a corrugated SiON dielectric layer is grown on the surface, tapered vias are etched, and copper metal is filled using a pulse electroplating process to achieve internal interconnection, forming a metal interconnect structure; and gradient SiN is sequentially deposited on its surface. X A thin film is used to coat the surface of a heterogeneous structure with Au / Sn eutectic solder. A miniature Pt temperature sensor is integrated into the package cavity and coated with a polysilazane composite protective layer. This effectively improves the performance stability and reliability of the chip over a wide temperature range, and adapts it to complex high and low temperature environments.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, and in particular to a MEMS optimized process for a wide-temperature-range silicon pressure sensor chip. Background Technology

[0002] Wide-temperature-range silicon pressure sensor chips have important applications in aerospace, automotive electronics, deep-sea exploration, and industrial automation. These fields typically face extreme temperature environments (e.g., -60℃ to 220℃), placing extremely high demands on the temperature stability, accuracy, and reliability of the sensors. However, traditional pressure sensor chips are susceptible to thermal stress in wide-temperature environments, leading to decreased measurement accuracy, increased hysteresis errors, and even structural failure, making it difficult to meet the long-term stable operation requirements under extreme conditions.

[0003] In existing technologies, traditional silicon pressure sensor chips mostly employ uniformly doped piezoresistive structures and single-material bonding processes, which have significant drawbacks in wide-temperature environments: First, the temperature coefficient matching of uniformly doped piezoresistive networks is poor, leading to severe temperature drift; second, stress concentration easily occurs at the single-material bonding interface during thermal cycling, causing structural cracking or performance degradation; in addition, traditional packaging processes have insufficient buffering capacity for thermal stress and are difficult to adapt to extreme temperature changes. These defects severely limit the application performance of traditional pressure sensor chips in wide-temperature environments.

[0004] Therefore, it is necessary to improve the process technology of silicon pressure sensor chips in the existing technology to solve the technical problem of poor performance in a wide temperature range. Summary of the Invention

[0005] The purpose of this invention is to provide a MEMS optimized process for a wide-temperature-range silicon pressure sensor chip, thereby solving the above-mentioned technical problems.

[0006] To achieve this objective, the present invention adopts the following technical solution:

[0007] A MEMS optimized process for a wide-temperature-range silicon pressure sensor chip includes:

[0008] Step S1: A honeycomb stress buffer cavity is formed on a double-sided polished silicon wafer using deep reactive ion etching technology. A SiO2 / SiN double-layer composite film is generated on the top silicon layer surface of the SOI wafer by thermal oxidation. Then, the SOI wafer and the silicon wafer are bonded using an argon plasma activation bonding process to form a heterostructure with matching thermal expansion coefficients.

[0009] Step S2: On the surface of the top silicon layer of the SOI wafer, a depth-direction doping concentration gradient of 5×10¹ is formed by a three-stage variable-angle ion implantation process. 8 ~2×10¹ 9cm⁻³, after implantation, local lattice repair was performed using laser annealing technology, and Cr / Pt / Au composite temperature compensation electrodes were fabricated using electron beam lithography to construct a gradient-doped piezoresistive network;

[0010] Step S3: A corrugated SiON dielectric layer is grown on the surface of the piezoresistive network. Tapered vias are prepared by dry etching and filled with copper metal by pulse electroplating to achieve internal interconnection and form a metal interconnect structure.

[0011] Step S4: Sequentially deposit gradient SiN on the surface of the metal interconnect structure. x Thin films are subjected to ultraviolet laser-induced crystallization processes to control film stress and form nanocrack buffer structures.

[0012] Step S5: Coat the surface of the heterostructure with Au / Sn eutectic solder, use a sealed encapsulation cavity, integrate a miniature Pt temperature sensor in the encapsulation cavity, and coat its surface with a polysilazane composite protective layer to obtain a wide temperature range silicon pressure sensor chip.

[0013] Optionally, step S1 specifically includes:

[0014] Step S11: Provide a double-sided polished silicon wafer with a thickness of 300 μm, and spin-coat a photoresist layer on the surface of the silicon wafer;

[0015] Step S12: The resist layer is processed using ultraviolet lithography to form a honeycomb pattern mask, wherein the ultraviolet wavelength is 365nm and the exposure dose is 200mJ / cm².

[0016] Step S13: A honeycomb-shaped stress buffer cavity is formed on the silicon wafer by deep reactive ion etching process. The stress buffer cavity has a pore size of 5 μm, a depth of 75 μm, and an aspect ratio of 15:1.

[0017] Step S14: After etching is completed, the residual photoresist on the honeycomb pattern mask is removed using an oxygen plasma photoresist removal process.

[0018] Optionally, step S14 may be followed by:

[0019] Step S15: Provide an SOI wafer and perform thermal oxidation treatment on the top silicon layer surface of the SOI wafer at a temperature of 1000℃, an oxygen flow rate of 2L / min, and a treatment time of 2h to generate a SiO2 layer.

[0020] Step S16: A SiN layer is deposited on the surface of the SiO2 layer using low-pressure chemical vapor deposition technology to form a SiO2 / SiN bilayer composite film.

[0021] Step S17: Place the silicon wafer and SOI wafer in a plasma cleaning chamber, introduce argon gas, and activate the bonding surface using radio frequency plasma.

[0022] In step S18, the activated silicon wafer and SOI wafer are aligned and bonded in a bonding machine, and a pressure of 5kN is applied while maintaining a temperature of 200°C to form a heterostructure with a matching coefficient of thermal expansion.

[0023] Optionally, step S2 specifically includes:

[0024] Step S21: Spin-coat photoresist onto the top silicon layer surface of the SOI wafer and form a piezoresistive network pattern mask using electron beam lithography; etch shallow trench structures on the top silicon layer surface using reactive ion etching process to serve as a mask layer for ion implantation.

[0025] Step S22: A tilted ion implantation process is used, wherein the tilted ions are B⁺ ions, the energy is 30 keV, and the dose is 5 × 10¹. 4 cm⁻², tilt angle 7°; boron ions are implanted on the surface of the top silicon layer to form a first doped region with a depth of 100 nm and a doping concentration of 5 × 10¹. 8 cm⁻³, after implantation, preliminary lattice repair was performed using a rapid thermal annealing process;

[0026] Step S23: Adjust the tilt angle of the B⁺ ion implantation to 15° to perform a second implantation, forming a second doped region with a doping depth of 250 nm and a doping concentration of 1 × 10¹. 9 cm⁻³, after injection, rapid thermal annealing is performed again for secondary lattice repair;

[0027] Step S24: Further adjust the tilt angle of B⁺ ion implantation to 25° for a second implantation, forming a third doped region with a doping depth of 400 nm and a doping concentration of 2 × 10¹. 9 cm⁻³; after implantation, laser annealing is performed to form a gradient-doped piezoresistive network.

[0028] Optionally, after step S24, the method further includes:

[0029] Step S25: Spin-coat photoresist onto the surface of the top silicon layer and form an electrode pattern using electron beam lithography; deposit a Cr / Pt / Au composite metal layer sequentially using magnetron sputtering and remove excess metal using a lift-off process to form a temperature compensation electrode; wherein the thickness of Cr is 20 nm, the thickness of Pt is 100 nm, and the thickness of Au is 50 nm.

[0030] Step S26: A SiN passivation layer is deposited on the surface of the piezoresistive network and the temperature compensation electrode at a deposition temperature of 400°C and an NH3 / SiH2Cl2 gas flow rate ratio of 4:1. Then, surface passivation is completed using plasma-enhanced chemical vapor deposition technology.

[0031] Optionally, step S3 specifically includes:

[0032] Step S31: On the surface of the piezoresistive network and the temperature compensation electrode, a corrugated SiON dielectric layer is grown using plasma-enhanced chemical vapor deposition at a deposition temperature of 300°C.

[0033] Step S32: Spin-coat photoresist onto the surface of the corrugated SiON dielectric layer, and form a via pattern mask using ultraviolet lithography; then etch a tapered via using reactive ion etching.

[0034] Step S33: Remove the residual photoresist in the tapered through-hole using an oxygen plasma photoresist removal process, with a power of 300W and a time of 3 minutes.

[0035] Step S34: On the inner wall of the tapered through hole and the surface of the corrugated SiON dielectric layer, a TiN diffusion barrier layer is deposited using atomic layer deposition (ALD) technology; wherein, ALD and TiN are used as precursors, the deposition temperature is 250℃, and the number of cycles is 50.

[0036] Step S35: In the tapered through hole and on the surface of the corrugated SiON dielectric layer, copper metal is filled by pulse electroplating to form a metal interconnect structure; after electroplating, excess copper layer is removed by chemical mechanical polishing to achieve surface treatment.

[0037] Optionally, step S4 specifically includes:

[0038] Step S41: On the surface of the metal interconnect structure, gradient SiN is deposited using plasma-enhanced chemical vapor deposition. x A thin film, wherein the stress of the thin film varies from -500MPa to +200MPa, the total thickness is 1μm, and the deposition temperature is 350℃;

[0039] Step S42, using ultraviolet laser to treat the gradient SiN x Local crystallization treatment is performed on the thin film to regulate the stress distribution and form a stress buffer region.

[0040] Step S43, by controlling the laser scanning path and power density, in the gradient SiN x Nanocracks are induced on the surface of the thin film, and the nanocracks are distributed in a network to release thermal stress.

[0041] Step S44: The gradient SiN is cleaned using an ultrasonic cleaning process.x The film surface is treated to remove particulate contaminants;

[0042] Step S45: On the surface of the nanocrack buffer structure, Al2O is deposited using atomic layer deposition technology. x Transition layer; wherein ALD and Al2O3 are used as precursors, the deposition temperature is 200℃, and the number of cycles is 30.

[0043] Optionally, step S5 specifically includes:

[0044] Step S51: On the surface of the heterostructure, Au / Sn eutectic solder is coated using a screen printing process. The solder composition is Au-20wt%Sn. After coating, the organic solvent is removed by a pre-baking process.

[0045] Step S52: Provide a transparent PC board and two transparent pressure-sensitive adhesive layers, attach the transparent pressure-sensitive adhesive layers to the two end faces of the transparent PC board respectively, and align the heterostructure as a whole with the transparent PC board in a bonding machine;

[0046] Step S53: At room temperature, the heterogeneous structure and the transparent PC board are pre-pressed together using a cold pressing process to achieve initial bonding of the interface.

[0047] Optionally, after step S53, the method further includes:

[0048] Step S54: Place the pre-pressed structure in a reflow oven and perform reflow bonding in a nitrogen atmosphere to melt the Au / Sn eutectic solder and form a sealed cavity.

[0049] Step S55: A miniature Pt temperature sensor is integrated into the sealed cavity, and the temperature sensor is connected to an external circuit by gold wire bonding.

[0050] Step S56: On the surface of the sealed cavity, a polysilazane composite protective layer is coated using a spin coating process, followed by curing to form a surface protective layer with a matching coefficient of thermal expansion.

[0051] Compared with existing technologies, this invention has the following advantages: First, a honeycomb-shaped stress buffer cavity is etched on a silicon wafer, and a SiO2 / SiN composite film is generated on the SOI wafer surface. This film is then bonded using argon plasma activation to form a heterostructure with matched thermal expansion coefficients. Subsequently, a gradient-doped piezoresistive network is constructed on the top silicon layer surface of the SOI wafer through variable-angle ion implantation and laser annealing, and a Cr / Pt / Au temperature compensation electrode is fabricated. Next, a corrugated SiON dielectric layer is grown on the piezoresistive network surface, and tapered vias are fabricated. Copper metal is then filled using pulse electroplating to form an interconnect structure. Finally, gradient SiN is deposited. xThe thin film is crystallized by ultraviolet laser to form a nanocrack buffer layer; finally, Au / Sn eutectic solder is coated on the surface of the heterostructure, and a miniature Pt temperature sensor is integrated using wafer-level packaging technology. A polysilazane protective layer is then coated to complete the fabrication of a wide-temperature-range silicon pressure sensor chip. This process effectively improves the performance stability and temperature change resistance of the chip in a wide temperature range by adopting an innovative design of a heterostructure with matched thermal expansion coefficients, a gradient doped piezoresistive network, and a nanocrack buffer layer, thus adapting to complex high-temperature and low-temperature environmental conditions. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0054] Figure 1 This is one of the flowcharts illustrating the MEMS optimized process for the wide-temperature-range silicon pressure sensor chip in this embodiment.

[0055] Figure 2 This is the second flowchart illustrating the MEMS optimized process for the wide-temperature-range silicon pressure sensor chip in this embodiment.

[0056] Figure 3 This is the third flowchart illustrating the MEMS optimized process for the wide-temperature-range silicon pressure sensor chip in this embodiment. Detailed Implementation

[0057] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0058] In the description of this invention, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the connection.

[0059] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0060] Example 1:

[0061] Combination Figures 1 to 3 As shown, this embodiment of the invention provides a MEMS optimized process for a wide-temperature-range silicon pressure sensor chip, including:

[0062] Step S1: A honeycomb stress buffer cavity is formed on a double-sided polished silicon wafer using deep reactive ion etching technology. A SiO2 / SiN double-layer composite film is generated on the top silicon layer surface of the SOI wafer by thermal oxidation. Then, the SOI wafer and the silicon wafer are bonded using an argon plasma activation bonding process to form a heterostructure with matching thermal expansion coefficients.

[0063] Step S2: On the surface of the top silicon layer of the SOI wafer, a depth-direction doping concentration gradient of 5×10¹ is formed by a three-stage variable-angle ion implantation process. 8 ~2×10¹ 9 cm⁻³, after implantation, local lattice repair was performed using laser annealing technology, and Cr / Pt / Au composite temperature compensation electrodes were fabricated using electron beam lithography to construct a gradient-doped piezoresistive network;

[0064] Constructing a gradient-doped piezoresistive network: On the surface of the top silicon layer of the SOI wafer, a depth-direction doping concentration gradient (5×10¹) is formed through a three-stage variable-angle ion implantation process (B⁺ ion energy 30 / 50 / 80keV). 8 ~2×10¹ 9 After implantation, local lattice repair was performed using laser annealing technology (wavelength 532nm, power density 20kW / cm²), and a Cr / Pt / Au composite temperature compensation electrode (total thickness 170nm) was fabricated using electron beam lithography.

[0065] Step S3: A corrugated SiON dielectric layer is grown on the surface of the piezoresistive network. Tapered vias are prepared by dry etching and filled with copper metal by pulse electroplating to achieve internal interconnection, forming a metal interconnect structure.

[0066] Step S4: Sequentially deposit gradient SiN on the surface of the metal interconnect structure. x Thin films are subjected to ultraviolet laser-induced crystallization to control film stress and form nanocrack buffer structures.

[0067] Step S5: Coat the surface of the heterostructure with Au / Sn eutectic solder, use a sealed encapsulation cavity, integrate a miniature Pt temperature sensor in the encapsulation cavity, and coat its surface with a polysilazane composite protective layer to obtain a wide temperature range silicon pressure sensor chip.

[0068] Implement temperature self-compensating packaging: Coat the wafer surface with Au / Sn eutectic solder (10μm thick), use wafer-level packaging process (reflow temperature 320℃) to form a sealed cavity, and integrate a miniature Pt temperature sensor (size 50×50μm²) in the package cavity. Finally, coat the surface with a polysilazane composite protective layer (5μm thick, coefficient of thermal expansion 3.2ppm / ℃).

[0069] The working principle of this invention is as follows: First, a honeycomb-shaped stress buffer cavity is etched on a silicon wafer, and a SiO2 / SiN composite film is generated on the surface of the SOI wafer. This film is then bonded using argon plasma activation to form a heterostructure with matched thermal expansion coefficients. Subsequently, a gradient-doped piezoresistive network is constructed on the surface of the top silicon layer of the SOI wafer through variable-angle ion implantation and laser annealing, and a Cr / Pt / Au temperature compensation electrode is fabricated. Next, a corrugated SiON dielectric layer is grown on the surface of the piezoresistive network, and tapered vias are fabricated. Copper is then filled using pulse electroplating to form an interconnect structure. Finally, gradient SiN is deposited. x The thin film is crystallized by ultraviolet laser to form a nanocrack buffer layer; finally, Au / Sn eutectic solder is coated on the surface of the heterostructure, and a miniature Pt temperature sensor is integrated using wafer-level packaging technology. A polysilazane protective layer is then coated to complete the fabrication of a wide-temperature-range silicon pressure sensor chip. This process effectively improves the performance stability and temperature change resistance of the chip in a wide temperature range by adopting an innovative design of a heterostructure with matched thermal expansion coefficients, a gradient doped piezoresistive network, and a nanocrack buffer layer, thus adapting to complex high-temperature and low-temperature environmental conditions.

[0070] In this embodiment, step S1 specifically includes:

[0071] Step S11: Provide a double-sided polished silicon wafer with a thickness of 300 μm, and spin-coat a photoresist layer on the surface of the silicon wafer.

[0072] A double-sided polished silicon wafer (300 μm thick) is provided, and a photoresist (preferably 5 μm thick) is spin-coated onto the surface of the silicon wafer.

[0073] Step S12: The resist layer is processed using ultraviolet lithography to form a honeycomb pattern mask, wherein the ultraviolet wavelength is 365nm and the exposure dose is 200mJ / cm².

[0074] Step S13: A honeycomb stress buffer cavity is formed on the silicon wafer by deep reactive ion etching process. The stress buffer cavity has a pore size of 5 μm, a depth of 75 μm, and an aspect ratio of 15:1.

[0075] A honeycomb-shaped stress buffer cavity was etched on a silicon wafer using a deep reactive ion etching process (DRIE, SF6 / C4F8 gas flow ratio 3:1, RF power 800W, etching rate 5μm / min).

[0076] Step S14: After etching is completed, the residual photoresist on the honeycomb pattern mask is removed using an oxygen plasma photoresist removal process.

[0077] After etching, residual photoresist is removed using an oxygen plasma stripping process (300W power, 5min time).

[0078] Step S15: Provide an SOI wafer and perform thermal oxidation treatment on the surface of the top silicon layer of the SOI wafer at a temperature of 1000℃, an oxygen flow rate of 2L / min, and a treatment time of 2h to generate a SiO2 layer.

[0079] An SOI wafer (top silicon layer thickness 10μm, buried oxide layer thickness 1μm) is provided, and a SiO2 layer (thickness 500nm) is generated by thermal oxidation treatment on the surface of the top silicon layer of the SOI wafer (temperature 1000℃, oxygen flow rate 2L / min, time 2h).

[0080] Step S16: A SiN layer is deposited on the surface of the SiO2 layer using low-pressure chemical vapor deposition technology to form a SiO2 / SiN bilayer composite film.

[0081] Subsequently, a SiN layer (200 nm thick) was deposited on the surface of the SiO2 layer using low-pressure chemical vapor deposition (LPCVD, temperature 780℃, NH3 / SiH2Cl2 gas flow ratio 5:1, pressure 200 mTorr), forming a SiO2 / SiN bilayer composite film (total thickness 700 nm).

[0082] Step S17: Place the silicon wafer and SOI wafer in a plasma cleaning chamber, respectively, introduce argon gas, and use radio frequency plasma to activate the bonding surface.

[0083] Argon plasma activation bonding: The silicon wafer and SOI wafer are placed in a plasma cleaning chamber, and argon gas (flow rate 50 sccm, pressure 50 mTorr) is introduced. Radio frequency plasma (power 100W, time 30s) is used to activate the bonding surface.

[0084] In step S18, the activated silicon wafer and SOI wafer are aligned and bonded in a bonding machine, and a pressure of 5kN is applied while maintaining a temperature of 200°C to form a heterostructure with a matching coefficient of thermal expansion.

[0085] The activated silicon wafer and SOI wafer are aligned and bonded in a bonding machine, and a pressure of 5kN is applied while maintaining a temperature of 200°C to form a heterogeneous structure with matching coefficients of thermal expansion. Preferably, after bonding, the wafer is annealed in a nitrogen atmosphere (temperature 400°C, time 2h) to enhance the bonding interface strength.

[0086] Argon plasma activation bonding process, including plasma cleaning, alignment and bonding, bonding pressure and annealing, ensures the matching of thermal expansion coefficients and interface strength of heterostructures.

[0087] In this embodiment, step S2 specifically includes:

[0088] Step S21: Spin-coat photoresist on the top silicon layer surface of the SOI wafer and form a piezoresistive network pattern mask using electron beam lithography; etch shallow trench structures on the top silicon layer surface using reactive ion etching process to serve as a mask layer for ion implantation.

[0089] Photoresist (2 μm thick) was spin-coated onto the top silicon layer of the SOI wafer, and a piezoresistive network pattern mask was formed using electron beam lithography (accelerating voltage 100 kV, exposure dose 500 μC / cm²). Shallow trench structures (200 nm deep) were etched on the top silicon layer surface using reactive ion etching (RIE, CF4 gas flow rate 50 sccm, RF power 300 W, time 2 min) as a mask layer for ion implantation.

[0090] The fabrication process of the ion implantation mask layer is described, including photoresist spin coating, electron beam lithography and RIE etching, and the shallow trench structure and key parameters of the mask layer are clarified.

[0091] Step S22: A tilted ion implantation process is used, with B⁺ ions as the tilted ions, energy of 30 keV, and dose of 5 × 10¹. 4 cm⁻², tilt angle 7°; boron ions are implanted on the surface of the top silicon layer to form the first doped region with a depth of 100 nm and a doping concentration of 5 × 10¹. 8 cm⁻³, after implantation, preliminary lattice repair was performed using a rapid thermal annealing process;

[0092] First variable-angle ion implantation: A tilted ion implantation process was used (B⁺ ions, energy 30 keV, dose 5 × 10¹). 4(cm⁻², tilt angle 7°), boron ions were implanted on the surface of the top silicon layer to form the first doped region (depth 100nm, doping concentration 5×10¹). 8 cm⁻³); after implantation, a rapid thermal annealing process (temperature 950℃, time 30s) was used for preliminary lattice repair.

[0093] Step S23: Adjust the tilt angle of the B⁺ ion implantation to 15° to perform a second implantation, forming a second doped region with a doping depth of 250 nm and a doping concentration of 1 × 10¹. 9 cm⁻³, after injection, rapid thermal annealing is performed again for secondary lattice repair;

[0094] Second variable-angle ion implantation: Adjust the tilt angle of the B⁺ ion implantation to 15°, using the same B⁺ ions (energy 50 keV, dose 1×10¹). 5 A second implantation is performed at a depth of 250 nm and a doping concentration of 1 × 10¹ cm⁻² to form a second doped region (depth 250 nm, doping concentration 1 × 10¹ cm⁻²). 9 cm⁻³); after injection, rapid thermal annealing is performed again (temperature 1000℃, time 20s).

[0095] Step S24: Further adjust the tilt angle of B⁺ ion implantation to 25° for a second implantation, forming a third doped region with a doping depth of 400 nm and a doping concentration of 2 × 10¹. 9 cm⁻³; after implantation, laser annealing is performed to form a gradient-doped piezoresistive network;

[0096] Third variable-angle ion implantation: The ion implantation angle was further adjusted to 25°, using B⁺ ions (energy 80keV, dose 2×10¹). 5 A third implantation was performed at a depth of 400 nm and a doping concentration of 2 × 10¹ cm⁻² to form the third doped region (depth 400 nm, doping concentration 2 × 10¹ cm⁻²). 9 cm⁻³); after implantation, laser annealing is performed (wavelength 532nm, power density 20kW / cm², pulse width 10ns); ion implantation is performed in three stages with varying angles to gradually form a gradient doping concentration distribution. Annealing is performed after each implantation to repair lattice damage and ensure the electrical performance of the doped region.

[0097] Step S25: Spin-coat photoresist on the surface of the top silicon layer and form an electrode pattern using electron beam lithography; deposit a Cr / Pt / Au composite metal layer sequentially by magnetron sputtering and remove excess metal by a lift-off process to form a temperature compensation electrode; wherein the thickness of Cr is 20nm, the thickness of Pt is 100nm, and the thickness of Au is 50nm.

[0098] Fabrication of temperature compensation electrodes: Photoresist (1.5 μm thick) was spin-coated onto the surface of the top silicon layer, and electrode patterns were formed using electron beam lithography (accelerating voltage 100 kV, exposure dose 300 μC / cm²). Cr / Pt / Au composite metal layers (thicknesses of 20 nm, 100 nm, and 50 nm, respectively) were sequentially deposited using magnetron sputtering (Ar gas flow rate 20 sccm, power 200 W, time 10 min), and excess metal was removed by a lift-off process to form the temperature compensation electrodes. The fabrication process of the temperature compensation electrodes, including photoresist spin-coating, electron beam lithography, magnetron sputtering, and lift-off processes, clearly defined the electrode materials and thicknesses.

[0099] Step S26: A SiN passivation layer is deposited on the surface of the piezoresistive network and the temperature compensation electrode at a deposition temperature of 400℃ and an NH3 / SiH2Cl2 gas flow rate ratio of 4:1. Then, surface passivation is completed using plasma-enhanced chemical vapor deposition technology.

[0100] Surface passivation treatment: A SiN passivation layer (100 nm thick, 400 °C deposition temperature, NH3 / SiH2Cl2 gas flow ratio of 4:1) is deposited on the surface of the piezoresistive network and temperature compensation electrode. Surface passivation is completed using plasma-enhanced chemical vapor deposition (PECVD, 150 W RF power, 300 mTorr pressure) to ensure device stability.

[0101] In this embodiment, step S3 specifically includes:

[0102] Step S31: A corrugated SiON dielectric layer is grown on the surface of the piezoresistive network and the temperature compensation electrode using plasma-enhanced chemical vapor deposition at a deposition temperature of 300°C.

[0103] Growth of a corrugated SiON dielectric layer: A corrugated SiON dielectric layer (1 μm thickness, 200 nm corrugation amplitude, and 5 μm period) was grown on the surface of a piezoresistive network and a temperature-compensated electrode using plasma-enhanced chemical vapor deposition (PECVD, SiH4 / N2O / NH3 gas flow ratio 1:2:1, RF power 200 W, pressure 400 mTorr) at a deposition temperature of 300 °C. The growth process of the corrugated SiON dielectric layer is described, including PECVD process parameters and key dimensions of the corrugated structure (amplitude and period).

[0104] Step S32: Spin-coat photoresist onto the surface of the corrugated SiON dielectric layer, and form a via pattern mask using ultraviolet lithography; then etch a tapered via using reactive ion etching.

[0105] Photoresist (3 μm thick) was spin-coated onto the surface of a corrugated SiON dielectric layer, and a via pattern mask was formed using ultraviolet lithography (wavelength 365 nm, exposure dose 250 mJ / cm²). Tapered vias (top diameter 2 μm, bottom diameter 1 μm, aspect ratio 5:1) were etched using reactive ion etching (RIE, CF4 / O2 gas flow ratio 4:1, RF power 350 W, time 5 min). The fabrication process of the tapered vias was explained, including photoresist spin-coating, ultraviolet lithography, RIE etching, and photoresist removal, and the geometric parameters of the vias were clarified.

[0106] Step S33: Remove residual photoresist in the tapered via using an oxygen plasma photoresist removal process, power 300W, time 3min;

[0107] Oxygen plasma stripping process (300W power, 3min time) is used to remove residual photoresist in tapered vias to ensure the cleanliness of the via inner wall;

[0108] Step S34: A TiN diffusion barrier layer is deposited on the inner wall of the tapered through-hole and the surface of the corrugated SiON dielectric layer using atomic layer deposition technology; wherein, ALD and TiN are used as precursors, the deposition temperature is 250℃, and the number of cycles is 50.

[0109] A TiN diffusion barrier layer (20 nm thick) is deposited on the inner wall of the tapered via and the surface of the corrugated SiON dielectric layer using atomic layer deposition (ALD, TiN precursor, deposition temperature 250℃, 50 cycles) to prevent subsequent copper interconnect diffusion. The TiN diffusion barrier layer is deposited using ALD technology to prevent copper interconnect diffusion and ensure device reliability.

[0110] Step S35: Copper metal is filled into the tapered through hole and the surface of the corrugated SiON dielectric layer using a pulse electroplating process to form a metal interconnect structure; after electroplating, excess copper layer on the surface is removed by chemical mechanical polishing to achieve surface treatment.

[0111] Pulse electroplating for copper filling: Copper is filled into the tapered vias and the surface of the corrugated SiON dielectric layer using a pulse electroplating process (alternating current density 0.5-2 A / dm², frequency 10 Hz, electroplating solution temperature 25 ℃) to form a metal interconnect structure. After electroplating, excess copper layer is removed by chemical mechanical polishing (CMP, polishing solution pH 4.0, pressure 3 psi, time 2 min) to achieve planarization. The use of pulse electroplating for copper filling and CMP for surface planarization ensures the conductivity and surface quality of the interconnect structure.

[0112] The copper interconnect structure was then annealed in a nitrogen atmosphere (400°C, 1 hour) to enhance the density and conductivity of the copper metal and reduce the interface resistance.

[0113] In this embodiment, step S4 specifically includes:

[0114] Step S41: Deposit gradient SiN on the surface of the metal interconnect structure using plasma-enhanced chemical vapor deposition. x The thin film has a stress gradient from -500MPa to +200MPa, a total thickness of 1μm, and a deposition temperature of 350℃.

[0115] Deposition gradient SiN x Thin film: Gradient SiN was deposited on the surface of the metal interconnect structure using plasma-enhanced chemical vapor deposition (PECVD, SiH4 / NH3 / N2 gas flow ratio 1:2:3, RF power 250W, pressure 300mTorr). x Thin films with stress gradients from -500 MPa to +200 MPa, a total thickness of 1 μm, and a deposition temperature of 350 °C were described; gradient SiN was described. x The thin film deposition process, including PECVD process parameters and stress gradient design, ensures the stress buffering performance of the thin film.

[0116] Step S42, using ultraviolet laser to treat gradient SiN x Local crystallization treatment is performed on the thin film to regulate the stress distribution and form a stress buffer region.

[0117] Ultraviolet laser (wavelength 355nm, power density 50mJ / cm², scanning speed 1mm / s) was used to scan gradient SiN. x The thin film undergoes localized crystallization treatment to regulate the stress distribution and form a stress buffer region.

[0118] Step S43, by controlling the laser scanning path and power density, in gradient SiN x Nanocracks are induced on the surface of the thin film, and the nanocracks are distributed in a network to release thermal stress.

[0119] Fabrication of nanocrack buffer structures: By controlling the laser scanning path and power density, gradient SiN... x Nanocracks (crack density 50 cracks / μm, single crack length <200nm) were induced on the thin film surface. The nanocracks were distributed in a network to release thermomechanical stress. By inducing crystallization and nanocrack generation through ultraviolet laser, a stress buffer structure was formed, and the laser parameters and crack distribution characteristics were clarified.

[0120] Step S44: Use ultrasonic cleaning process to clean gradient SiN x The film surface is treated to remove particulate contaminants;

[0121] Graded SiN was removed using an ultrasonic cleaning process (deionized water, frequency 40kHz, power 100W, time 5min). x Particulate contaminants on the film surface are eliminated to ensure surface cleanliness.

[0122] Step S45: Al2O3 is deposited on the surface of the nanocrack buffer structure using atomic layer deposition (ALD) technology. x Transition layer; wherein ALD and Al2O3 are used as precursors, the deposition temperature is 200℃, and the number of cycles is 30.

[0123] On the surface of the nanocrack buffer structure, Al2O3 was deposited using atomic layer deposition (ALD, Al2O3 precursor, deposition temperature 200℃, 30 cycles). x A transition layer (50nm thick) is used to enhance the adhesion of the subsequent passivation layer.

[0124] Then, annealing is performed on gradient SiN under a nitrogen atmosphere. x Thin film and Al2O x The transition layer is annealed (temperature 450℃, time 1h) to stabilize the stress distribution of the film and improve the interfacial bonding strength.

[0125] In this embodiment, step S5 specifically includes:

[0126] Step S51: On the surface of the heterogeneous structure, Au / Sn eutectic solder is coated using a screen printing process. The solder composition is Au-20wt%Sn. After coating, the organic solvent is removed by a pre-baking process.

[0127] Coating with Au / Sn eutectic solder: Au / Sn eutectic solder (10μm thickness) is applied to the surface of the heterostructure using a screen printing process. The solder composition is Au-20wt%Sn. After coating, organic solvents are removed by a pre-baking process (temperature 150℃, time 10min). The coating process of Au / Sn eutectic solder, including screen printing process parameters and solder composition, ensures solder uniformity and thickness consistency.

[0128] Step S52: Provide a transparent PC board and two transparent pressure-sensitive adhesive layers, attach the transparent pressure-sensitive adhesive layers to the two end faces of the transparent PC board respectively, and align the heterogeneous structure as a whole with the transparent PC board in a bonding machine;

[0129] A transparent PC board (500μm thick) and two transparent pressure-sensitive adhesive layers (50μm thick) are provided. The transparent pressure-sensitive adhesive layers are respectively bonded to the two ends of the transparent PC board. The heterogeneous structure is aligned with the transparent PC board in a bonding machine to ensure a positional accuracy of ≤5μm.

[0130] Step S53: At room temperature, a cold pressing process is used to pre-press the heterogeneous structure and the transparent PC board to achieve initial bonding of the interface.

[0131] At room temperature, a cold pressing process (pressure 1kN, time 5min) is used to pre-press the heterogeneous structure and the transparent PC board to ensure initial bonding of the interface;

[0132] Step S54: Place the pre-pressed structure in a reflow oven and perform reflow bonding in a nitrogen atmosphere to melt the Au / Sn eutectic solder and form a sealed cavity.

[0133] The pre-pressed structure was placed in a reflow oven and reflow bonding was performed under a nitrogen atmosphere (peak temperature 320℃, heating rate 3℃ / s, holding time 30s) to melt the Au / Sn eutectic solder and form a sealed cavity. The formation of the sealed cavity was achieved through the reflow bonding process, and the reflow temperature curve and holding time were determined.

[0134] Step S55: In the sealed cavity, a miniature Pt temperature sensor is integrated and connected to an external circuit via gold wire bonding.

[0135] Integrated miniature Pt temperature sensor: A miniature Pt temperature sensor (50×50μm²) is fabricated using microelectromechanical systems (MEMS) technology within a sealed cavity. The temperature sensor is connected to an external circuit via gold wire bonding (25μm wire diameter, bonding temperature 150℃, pressure 0.2N). The miniature Pt temperature sensor is integrated using MEMS technology, and the electrical connection is achieved through gold wire bonding to ensure the implementation of temperature compensation function.

[0136] Step S56: Apply a polysilazane composite protective layer to the surface of the sealed cavity using a spin coating process, and then perform a curing treatment to form a surface protective layer with a matching coefficient of thermal expansion.

[0137] Coating a polysilazane composite protective layer: A polysilazane composite protective layer (5 μm thick) is coated onto the surface of the sealed cavity using a spin-coating process (3000 rpm, 30 s), followed by curing (200℃, 1 h) to form a surface protective layer with a matching coefficient of thermal expansion (3.2 ppm / ℃). The formation of the polysilazane composite protective layer through spin-coating and curing processes ensures the long-term reliability of the device in a wide temperature range.

[0138] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A MEMS optimized process for a wide temperature range silicon pressure sensor chip, characterized in that, The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. Step S2, forming a deep direction doping concentration gradient 5×10¹ 8 2×10¹ 9 cm⁻³ on the top silicon layer surface of the SOI wafer by a three-time variable-angle ion implantation process, performing local lattice repair by laser annealing technology after implantation, and constructing a gradient-doped piezoresistive network by an electron beam lithography process to make Cr / Pt / Au composite temperature compensation electrodes. The application relates to a wide-temperature-range silicon pressure sensor chip. Step S4, depositing gradient SiN on the surface of the metal interconnection structure in sequence x The thin film is formed by a UV laser-induced crystallization process, stress of the thin film is regulated, and a nano-crack buffer structure is formed. The application relates to a wide-temperature-range silicon pressure sensor chip.

2. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 1, wherein, The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip.

3. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 2, wherein, The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip.

4. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 1, wherein, The application relates to a wide-temperature-range silicon pressure sensor chip. The application relates to a wide-temperature-range silicon pressure sensor chip. Step S22, using a tilt ion implantation process, the tilt ion is B⁺ ion, energy 30 keV, dose 5×10¹ 4 cm⁻², tilt angle 7°; boron ions are implanted on the surface of the top silicon layer to form a first layer of doped regions with a depth of 100 nm and a doping concentration of 5×10¹ 8 cm⁻³; after implantation, a rapid thermal annealing process is used for preliminary lattice repair; Step S23, adjust the tilt angle of B+ ion implantation to 15° for the second implantation, form the second layer of doped region, the doping depth is 250 nm, the doping concentration is 1×10¹ 9 cm⁻³, after implantation, rapid thermal annealing is performed again for secondary lattice repair; Step S24, further adjust the tilt angle of B+ ion implantation to 25° for the third implantation, forming a third layer of doped region, with a doping depth of 400 nm and a doping concentration of 2×10¹ 9 cm⁻³; after implantation, laser annealing is performed to form a gradient-doped piezoresistive network.

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The application relates to Step S26, depositing a SiN passivation layer on the surface of the piezoresistive network and temperature compensation electrode, deposition temperature 400℃, NH3 / SiH2Cl2 gas flow ratio 4:1, then using plasma enhanced chemical vapor deposition technology to complete surface passivation.

6. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 1, wherein, The step S3 specifically comprises: Step S31, growing a corrugated SiON dielectric layer on the surface of the piezoresistive network and temperature compensation electrode by using plasma enhanced chemical vapor deposition technology, deposition temperature 300℃; Step S32, spin coating photoresist on the surface of the corrugated SiON dielectric layer, using ultraviolet lithography technology to form a via pattern mask; etching a tapered via by a reactive ion etching process; Step S33, removing the residual photoresist in the tapered via by using oxygen plasma stripping process, power 300W, time 3min; Step S34, depositing a TiN diffusion barrier layer on the inner wall of the tapered via and the surface of the corrugated SiON dielectric layer by using atomic layer deposition technology; wherein ALD, TiN as precursor, deposition temperature 250℃, cycle number 50 times; Step S35, filling copper metal in the tapered via and the surface of the corrugated SiON dielectric layer by using pulse plating process to form a metal interconnection structure; after plating, removing the excess copper layer on the surface by chemical mechanical polishing to realize surface treatment.

7. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 1, wherein, The step S4 specifically comprises: Step S41, on the surface of the metal interconnection structure, gradient SiN is deposited by using plasma enhanced chemical vapor deposition technology x a film, stress of which changes from -500 MPa to +200 MPa, total thickness of which is 1 μm, and deposition temperature of which is 350 °C; Step S42, using ultraviolet laser to locally crystallize the gradient SiN x thin film to regulate the stress distribution of the thin film and form a stress buffer region; Step S43, by controlling the laser scanning path and power density, in the gradient SiN x The thin film surface induces the generation of nano-cracks, which are distributed in a network for releasing thermal stress; Step S44, using ultrasonic cleaning process to the gradient SiN x thin film surface treatment, remove the particle contamination; Step S45, on the surface of the nano-crack buffer structure, Al2O3 is deposited by atomic layer deposition technology x Transition layer; wherein, ALD, Al2O3 as a precursor, deposition temperature 200 ℃, cycle 30 times.

8. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 1, wherein, The step S5 specifically comprises: Step S51, coating Au / Sn eutectic solder on the surface of the whole heterostructure by using screen printing process, the solder composition is Au-20wt%Sn, and after coating, removing the organic solvent by pre-baking process; Step S52, providing a transparent PC plate and two pieces of transparent pressure sensitive adhesive layer, attaching the transparent pressure sensitive adhesive layer to the two end faces of the transparent PC plate respectively, and aligning the whole heterostructure and the transparent PC plate in a bonder; Step S53, pre-pressing the whole heterostructure and the transparent PC plate by using cold pressing process in a room temperature environment to make the interface preliminarily attached.

9. The MEMS optimized process for wide temperature silicon pressure sensor die of claim 8, wherein, The step S53 further comprises: Step S54, placing the pre-pressed structure in a reflow oven and performing reflow bonding in a nitrogen atmosphere to make the Au / Sn eutectic solder melt and form a sealed cavity; Step S55, integrating a micro Pt temperature sensor in the sealed cavity, and connecting the temperature sensor with an external circuit by gold wire bonding; Step S56, coating a polysilazane composite protective layer on the surface of the sealed cavity by using spin coating process, and then performing curing treatment to form a surface protective layer with a matching thermal expansion coefficient.

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