A method for preparing a sample for measuring reliability of a three-terminal device in situ by transmission electron microscopy

Abstract

The application discloses a transmission electron microscope sample preparation method for measuring reliability of three-terminal devices in situ, and mainly solves the problems of electrode connection difficulty and ion beam damage in the prior art.The implementation scheme is as follows: the device to be measured is placed into a focused ion beam scanning electron microscope; the image is adjusted to determine the sampling position; the ion beam is used to obliquely cut the device to be measured to expose the electrode section; a Pt layer is deposited between the source electrode and the gate electrode of the device to lead out the gate electrode; a SiO2 layer is deposited on the Pt layer to reduce the damage of the ion beam to the sample; the sample wafer is transferred from the device to a micro-electro-mechanical system chip; the Pt layer is deposited again at the contact position of the sample wafer and the micro-electro-mechanical system chip, and the sample wafer is connected with the chip; the sample wafer and the chip are selected and etched to make the three-terminal electrodes of the sample wafer be disconnected with each other; and the sample wafer is thinned by ions to be electron transparent.The application has the characteristics of high efficiency and visualization, is low in cost, high in timeliness, and can be used for real-time observation of the microstructure changes of the transistor three-terminal devices in the process of degradation and failure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of reliability analysis of electronic components, and particularly relates to a transmission electron microscope sample preparation method, which can be used for real-time observation of microstructure changes of a transistor three-terminal device during degradation and failure. BACKGROUND

[0002] Reliability analysis is a key link in device design and practical application. By understanding and analyzing the internal physicochemical properties of the device and its degradation and failure mechanism in the application process, the device design, manufacturing and application can be improved. In order to study the reliability problem, it is urgent to use advanced high spatial resolution failure analysis technology and develop corresponding sample preparation methods to accurately find the degradation and failure mechanism.

[0003] At present, the mainstream idea of studying device reliability problems is to apply single excitation and multi-physical field combined excitation to the device to make it degrade or completely fail. Then, by comparing the degradation or failure conditions under different excitation, different technical means and different processes, the mechanism and position of device failure are deduced. This forensic dissection type examination after the device fails is often laborious and tedious. Although some researchers have begun to use scanning electron microscopy (SEM) and transmission electron microscopy (TEM) for experiments, most of them are limited to the study of two-terminal devices, and the in-situ transmission electron microscopy study of transistor three-terminal devices is very limited.

[0004] In-situ transmission electron microscopy has great potential in device reliability research. This technology allows researchers to directly observe the microstructure changes of the sample under single excitation and multi-physical field combined excitation from the atomic level in real time, which helps to explore the mechanism of device degradation and failure. The difficulty of this technology lies in how to prepare an electron-transparent sample that meets the observation conditions. For example, a transistor three-terminal device contains a source, a drain and a gate. It is a great technical challenge to disconnect the three terminals from each other and connect them to the micro-electro-mechanical system (MEMS) chip electrodes, especially the connection of the gate to the MEMS chip electrodes. During the thinning process in the focused ion beam scanning electron microscope (FIB-SEM) chamber, the ion beam may cause damage to the sample surface. How to protect the sample is also a big difficulty. Therefore, there is an urgent need for a transmission electron microscope sample preparation method for in-situ measurement of the reliability of three-terminal devices to provide help for targeted improvement of the reliability of the device.

[0005] The patent document with the application number CN201320631538.3 discloses a "transmission electron microscope sample stage for in-situ measurement of nanodevices", which comprises a metal nanoprober, an insulating plug and a sample support stage. The front and back surfaces of the insulating plug are respectively provided with a plurality of metal electrodes, and the corresponding metal electrodes are electrically connected through metallized through holes. One end of the sample support stage is connected with the insulating plug, and the other end is provided with a sampling area and a testing area. The testing area is a metal electrode provided on the surface of the sample support stage and suspended. The metal electrode of the sample support stage is in conductive connection with the metal electrode of the insulating plug. The metal nanoprober, the testing area metal electrode and the measured sample constitute a three-terminal field effect transistor. This structure can observe the sample at the atomic scale resolution and perform real-time electrical measurement, and in-situ reveal the electrical properties and nanostructure changes of the unit to be measured. However, the metal nanoprober increases the additional mechanical stress, which may cause damage to the sample. At the same time, the sample stage is fixed, which is not conducive to the real-time observation of the microstructure of the sample from multiple angles. In addition, the cost of the transmission electron microscope sample stage for in-situ measurement of nanodevices is high.

[0006] Wang et al. in "Grainsize-induced thermo-mechanical coupling in zirconium thin films" published in Journal of Thermal Analysis and Calorimetry proposed a MEMS chip with mechanical driving, heating and electrical biasing characteristics. The MEMS chip has three pairs of electrical contact pads: A-A', B-B' and C-C', which can be installed on a custom-made transmission electron microscope in-situ sample holder to perform real-time observation. However, this use of MEMS chip to assist in observing the sample requires customizing MEMS chips for different sizes of transistor three-terminal device samples to achieve three-terminal connection, which will result in longer experimental period and higher cost.

[0007] The patent document with the application number CN202110471682.4 discloses a "transmission electron microscope sample preparation method for observing integrated circuit structure and its evolution in situ". The implementation scheme includes: placing an in-situ power supply chip with at least three electrodes and an integrated circuit sample to be detected into a double-beam device at the same time, and the in-situ power supply chip contains at least one hollow through-hole region. The method simulates the changes of the device in the running process by connecting the three-pole structure to the electrodes of the in-situ power supply chip and then connecting to the external control power supply, prevents the interference of the sample matrix on the loaded signal through the insulating layer on the surface of the integrated circuit sample, and avoids the high design cost and the effort to reform the function of the transmission electron microscope itself by designing the hollow area of the in-situ power supply chip sample area to facilitate the penetration of the electron beam, so that the transmission electron microscope can real-time represent the structure and its evolution of the integrated circuit sample under normal working condition. Since the relationship between the three-pole structure and the electrodes of the in-situ power supply chip and the relationship between the gate covered with the passivation layer and the electrodes of the in-situ MEMS chip are not detailed, it is difficult to more effectively complete the transmission electron microscope sample preparation according to the technical scheme. SUMMARY

[0008] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a transmission electron microscope sample preparation method for in-situ measurement of three-terminal device reliability, which can reduce the transmission electron microscope sample preparation period, reduce the sample preparation cost, and realize high-efficiency, visualized in-situ transmission electron microscope sample preparation of transistor three-terminal devices.

[0009] The technical idea for achieving the purpose of the present application is to realize the ordered connection of the source-gate-drain three electrodes of the transistor three-terminal device and the two-terminal MEMS chip electrodes by depositing conductive materials, to reduce the sample preparation cost without having to spend a long period of time to customize expensive three-terminal MEMS chip electrodes, and to avoid the problem of easy short circuit between the source-gate-drain three electrodes by selecting a circuit breaker, to reduce the damage of the ion beam to the sample during processing and ensure the quality of the sample by FIB-SEM layer protection design.

[0010] According to the above idea, the technical scheme of the present application includes the following steps:

[0011] (1) Put the pin table containing the transistor three-terminal device to be measured and the micro-electromechanical system (MEMS) chip into the sample table of the focused ion beam scanning electron microscope (FIB-SEM) chamber and extract the air to obtain a vacuum environment;

[0012] (2) Adjust the focal length to the clear image in the electron microscope field of view at the electron beam window of the FIB-SEM, place the gate of the transistor at the center position of the electron microscope field of view, and symmetrically distribute the source and drain on both sides of the gate;

[0013] (3) Adjust the focal length to the clear image at the ion beam window of the FIB-SEM, and then rotate the sample table to cut a diagonal section of the transistor with the ion beam;

[0014] (4) Depositing Pt layer on top and inclined section of source and gate of transistor, and temporarily short-circuiting the two electrodes of source and gate;

[0015] (5) Depositing SiO2 protective layer on Pt layer on top and inclined section of source and gate of transistor and on drain of transistor to reduce ion beam damage;

[0016] (6) Cutting out sample sheet from transistor by means of single-sided slotting and U-shaped cutting in sequence, and transferring the sample sheet to MEMS chip in situ transmission electron microscope by mechanical hand extraction;

[0017] (7) Depositing Pt layer on the contact between source, gate and drain three electrodes of sample sheet and electrodes of MEMS chip, and connecting the source, gate and drain three electrodes of sample sheet with corresponding electrodes of MEMS chip respectively;

[0018] (8) Ion beam etching part of area on MEMS chip by FIB-SEM to disconnect the source, gate and drain three electrodes of sample sheet from each other;

[0019] (9) Single-sided ion thinning sample sheet on MEMS chip by ion beam of FIB-SEM to electron beam easy to penetrate, and finally completing the preparation of electron transparent sample.

[0020] Compared with the prior art, the present application has the following advantages:

[0021] Firstly, the present application realizes the connection between transistor three-terminal device and in-situ transmission electron microscope MEMS chip by FIB-SEM, and can observe the degradation and failure behavior of electron transparent device sample under thermal-electric coupling condition in real time;

[0022] Secondly, the present application adopts FIB-SEM laminated protection design, and can reduce the damage of ion beam to sample during sample preparation by depositing Pt layer and SiO2 protective layer on top and inclined section of device, and achieve the effect of protecting the device;

[0023] Thirdly, the present application completes the sample preparation of three-terminal device on general two-terminal MEMS chip electrode without customizing special three-terminal MEMS chip electrode, and saves the sample preparation time and cost. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is the implementation flowchart of the present application;

[0025] Figure 2 is the structure schematic diagram of transistor three-terminal device in the present application;

[0026] Figure 3 is the schematic diagram of target position inclined section in the present application;

[0027] Figure 4 Schematic diagram for first time deposition of Pt layer in the present application;

[0028] Figure 5 Schematic diagram for deposition of SiO2 protective layer in the present application;

[0029] Figure 6 Schematic diagram for U-shaped cutting three-dimensional structure in the present application;

[0030] Figure 7 Schematic diagram for second time deposition of Pt layer in the present application;

[0031] Figure 8 Schematic diagram for one-side ion thinning in the present application;

[0032] Figure 9 Schematic diagram for sample preparation of electron transparent sample in the present application; DETAILED DESCRIPTION

[0033] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application.

[0034] The transistor three-terminal device used in the present example is an AlGaN / GaN heterojunction, which comprises a source 1, a gate 2, a drain 3, a passivation layer 4 and a heterojunction 5, as shown in Figure 2 .

[0035] The focused ion beam scanning electron microscope FIB-SEM used in the present example is provided with control software for controlling the whole sample preparation and its corresponding function keys, wherein the Pump key is used for extracting the gas in the FIB-SEM chamber, the Beam key is used for controlling the electron beam and the ion beam, the Focus key is used for adjusting the focal length of the electron microscope, the Stage Z up / down key is used for adjusting the height of the sample stage, and the Easylift needle of the mechanical hand is used for extracting the sample.

[0036] Referring to Figure 1 , the implementation steps of the present example are as follows:

[0037] Step 1: sample introduction.

[0038] 1.1) After the focused ion beam scanning electron microscope FIB-SEM is exhausted, the electron beam source and the ion beam source of the FIB-SEM are turned off;

[0039] 1.2) horizontally slowly pull open the hatch of the FIB-SEM, put the pin table on which the AlGaN / GaN device to be tested and the MEMS chip are placed into the in-situ sample rod support, then insert the in-situ sample rod support into the sample stage in the FIB-SEM chamber for fixation, and close the hatch;

[0040] 1.3) Click the Pump key of the control software in the FIB-SEM to extract the gas in the chamber, so that the gas pressure in the chamber is reduced to 5x10 -3 Pa below, to obtain a vacuum environment.

[0041] Step 2: Determine the sampling position.

[0042] 2.1) Turn on the electron beam and ion beam Beam keys of the control software in the FIB-SEM, adjust the working distance, that is, place the region to be sampled of the transistor in the center of the electron microscope field of view, and adjust the Focus key at a magnification of less than 5000 times, and then adjust the height of the sample stage multiple times to be at a working distance of 4 mm from the ion beam source;

[0043] 2.2) Adjust the sample stage to 0°, and adjust the sampling position to the center of the electron beam window, then tilt the sample stage to 15°, adjust the sampling position to the center of the electron beam window through the Stage Z up / down key, then tilt the sample stage to 52°, further adjust the sampling position to the center of the electron beam window, a total of three times to complete the centration height adjustment;

[0044] 2.3) Move the FIB-SEM sample stage to place the gate of the transistor three-terminal device in the center of the electron microscope field of view, and the source and drain are symmetrically distributed on both sides, as shown in Figure 2 .

[0045] Step 3: Oblique cutting of the device sample.

[0046] 3.1) Magnify the transistor three-terminal device at the electron beam window of the FIB-SEM, that is, adjust the focus at a high magnification of 5000-15000 times at the ion beam window until the image is clear. Since multiple electron beam or ion beam scans are required during the adjustment process, this will cause damage to the surface of the device sample, and the damage intensity of the electron beam scan is smaller than that of the ion beam scan, therefore, the present example adopts the mode of first electron beam scanning and then ion beam scanning to effectively reduce the damage to the device sample;

[0047] 3.2) Rotate the FIB-SEM sample stage, and use the ion beam to cut a 20°-50° oblique section at the sampling position of the transistor, so as to expose the source-gate-drain three electrodes, facilitating subsequent deposition of a Pt layer, as shown in Figure 3 .

[0048] Step 4: First deposition of a Pt layer between the source and gate of the AlGaN / GaN device to be tested.

[0049] As shown in Figure 4As shown, in FIB-SEM, a Pt layer 6 with a thickness of 1µm to 2µm is deposited for the first time on the top and oblique section of the AlGaN / GaN device between the source and gate using a Pt deposition source, to ensure conductivity between the Pt layer and the upper half of the gate. During the Pt deposition process, it is important to avoid completely covering the gate, which could affect the subsequent complete disconnection between the source and gate. Pt deposition can reduce damage to the sample sheet from the ion beam during FIB-SEM processing.

[0050] A gate is led out from the deposited Pt layer and connected to the electrode of the MEMS chip. The source and gate of the AlGaN / GaN device under test are then temporarily short-circuited so that the two electrodes can be disconnected in the future using a selective disconnection method.

[0051] Step 5: Deposit a SiO2 protective layer.

[0052] like Figure 5 As shown, in FIB-SEM, a SiO2 protective layer 7 with a thickness of 0.1µm to 1µm is deposited on the top of the AlGaN / GaN device and on the Pt layer of the oblique section using a SiO2 deposition source. This is to protect the sample and reduce the damage to the sample caused by the ion beam during the FIB-SEM processing. On the other hand, the insulating properties of SiO2 are used to ensure that the current flows only from both ends of the first deposited Pt layer.

[0053] Step 6: Cut and transfer the sample sheet.

[0054] 6.1) Single-sided trenching: Adjust the ion beam perpendicular to the transistor surface, and use the ion beam to create a trench at the transistor sampling location. The voltage used is 30kV, and the current is 20nA-30nA, which should be adjusted according to the device size. Then, rotate the vertical axis of the sample stage to 54° and trim the side of the transistor. The voltage used is 30kV, and the current is 9.1nA-15nA, which should be adjusted according to the device size.

[0055] 6.2) U-shaped cutting: The left and bottom sides of the sample sheet are cut using the FIB-SEM ion beam, while the right side remains connected to the transistor. The Easylift probe of the FIB-SEM is lowered and connected to the cut side of the sample sheet. Then, the remaining support portion on the right side is cut using the FIB-SEM ion beam. At this point, the sample sheet is only connected to the Easylift probe. Figure 6 The image shows an Easylift needle 8;

[0056] 6.3) sample transfer: the sample wafer is removed from the transistor substrate with the Easylift needle, and the removed sample wafer is transferred onto the substrate of the MEMS chip by lifting the Easylift needle; then the connection between the Easylift needle and the sample wafer is cut off, and the Easylift needle is removed.

[0057] Step 7: second Pt layer deposition.

[0058] Pt layers are deposited at the contact points of the source-gate-drain three-electrode of the sample wafer and the first electrode, the second electrode, and the third electrode of the MEMS chip, so that the sample wafer and the MEMS chip are connected as a whole, as shown in FIG. 6C, wherein 9 is the substrate, 10 is the first electrode, 11 is the second electrode, 12 is the third electrode, 13 is the gate Pt layer, 15 is the drain Pt layer, 16 is the source Pt layer, and 18 is the hollow area. Figure 7

[0059] Step 8: selective disconnection.

[0060] 8.1) The area on the substrate of the MEMS chip, including the partial area between the first electrode 10 and the second electrode 11, is etched by the ion beam of the FIB-SEM, as shown in FIG. 6D, wherein the first area 14 is etched. Figure 7

[0061] 8.2) The area on the sample wafer and below the sample wafer, including the partial source electrode of the sample wafer, the partial second electrode below the source electrode, and the partial substrate below the second electrode, is etched by the ion beam of the FIB-SEM, as shown in FIG. 6E, wherein the second area 17 is etched. Figure 7

[0062] Step 9: The sample wafer is thinned on one side to electron transparency by the ion beam of the FIB-SEM.

[0063] 9.1) The vertical axis of the sample stage of the FIB-SEM is rotated by ±0.3°, the voltage is set to 30 kV, the current is set to 0.44-0.26 nA, and the upper part of the sample wafer is etched by the ion beam at the electron beam window of the electron microscope for a first rough thinning with a depth of 3-6 μm.

[0064] 9.2) The vertical axis of the sample stage of the FIB-SEM is rotated by ±0.3° again, the voltage is set to 30 kV, the current is set to 46-90 pA, and the upper part of the sample wafer is etched by the ion beam at the electron beam window of the electron microscope for a second fine thinning with a depth of 3-6 μm.

[0065] ​​​9.3) Rotate the vertical axis of the sample stage of the FIB-SEM by ±3°, set the voltage to 5kV and the current to 63pA, use the ion beam to etch the upper part of the sample wafer in the electron beam window of the electron microscope for 30-50s of fine thinning, if the sample wafer is obviously bent during the thinning process, correct it to facilitate subsequent processing;

[0066] 9.4) Rotate the vertical axis of the sample stage of the FIB-SEM by ±5°, set the voltage to 2kV and the current to 44pA, use the ion beam to etch the upper part of the sample wafer in the electron beam window of the electron microscope for 30-50s of fine thinning, to obtain the thinned sample wafer, as shown in Figure 8 . Figure 8 Among them, 19 is the thinned sample wafer, and 20 is the etched part;

[0067] 9.5) Adjust the parameters used according to the actual sample needs, and repeat the fine thinning operation several times to make the thickness of the sample wafer 10nm-100nm. During the thinning process, the passivation layer on the electrode of the sample wafer is removed, the gate is connected with the first deposited Pt layer, and finally an electron-transparent sample wafer is formed, and the sample preparation is completed, as shown in Figure 9 .

[0068] The effects of the present application can be further illustrated by the following experimental results:

[0069] I. Experimental process

[0070] The process of the experiment is as follows:

[0071] The transistor device to be sampled is an AlGaN / GaN HEMT, and the transistor device is placed in the FIB-SEM; the transistor device is obliquely cut to form an oblique section of the target position; a sample wafer is obtained from the oblique section of the transistor, and the sample wafer is extracted and placed on the substrate of the MEMS chip; the electron beam image of the MEMS chip in the FIB-SEM is enlarged; a Pt layer is first deposited on the source and gate of the transistor to lead out the gate; a SiO2 protective layer is then deposited on the Pt layer to protect the device. A selected area is etched on the MEMS chip substrate using the ion beam of the FIB-SEM; finally, the sample wafer is thinned on one side using the ion beam of the FIB-SEM to prepare an electron-transparent sample.

[0072] II. Experimental content and result analysis

[0073] The electron transparent sample of the AlGaN / GaN device prepared by FIB-SEM is mounted on the MEMS chip of the in-situ sample rod holder, and the in-situ sample rod is inserted into the TEM cavity, and the electrical characteristics and failure process of the electron transparent sample are observed in real time under the application of gate bias and drain bias, and the results are as follows:

[0074] When the gate voltage of-4V is applied to the electron transparent sample, part of the gate metal melts and disappears immediately, which indicates that the three-terminal connection of the electron transparent sample is normal, and there is no leakage behavior. Although different size Pt particles appear in the Pt protective layer, the electron transparent sample is not damaged, which indicates that the protection design of the FIB-SEM sample preparation stack successfully plays a protective role.

[0075] Under the drain bias, due to the enhancement of the piezoelectric effect, the drain current density can be higher than that on the electron transparent sample, heat accumulation is generated, and the electron transparent sample can exhibit a similar "spring stretching" effect.

[0076] When the drain bias voltage is increased to the material layer beyond the thermal expansion limit, the electron transparent sample is finally broken and damaged by the so-called "spring fracture" failure behavior, and this phenomenon under the limit condition can also be successfully observed.

[0077] The above experiments show that the three-terminal device sample preparation process can be completed on a two-terminal general MEMS chip without the need to customize a special three-terminal MEMS chip, and the prepared electron transparent sample can also meet the needs of electron microscope observation, and the research and development time and cost are saved.

[0078] The above description is only one specific example of the present application and does not constitute any limitation on the present application. Obviously, for those skilled in the art, after understanding the content and principles of the present application, various modifications and changes in form and details can be made without departing from the principles and structures of the present application. For example, in the present application, the way of connecting the sample sheet with the MEMS chip by depositing conductive material is also shown, and mirror or other deformation connection methods can be made on this basis, and these modifications and changes based on the idea of the present application are still within the protection scope of the claims of the present application.

[0079] It should be noted that the step numbers in the specification and claims of the present application are only for the clear description of the embodiments of the present application, and are not limited in sequence. The present application has been described above with reference to specific embodiments. Obviously, for those skilled in the art, after understanding the content and principles of the present application, various modifications and changes in form and details can be made without departing from the principles and structures of the present application.

Claims

1. A transmission electron microscope sample preparation method for in-situ measurement of the reliability of a three-terminal device, characterized in that, Includes the following steps: (1) Insert the pin stage containing the transistor under test (a three-terminal device) and the microelectromechanical system (MEMS) chip into the sample stage of the focused ion beam scanning electron microscope (FIB-SEM) chamber and evacuate the air to obtain a vacuum environment. (2) In the electron beam window of FIB-SEM, adjust the focus until the image in the electron microscope field of view is clear, place the gate of the transistor in the center of the electron microscope field of view, and make the source and drain symmetrically distributed on both sides of the gate. (3) In the ion beam window of FIB-SEM, adjust the focus until the image is clear, then rotate the sample stage and use the ion beam to cut out a slanted section of the transistor. (4) Deposit a Pt layer on the top of the source and gate of the transistor and on the oblique section, and temporarily short-circuit the source and gate electrodes; (5) Deposit a SiO2 protective layer on the Pt layer at the top of the transistor source and gate and on the oblique section and on the drain of the transistor to reduce ion beam damage; (6) The sample sheet is cut from the transistor by means of single-sided grooving and U-shaped cutting, and the sample sheet is transferred to the MEMS chip by means of robotic arm extraction. (7) A Pt layer is deposited at the contact points between the source, gate, and drain electrodes of the sample sheet and the electrodes of the MEMS chip, and the source, gate, and drain electrodes of the sample sheet are connected to the corresponding electrodes of the MEMS chip respectively; the deposition of the Pt layer at the contact points between the source, gate, and drain electrodes of the sample sheet and the electrodes of the MEMS chip is to deposit the Pt layer at the contact points between the source electrode of the sample sheet and the first electrode of the MEMS chip, the contact points between the gate electrode of the sample sheet and the second electrode of the MEMS chip, and the contact points between the drain electrode of the sample sheet and the third electrode of the MEMS chip respectively, so as to fix the sample sheet on the MEMS chip. (8) Use FIB-SEM to etch a portion of the MEMS chip with an ion beam to disconnect the source, gate and drain electrodes of the sample sheet. Specifically, the ion beam of FIB-SEM is used to first etch a portion of the area between the first and second electrodes of the MEMS chip; then, a portion of the source electrode of the sample sheet and a portion of the second electrode and substrate area of ​​the MEMS chip below it are etched. (9) The sample thin film on the MEMS chip is thinned by ion beam of FIB-SEM on one side until the electron beam can easily penetrate, and finally the electronic transparent sample is prepared.

2. The method according to claim 1, characterized in that, In step (3), an oblique section of the transistor is cut out using an ion beam. The oblique section is cut on the surface of the transistor at an angle q of 20° to 50° with the vertical plane to expose the source, gate, and drain electrodes for Pt deposition.

3. The method according to claim 1, characterized in that, In step (4), a Pt layer with a thickness of 1um to 2um is deposited on the top of the source and gate of the transistor and on the oblique section. This layer is used to bring out the gate located in the middle of the transistor to the side so that the gate can be connected to the electrode of the MEMS chip, thereby reducing the damage caused by the ion beam during the FIB-SEM process.

4. The method according to claim 1, characterized in that, In step (5), a SiO2 protective layer with a thickness of 0.1um to 1um is deposited on the Pt layer at the top of the transistor source and gate and the oblique section and the transistor drain to reduce the damage caused by the ion beam during the FIB-SEM process and to make the current flow only from both ends of the first deposited Pt layer.

5. The method according to claim 1, characterized in that, In step (6), a thin sample sheet is cut from the transistor by means of single-sided grooving and U-shaped cutting, which is achieved as follows: (6a) Adjust the ion beam of FIB-SEM to be perpendicular to the upper surface of the electrode of the cut transistor, use the ion beam to dig a groove at the sampling position, then tilt the sample stage and refine one side of the sampling part in the groove. (6b) Using the ion beam of FIB-SEM, one side of the sampled portion is cut off from the transistor and the bottom is cut off from the transistor, while the other side remains connected to the transistor as a support. The Pt deposition source is then inserted, and the Easylift needle of the robotic arm is then inserted. Connect it to the side of the part to be sampled that has been cut off, and then use the ion beam of FIB-SEM to cut off the remaining support part on the other side, and cut out the sample sheet from the transistor.

6. The method according to claim 1, characterized in that, In step (6), the sample sheet is transferred to the in-situ transmission electron microscope MEMS chip by means of extraction by a robotic arm. The Easylift needle of the robotic arm is used to first remove the sample sheet from the transistor substrate. Then, the Easylift needle is lifted and the Pt deposition source is withdrawn. The Easylift needle is then used to transfer the removed sample sheet and bond it to the pre-prepared MEMS chip. The Pt deposition source is used to weld it to the electrode of the MEMS chip. Then the Easylift needle and the Pt deposition source are withdrawn.

7. The method according to claim 1, characterized in that, In step (9), the ion beam of FIB-SEM is used to perform unilateral ion thinning on the sample sheet on the MEMS chip, which is achieved as follows: (9a) Rotate the vertical axis of the FIB-SEM sample stage, set the voltage to 30kV and the current to 0.44~0.26nA, and use an ion beam to etch the upper part of the sample sheet in the electron beam window of the electron microscope to perform a first coarse thinning with a depth of 3~6μm. (9b) Rotate the vertical axis of the FIB-SEM sample stage, set the voltage to 30kV and the current to 46~90pA, and use an ion beam to etch the upper part of the sample sheet in the electron beam window of the electron microscope to perform secondary thinning to a depth of 3~6μm. (9c) Rotate the vertical axis of the FIB-SEM sample stage, set the voltage to 5kV and the current to 63pA, and use the ion beam to etch the upper part of the sample sheet in the electron beam window of the electron microscope for three fine thinning operations with a time of 30~50s. If the sample sheet shows obvious bending during the thinning process, it should be corrected to facilitate subsequent processing. (9d) Rotate the vertical axis of the FIB-SEM sample stage, set the voltage to 2kV and the current to 44pA, and use the ion beam to etch the upper part of the sample sheet in the electron beam window of the electron microscope to perform four fine thinning operations for 30~50s. (9e) Adjust all the values ​​in the above steps according to the actual sample requirements, so that the thickness of the electronically transparent sample is 10nm~100nm, and remove the passivation layer on the electrode of the sample sheet to connect the gate with the first deposited Pt layer. To facilitate electron beam penetration.

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