Abnormal power failure test method and system for chip, equipment and medium

Abstract

The invention discloses an abnormal power failure test method and system for a chip, equipment and a medium. Relates to the technical field of chip testing. The abnormal power failure test system comprises a test fixture, a voltage-stabilized source, a timing on-off relay, a stepping relay and an upper computer. The method comprises the following steps: when a shutdown charging function of a test fixture is closed, in the process that a test control module responds to a read-write test instruction to perform a read-write test on a chip to be tested, an upper computer responds to a random power-down control instruction, controls the working states of a timing on-off relay and a stepping relay, continuously performs power-down control for multiple times, and controls the working states of the timing on-off relay and the stepping relay to perform the read-write test on the chip to be tested; multiple power failure faults are manufactured; the power-down control instruction is one of a timing power-down single-mode instruction, a stepping power-down single-mode instruction and a combined power-down mode instruction; and the test control module automatically returns a read-write test result after each power-down fault occurs to the upper computer so as to realize an abnormal power-down test on the to-be-tested chip. The reliability and the accuracy of the abnormal power failure test can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a method for abnormal power failure testing of a chip and a system, device, and medium thereof. Background Art

[0002] In the test of embedded chips, power-off test is a very important test item. Usually, power-off test is divided into normal power-off test and abnormal power-off test. During the reading and writing process of embedded chips (such as storage chips), normal power-off test or abnormal power-off test can be carried out to test the stability and reliability of embedded chips. Among them, the normal power-off test is that the host sends a command to notify the embedded chip that it is about to be powered off, and the corresponding data is saved and subsequent data operations are stopped to perform the power-off test; the abnormal power-off test is to suddenly disconnect the device power supply when the embedded chip is still working, and perform the power-off test.

[0003] In the related art, the abnormal power failure test process requires manual switching of the power supply to simulate the power failure fault scenario, but the manual work efficiency is low, resulting in a limited number and type of manual simulation of power failure fault scenarios. Therefore, the abnormal power failure test based on manual power on and off to simulate power failure is difficult to cover some low-probability abnormal power failure events in actual application scenarios; the reliability and accuracy of the abnormal power failure test results are not high. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for abnormal power failure testing of a chip and its system, equipment, and medium, which can randomly create multiple abnormal power failure faults, realize automated abnormal power failure testing, and improve the reliability and accuracy of abnormal power failure testing.

[0005] In a first aspect, an embodiment of the present application provides a method for abnormal power failure testing of a chip, which is applied to an abnormal power failure testing system, wherein the system comprises: a test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay, and a host computer; wherein the test fixture comprises: a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive electrode of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port;

[0006] The method comprises:

[0007] When the shutdown charging function of the test fixture is turned off, the test control module performs a read-write test on the chip to be tested in response to a read-write test instruction sent by the host computer through the serial port;

[0008] During the read-write test, the host computer controls the working states of the timing on-off relay and the stepping relay in response to a random power-off control instruction, continuously performs multiple power-off controls, and creates multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction;

[0009] The test control module automatically records the read-write test results after each power-off failure occurs, and automatically returns the read-write test results to the host computer through the serial port to implement abnormal power-off testing of the chip to be tested.

[0010] In a second aspect, an embodiment of the present application provides an abnormal power failure test system, comprising:

[0011] A test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer; wherein the test fixture comprises: a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive pole of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port; the abnormal power-off test system is used to execute the abnormal power-off test method for the chip as described in any one of the embodiments of the first aspect.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the abnormal power-off testing method for a chip as described in any one of the embodiments of the first aspect.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the abnormal power-off testing method for a chip as described in any one of the embodiments of the first aspect.

[0014] The embodiment of the present application includes: an abnormal power-off test system includes: a test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer; wherein the test fixture includes: a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive pole of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port; through the abnormal power-off test system, in the process of performing an abnormal power-off test on the chip to be tested, first, when the shutdown charging function of the test fixture is turned off, the test control module responds to the read-write test instructions sent by the host computer through the serial port to perform a read-write test on the chip to be tested; then, during the read-write test process, The host computer responds to the random power-off control instruction, controls the working state of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction; thereby, it is possible to randomly create multiple abnormal power-off faults during the read-write test process to simulate multiple actual abnormal power-off faults, and lay the foundation for realizing automated abnormal power-off testing; finally, the test control module automatically records the read-write test results after each power-off fault occurs, and automatically returns the read-write test results to the host computer through the serial port to realize abnormal power-off testing of the chip to be tested; and realizes automated abnormal power-off testing, and improves the reliability and accuracy of abnormal power-off testing. That is to say, the embodiment of the present application can randomly create multiple abnormal power-off faults, realize automated abnormal power-off testing, and improve the reliability and accuracy of abnormal power-off testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the overall architecture of an abnormal power failure test system provided by an embodiment of the present application;

[0016] Figure 2 This is a schematic flow chart of the steps of a method for abnormal power failure testing of a chip provided by an embodiment of the present application;

[0017] Figure 3 It is a schematic diagram of a specific process of performing power-off control when the power-off control instruction is a combined power-off mode instruction provided by an embodiment of the present application;

[0018] Figure 4 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0020] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0022] Explanation of several terms involved in this application:

[0023] The TX port and RX port in the serial device server refer to the transmit (TX) and receive (RX) pins in serial communication. The TX port is used to send data, while the RX port is used to receive data. In serial communication, these two pins are the key parts to achieve data transmission.

[0024] The Universal Serial Bus (USB) interface is a serial bus standard and a technical specification for an input and output interface. It is widely used in information communication products such as personal computers and mobile devices.

[0025] The present application discloses a method for abnormal power-off testing of a chip, an abnormal power-off testing system, an electronic device and a computer-readable storage medium; and relates to the field of chip testing technology. The abnormal power-off testing system includes: a test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer; the method includes: when the shutdown charging function of the test fixture is turned off, in the process of the test control module responding to the read-write test instruction to perform a read-write test on the chip to be tested, the host computer responds to the random power-off control instruction, controls the working state of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults; the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction; the test control module automatically returns the read-write test results after each power-off fault occurs to the host computer, so as to realize the abnormal power-off test of the chip to be tested. It can improve the reliability and accuracy of the abnormal power-off test.

[0026] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0027] like Figure 1 As shown, the abnormal power failure test system includes: a test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer. Among them, the test fixture includes: a test control module, a fixture power module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive pole of the fixture power module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port. It can be understood that the negative pole of the fixture power module is grounded.

[0028] The stabilized power supply is used to provide power to the test fixture through the positive electrode of the fixture power module. Specifically, in one embodiment, the stabilized power supply may be a 4.2V stabilized power supply.

[0029] The timing on-off relay is used to control the circuit between the output end of the voltage-stabilized power supply and the positive pole of the fixture power module to be disconnected or conducted.

[0030] The stepper relay is used to control the disconnection or conduction of the circuit between the host computer and the USB interface of the test fixture. Specifically, the stepper relay is a 5V relay. The stepper relay is connected to the USB interface of the test fixture via a USB charging data cable. It should be noted that when the host computer is connected to the USB interface of the test fixture via the stepper relay, the host computer plays the role of providing power to the stepper relay.

[0031] It is understandable that in the abnormal power-off test system, when the stepping relay is powered on and the timing on-off relay electrically connected to the voltage-stabilized power supply is powered on, the test fixture will be powered on and start up, entering the power-on operation phase of the test fixture.

[0032] The test fixture is used to load the chip to be tested, and the test control module of the test fixture is used to: when the test fixture is turned off and the charging function is turned off, respond to the read and write test instructions sent by the host computer through the serial port, and perform read and write tests on the chip to be tested; and automatically record the read and write test results after each power failure, and automatically return the read and write test results to the host computer through the serial port to realize the abnormal power failure test of the chip to be tested; and realize the automated abnormal power failure test. Specifically, the test fixture can be all Android system products with built-in batteries such as mobile phones and tablets, and have been debugged in advance. The test fixture can be a test fixture of different CPU platforms in the abnormal power failure test system of mobile phones and tablets. The mainstream CPU platforms on the market, such as MTK, Qualcomm, and Unisoc platforms, can be used; so that the abnormal power failure test system of this application has high compatibility. Therefore, this application does not make specific restrictions on the type of CPU platform used by the test fixture. The test fixture can be all Android system products with built-in batteries such as mobile phones and tablets.

[0033] Specifically, the positive and negative electrodes are led out through the interface of the battery of the test fixture.

[0034] Specifically, the serial port includes: TX port and RX port. When the test fixture is powered on, it receives the read and write test instructions sent by the host computer through the RX port to perform read and write tests on the chip under test; after the read and write tests are completed, the read and write test results are returned to the host computer through the TX port.

[0035] Specifically, the chip to be tested is an EMMC storage chip or other chip that needs to be tested for abnormal power failure.

[0036] Specifically, the host computer is used to send read and write test instructions to the test control module of the test fixture through the serial port, so that the test fixture performs read and write tests on the chip to be tested; during the read and write test process, in response to the random power-off control instruction, the working state of the timing on-off relay and the stepping relay is controlled, and multiple power-off controls are continuously performed to create multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction; thereby, multiple abnormal power-off faults can be randomly created during the read and write test process to simulate multiple actual abnormal power-off faults, laying the foundation for realizing automated abnormal power-off testing; it is also used to automatically obtain the read and write test results recorded by the test control module after each power-off fault occurs through the serial port, so as to realize abnormal power-off testing of the chip to be tested; automated abnormal power-off testing is realized, and the reliability and accuracy of abnormal power-off testing are improved.

[0037] It should be noted that the embodiment of the present application can perform abnormal power-off tests on battery products. During the chip testing process, it is necessary to perform abnormal power-off tests on the EMMC storage chip waiting to be tested on the test fixture. Based on this, the abnormal power-off test system provided by the embodiment of the present application uses two relays to combine and match the debugged test fixture to control the on-off state of the circuit in which the relay is located; in the read-write test process, it can randomly create a variety of abnormal power-off faults, realize automated abnormal power-off testing, and improve the reliability and accuracy of abnormal power-off testing; and the overall abnormal power-off test system has low cost and high compatibility.

[0038] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0039] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0040] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0041] Based on the above system structure, various embodiments of the abnormal power-off testing method for a chip of the present application are proposed below.

[0042] First, as Figure 2 As shown, the abnormal power-off test method for the chip can be applied to the following Figure 1 In the abnormal power-off test system shown, the abnormal power-off test system includes: a test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer; wherein the test fixture includes: a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive pole of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port. The abnormal power-off test method for the chip may include but is not limited to steps S110 to S130.

[0043] Step S110: When the shutdown charging function of the test fixture is turned off, the test control module responds to the read-write test instructions sent by the host computer through the serial port to perform a read-write test on the chip under test.

[0044] Step S120: During the read and write test, the host computer responds to random power-off control instructions, controls the working states of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction.

[0045] Step S130: the test control module automatically records the read-write test results after each power failure occurs, and automatically returns the read-write test results to the host computer through the serial port to implement abnormal power failure testing of the chip to be tested.

[0046] According to some embodiments of the present application, before step S110, the abnormal power-off test method for the chip further includes: the test fixture receives an input shutdown charging shutdown instruction when the unlocking switch of the original equipment manufacturer is turned on; in response to the shutdown charging shutdown instruction, the shutdown charging function is turned off. After the shutdown charging function is turned off, the test fixture can only be charged in the power-on state, that is, it will automatically change from the power-off state to the power-on state when charging, thereby laying a foundation for simulating abnormal power-off faults and performing abnormal power-off tests.

[0047] The specific process of turning off the shutdown charging function is: first enter the developer options and turn on the OEM switch (original equipment manufacturer unlock switch); then use the command line instruction to enter the specific shutdown charging shutdown instruction to turn off the shutdown charging function. For test fixtures using different CPU platforms, the debugging code used when turning off the shutdown charging function is different. This application does not make specific restrictions on the debugging code used to turn off the shutdown charging function.

[0048] To further explain step S110, the read-write test performed by the test control module on the chip under test in response to the read-write test instruction specifically refers to: the test control module performs a write operation to write the test data into the chip under test, and the chip under test stores the test data. The test control module then performs a read operation to read the test data from the chip under test to obtain read-back data; the read-back data is compared with the test data to obtain a read-write test result to determine the correctness of the read and write, thereby judging the performance of the chip under test.

[0049] To further illustrate step S120, the working states of the timing on-off relay include: a normally open state and a timed power-off state; when the timing on-off relay operates in the normally open state, the circuit between the output end of the voltage-stabilized power supply and the positive pole of the fixture power module remains conductive; when the timing on-off relay operates in the timed power-off state, the circuit between the output end of the voltage-stabilized power supply and the positive pole of the fixture power module is switched on and off regularly.

[0050] To further illustrate step S120, the working states of the stepper relay include: a normally open state and a stepping power-off state; when the stepper relay works in the normally open state, the circuit between the host computer and the USB interface remains conductive; when the stepper relay works in the stepping power-off state, the circuit between the host computer and the USB interface is powered off once after each stepping time interval.

[0051] To further explain step S120, the random power-off control instruction means that in a longer test cycle, the power-off control instruction received by the host computer may be a timed power-off single mode instruction, a step-by-step power-off single mode instruction, or a combined power-off mode instruction. For example, assume that the complete test cycle is 72 hours, and the complete test cycle includes a test sub-cycle (for example, 4 hours is one test sub-cycle). Within 72 hours, the power-off fault manufacturing mode is randomly switched; that is, the timed power-off single mode instruction, the step-by-step power-off single mode instruction, or the combined power-off mode instruction is randomly executed in each test sub-cycle. For example, in the first test sub-cycle, the timed power-off single mode instruction is executed to create a timed power-off fault; in the second test sub-cycle, the stepping power-off single mode instruction is executed to create a stepping power-off fault; in the third test sub-cycle, the combined power-off mode instruction is executed to create a stepping power-off fault and a timed power-off fault at the same time; in the fourth test sub-cycle, the stepping power-off single mode instruction is executed, and so on; based on the random power-off control instruction, multiple power-off controls are performed randomly and continuously. It should be noted that the random power-off control instruction can be set by the host computer.

[0052] Further explanation of step S130, step S130 includes: after each power failure occurs, the test control module of the test fixture will automatically record and print the entire test status and read-write test results of the power failure test process using a log, and return the log recording the read-write test results to the host computer to complete the abnormal power failure test of the chip to be tested. Then, the host computer analyzes the test results of the entire log, thereby evaluating the chip test results, determining whether the chip to be tested is abnormal, and evaluating the performance of the chip to be tested.

[0053] It should be noted that the embodiment of the present application performs an abnormal power-off test of a dead loop on the chip to be tested. When the preset deadline of the overall test cycle is reached, the abnormal power-off test of the chip to be tested is stopped. It is understandable that in order to ensure the reliability of the abnormal power-off test, it is usually necessary to perform thousands or even more power-off tests (e.g., 5000 times of step-by-step power-off and power-on) to meet the test requirements. Therefore, under the premise of meeting the test requirements, the embodiment of the present application does not make specific restrictions on the duration of the overall test cycle.

[0054] Through step S110 to step S130, in the process of performing abnormal power-off test on the chip to be tested through the abnormal power-off test system, first, when the shutdown charging function of the test fixture is turned off, the test control module responds to the read-write test instructions sent by the host computer through the serial port to perform read-write test on the chip to be tested; then, during the read-write test process, the host computer responds to the random power-off control instructions, controls the working state of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults; wherein the power-off control instruction is one of the following : Timed power-off single mode instruction, step power-off single mode instruction, combined power-off mode instruction; thus, it is possible to randomly create multiple abnormal power-off faults during the read-write test to simulate multiple actual abnormal power-off faults, laying the foundation for realizing automated abnormal power-off testing; finally, the test control module automatically records the read-write test results after each power-off fault occurs, and automatically returns the read-write test results to the host computer through the serial port to realize abnormal power-off testing of the chip to be tested; automated abnormal power-off testing is realized, and the reliability and accuracy of abnormal power-off testing are improved. Therefore, the embodiment of the present application can randomly create multiple abnormal power-off faults, realize automated abnormal power-off testing, and improve the reliability and accuracy of abnormal power-off testing.

[0055] According to some embodiments of the present application, when the power-off control instruction is: a timed power-off single mode instruction; step S120 is further described, wherein the host computer responds to the random power-off control instruction, controls the working status of the timed on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults, including but not limited to steps S210 to S220.

[0056] Step S210: The host computer responds to the timed power-off single mode instruction to control the stepping relay to operate in a normally open state and not to operate in a stepping power-off state.

[0057] Step S220: According to the preset first fixed time delay and second fixed time delay, the timing on-off relay is controlled to operate in the timing power-off state, and the timing power-off control is continuously and repeatedly performed multiple times to create multiple timing power-off faults.

[0058] It should be noted that in the single working mode of creating a timed power failure, the stepping relay works in the normally open state, so that the circuit between the host computer and the USB interface of the test fixture remains conductive, providing power to keep the test fixture powered on. At the same time, the timed on-off relay works in the timed power failure state to create multiple timed power failures.

[0059] Through step S210 to step S220, a single manufacturing timed power-off fault working mode is implemented, which is conducive to enriching the types of manufacturing power-off faults, enriching abnormal power-off test scenarios, and improving the reliability of abnormal power-off tests.

[0060] According to some embodiments of the present application, when the power-off control instruction is: a stepping power-off single mode instruction; step S120 is further described, wherein the host computer responds to the random power-off control instruction, controls the working status of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults, including but not limited to steps S310 to S320.

[0061] Step S310: The host computer responds to the stepping power-off single mode instruction to control the timing on-off relay to operate in a normally open state and not operate in a timing power-off state.

[0062] Step S320: According to the preset step value and the preset third fixed delay, the stepping relay is controlled to operate in the stepping power-off state, and the stepping power-off control is continuously performed multiple times to create multiple stepping power-off faults.

[0063] It should be noted that in the single working mode of creating a stepper power-off fault, the timing on-off relay works in the normally open state, so that the circuit between the output end of the voltage-stabilized power supply and the positive pole of the fixture power module of the test fixture is turned on, supplying power to the test fixture to ensure that the test fixture is turned on; at the same time, the stepper relay works in the stepper power-off state to create multiple stepper power-off faults.

[0064] Through step S310 to step S320, a single manufacturing step power-off fault working mode is realized, which is conducive to enriching the types of manufacturing power-off faults, enriching abnormal power-off test scenarios, and further improving the reliability of abnormal power-off testing.

[0065] According to some embodiments of the present application, Figure 3 As shown, when the power-off control instruction is: a combined power-off mode instruction; further illustrating step S120, wherein the host computer responds to the random power-off control instruction, controls the working state of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults, including but not limited to steps S410 to S420.

[0066] Step S410: The host computer responds to the combined power-off mode instruction, controls the timing on-off relay to operate in the timing power-off state according to the preset first fixed delay and second fixed delay, continuously performs multiple timing power-off controls, and creates multiple timing power-off faults.

[0067] Step S420: At the same time, according to the preset step value and the preset third fixed delay, the stepping relay is controlled to operate in the stepping power-off state, and multiple stepping power-off controls are continuously performed to create multiple stepping power-off faults.

[0068] It is understandable that although the embodiments of the present application perform the step power-off control and the step power-off control at the same time, since the time parameters (the first fixed delay and the second fixed delay) used in the timed power-off control and the time parameters (the preset step value and the preset third fixed delay) used in the step power-off control are different and the control mechanisms are different, each manufacturing of the timed power-off fault and each manufacturing of the step power-off fault are not simultaneous. It is possible that a timed power-off fault occurs, and after the timed power-off fault is restored, one or more step power-off faults occur immediately; or during the period when a timed power-off fault occurs, one or more step power-off faults occur; or a timed power-off fault and a step power-off fault occur at the same time; or a step power-off fault occurs, and after the step power-off fault is restored, a timed power-off fault occurs immediately, and so on. It can be seen that in the combined power-off working mode, there are multiple occurrences of the timed power-off fault and the step power-off fault, that is, there are multiple combination faults determined by the timed power-off fault and the step power-off fault, thereby improving the randomness and diversity of the power-off fault.

[0069] Through step S410 to step S420, a combined power-off working mode of manufacturing timed power-off faults and stepping power-off faults is realized, the randomness of power-off faults is improved, the abnormal power-off test scenarios are further enriched, and the reliability of abnormal power-off tests is further improved.

[0070] According to some embodiments of the present application, the specific process of manufacturing a timed power-off fault in step S220 and step S410 is further described. According to the preset first fixed delay and second fixed delay, the timed on-off relay is controlled to work in a timed power-off state, and multiple timed power-off controls are continuously and repeatedly performed to manufacture multiple timed power-off faults, including but not limited to steps S510 to S530.

[0071] Step S510: When the timing on-off relay is powered on and powered on for a first fixed delay, the timing on-off relay is powered off to disconnect the circuit between the output end of the voltage-stabilized power supply and the positive pole of the fixture power module, thereby creating a timing power-off fault.

[0072] Step S520: When the timing on-off relay is powered off and the power failure lasts for a second fixed delay, the timing on-off relay is powered on to restore the circuit between the output end of the voltage-stabilized power supply and the positive electrode of the fixture power module.

[0073] Step S530: According to the first fixed time delay and the second fixed time delay, the timing on-off relay is controlled to be powered on and off in a continuous and alternating manner to create multiple timing power-off faults.

[0074] It is understandable that the first fixed time delay and the second fixed time delay may be the same or different. The test manager may debug the timing on-off relay and set the values ​​of the first fixed time delay and the second fixed time delay according to the actual test requirements. Therefore, this application does not make specific restrictions on the values ​​of the first fixed time delay and the second fixed time delay.

[0075] Through steps S510 to S530, the timing on-off relay is controlled to power on and off alternately through the preset first fixed delay and the second fixed delay, thereby realizing the timing power-off fault occurrence mechanism; this is conducive to simulating timing power-off faults and enriching abnormal power-off test scenarios.

[0076] Take an example to illustrate steps S510 to S530. When the first fixed delay is set to 2 seconds and the second fixed delay is set to 5 seconds. The specific process of creating a timed power-off fault is: power on the timed on-off relay, and after the power-on lasts for 2 seconds, power off the timed on-off relay, and the first timed power-off fault occurs; after the power-off lasts for 5 seconds, power on the timed on-off relay, and after the power-on lasts for 2 seconds, power off the timed on-off relay, and the second timed power-off fault occurs; after the power-off lasts for 5 seconds, power on the timed on-off relay, and after the power-on lasts for 2 seconds, power off the timed on-off relay, and the third timed power-off fault occurs; and so on, the timed on-off relay is alternately controlled to be powered on and off in a cycle to achieve multiple timed power-off faults.

[0077] According to some embodiments of the present application, the specific process of manufacturing the step power-off state in step S320 and step S420 is further described. Among them, according to the preset step value and the preset third fixed delay, the stepping relay is controlled to work in the step power-off state, and multiple step power-off controls are continuously performed to manufacture multiple step power-off faults, including but not limited to steps S610 to S650.

[0078] Step S610: Add the last acquired first power-on duration delay and the preset step value to obtain an updated current second power-on duration delay.

[0079] Step S620: When the stepping relay is powered on and the power-on period lasts for a second power-on delay, the stepping relay is powered off to disconnect the circuit between the host computer and the USB interface, thereby creating a stepping power-off fault.

[0080] Step S630: When the stepping relay is powered off and the power-off lasts for a third fixed time delay, the stepping relay is powered on to restore the circuit between the host computer and the USB interface.

[0081] Step S640: Add the current second power-on duration delay and the preset step value to obtain an updated third power-on duration delay; and control the stepping relay to power off according to the third power-on duration to create the next stepping power-off fault.

[0082] Step S650: repeatedly and continuously updating the power-on duration delay and performing step-by-step power-off to create multiple step-by-step power-off faults.

[0083] It is understandable that the preset step value can be 0.1 seconds, 0.2 seconds, etc. The test manager can debug the stepping relay and set the value of the preset step value according to the actual test requirements. Therefore, this application does not make specific restrictions on the value of the preset step value.

[0084] It is understandable that the third fixed delay may be 5 seconds, 8 seconds, etc. The test manager may set the value of the third fixed delay according to actual test requirements. Therefore, this application does not impose any specific restrictions on the value of the third fixed delay.

[0085] Through steps S610 to S650, the power-off interval time is continuously updated by the preset step value, and the timing on-off relay is controlled to power on and off alternately in a continuous cycle according to the step power-off interval time and the preset third fixed delay, thereby realizing the step power-off fault occurrence mechanism; creating a step power-off fault, improving the randomness of the power-off fault, and enriching the abnormal power-off test scenarios.

[0086] An example is given to illustrate steps S610 to S650. When the preset step value is set to 0.1 seconds, the third fixed delay is set to 5 seconds. The specific process of creating a stepping power-off fault is as follows: power on the stepping relay, and after the power-on lasts for 0.1 seconds, the stepping relay is powered off (that is, powered off), and the first stepping power-off fault occurs; after the power-off lasts for 5 seconds, the stepping relay is powered on, and after the power-on lasts for 0.2 seconds (the last first power-on delay of 0.1 seconds is added to the preset step value of 0.1 seconds, and the second power-on delay of 0.2 seconds is obtained), the stepping relay is powered off, and the second stepping power-off fault occurs; after the power-off lasts for 5 seconds, the stepping relay is powered on, and after the power-on lasts for 0.3 seconds (the last first power-on delay of 0.2 seconds is added to the preset step value of 0.1 seconds, and the second power-on delay of 0.3 seconds is obtained), the stepping relay is powered off, and the third stepping power-off fault occurs; and so on, the timing on-off relay is controlled to power on and off in a cyclic and alternating manner to achieve multiple timing power-off faults.

[0087] like Figure 4 As shown, the present invention also provides an electronic device, including:

[0088] The processor 401 may be implemented by a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0089] The memory 402 may be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, or a random access memory. The memory 402 may store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 402, and the processor 401 calls and executes the abnormal power-off test method for the chip in the embodiment of this application;

[0090] Input / output interface 403, used to implement information input and output;

[0091] Communication interface 404, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WI FI, Bluetooth, etc.);

[0092] Bus 405 , which transmits information between various components of the device (e.g., processor 401 , memory 402 , input / output interface 403 , and communication interface 404 );

[0093] The processor 401 , the memory 402 , the input / output interface 403 and the communication interface 404 are connected to each other in communication within the device via the bus 405 .

[0094] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned abnormal power-off test method for a chip is implemented.

[0095] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0096] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0097] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for abnormal power failure testing of a chip, characterized in that: Applied to an abnormal power-off test system, the system comprises: a test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer; wherein the test fixture comprises: a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive electrode of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port; The method comprises: When the shutdown charging function of the test fixture is turned off, the test control module performs a read-write test on the chip to be tested in response to a read-write test instruction sent by the host computer through the serial port; During the read-write test, the host computer controls the working states of the timing on-off relay and the stepping relay in response to a random power-off control instruction, continuously performs multiple power-off controls, and creates multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction; The test control module automatically records the read-write test results after each power-off failure occurs, and automatically returns the read-write test results to the host computer through the serial port to implement abnormal power-off testing of the chip to be tested.

2. The abnormal power-off test method for a chip according to claim 1, characterized in that: When the power-off control instruction is: the timed power-off single mode instruction; the host computer responds to the random power-off control instruction, controls the working state of the timed on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults, including: The host computer controls the stepping relay to operate in a normally open state and not operate in a stepping power-off state in response to the timed power-off single mode instruction; According to the preset first fixed time delay and second fixed time delay, the timing on-off relay is controlled to operate in a timing power-off state, and multiple timing power-off controls are continuously and repeatedly performed to create multiple timing power-off faults.

3. The abnormal power-off test method for a chip according to claim 1, characterized in that: When the power-off control instruction is: the step power-off single mode instruction; the host computer responds to the random power-off control instruction, controls the working state of the timing on-off relay and the step relay, continuously performs multiple power-off controls, and creates multiple power-off faults, including: The host computer responds to the stepping power-off single mode instruction to control the timing on-off relay to work in a normally open state and not to work in a timing power-off state; According to the preset step value and the preset third fixed time delay, the stepping relay is controlled to operate in a stepping power-off state, and multiple stepping power-off controls are continuously performed to create multiple stepping power-off faults.

4. The abnormal power-off test method for a chip according to claim 1, characterized in that: When the power-off control instruction is: the combined power-off mode instruction; the host computer responds to the random power-off control instruction, controls the working state of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and creates multiple power-off faults, including: The host computer responds to the combined power-off mode instruction, controls the timing on-off relay to operate in the timing power-off state according to the preset first fixed delay and second fixed delay, continuously performs multiple timing power-off controls, and creates multiple timing power-off faults; At the same time, according to the preset step value and the preset third fixed time delay, the stepping relay is controlled to operate in a stepping power-off state, and multiple stepping power-off controls are continuously performed to create multiple stepping power-off faults.

5. The abnormal power-off test method for a chip according to claim 2 or 4, characterized in that: The method of controlling the timing on-off relay to operate in a timing power-off state according to the preset first fixed time delay and the second fixed time delay, continuously and repeatedly performing multiple timing power-off controls, and creating multiple timing power-off faults, includes: When the timing on-off relay is powered on and the power-on continues for the first fixed time delay, the timing on-off relay is powered off, so that the circuit between the output end of the voltage-stabilized power supply and the positive electrode of the fixture power module is disconnected, thereby creating a timing power-off fault; When the timing on-off relay loses power and the power failure lasts for the second fixed time delay, the timing on-off relay is powered on to restore the circuit between the output end of the voltage-stabilized power supply and the positive electrode of the fixture power module; According to the first fixed time delay and the second fixed time delay, the timing on-off relay is controlled to be powered on and off in a continuous and alternating cycle, thereby creating multiple timing power-off faults.

6. The abnormal power failure test method for a chip according to claim 3 or 4, characterized in that: The stepping relay is controlled to operate in a stepping power-off state according to a preset step value and a preset third fixed time delay, and multiple stepping power-off controls are continuously performed to create multiple stepping power-off faults, including: Adding the last acquired first power-on duration delay and the preset step value to obtain an updated current second power-on duration delay; When the stepping relay is powered on and the power-on continues for the second power-on delay, the stepping relay is powered off, so that the circuit between the host computer and the USB interface is disconnected, thereby creating a stepping power-off fault; When the stepping relay is powered off and the power-off lasts for the third fixed time delay, the stepping relay is powered on to restore the circuit between the host computer and the USB interface; Adding the current second power-on duration delay and the preset step value to obtain an updated third power-on duration delay; controlling the stepping relay to power off according to the third power-on duration to create the next stepping power-off fault; Repeatedly and continuously update the power-on delay and perform step-by-step power-off to create multiple step-by-step power-off faults.

7. The abnormal power-off test method for a chip according to claim 1, characterized in that: Before the test control module performs a read-write test on the chip under test in response to a read-write test instruction sent by the host computer through the serial port, the method further includes: The test fixture receives an input shutdown charging shutdown instruction when the unlocking switch of the original equipment manufacturer is turned on; In response to the shutdown charging shutdown instruction, the shutdown charging function is turned off.

8. An abnormal power failure test system, characterized in that: include: A test fixture, a voltage-stabilized power supply, a timing on-off relay, a stepping relay and a host computer; wherein the test fixture comprises: a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the voltage-stabilized power supply is connected to the positive pole of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and to the test control module through the serial port; the abnormal power-off test system is used to execute the abnormal power-off test method for the chip as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the abnormal power-off testing method for the chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the abnormal power-off testing method for a chip according to any one of claims 1 to 7.

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