A RISC-V DSP chip test communication method, system and storage medium
By setting read and write data rules and testing agent communication in RISC-V DSP chip test, the problem of test communication accuracy and inefficiency in the prior art is solved, and high accuracy and efficient chip functional level testing is achieved.
Patent Information
- Application Number
- CN202411789204.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-04-04
AI Technical Summary
In the functional-level ATE test of RISC-V DSP chips, it is difficult for the prior art to achieve high accuracy and secure test communication, resulting in inefficient testing.
By setting data reading rules and writing rules, finding and writing data information based on address information, obtaining and adjusting the output parameters of the chip, and verifying and adjusting the output parameters through test agent communication, thereby improving the accuracy and efficiency of the test.
Improve the accuracy and efficiency of RISC-V DSP chip test communication, ensuring the safety and comprehensiveness of the test.
Smart Images
Figure CN119758025A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip testing, and more specifically, to a RISC-V DSP chip testing communication method, system and storage medium. Background Art
[0002] When the RISC-V DSP chip is tested at the functional level ATE (Automatic Test Equipment), a specific test program is usually required for each function that needs to be tested. The test program is simulated in the RTL simulation environment to generate a test waveform passing through the JTAG / CJTAG pin of the chip. This waveform completes the function of loading the current test program into the RAM of the chip under test and controlling the chip to run this test program.
[0003] Since the R&D personnel of the functional modules are familiar with the modules, the participation of R&D personnel in the chip functional level test is conducive to improving the comprehensiveness of the test. In order to improve the participation of R&D personnel, the script writing and demand conversion required for chip testing are realized through the test agent communication method. In order to ensure the security and accuracy of communication, a RISC-V DSP chip test communication technology is urgently needed. Summary of the invention
[0004] In view of the above problems, the purpose of the present invention is to provide a RISC-V DSP chip test communication method, system and storage medium. First, according to the set read data rule, the first data information is searched according to the first address information; secondly, by analyzing the first data information, according to the set write data rule, the preset data is written to the first address information; then, the first output parameter of the chip is obtained, and the second waveform information is obtained according to the set configuration script; finally, when the first waveform information of the chip is the same as the second waveform information, the third waveform information can be determined according to the second output parameter; the accuracy of data communication is improved by the preset read data rule and write data rule; the output parameters of the chip test are verified and adjusted by the test agent communication method, thereby improving the efficiency of the chip functional level test.
[0005] A first aspect of the present invention provides a RISC-V DSP chip test communication method, the method comprising:
[0006] Obtaining first address information;
[0007] Obtaining first data information according to the first address information;
[0008] Determining whether the first data information is a preset first data threshold;
[0009] If yes, writing a preset second data threshold according to the first address information;
[0010] Acquire first waveform information and first output parameter;
[0011] Determining second waveform information according to the first output parameter;
[0012] Determining whether the first waveform information matches the second waveform information;
[0013] If yes, get the second output parameter;
[0014] According to the second output parameter, third waveform information is determined.
[0015] In this solution, the first data information is obtained according to the first address information, specifically:
[0016] Sending a first enable signal;
[0017] Within a preset first time, determining whether a first feedback instruction is received;
[0018] If yes, obtain first read data and a first check code according to the first address information;
[0019] Obtaining a second check code according to the first read data and a preset check code calculation rule;
[0020] Determining whether the first verification code is the same as the second verification code;
[0021] If so, the first read data is the first data information.
[0022] In this solution, the second data threshold value preset according to the first address information is written as follows:
[0023] Sending a second enable signal;
[0024] Within a preset first time, determining whether a second feedback instruction is received;
[0025] If yes, obtaining third verification code information according to the first address information and the second data threshold and a preset verification code calculation rule;
[0026] A first write instruction is generated and sent according to the first address information, the second data threshold and the third check code information.
[0027] In this solution, the second waveform information is determined according to the first output parameter, specifically:
[0028] Reading a configuration script file, and obtaining a first configuration parameter according to the configuration script file;
[0029] Determining an output interface according to the first output parameter;
[0030] According to the first output parameter and the first configuration parameter, second waveform information is obtained according to a preset waveform generation script.
[0031] This plan also includes:
[0032] When it is determined that the first data information is not a preset first data threshold;
[0033] Get second time information;
[0034] Determining whether the second time information exceeds a preset time threshold;
[0035] If yes, send the preset reset command.
[0036] This plan also includes:
[0037] Get output parameter list information;
[0038] The second output parameter is determined according to the output parameter list information and the first output parameter.
[0039] A second aspect of the present invention provides a RISC-V DSP chip test communication system, including a RISC-V DSP chip test communication method program, wherein the RISC-V DSP chip test communication method program implements the following steps when executed by the processor:
[0040] Obtaining first address information;
[0041] Obtaining first data information according to the first address information;
[0042] Determining whether the first data information is a preset first data threshold;
[0043] If yes, writing a preset second data threshold according to the first address information;
[0044] Acquire first waveform information and first output parameter;
[0045] Determining second waveform information according to the first output parameter;
[0046] Determining whether the first waveform information matches the second waveform information;
[0047] If yes, get the second output parameter;
[0048] According to the second output parameter, third waveform information is determined.
[0049] In this solution, the first data information is obtained according to the first address information, specifically:
[0050] Sending a first enable signal;
[0051] Within a preset first time, determining whether a first feedback instruction is received;
[0052] If yes, obtain first read data and a first check code according to the first address information;
[0053] Obtaining a second check code according to the first read data and a preset check code calculation rule;
[0054] Determining whether the first verification code is the same as the second verification code;
[0055] If so, the first read data is the first data information.
[0056] In this solution, the preset second data threshold is written according to the first address information, specifically:
[0057] Sending a second enable signal;
[0058] Within a preset first time, determining whether a second feedback instruction is received;
[0059] If yes, obtaining third verification code information according to the first address information and the second data threshold and a preset verification code calculation rule;
[0060] A first write instruction is generated and sent according to the first address information, the second data threshold and the third check code information.
[0061] A third aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a RISC-V DSP chip test communication method program. When the RISC-V DSP chip test communication method program is executed by a processor, the steps of the RISC-V DSP chip test communication method as described in any one of the above items are implemented.
[0062] The present invention provides a RISC-V DSP chip test communication method, system and storage medium. Firstly, first data information is searched and obtained according to first address information and preset data reading rules; secondly, when the first data information is judged to be a preset first data threshold, a second data threshold is written into the first address information according to a preset data writing rule; then, second waveform information is obtained according to a first output parameter in the chip and a corresponding configuration script; finally, when the second waveform information is the same as the first waveform information in the chip, third waveform information is determined according to the second output parameter for chip function testing; the present invention improves the accuracy of data communication through preset data reading rules and data writing rules; and verifies and adjusts the output parameters of chip testing through test agent communication, thereby improving the efficiency of chip function level testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope.
[0064] Figure 1 A flow chart of a RISC-V DSP chip test communication method of the present invention is shown;
[0065] Figure 2 A flowchart of reading data provided by an embodiment of the present invention is shown;
[0066] Figure 3 A flowchart of writing data provided by an embodiment of the present invention is shown;
[0067] Figure 4 A block diagram of a RISC-V DSP chip test communication system of the present invention is shown. DETAILED DESCRIPTION
[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0069] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present invention are clearly defined in this way.
[0070] The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The steps before or after the method of the embodiment of the present invention are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or a step or several steps can be removed from these processes.
[0071] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.
[0072] Figure 1 A flow chart of a RISC-V DSP chip test communication method of the present invention is shown.
[0073] like Figure 1 As shown, the first aspect of the present invention discloses a RISC-V DSP chip test communication method, the method comprising:
[0074] Obtaining first address information;
[0075] Obtaining first data information according to the first address information;
[0076] Determining whether the first data information is a preset first data threshold;
[0077] If yes, writing a preset second data threshold according to the first address information;
[0078] Acquire first waveform information and first output parameter;
[0079] Determining second waveform information according to the first output parameter;
[0080] Determining whether the first waveform information matches the second waveform information;
[0081] If yes, get the second output parameter;
[0082] According to the second output parameter, third waveform information is determined.
[0083] It should be noted that the first address information is the memory address for storing flag data in the chip; the first data information is the data stored in the first address information in the chip; the first output parameter is the parameter for adjusting the output waveform during the functional level test of the chip; the first waveform information is the output waveform stored by the chip according to the first output parameter; the second waveform information is the output waveform obtained according to the preset configuration module script and the first output parameter; the second output parameter is one of the verification conditions during the functional level test of the chip; the third waveform information is the output waveform obtained according to the preset configuration module script and the second output parameter.
[0084] In this embodiment, whether the output parameter can be adjusted is first analyzed by the flag data to improve the accuracy of data communication; then the output parameters of the chip test are verified and adjusted by the test agent communication, thereby improving the efficiency of the chip functional level test. First, according to the first address information, the first data information is found according to the preset read data timing. When it is judged that the first data information is the preset first data threshold, it means that the chip has completed the test of the current output parameter and is in the chip idle state. At this time, by writing the second data threshold to the first address information according to the preset write data timing, it is used to indicate that the agent program communication state has been entered, and the output parameter can be adjusted. Then, the first output parameter and the first waveform information of the current chip test are obtained; according to the first output parameter, the second waveform information is generated according to the preset module configuration script; when the first waveform information and the second waveform information match each other, it means that the two use the same module configuration script, and the next output parameter test can be performed. Finally, according to the second output parameter, the third waveform information is produced according to the preset module configuration script for chip functional level test. By automatically checking the module configuration and switching the output parameters, the efficiency of the chip functional level test is improved.
[0085] Figure 2 A flow chart of reading data provided by an embodiment of the present invention is shown.
[0086] According to an embodiment of the present invention, Figure 2 As shown, the first data information is obtained according to the first address information, specifically:
[0087] Sending a first enable signal;
[0088] Within a preset first time, determining whether a first feedback instruction is received;
[0089] If yes, obtain first read data and a first check code according to the first address information;
[0090] Obtaining a second check code according to the first read data and a preset check code calculation rule;
[0091] Determining whether the first verification code is the same as the second verification code;
[0092] If so, the first read data is the first data information.
[0093] It should be noted that the first enable signal is an enable signal used to notify the chip controller that a read operation is about to occur; the first feedback instruction is a response of the chip control interface to allow the read operation; the first read data is the data stored in the first address information location in the chip memory; the first check code is a check code generated by the chip based on the first read data; and the second check code is a check code generated by the test agent program based on the first read data.
[0094] As a read data timing, in this embodiment, first, a first enable signal is sent, and whether a read data operation can be performed is determined according to the response time of the first feedback instruction. Secondly, when the read data operation is allowed, the first read data and the first check code are obtained according to the first address information according to the reading rule. Then, according to the first read data, according to the preset check code generation rule, including but not limited to the cyclic redundancy check, the second check code is calculated. Finally, it is determined whether the first check code is the same as the second check code. If so, it indicates that the data transmission process is normal, and the first read data is undisturbed data, which can be identified as the first data information.
[0095] Figure 3 A flowchart of writing data provided by an embodiment of the present invention is shown.
[0096] According to an embodiment of the present invention, Figure 3 As shown, the second data threshold value preset according to the first address information is written as follows:
[0097] Sending a second enable signal;
[0098] Within a preset first time, determining whether a second feedback instruction is received;
[0099] If yes, obtaining third verification code information according to the first address information and the second data threshold and a preset verification code calculation rule;
[0100] A first write instruction is generated and sent according to the first address information, the second data threshold and the third check code information.
[0101] It should be noted that the second enable signal is an enable signal used to notify the chip controller that a write operation is about to occur; the second feedback instruction is a response of the chip control interface to allow the write operation; the third verification code information is a verification code generated by the test agent program based on the write address and write data; the first write instruction is an instruction to write setting data to the chip setting address.
[0102] As a data writing sequence, in this embodiment, the second enable signal is first sent, and whether the data writing operation can be performed is determined according to the response time of the second feedback instruction. Then, when the data writing operation is allowed, the third check code is calculated according to the first address information and the second data threshold according to the preset check code generation rules, including but not limited to cyclic redundancy check. Finally, the first write instruction is generated according to the first address information, the second data threshold and the third check code information, and the second data threshold is written to the position of the first address information of the chip.
[0103] According to an embodiment of the present invention, determining the second waveform information according to the first output parameter is specifically:
[0104] Reading a configuration script file, and obtaining a first configuration parameter according to the configuration script file;
[0105] Determining an output interface according to the first output parameter;
[0106] According to the first output parameter and the first configuration parameter, second waveform information is obtained according to a preset waveform generation script.
[0107] It should be noted that, in this embodiment, the corresponding output waveform is generated according to the preset module configuration script based on the output parameters. First, the configuration script file is read to obtain the first configuration parameter of the configuration module of the functional test; wherein the configuration module includes but is not limited to clock, power supply, system control, etc. Then, according to the first output parameter, the output interface or pin of the output module is determined. Finally, the first output parameter and the first configuration parameter are passed into the waveform generation script to obtain the second waveform information for chip functional level testing.
[0108] According to an embodiment of the present invention, it also includes:
[0109] When it is determined that the first data information is not a preset first data threshold;
[0110] Get second time information;
[0111] Determining whether the second time information exceeds a preset time threshold;
[0112] If yes, send the preset reset command.
[0113] It should be noted that when the first data information is not the preset first data threshold, it means that the chip has not completed the test of the current output parameter and is in a busy state. In this embodiment, the time when the chip is in a busy state is recorded, that is, the second time information. When the second time information exceeds the preset time threshold, it means that the test running time exceeds the set range, and there is a risk of program running away or chip error. At this time, by sending a preset reset instruction, the chip is reset and in an idle state.
[0114] According to an embodiment of the present invention, it also includes:
[0115] Get output parameter list information;
[0116] The second output parameter is determined according to the output parameter list information and the first output parameter.
[0117] It should be noted that, in this embodiment, the output parameters of the output module in each output state during the chip function level test are stored through lists, scripts, etc. The output parameter list is searched according to the first output parameter. If the first output parameter is not the last output parameter in the output parameter list, it means that the output module has not been tested. At this time, the next output parameter in the output list is selected as the second output parameter.
[0118] It is worth mentioning that it also includes:
[0119] Obtaining second address information;
[0120] Obtaining first flag information according to the second address information;
[0121] Determine whether the first flag bit information is in a locked state;
[0122] If so, read and write operations of the preset address space are prohibited.
[0123] It should be noted that the second address information is the memory address for storing the first flag information in the chip; the first flag information is a flag indicating whether the chip is in a locked or unlocked state. In this embodiment, according to the second address information, the first flag information is found according to the preset read data timing. The first flag information is used to determine whether the chip is in a locked state. If so, it indicates that the chip is prohibited from writing data to the memory in the preset address space. Write protection is used to prevent the chip from being interfered with by communication during the test process.
[0124] It is worth mentioning that it also includes:
[0125] Obtaining second address information;
[0126] According to the second address information, a preset unlocking or locking instruction is sent to adjust the first flag bit information.
[0127] It should be noted that in this embodiment, according to the second address information and the unlock or lock flag, the first flag information is adjusted according to the preset write data timing to implement the chip unlock or lock operation, that is, to turn off or turn on the write protection function for the memory in the preset address space.
[0128] Figure 4 A block diagram of a RISC-V DSP chip test communication system of the present invention is shown.
[0129] like Figure 4 As shown, the second aspect of the present invention discloses a RISC-V DSP chip test communication system 4, including a memory 41 and a processor 42, wherein the memory includes a RISC-V DSP chip test communication method program, and when the RISC-V DSP chip test communication method program is executed by the processor, the following steps are implemented:
[0130] Obtaining first address information;
[0131] Obtaining first data information according to the first address information;
[0132] Determining whether the first data information is a preset first data threshold;
[0133] If yes, writing a preset second data threshold according to the first address information;
[0134] Acquire first waveform information and first output parameter;
[0135] Determining second waveform information according to the first output parameter;
[0136] Determining whether the first waveform information matches the second waveform information;
[0137] If yes, get the second output parameter;
[0138] According to the second output parameter, third waveform information is determined.
[0139] It should be noted that the first address information is the memory address for storing flag data in the chip; the first data information is the data stored in the first address information in the chip; the first output parameter is the parameter for adjusting the output waveform during the functional level test of the chip; the first waveform information is the output waveform stored by the chip according to the first output parameter; the second waveform information is the output waveform obtained according to the preset configuration module script and the first output parameter; the second output parameter is one of the verification conditions during the functional level test of the chip; the third waveform information is the output waveform obtained according to the preset configuration module script and the second output parameter.
[0140] In this embodiment, whether the output parameter can be adjusted is first analyzed by the flag data to improve the accuracy of data communication; then the output parameters of the chip test are verified and adjusted by the test agent communication, thereby improving the efficiency of the chip functional level test. First, according to the first address information, the first data information is found according to the preset read data timing. When it is judged that the first data information is the preset first data threshold, it means that the chip has completed the test of the current output parameter and is in the chip idle state. At this time, by writing the second data threshold to the first address information according to the preset write data timing, it is used to indicate that the agent program communication state has been entered, and the output parameter can be adjusted. Then, the first output parameter and the first waveform information of the current chip test are obtained; according to the first output parameter, the second waveform information is generated according to the preset module configuration script; when the first waveform information and the second waveform information match each other, it means that the two use the same module configuration script, and the next output parameter test can be performed. Finally, according to the second output parameter, the third waveform information is produced according to the preset module configuration script for chip functional level test. By automatically checking the module configuration and switching the output parameters, the efficiency of the chip functional level test is improved.
[0141] According to an embodiment of the present invention, obtaining the first data information according to the first address information is specifically:
[0142] Sending a first enable signal;
[0143] Within a preset first time, determining whether a first feedback instruction is received;
[0144] If yes, obtain first read data and a first check code according to the first address information;
[0145] Obtaining a second check code according to the first read data and a preset check code calculation rule;
[0146] Determining whether the first verification code is the same as the second verification code;
[0147] If so, the first read data is the first data information.
[0148] It should be noted that the first enable signal is an enable signal used to notify the chip controller that a read operation is about to occur; the first feedback instruction is a response of the chip control interface to allow the read operation; the first read data is the data stored in the first address information location in the chip memory; the first check code is a check code generated by the chip based on the first read data; and the second check code is a check code generated by the test agent program based on the first read data.
[0149] As a read data timing, in this embodiment, first, a first enable signal is sent, and whether a read data operation can be performed is determined according to the response time of the first feedback instruction. Secondly, when the read data operation is allowed, the first read data and the first check code are obtained according to the first address information according to the reading rule. Then, according to the first read data, according to the preset check code generation rule, including but not limited to the cyclic redundancy check, the second check code is calculated. Finally, it is determined whether the first check code is the same as the second check code. If so, it indicates that the data transmission process is normal, and the first read data is undisturbed data, which can be identified as the first data information.
[0150] According to an embodiment of the present invention, writing a preset second data threshold according to the first address information is specifically:
[0151] Sending a second enable signal;
[0152] Within a preset first time, determining whether a second feedback instruction is received;
[0153] If yes, obtaining third verification code information according to the first address information and the second data threshold and a preset verification code calculation rule;
[0154] A first write instruction is generated and sent according to the first address information, the second data threshold and the third check code information.
[0155] It should be noted that the second enable signal is an enable signal used to notify the chip controller that a write operation is about to occur; the second feedback instruction is a response of the chip control interface to allow the write operation; the third verification code information is a verification code generated by the test agent program based on the write address and write data; the first write instruction is an instruction to write setting data to the chip setting address.
[0156] As a data writing sequence, in this embodiment, the second enable signal is first sent, and whether the data writing operation can be performed is determined according to the response time of the second feedback instruction. Then, when the data writing operation is allowed, the third check code is calculated according to the first address information and the second data threshold according to the preset check code generation rules, including but not limited to cyclic redundancy check. Finally, the first write instruction is generated according to the first address information, the second data threshold and the third check code information, and the second data threshold is written to the position of the first address information of the chip.
[0157] According to an embodiment of the present invention, determining the second waveform information according to the first output parameter is specifically:
[0158] Reading a configuration script file, and obtaining a first configuration parameter according to the configuration script file;
[0159] Determining an output interface according to the first output parameter;
[0160] According to the first output parameter and the first configuration parameter, second waveform information is obtained according to a preset waveform generation script.
[0161] It should be noted that, in this embodiment, the corresponding output waveform is generated according to the preset module configuration script based on the output parameters. First, the configuration script file is read to obtain the first configuration parameter of the configuration module of the functional test; wherein the configuration module includes but is not limited to clock, power supply, system control, etc. Then, according to the first output parameter, the output interface or pin of the output module is determined. Finally, the first output parameter and the first configuration parameter are passed into the waveform generation script to obtain the second waveform information for chip functional level testing.
[0162] According to an embodiment of the present invention, it also includes:
[0163] When it is determined that the first data information is not a preset first data threshold;
[0164] Get second time information;
[0165] Determining whether the second time information exceeds a preset time threshold;
[0166] If yes, send the preset reset command.
[0167] It should be noted that when the first data information is not the preset first data threshold, it means that the chip has not completed the test of the current output parameter and is in a busy state. In this embodiment, the time when the chip is in a busy state is recorded, that is, the second time information. When the second time information exceeds the preset time threshold, it means that the test running time exceeds the set range, and there is a risk of program running away or chip error. At this time, by sending a preset reset instruction, the chip is reset and in an idle state.
[0168] According to an embodiment of the present invention, it also includes:
[0169] Get output parameter list information;
[0170] The second output parameter is determined according to the output parameter list information and the first output parameter.
[0171] It should be noted that, in this embodiment, the output parameters of the output module in each output state during the chip function level test are stored through lists, scripts, etc. The output parameter list is searched according to the first output parameter. If the first output parameter is not the last output parameter in the output parameter list, it means that the output module has not been tested. At this time, the next output parameter in the output list is selected as the second output parameter.
[0172] It is worth mentioning that it also includes:
[0173] Obtaining second address information;
[0174] Obtaining first flag information according to the second address information;
[0175] Determine whether the first flag bit information is in a locked state;
[0176] If so, read and write operations of the preset address space are prohibited.
[0177] It should be noted that the second address information is the memory address for storing the first flag information in the chip; the first flag information is a flag indicating whether the chip is in a locked or unlocked state. In this embodiment, according to the second address information, the first flag information is found according to the preset read data timing. The first flag information is used to determine whether the chip is in a locked state. If so, it indicates that the chip is prohibited from writing data to the memory in the preset address space. Write protection is used to prevent the chip from being interfered with by communication during the test process.
[0178] It is worth mentioning that it also includes:
[0179] Obtaining second address information;
[0180] According to the second address information, a preset unlocking or locking instruction is sent to adjust the first flag bit information.
[0181] It should be noted that in this embodiment, according to the second address information and the unlock or lock flag, the first flag information is adjusted according to the preset write data timing to implement the chip unlock or lock operation, that is, to turn off or turn on the write protection function for the memory in the preset address space.
[0182] A third aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a RISC-V DSP chip test communication method program. When the RISC-V DSP chip test communication method program is executed by a processor, the steps of the RISC-V DSP chip test communication method as described in any one of the above items are implemented.
[0183] The present invention provides a RISC-V DSP chip test communication method, system and storage medium. Firstly, first data information is searched and obtained according to first address information and preset data reading rules; secondly, when the first data information is judged to be a preset first data threshold, a second data threshold is written into the first address information according to a preset data writing rule; then, second waveform information is obtained according to a first output parameter in the chip and a corresponding configuration script; finally, when the second waveform information is the same as the first waveform information in the chip, third waveform information is determined according to the second output parameter for chip function testing; the present invention improves the accuracy of data communication through preset data reading rules and data writing rules; and verifies and adjusts the output parameters of chip testing through test agent communication, thereby improving the efficiency of chip function level testing.
[0184] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0185] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A RISC-V DSP chip test communication method, characterized in that: The method comprises: Obtaining first address information; Obtaining first data information according to the first address information; Determining whether the first data information is a preset first data threshold; If yes, writing a preset second data threshold according to the first address information; Acquire first waveform information and first output parameter; Determining second waveform information according to the first output parameter; Determining whether the first waveform information matches the second waveform information; If yes, get the second output parameter; According to the second output parameter, third waveform information is determined.
2. A RISC-V DSP chip test communication method according to claim 1, characterized in that: The obtaining of the first data information according to the first address information is specifically: Sending a first enable signal; Within a preset first time, determining whether a first feedback instruction is received; If yes, obtain first read data and a first check code according to the first address information; Obtaining a second check code according to the first read data and a preset check code calculation rule; Determining whether the first verification code is the same as the second verification code; If so, the first read data is the first data information.
3. A RISC-V DSP chip test communication method according to claim 1, characterized in that: The step of writing a preset second data threshold according to the first address information is specifically: Sending a second enable signal; Within a preset first time, determining whether a second feedback instruction is received; If yes, obtaining third verification code information according to the first address information and the second data threshold and a preset verification code calculation rule; A first write instruction is generated and sent according to the first address information, the second data threshold and the third check code information.
4. A RISC-V DSP chip test communication method according to claim 1, characterized in that: The determining of the second waveform information according to the first output parameter is specifically: Reading a configuration script file, and obtaining a first configuration parameter according to the configuration script file; Determining an output interface according to the first output parameter; According to the first output parameter and the first configuration parameter, second waveform information is obtained according to a preset waveform generation script.
5. A RISC-V DSP chip test communication method according to claim 1, characterized in that: Also includes: When it is determined that the first data information is not a preset first data threshold; Get second time information; Determining whether the second time information exceeds a preset time threshold; If yes, a preset reset instruction is sent.
6. A RISC-V DSP chip test communication method according to claim 1, characterized in that: Also includes: Get output parameter list information; The second output parameter is determined according to the output parameter list information and the first output parameter.
7. A RISC-V DSP chip test communication system, characterized in that: The system includes a memory and a processor, wherein the memory includes a RISC-V DSP chip test communication method program, and when the RISC-V DSP chip test communication method program is executed by the processor, the following steps are implemented: Obtaining first address information; Obtaining first data information according to the first address information; Determining whether the first data information is a preset first data threshold; If yes, writing a preset second data threshold according to the first address information; Acquire first waveform information and first output parameter; Determining second waveform information according to the first output parameter; Determining whether the first waveform information matches the second waveform information; If yes, get the second output parameter; According to the second output parameter, third waveform information is determined.
8. A RISC-V DSP chip test communication system according to claim 7, characterized in that: The obtaining of the first data information according to the first address information is specifically: Sending a first enable signal; Within a preset first time, determining whether a first feedback instruction is received; If yes, obtain first read data and a first check code according to the first address information; Obtaining a second check code according to the first read data and a preset check code calculation rule; Determining whether the first verification code is the same as the second verification code; If so, the first read data is the first data information.
9. A RISC-V DSP chip test communication system according to claim 7, characterized in that: The step of writing a preset second data threshold according to the first address information is specifically: Sending a second enable signal; Within a preset first time, determining whether a second feedback instruction is received; If yes, obtaining third verification code information according to the first address information and the second data threshold and a preset verification code calculation rule; A first write instruction is generated and sent according to the first address information, the second data threshold and the third check code information.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer-readable storage medium includes a RISC-V DSP chip test communication method program. When the RISC-V DSP chip test communication method program is executed by a processor, the steps of the RISC-V DSP chip test communication method as described in any one of claims 1 to 6 are implemented.