Digital multi-beam phased array radar signal processing system and method, radar

Abstract

The present invention discloses a digital multi-beam phased array radar signal processing system and method, and a radar. The system comprises a signal preprocessing unit, a first signal processing unit, and a second signal processing unit. By adopting FPGA as a main control chip of multiple data fusion units in the signal preprocessing unit, adopting FPGA as a main control chip of the first signal processing unit, and adopting CPU as a main control chip of the second signal processing unit, the signal preprocessing unit, the first signal processing unit, and the second signal processing unit have their own division of labor. The primary DBF unit and the secondary DBF unit in the first signal processing unit are used to realize DBF signal processing of original IQ data to obtain a target beam signal. The second signal processing unit realizes signal processing of the target beam signal to obtain a target output signal, thereby being able to meet the real-time requirements of digital signal processing of large-scale antenna arrays, and reducing cost pressure while meeting performance indicators.

Description

Technical Field

[0001] The embodiments of the present invention relate to but are not limited to the technical field of digital phased array radar, and in particular to a digital multi-beam phased array radar signal processing system and method, and radar. Background Art

[0002] For digital phased array radar, as the size of the phased array increases, the number of transceiver units increases, the number of signal transceiver channels increases, and the amount of transceiver data increases dramatically. Radar is a real-time system, and data needs to be processed quickly, but the dramatic increase in data places stringent demands on data transmission links and data processing capabilities.

[0003] The existing system architecture is centralized processing, which uploads a large amount of data to the data processing server for centralized processing. Limited by the insufficient computing power of the DBF (Digital Beam Forming) unit and the signal processing unit under the current processing system architecture, it can no longer meet the data processing requirements of larger phased array radars. Even if the computing power is increased by increasing the number of CPUs (Central Processing Units), the physical complexity and processing time will increase greatly, the failure rate will be higher, and the cost will increase significantly.

[0004] As the array area increases, the number of receiving channels can reach thousands or even tens of thousands. Figure 1 As shown in the figure, the raw IQ data collected by a single DTR unit is already several hundred MB / S. The raw data of all channels combined can reach several hundred GB / S or even higher. General DBF units are composed of DSPs or MCUs that can perform multi-core parallel processing. Limited by the signal processing capabilities, when processing a large amount of data, most of the data reception and processing work can only be completed through a large number of DSPs or MCUs. The signal processing unit at the later stage generally uses the CPU for corresponding processing. The more data from the array, the more computing servers are needed for processing, resulting in high system complexity and greatly increased costs. After all, radar is a real-time system, and the actual detection results need to be generated quickly for customers, so data transmission and processing cannot take too long. A highly complex system brings greater processing delays, which is unacceptable for a real-time system.

[0005] In general, the existing signal processing system has the following disadvantages: 1. In the face of increasing array data, more and more powerful signal processing units are required, which greatly increases the cost. 2. Large amounts of data processing require more processing time, so that real-time performance cannot be guaranteed. 3. The working coupling between a large number of computing servers leads to complex hardware links, and the design and maintenance costs are very high. Summary of the invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The embodiments of the present invention provide a digital multi-beam phased array radar signal processing system and method, and radar, which can meet the real-time requirements of digital signal processing of large-scale antenna arrays, and can greatly reduce cost pressure while meeting performance indicators.

[0008] A first aspect of an embodiment of the present invention provides a digital multi-beam phased array radar signal processing system, comprising:

[0009] A signal preprocessing unit, composed of a plurality of data fusion units, each of which is composed of an FPGA, and is used to perform left and right channel data superposition on left and right multi-channel original IQ data received from a positive even number of sub-array units in an antenna array plane, to obtain superimposed array plane array IQ data;

[0010] At least one first signal processing unit, the first signal processing unit includes at least one primary DBF unit, at least one secondary DBF unit and a system management unit, the primary DBF unit, the secondary DBF unit and the system management unit all use FPGA as a main control chip, each secondary DBF unit is correspondingly connected to at least one primary DBF unit, each primary DBF unit is correspondingly connected to at least one data fusion unit, and the primary DBF unit and the secondary DBF unit are controlled by the system management unit; the primary DBF unit is used to perform weighted summation processing on the superimposed array IQ data to obtain a partial beam signal formed in the target direction; the secondary DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain a target beam signal;

[0011] The second signal processing unit is composed of a multi-core CPU and a 100G network card. The second signal processing unit is used to perform signal processing on the target beam signal to obtain a target output signal.

[0012] In some embodiments, the first signal processing unit also includes a single-chip microcomputer. After the system management unit starts running by loading an initialization program from the single-chip microcomputer, it receives a first target FPGA program and a second target FPGA program sent from the network, loads the first target FPGA program to the first-level DBF unit, so that the first-level DBF unit runs according to the first target FPGA program; and loads the second target FPGA program to the second-level DBF unit, so that the second-level DBF unit runs according to the second target FPGA program.

[0013] In some embodiments, the primary DBF unit is used to perform weighted sum processing on the superimposed IQ data of the array to obtain a partial beam signal formed in the target direction, specifically:

[0014] The first-level DBF unit obtains the weighting matrix sent by the system management unit;

[0015] The first-level DBF unit unpacks the superimposed array IQ data according to a preset protocol to obtain the unpacked array IQ data;

[0016] The first-level DBF unit performs a complex matrix multiplication operation of digital beam synthesis on the unpacked array IQ data and the weighting matrix to obtain the partial beam signal formed in the target direction, wherein the array IQ data and the weighting matrix are both complex matrices of order N, and N is a configurable positive integer.

[0017] In some embodiments, the main control chip FPGA of the first-level DBF unit includes a hardware TCP server and a hardware TCP client. The hardware TCP server and the hardware TCP client are both instantiated from a hardware TCP communication IP. The hardware TCP communication IP integrates TCP protocol, ARP protocol and ICMP protocol.

[0018] In some embodiments, the secondary DBF unit is used to perform spatial domain filtering on the partial beam signal to obtain a target beam signal, specifically:

[0019] The secondary DBF unit obtains the partial beam signal from the primary DBF unit by using the Aurora64b / 66b protocol;

[0020] The secondary DBF unit performs spatial domain filtering processing on the partial beam signal to obtain the target beam signal, wherein the spatial domain filtering processing includes superposition processing on the partial beam signal formed in the target direction.

[0021] In some embodiments, the second signal processing unit is used to perform signal processing on the target beam signal to obtain a target output signal, specifically:

[0022] The second signal processing unit divides the multi-core CPU into a first group CPU core and a second group CPU core according to a preset rule, wherein each CPU core in the first group CPU core is used to correspond to a 10 Gigabit receiving channel to receive the target beam signal, and the second group CPU core is used to perform signal processing on the target beam signal;

[0023] The first grouping CPU core receives the target beam signal through the QSFP interface provided by the 100G network card;

[0024] The second group CPU core performs signal processing on the target beam signal to obtain the target output signal, wherein the signal processing includes matched filtering and fast Fourier transform processing.

[0025] In some embodiments, each of the 100G network cards provides two QSFP interfaces, and the two QSFP interfaces respectively receive the target beam signals sent from the two secondary DBF units.

[0026] In some embodiments, each of the first-level DBF units processes the array IQ data sent from X data fusion units, where X is less than or equal to 4; and each of the second-level DBF units processes the partial beam signals sent from Y first-level DBF data, where Y is less than or equal to 8.

[0027] A second aspect of an embodiment of the present invention provides a radar, comprising the digital multi-beam phased array radar signal processing system as described in the first aspect.

[0028] A third aspect of an embodiment of the present invention provides a digital multi-beam phased array radar signal processing method, which is applied to the digital multi-beam phased array radar signal processing system as described in the first aspect, and the method includes:

[0029] Receiving, by the signal preprocessing unit, left and right multi-channel original IQ data sent from a positive even number of sub-array units in the antenna array plane;

[0030] The data fusion unit performs left and right channel data superposition on the left and right multiple-channel original IQ data to obtain superimposed array IQ data;

[0031] Performing weighted sum processing on the superimposed IQ data of the array face through the first-level DBF unit to obtain a partial beam signal;

[0032] The secondary DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain a target beam signal;

[0033] The target beam signal is processed by the second signal processing unit to obtain a target output signal.

[0034] The digital multi-beam phased array radar signal processing system and method and radar provided by the embodiment of the present invention, the digital multi-beam phased array radar signal processing system includes a signal preprocessing unit, at least one first signal processing unit and a second signal processing unit, wherein the signal preprocessing unit is composed of a plurality of data fusion units, the data fusion unit is composed of an FPGA, and the data fusion unit is used to perform left and right channel data superposition on the left and right multi-channel original IQ data received from a positive even number of sub-array units in the antenna array surface to obtain superimposed array surface array IQ data; the first signal processing unit includes at least one primary DBF unit, at least one secondary DBF unit and a system management unit, the primary DBF unit, the secondary DBF unit Both the secondary DBF unit and the system management unit use FPGA as the main control chip, each secondary DBF unit is connected to at least one primary DBF unit, each primary DBF unit is connected to at least one data fusion unit, and the primary DBF unit and the secondary DBF unit are controlled by the system management unit; the primary DBF unit is used to perform weighted summation processing on the superimposed array IQ data to obtain the partial beam signal formed in the target direction; the secondary DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain the target beam signal; the second signal processing unit is composed of a multi-core CPU and a 100G network card, and the second signal processing unit is used to perform signal processing on the target beam signal to obtain the target output signal. Based on this, by adopting FPGA as the main control chip of multiple data fusion units in the signal preprocessing unit, adopting FPGA as the main control chip of the first signal processing unit, and adopting CPU as the main control chip of the second signal processing unit, the signal preprocessing unit, the first signal processing unit and the second signal processing unit have their own division of labor. The multiple data fusion units in the signal preprocessing unit can superimpose the left and right channel data of the left and right multi-channel original IQ data to obtain the superimposed array IQ data, and can process multiple data streams in parallel, thereby greatly improving the utilization rate of channel resources. The first-level DBF unit and the second-level DBF unit in the first signal processing unit are used to realize DBF signal processing of the original IQ data to obtain the target beam signal. The second signal processing unit realizes signal processing of the target beam signal to obtain the target output signal. The first signal processing unit realizes digital beam synthesis by using FPGA for weighted summation processing. Since FPGA is used to realize digital beam synthesis calculation, the algorithm originally required to be implemented in the CPU is delegated to physical hardware for implementation, which can effectively reduce the data calculation delay caused by the traditional calculation method. Therefore, the calculation delay is greatly reduced, and the computing power per unit power consumption per unit time is improved. When there are more data processing requirements, it is only necessary to increase the number of first signal processing units.The digital multi-beam phased array radar signal processing system provided by the embodiment of the present invention is a heterogeneous digital signal processing computing system, which greatly reduces the difficulty and complexity of signal processing, and at the same time greatly saves the communication links required to transmit more data, reducing maintenance costs. It can not only meet the real-time requirements of digital signal processing of large-scale antenna arrays, but also greatly reduce cost pressure while meeting performance indicators.

[0035] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0037] Figure 1 Schematic diagram of the overall structure of the existing signal processing system;

[0038] Figure 2 A schematic diagram of the overall structure of a digital multi-beam phased array radar signal processing system provided by one embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the structure of a signal preprocessing unit provided by an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the structure of a first signal processing unit provided by an embodiment of the present invention;

[0041] Figure 5 A flow chart of a digital multi-beam phased array radar signal processing method provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification and claims and the following drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0044] In the embodiments of the present invention, the words "further", "exemplarily" or "optionally" are used to indicate examples, illustrations or descriptions, and should not be interpreted as being more preferred or more advantageous than other embodiments or designs. The use of the words "further", "exemplarily" or "optionally" is intended to present related concepts in a specific way.

[0045] First, several terms involved in the present invention are analyzed:

[0046] DBF: (Digital Beam Forming) digital beam synthesis;

[0047] DTR: (Digital Transmitter Receiver) digital transceiver system;

[0048] TR: (Transmitter Receiver) transceiver;

[0049] FFT: (Fast Fourier Transform) Fast Fourier Transform;

[0050] CPU: (Central Processing Unit) central processing unit;

[0051] DSP: (Digital Signal Process) digital signal processor;

[0052] FPGA: (Field Programmable Gate Array) field programmable gate array.

[0053] In order to more conveniently describe the working principle of the embodiment of the present invention later, an introduction to relevant technical scenarios is first given below.

[0054] Radars that use a fully digital phased array system use digital multi-beamforming technology and the same antenna aperture to transmit a wide beam, which can simultaneously form multiple independent receiving beams. They have the advantages of fast beam scanning, spatial orientation, spatial filtering, and spatial power synthesis capabilities, and can achieve multi-target detection and tracking. They can also achieve multi-target multi-point reconnaissance, interference, and detection according to mission planning, greatly improving the performance of the radar. Currently, digital phased array radars have certain applications in both military and civilian fields.

[0055] The digital phased array radar system is generally composed of an antenna unit, a TR unit, a DBF unit, and a signal processing unit. For the digital phased array radar receiving link, the antenna unit receives the reflected signal from the target and sends it to the TR unit for amplification and down-conversion to obtain an intermediate frequency signal. The intermediate frequency signal is digitized by the DTR component and transmitted to the DBF module through the transmission link for beam synthesis. The obtained beam signal is then sent to the signal processing unit for matching filtering, FFT and other processing. Generally, the DBF unit and signal processing can be regarded as a system module, collectively referred to as a digital signal processing module.

[0056] For digital phased array radar, as the size of the phased array increases, the number of transceiver units increases, the number of signal transceiver channels increases, and the amount of transceiver data increases dramatically. Radar is a real-time system, and data needs to be processed quickly, but the dramatic increase in data places stringent requirements on data transmission links and data processing capabilities.

[0057] The existing system architecture is centralized processing, which uploads a large amount of data to the data processing server for centralized processing. Limited by the insufficient computing power of the DBF unit and signal processing unit under the current processing system architecture, it can no longer meet the data processing requirements of larger phased array radars. Even if the computing power is increased by increasing the number of processors, the physical complexity and processing time will be greatly increased, the failure rate will be higher, and the cost will be greatly increased.

[0058] Phased array radar is a phase-controlled electronically scanned array radar that uses electronic scanning to quickly and accurately form a radar beam within a few microseconds.

[0059] As the array area increases, the number of receiving channels can reach thousands or even tens of thousands. Figure 1As shown in the figure, the raw IQ data collected by a single DTR unit is already several hundred MB / S. The raw data of all channels combined can reach several hundred GB / S or even higher. General DBF units are composed of DSPs or MCUs that can perform multi-core parallel processing. Limited by the signal processing capabilities, when processing a large amount of data, most of the data reception and processing work can only be completed through a large number of DSPs or MCUs. The signal processing unit at the later stage generally uses the CPU for corresponding processing. The more data from the array, the more computing servers are needed for processing, resulting in high system complexity and greatly increased costs. After all, radar is a real-time system, and the actual detection results need to be generated quickly for customers, so data transmission and processing cannot take too long. A highly complex system brings greater processing delays, which is unacceptable for a real-time system.

[0060] In general, the existing signal processing systems have the following shortcomings: 1. In the face of increasing array data, more and more powerful signal processing units are needed, which greatly increases the cost. 2. Large amounts of data processing require more processing time, so that real-time performance cannot be guaranteed. 3. The working coupling between a large number of computing servers leads to complex hardware links, and the design and maintenance costs are very high.

[0061] In order to solve the technical problem that the architecture of the existing signal processing system cannot meet the computing power requirements under the background of increasing radar data volume, the embodiments of the present invention provide a digital multi-beam phased array radar signal processing system and method, and radar, wherein the digital multi-beam phased array radar signal processing system includes a signal preprocessing unit, at least one first signal processing unit and a second signal processing unit, wherein the signal preprocessing unit is composed of a plurality of data fusion units, the data fusion unit is composed of FPGA, and the data fusion unit is used to perform left and right channel data superposition on the left and right multi-channel original IQ data received from a positive even number of sub-array units in the antenna array surface to obtain superimposed array surface array IQ data; the first signal processing unit includes at least one primary DBF unit, at least one secondary DB F unit and system management unit, the first-level DBF unit, the second-level DBF unit and the system management unit all use FPGA as the main control chip, each second-level DBF unit is connected to at least one first-level DBF unit, each first-level DBF unit is connected to at least one data fusion unit, and the first-level DBF unit and the second-level DBF unit are controlled by the system management unit; the first-level DBF unit is used to perform weighted summation processing on the superimposed array IQ data to obtain the partial beam signal formed in the target direction; the second-level DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain the target beam signal; the second signal processing unit is composed of a multi-core CPU and a 100G network card, and the second signal processing unit is used to perform signal processing on the target beam signal to obtain the target output signal. Based on this, by adopting FPGA as the main control chip of multiple data fusion units in the signal preprocessing unit, adopting FPGA as the main control chip of the first signal processing unit, and adopting CPU as the main control chip of the second signal processing unit, the signal preprocessing unit, the first signal processing unit and the second signal processing unit have their own division of labor. The multiple data fusion units in the signal preprocessing unit can superimpose the left and right channel data of the left and right multi-channel original IQ data to obtain the superimposed array IQ data, and can process multiple data streams in parallel, thereby greatly improving the utilization rate of channel resources. The first-level DBF unit and the second-level DBF unit in the first signal processing unit are used to realize DBF signal processing of the original IQ data to obtain the target beam signal. The second signal processing unit realizes signal processing of the target beam signal to obtain the target output signal. The first signal processing unit realizes digital beam synthesis by using FPGA for weighted summation processing. Since FPGA is used to realize digital beam synthesis calculation, the algorithm originally required to be implemented in the CPU is delegated to physical hardware for implementation, which can effectively reduce the data calculation delay caused by the traditional calculation method. Therefore, the calculation delay is greatly reduced, and the computing power per unit power consumption per unit time is improved. When there are more data processing requirements, it is only necessary to increase the number of first signal processing units.The digital multi-beam phased array radar signal processing system provided by the embodiment of the present invention is a heterogeneous digital signal processing computing system, which greatly reduces the difficulty and complexity of signal processing, and at the same time greatly saves the communication links required to transmit more data, reducing maintenance costs. It can not only meet the real-time requirements of digital signal processing of large-scale antenna arrays, but also greatly reduce cost pressure while meeting performance indicators.

[0062] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0063] like Figure 2 As shown, Figure 2 It is a structural schematic diagram of a digital multi-beam phased array radar signal processing system provided by an embodiment of the present invention. The digital multi-beam phased array radar signal processing system belongs to a heterogeneous digital signal processing system, which includes a signal preprocessing unit, at least one first signal processing unit and a second signal processing unit, wherein the signal preprocessing unit is composed of a plurality of data fusion units, the data fusion unit is composed of an FPGA, and the data fusion unit is used to perform left and right channel data superposition on the left and right multi-channel original IQ data received from a positive and even number of sub-array units in the antenna array, to obtain the superimposed array array IQ data; the first signal processing unit includes at least one primary DBF unit, at least one secondary DBF unit and a system management unit, and the primary DBF unit, the secondary DBF unit and the system management unit are all adopted FPGA is used as the main control chip. Each secondary DBF unit is connected to at least one primary DBF unit, and each primary DBF unit is connected to at least one data fusion unit. The primary DBF unit and the secondary DBF unit are controlled by the system management unit. The primary DBF unit is used to perform weighted summation processing on the superimposed array IQ data to obtain the partial beam signal formed in the target direction. The secondary DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain the target beam signal. The second signal processing unit is composed of a multi-core CPU and a 100G network card. The second signal processing unit is used to perform signal processing on the target beam signal to obtain the target output signal.

[0064] like Figure 2As shown, the signal preprocessing unit, signal processing unit 1 and signal processing unit 2 constitute a heterogeneous digital signal processing system. The heterogeneous digital signal processing system divides the array unit into scales. The antenna array is responsible for sending and receiving radar signals and converting data into original IQ data. The antenna array communicates with the signal preprocessing unit and transmits data, in which the data is preprocessed. This step will be completed in the radar head. The preprocessed data is reduced in size and then transmitted to the signal processing unit 1. Part of the DBF processing will be completed in the signal processing unit 1. Finally, the processed signal will be handed over to the signal processing unit 2 to complete the final pulse compression, FFT and other signal processing. This heterogeneous digital signal processing system splits the project originally completed by one unit into several steps, greatly reducing the difficulty and complexity of signal processing, and at the same time greatly saving the communication links required to transmit more data and reducing maintenance costs. It should be noted that when there are more data processing requirements, it is only necessary to increase the number of signal processing units 1.

[0065] like Figure 3 As shown, the signal preprocessing unit is composed of a multi-channel data fusion unit to realize the function of synthesizing multi-channel array data into one channel. The data fusion unit is mainly composed of FPGA. The original IQ data collected from the positive and even sub-array units is transmitted to the data fusion unit through the Aurora64b / 66b protocol. The data fusion unit realizes the left and right channel superposition of the left and right N channel IQ data (Channel_IQ), and the superimposed data satisfies the following formula:

[0066]

[0067] After superposition, the array IQ data (Array_IQ) is packaged and compressed. Through time division multiplexing, a pulse data waveform is transmitted, so that multiple data streams can be processed in parallel, greatly improving the utilization of channel resources. In order to ensure data correctness and no omissions, the hardware TCP client IP is implemented in the data fusion unit. This IP fully implements the TCP communication protocol and integrates ARP, ICMP and other functions. The communication bandwidth can reach 10Gdps, which can transmit data stably and quickly.

[0068] like Figure 4 As shown, the signal processing unit 1 is composed of three sub-units: a primary DBF unit, a secondary DBF unit, and a system management unit. The primary DBF unit and the secondary DBF unit in the signal processing unit 1 are function execution components, and the system management unit is the main control and monitoring unit. It should be noted that the number of the primary DBF unit and the secondary DBF unit in the signal processing unit 1 can be configured according to actual data processing requirements.

[0069] It is understandable that the system management unit communicates over the network through an independent 10GQSFP, and implements the FreeRTOS system in the FPGA of the system management unit to operate and manage the entire signal processing unit 1. In order to reduce the risk of program leakage and maintain program security, when the digital signal processing system is started, the system management unit will first load itself through the single-chip microcomputer. The system management unit's own program is encrypted and stored in an external Flash. After the single-chip microcomputer decrypts the program, it completes the loading of the FPGA of the system management unit through the JTAG interface. When the system management unit is running, it receives the FPGA program of the first-level DBF unit and the second-level DBF unit through the network to load the program into the first-level DBF unit and the second-level DBF unit. The system management unit can realize the simultaneous loading of different programs of multiple FPGAs through the hardware JTAG interface, which greatly improves the initialization speed. In addition, the programs are all issued by the network, and the program files will no longer be retained locally, which fundamentally prevents the leakage of core programs.

[0070] In one embodiment, the microcontroller loading method can use Flash to store the bin file of FPGA, and encrypt, CRC check, and back up the bin file data in Flash; FPGA loads the hardware IP of other FPGAs, sends the bin file of FPGA through the network, and then loads the other FPGAs through FPGA. Program files do not need to be saved locally, which can greatly reduce the risk of program leakage.

[0071] It can be understood that the first-level DBF unit and the second-level DBF unit are the core computing components of the signal processing unit 1. The first-level DBF unit receives the fused original array IQ data from the data fusion module, and can be restored to the original array IQ data (Array_IQ) after protocol unpacking. The DBF operation is performed in order to form a receiving beam in the desired direction by means of digital signals using the aperture of the array antenna in the case of omnidirectional array antenna reception. In the first step of DBF processing, the data needs to be weighted and summed, because the input radar data is an N-order complex matrix. Weighted processing requires complex multiplication of this N-order matrix and the weighted matrix to obtain a partial beam signal (Part_Beam_IQ). The implementation algorithm is as follows:

[0072]

[0073] The weighted matrix is ​​also an N-order complex matrix, which is sent from the network by the system management unit and then sent to the first-level DBF unit via Aurora8b / 10b. The order of the calculated complex matrix can be modified according to actual needs, which can reduce many useless calculations and improve calculation efficiency. If the CPU is used to process large complex matrix multiplication, it will consume a lot of system resources and the speed is slow. Using FPGA to implement the entire DBF matrix weighted operation process through hardware can save a lot of CPU system resources. At the same time, because FPGA can perform multiple parallel calculations, it can get results faster, thereby greatly reducing the calculation time.

[0074] The secondary DBF unit performs spatial filtering on the signal after the primary DBF unit completes the matrix weighting operation. The data operation satisfies the following formula:

[0075]

[0076] That is, the signals in the desired direction are superimposed to maximize the energy in the desired direction, thereby obtaining the desired beam signal (Beam_IQ). After the data is processed, the secondary DBF unit needs to transmit the data to the signal processing unit 2.

[0077] It can be understood that both the primary DBF unit and the secondary DBF unit are functional components with FPGA as the core. The primary DBF unit implements the hardware TCP server IP, which fully implements the TCP communication protocol and integrates functions such as ARP and ICMP. The communication bandwidth can reach 10Gdps and can stably and quickly receive data content from the client. The Aurora64b / 66b protocol can be used for data transmission between the primary DBF unit and the secondary DBF unit. The secondary DBF unit implements four 10GSFP communications to QSFP communications, so that the secondary DBF unit can provide higher bandwidth to transmit data to the signal processing unit 2 faster.

[0078] It can be understood that the signal processing unit 2 is composed of a multi-core CPU and a 100G network card. The 10G network card provides a 10G communication network port connected to the signal processing unit 1. A 100G network card can provide two QSFP interfaces, which can receive data from two secondary DBFs. The multi-core CPU can be divided into two groups, in which each core of one group corresponds to a 10G receiving channel to avoid mutual interference in data reception and improve stability. The CPU core of the other group can be used to perform related data processing including matched filtering, FFT, etc. It should be noted that the signal processing unit 2 can also save the corresponding data results.

[0079] It should be noted that, in order to target different types of radars, one data fusion unit can support the transmission and reception of two antenna arrays, one first-level DBF unit can support the data upload processing requirements of up to four data fusion units, and one second-level DBF unit can also support up to eight first-level DBF data upload processing requirements. With different channel requirements, only the corresponding processing unit needs to be added.

[0080] It can be understood that the present invention adopts FPGA+CPU architecture to realize signal processing of digital multi-beam phased array radar. FPGA is used as the main control chip of signal processing unit 1, and CPU is used as the main control chip of signal processing unit 2. The two signals have clear division of labor: the first-level DBF unit and the second-level DBF unit in signal processing unit 1 realize DBF signal processing of original IQ data, and signal processing unit 2 realizes pulse compression of beam signal, and FFT and other operations, and can save the corresponding data results.

[0081] It can be understood that the digital multi-beam phased array radar signal processing system of the present invention includes multiple data fusion modules, multiple signal processing units 1 and a signal processing unit 2. When the scale of the radar phased array increases, the corresponding signal processing requirements can be achieved by adding data fusion units and signal processing units 1. The distributed signal processing method can effectively reduce the complexity of the entire signal processing system and effectively reduce cost pressure.

[0082] It can be understood that for the signal processing unit 1, it uses FPGA to implement DBF complex matrix operations, and its operation order can be adjusted in real time according to actual needs. The maximum data processing bandwidth is 40.96Gdps. The use of FPGA to implement DBF calculations greatly reduces the calculation delay and improves the calculation capacity per unit power consumption per unit time. When there are more data processing requirements, only the signal processing unit 1 needs to be added.

[0083] It can be understood that for the data fusion unit and the signal processing unit 1, FPGA is used to implement the 10G TCP communication IP, and the communication bandwidth can reach 10Gdps. This IP not only implements the TCP protocol, but also integrates ARP, ICMP and other functions to ensure stable and reliable data transmission and the convenience of debugging and testing.

[0084] It can be understood that the present invention adopts FPGA+CPU architecture to realize signal processing of digital multi-beam phased array radar. The signal preprocessing unit and the signal processing unit 1 use FPGA as the main core component, and the algorithm that originally needs to be implemented in the CPU is decentralized to physical hardware for implementation, which can effectively reduce the data delay caused by traditional calculation methods. The physical implementation of a large number of complex matrix operations further improves the computing power per unit power consumption.

[0085] It can be understood that the present invention reduces the use of peripheral network communication devices and the complexity of physical connections through the implementation of 10G hardware TCP communication IP, while improving device reliability and alleviating the pressure on bandwidth in data communication, thereby achieving greater efficiency in real-time communication with less resource usage.

[0086] An embodiment of the present invention further provides a radar, which includes the above-mentioned digital multi-beam phased array radar signal processing system.

[0087] In one embodiment, since the radar adopts the above-mentioned digital multi-beam phased array radar signal processing system, the radar can achieve the same technical effect as the above-mentioned digital multi-beam phased array radar signal processing system. The digital multi-beam phased array radar signal processing system includes a signal preprocessing unit, at least one first signal processing unit and a second signal processing unit, wherein the signal preprocessing unit is composed of a plurality of data fusion units, the data fusion unit is composed of FPGA, and the data fusion unit is used to perform left and right channel data superposition on the left and right multi-channel original IQ data received from the positive and even sub-array units in the antenna array surface to obtain the superimposed array surface array IQ data; the first signal processing unit includes at least one primary DBF unit, at least one secondary DBF unit and a system management unit, and the primary DBF unit, the secondary DBF unit and the system management unit all use FPGA as Main control chip, each secondary DBF unit is connected to at least one primary DBF unit, each primary DBF unit is connected to at least one data fusion unit, and the primary DBF unit and the secondary DBF unit are controlled by the system management unit; the primary DBF unit is used to perform weighted summation processing on the superimposed array IQ data to obtain the partial beam signal formed in the target direction; the secondary DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain the target beam signal; the second signal processing unit is composed of a multi-core CPU and a 100G network card, and the second signal processing unit is used to perform signal processing on the target beam signal to obtain the target output signal. Based on this, by adopting FPGA as the main control chip of multiple data fusion units in the signal preprocessing unit, adopting FPGA as the main control chip of the first signal processing unit, and adopting CPU as the main control chip of the second signal processing unit, the signal preprocessing unit, the first signal processing unit and the second signal processing unit have their own division of labor. The multiple data fusion units in the signal preprocessing unit can superimpose the left and right channel data of the left and right multi-channel original IQ data to obtain the superimposed array IQ data, and can process multiple data streams in parallel, thereby greatly improving the utilization rate of channel resources. The first-level DBF unit and the second-level DBF unit in the first signal processing unit are used to realize DBF signal processing of the original IQ data to obtain the target beam signal. The second signal processing unit realizes signal processing of the target beam signal to obtain the target output signal. The first signal processing unit realizes digital beam synthesis by using FPGA for weighted summation processing. Since FPGA is used to realize digital beam synthesis calculation, the algorithm originally required to be implemented in the CPU is delegated to physical hardware for implementation, which can effectively reduce the data calculation delay caused by the traditional calculation method. Therefore, the calculation delay is greatly reduced, and the computing power per unit power consumption per unit time is improved. When there are more data processing requirements, it is only necessary to increase the number of first signal processing units.The digital multi-beam phased array radar signal processing system provided by the embodiment of the present invention is a heterogeneous digital signal processing computing system, which greatly reduces the difficulty and complexity of signal processing, and at the same time greatly saves the communication links required to transmit more data, reducing maintenance costs. It can not only meet the real-time requirements of digital signal processing of large-scale antenna arrays, but also greatly reduce cost pressure while meeting performance indicators.

[0088] like Figure 5 As shown, an embodiment of the present invention further provides a digital multi-beam phased array radar signal processing method, which can be applied to the above-mentioned digital multi-beam phased array radar signal processing system, and the method includes but is not limited to the following steps:

[0089] Step S101: receiving left and right multi-channel original IQ data sent from a positive even number of sub-array units in an antenna array plane through a signal preprocessing unit;

[0090] Step S102: superimposing left and right channel data of the left and right multi-channel original IQ data by a data fusion unit to obtain superimposed array IQ data;

[0091] Step S103: performing weighted summation processing on the superimposed array IQ data through a first-level DBF unit to obtain a partial beam signal;

[0092] Step S104: performing spatial filtering processing on part of the beam signals through a secondary DBF unit to obtain a target beam signal;

[0093] Step S105: performing signal processing on the target beam signal by the second signal processing unit to obtain a target output signal.

[0094] In this embodiment, the signal preprocessing unit receives the left and right multi-channel original IQ data sent from the positive even number of sub-array units in the antenna array; the data fusion unit superimposes the left and right channel data of the left and right multi-channel original IQ data to obtain the superimposed array array IQ data; the first-level DBF unit performs weighted summation processing on the superimposed array array IQ data to obtain a partial beam signal; the second-level DBF unit is used to perform spatial domain filtering processing on the partial beam signal to obtain the target beam signal; the second signal processing unit performs signal processing on the target beam signal to obtain the target output signal. The digital multi-beam phased array radar signal processing method of the embodiment of the present invention can meet the real-time requirements of digital signal processing of large-scale antenna arrays, and can greatly reduce cost pressure while meeting performance indicators.

[0095] Based on this, by adopting FPGA as the main control chip of the first signal processing unit, by adopting FPGA as the main control chip of multiple data fusion units in the signal preprocessing unit, and adopting CPU as the main control chip of the second signal processing unit, the signal preprocessing unit, the first signal processing unit and the second signal processing unit have their own division of labor. The multiple data fusion units in the signal preprocessing unit can superimpose the left and right channel data of the original IQ data collected from the positive even number of sub-array units to obtain the superimposed array IQ data, and can process multiple data streams in parallel, thereby greatly improving the utilization rate of channel resources. The primary DBF unit and the secondary DBF unit in the first signal processing unit are used to realize DBF signal processing of the original IQ data to obtain the target beam signal. The second signal processing unit realizes signal processing of the target beam signal to obtain the target output signal. The first signal processing unit realizes digital beam synthesis by using FPGA for weighted summation processing. Since FPGA is used to realize digital beam synthesis calculation, the algorithm that originally needs to be implemented in the CPU is transferred to physical hardware for implementation, which can effectively reduce the data calculation delay caused by the traditional calculation method. Therefore, the calculation delay is greatly reduced, and the computing power per unit power consumption per unit time is improved. When there are more data processing requirements, it is only necessary to increase the number of first signal processing units. The digital multi-beam phased array radar signal processing system provided by the embodiment of the present invention is a heterogeneous digital signal processing and computing system, which greatly reduces the difficulty and complexity of signal processing, and at the same time greatly saves the communication links required to transmit more data, reducing maintenance costs.

[0096] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions under the shared conditions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A digital multi-beam phased array radar signal processing system, characterized in that: include: A signal preprocessing unit, composed of a plurality of data fusion units, each of which is composed of an FPGA, and is used to perform left and right channel data superposition on left and right multi-channel original IQ data received from a positive even number of sub-array units in an antenna array plane, to obtain superimposed array plane array IQ data; At least one first signal processing unit, the first signal processing unit includes at least one primary DBF unit, at least one secondary DBF unit, a system management unit and a single chip microcomputer. After the single chip microcomputer loads an initialization program and starts to run, the system management unit receives a first target FPGA program and a second target FPGA program issued by the network, loads the first target FPGA program to the primary DBF unit, so that the primary DBF unit runs according to the first target FPGA program; and loads the second target FPGA program to the secondary DBF unit, so that the secondary DBF unit runs according to the second target FPGA program; the primary DBF unit, the secondary DBF unit and the system management unit all use FPGA as a main control chip, each of the secondary DBF units is correspondingly connected to at least one primary DBF unit, each of the primary DBF units is correspondingly connected to at least one data fusion unit, and the primary DBF unit and the secondary DBF unit are controlled by the system management unit; the primary DBF unit is used to perform weighted summation processing on the superimposed IQ data of the array to obtain a partial beam signal formed in the target direction; The secondary DBF unit is used to perform spatial domain filtering on the partial beam signal to obtain a target beam signal; The second signal processing unit is composed of a multi-core CPU and a 100G network card. The second signal processing unit is used to perform signal processing on the target beam signal to obtain a target output signal.

2. The digital multi-beam phased array radar signal processing system according to claim 1, characterized in that: The first-level DBF unit is used to perform weighted summation processing on the superimposed IQ data of the array to obtain a partial beam signal formed in the target direction, specifically: The first-level DBF unit obtains the weighting matrix sent by the system management unit; The first-level DBF unit unpacks the superimposed array IQ data according to a preset protocol to obtain the unpacked array IQ data; The first-level DBF unit performs a complex matrix multiplication operation of digital beam synthesis on the unpacked array IQ data and the weighting matrix to obtain the partial beam signal formed in the target direction, wherein the array IQ data and the weighting matrix are both complex matrices of order N, and N is a configurable positive integer.

3. The digital multi-beam phased array radar signal processing system according to claim 1, characterized in that: The main control chip FPGA of the data fusion unit and the first-level DBF unit includes a hardware TCP server and a hardware TCP client. The hardware TCP server and the hardware TCP client are both instantiated from a hardware TCP communication IP. The hardware TCP communication IP integrates the TCP protocol, the ARP protocol and the ICMP protocol.

4. The digital multi-beam phased array radar signal processing system according to claim 1, characterized in that: The secondary DBF unit is used to perform spatial domain filtering on the partial beam signal to obtain the target beam signal, specifically: The secondary DBF unit obtains the partial beam signal from the primary DBF unit by using the Aurora64b / 66b protocol; The secondary DBF unit performs spatial domain filtering processing on the partial beam signal to obtain the target beam signal, wherein the spatial domain filtering processing includes superposition processing on the partial beam signal formed in the target direction.

5. The digital multi-beam phased array radar signal processing system according to claim 1, characterized in that: The second signal processing unit is used to perform signal processing on the target beam signal to obtain a target output signal, specifically: The second signal processing unit divides the multi-core CPU into a first group CPU core and a second group CPU core according to a preset rule, wherein each CPU core in the first group CPU core is used to correspond to a 10 Gigabit receiving channel to receive the target beam signal, and the second group CPU core is used to perform signal processing on the target beam signal; The first grouping CPU core receives the target beam signal through the QSFP interface provided by the 100G network card; The second group CPU core performs signal processing on the target beam signal to obtain the target output signal, wherein the signal processing includes matched filtering and fast Fourier transform processing.

6. The digital multi-beam phased array radar signal processing system according to claim 1, characterized in that: Each of the 100G network cards provides two QSFP interfaces, and the two QSFP interfaces respectively receive the target beam signals sent from the two secondary DBF units.

7. The digital multi-beam phased array radar signal processing system according to claim 1, characterized in that: Each of the first-level DBF units processes the array IQ data sent by X data fusion units, where X is less than or equal to 4; each of the second-level DBF units processes the partial beam signals sent by Y first-level DBF data, where Y is less than or equal to 8.

8. A radar, characterized in that: It comprises a digital multi-beam phased array radar signal processing system as described in any one of claims 1 to 7.

9. A digital multi-beam phased array radar signal processing method, characterized in that: Applied to the digital multi-beam phased array radar signal processing system according to any one of claims 1 to 7, the method comprising: Receiving, by the signal preprocessing unit, left and right multi-channel original IQ data sent from a positive even number of sub-array units in the antenna array plane; The data fusion unit performs left and right channel data superposition on the left and right multiple-channel original IQ data to obtain superimposed array IQ data; Performing weighted sum processing on the superimposed IQ data of the array face through the first-level DBF unit to obtain a partial beam signal; The secondary DBF unit is used to perform spatial filtering processing on the partial beam signal to obtain a target beam signal; The target beam signal is processed by the second signal processing unit to obtain a target output signal.

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