Opus correction method

Abstract

The present application provides an OPC correction method, which comprises: providing a target layer pattern and a mask pattern, each side of the target layer pattern is within the range represented by the mask pattern and can freely move within the range; in the model-based OPC correction process, no mask design rule is set, so that the target layer pattern freely moves within the range represented by the mask pattern until the expected simulation size is reached, and the target mask pattern is selected; the target mask pattern is subjected to an angle removal treatment, and the target mask pattern after the angle removal treatment is measured to evaluate whether it violates the mask design rule, if it violates the mask design rule, the angle removal treatment is continuously performed, if it does not violate the mask design rule, the target mask pattern is subjected to model simulation and evaluated whether it reaches the expected simulation size of the target layer pattern. The present application solves the problem that the existing OPC correction iteration process is easy to violate the mask design rule.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly to an OPC correction method. BACKGROUND

[0002] In the semiconductor manufacturing process, due to the optical proximity effect, the photolithography exposure will produce pattern distortion, including corner-rounding, line end shorten and inter-pattern proximity. The optical proximity correction (OPC) is to correct the pattern distortion caused by the optical interference and diffraction effect, so the OPC becomes an indispensable link in the semiconductor manufacturing process. With the reduction of the semiconductor manufacturing process node, especially for the process node below 14nm, the critical dimension of the pattern approaches the lithography limit, and the pattern structure is relatively more complex, so the OPC correction is facing a great challenge.

[0003] The via layer plays a role of connecting the upper and lower layers in chip manufacturing, and is generally used for the interconnection of MOS structure and the interconnection of metal layer. With the reduction of the process node, the MOS structure unit is compact, and the minimum line width and space of the via layer process will also be reduced. The staggered structure is a common structure of the via layer, and its typical feature is that the angle-to-angle space between patterns is generally less than 20nm. The OPC correction is essentially an iterative process, and the predicted contour is infinitely close to the target value through model simulation. In the correction process, the mask design rule (MRC) is artificially set, including the mask resolution minimum critical dimension (CD) and the mask resolution minimum space, and the setting principle of the MRC is generally determined by the process node. For the staggered via structure in the OPC correction, due to the very small space between patterns, the OPC correction space is very limited, and generally after several iteration cycles, the MRC will be violated. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an OPC correction method for solving the problem that the existing OPC correction iteration process is easy to violate the mask design rule.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides an OPC correction method, which comprises:

[0006] providing densely staggered target layer patterns and mask plate patterns, wherein the target layer patterns and the mask plate patterns have the same shape, and each side of the target layer patterns is within the range represented by the mask plate patterns and can be freely moved within the range;

[0007] In the model-based OPC correction process, no mask design rule is set, so that the target layer pattern is free to move within the range represented by the mask pattern until the expected simulation size is reached, and the target mask pattern is selected, wherein the target mask pattern is a pattern that violates the mask design rule;

[0008] The target mask pattern is subjected to an angle removal process, and the target mask after the angle removal process is measured to evaluate whether it violates the mask design rule. If it violates the mask design rule, the angle removal process is continued. If it does not violate the mask design rule, the target mask is simulated and evaluated to determine whether it reaches the expected simulation size of the target layer pattern.

[0009] The mask design rule includes a mask resolution minimum critical dimension and a mask resolution minimum pitch. The critical dimension of the target mask pattern is smaller than the mask resolution minimum critical dimension, and the pitch is smaller than the mask resolution minimum pitch, which is a violation of the mask design rule.

[0010] Optionally, the target layer pattern and the mask pattern are square patterns, and the target layer pattern is used to form a via on a wafer.

[0011] Optionally, the densely staggered target layer pattern and the mask pattern are multiple rows and multiple columns of the target layer pattern and the mask pattern staggered, and adjacent next row target layer pattern / mask pattern and previous row target layer pattern / mask pattern are on the same angle line.

[0012] Optionally, the pitch between the next row mask pattern and the adjacent previous row mask pattern is less than 20 nm.

[0013] Optionally, if the mask design rule is violated, the method of continuing the angle removal process includes:

[0014] The angle removal size is increased by 1 nm to obtain a new angle removal size, and the target mask is processed with the new angle removal size. The angle removal process of the target mask is to remove the four corners of the target mask, and the removed corners are isosceles triangles, and the length of the edge at the vertex is the angle removal size.

[0015] Optionally, the mask design rule is determined by the process node.

[0016] Optionally, for a 14 nm process node, the mask resolution minimum critical dimension has a value of 18 nm, and the mask resolution minimum pitch has a value of 12 nm.

[0017] Optionally, for the target mask pattern meeting the mask design rule, model simulation is performed on the target mask pattern, and whether the simulation profile, PVband and Meef meet the requirements is checked. If yes, the final required target mask pattern and its corresponding de-angulation size are obtained.

[0018] Optionally, the model-based OPC correction includes multiple iteration loop operations.

[0019] As described above, the OPC correction method of the present application takes the dense staggered structure of the via layer as the research object, and proposes to solve the MRC problem by de-angulating the mask pattern. In the implementation process, the target layer pattern is first subjected to conventional MBOPC correction, and no MRC parameter is set in the correction process, so that the target layer pattern is moved to the ideal position; then the mask pattern violating the MRC is selected and repaired; and the mask pattern is de-angulated by selecting a suitable de-angulation size, the purpose of which is to eliminate the MRC; the selection of the de-angulation size is determined by the results of model simulation, the gradient control de-angulation size changes from 0 to a certain value until the MRC is not violated, and at this time the model simulation size is close to the target size, thereby solving the problem of violating the MRC in the correction process. By repairing and optimizing the de-angulation size of the mask pattern, the simulation profile of the exposure pattern is not only on-target, but also meets the production requirements of pvband and meef under the condition of PW (process window). BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A flowchart of the OPC correction method of the present application is shown.

[0021] Figure 2 A schematic diagram of the target layer pattern of the present application is shown.

[0022] Figure 3 A schematic diagram of the mask pattern of the present application is shown.

[0023] Figure 4 A schematic diagram of the de-angulation size control of the present application is shown.

[0024] Figure 5 A schematic diagram of the mask pattern corresponding to different de-angulation sizes of the present application is shown. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described below through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied through other different embodiments, and various modifications or changes can be made to the details in the present specification without departing from the spirit of the present application.

[0026] Referring to Figures 1 to 5 It is to be understood that the figures provided in the embodiments are only schematic and that the actual implementation of the application can vary from the schematic illustrations as shown and described herein, and that the geometrical shapes and their relative sizing and proportions of the various elements illustrated in the figures are not necessarily drawn to scale, and that the actual implementation of the application can vary from the schematic illustrations as shown and described herein.

[0027] As shown in Figure 1 The embodiment provides an OPC correction method, which comprises the following steps:

[0028] Providing densely staggered target layer patterns and mask patterns, wherein the target layer patterns and the mask patterns have the same shape, and each side of the target layer patterns is within the range represented by the mask patterns and can freely move within the range;

[0029] In the model-based OPC correction process, no mask design rule is set, so that the target layer patterns freely move within the range represented by the mask patterns until the expected simulation size is reached, and a target mask pattern is selected, wherein the target mask pattern is a pattern that violates the mask design rule;

[0030] The target mask pattern is subjected to an angle removal process, and the target mask after the angle removal process is measured to evaluate whether it violates the mask design rule. If the mask design rule is violated, the angle removal process is continued. If the mask design rule is not violated, the target mask is subjected to model simulation and evaluated whether it reaches the expected simulation size of the target layer pattern.

[0031] The mask design rule includes a mask resolution minimum critical dimension and a mask resolution minimum pitch. The critical dimension of the target mask pattern is smaller than the mask resolution minimum critical dimension, and the pitch is smaller than the mask resolution minimum pitch, which is a violation of the mask design rule.

[0032] Specifically, the target layer pattern and the mask pattern are square patterns, and the target layer pattern is used to form a via on a wafer.

[0033] Specifically, the densely staggered target layer patterns and mask patterns are multiple rows and multiple columns of staggered target layer patterns and mask patterns, and adjacent next row target layer patterns / mask patterns and previous row target layer patterns / mask patterns are on the same corner line.

[0034] Specifically, the pitch between the next row mask pattern and the adjacent previous row mask pattern is less than 20 nm.

[0035] Specifically, if the mask design rules are violated, the method for continuing the decornening process includes: increasing the decornening size in increments of 1nm to obtain a new decornening size, and processing the target mask with the new decornening size. The decornening process of the target mask involves removing the four corners of the target mask, and the removed corners are isosceles triangles with the length of the side containing the vertex being the decornening size.

[0036] Specifically, the mask design rules are determined by the process nodes.

[0037] Specifically, for the 14nm process node, the minimum critical dimension of the mask resolution is 18nm, and the minimum spacing of the mask resolution is 12nm.

[0038] Specifically, for a target mask pattern that meets the mask design rules, a model simulation is performed, and the simulation contour, PVband, and Meef are checked to see if they meet the requirements. If they do, the final target mask pattern and its corresponding decornering dimensions are obtained.

[0039] In this embodiment, PVband is the process fluctuation bandwidth value, and Meef is the mask error enhancement factor.

[0040] Specifically, model-based OPC correction involves multiple iterative loop operations.

[0041] like Figures 2 to 5 As shown, in this embodiment, taking the 14nm node as an example, the minimum critical size of the mask resolution based on the model-based OPC (MBOPC) mask design rule (MRC) is set to 18nm, and the minimum mask resolution pitch is set to 12nm. Using a staggered aperture structure with a diagonal pitch of 110nm (where 67*1.414+15.4=110nm), a target layer pattern size of 67nm, and a diagonal pitch of 15.4nm as the research object, the edges of the target mask pattern are processed in three segments, and the corner removal dimensions are adjusted to 0nm, 5nm, 10nm, 15nm, and 20nm respectively to study the influence of different corner removal dimensions on the mask design rule. In the case of no segmentation (i.e., when the corner removal dimension is 0nm), Figure 3The size of the target mask pattern is 70.9 nm*73.6 nm, and the space between the target mask patterns is 8.8 nm, which is less than the set MRC space 12 nm, violating the mask pattern design rule space 12 nm. When the de- cornering size is 0 nm, the space between the target mask patterns is only 8.8 nm, violating the MRC. The purpose of de-cornering repair of the target mask pattern is to solve the MRC problem, while meeting the contour / pw cd / PV band / Meef parameters equivalent to the target target mask pattern, that is, the contour is allowed to change + / - 1.0 nm, the pw cd / PV band changes + / - 0.5 nm, and the Meef <= 4.5. In addition, the larger the space between the target mask patterns is, the better. When the de-cornering size of the target mask pattern is 5 nm, the space between the target mask patterns increases to 15.2 nm, the simulation size under normal conditions is 68.6 nm, the process window exposure dose is reduced by 4%, the pw cd is 64 nm when the focus plane is moved up by 35 nm, the PV band is 3.9 nm, and the Meef is 4.1 nm. Compared with the un-repaired target mask pattern, the contour cd is increased by 1.4 nm, and the pw cd is increased by 1.5 nm. When the de-cornering size of the target mask pattern is 7 nm, the space between the target mask patterns increases to 18.1 nm, the simulation size under normal conditions is 67.3 nm, the process window exposure dose is reduced by 4%, the pw cd is 62.5 nm when the focus plane is moved up by 35 nm, the PV band is 4.0 nm, and the Meef is 4.2 nm. The parameters are almost equivalent to those of the un-repaired target mask pattern. Therefore, 7 nm is the best de-cornering length. When the de-cornering size of the target mask pattern is 15 nm, the space between the target mask patterns increases to 30.02 nm, the simulation size under normal conditions is 55.2 nm, the process window exposure dose is reduced by 4%, the pw cd is 48.5 nm when the focus plane is moved up by 35 nm, the PV band is 5.5 nm, and the Meef is 5.6 nm. Compared with the un-repaired target mask pattern, the simulation parameters differ greatly and cannot meet the production requirements. Table 1 provides the simulation results under different de-cornering sizes.

[0042] Table 1:

[0043]

[0044] Figure 5 In the figure, the light blue square box represents the target value after the target layer pattern moves freely, the entire purple area represents the target mask pattern, and the red circle represents the simulation contour. From Figure 3 It can be seen from the figure that when the de-cornering length is 0 nm, the space between the target mask patterns is only 8.8 nm, violating the MRC. The purpose of de-cornering repair of the target mask pattern is to solve the MRC problem, while meeting the contour / pw cd / PV band / Meef parameters equivalent to the target target mask pattern, that is, the contour is allowed to change + / - 1.0 nm, the pw cd / PV band changes + / - 0.5 nm, and the Meef <= 4.5. In addition, the larger the space between the target mask patterns is, the better. When the de-cornering size of the target mask pattern is 5 nm, the space between the target mask patterns increases to 15.2 nm, the simulation size under normal conditions is 68.6 nm, the process window exposure dose is reduced by 4%, the pw cd is 64 nm when the focus plane is moved up by 35 nm, the PV band is 3.9 nm, and the Meef is 4.1 nm. Compared with the un-repaired target mask pattern, the contour cd is increased by 1.4 nm, and the pw cd is increased by 1.5 nm. When the de-cornering size of the target mask pattern is 7 nm, the space between the target mask patterns increases to 18.1 nm, the simulation size under normal conditions is 67.3 nm, the process window exposure dose is reduced by 4%, the pw cd is 62.5 nm when the focus plane is moved up by 35 nm, the PV band is 4.0 nm, and the Meef is 4.2 nm. The parameters are almost equivalent to those of the un-repaired target mask pattern. Therefore, 7 nm is the best de-cornering length. When the de-cornering size of the target mask pattern is 15 nm, the space between the target mask patterns increases to 30.02 nm, the simulation size under normal conditions is 55.2 nm, the process window exposure dose is reduced by 4%, the pw cd is 48.5 nm when the focus plane is moved up by 35 nm, the PV band is 5.5 nm, and the Meef is 5.6 nm. Compared with the un-repaired target mask pattern, the simulation parameters differ greatly and cannot meet the production requirements. Table 1 provides the simulation results under different de-cornering sizes.Figure 3 In the target mask, the simulation contour reaches the target value when the de- cornering length is 6nm and 8nm, but deviates from the target value when the de- cornering length increases to 10nm and 15nm. Therefore, according to the above experimental results, the de-cornering size of the target mask pattern is not the larger the better, and when the de-cornering size is 5nm-8nm, the simulation requirements of MRC and contour can be met at the same time.

[0045] In summary, the OPC correction method of the present application takes the dense staggered structure of the via layer as the research object, and proposes to solve the MRC problem by de- cornering the mask pattern. In the implementation process, first, the target layer pattern is corrected by the conventional MBOPC, and no MRC parameter is set in the correction process, so that the target layer pattern moves to the ideal position; then the mask pattern that violates MRC is selected and repaired; the appropriate de-cornering size is selected to de-corner the mask pattern, the purpose of which is to eliminate MRC; the selection of de-cornering size is determined by the results of model simulation, the gradient control de-cornering size changes from 0 to a certain value until MRC is not violated, and at this time the model simulation size is close to the target size, thereby solving the problem of violating MRC in the correction process. By repairing and optimizing the de-cornering size of the mask pattern, the simulation contour of the exposure pattern is not only on-target, but also meets the production requirements of PVband and Meef under the condition of PW (process window). Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0046] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. An OPC correction method, characterized in that, The method includes: A densely interlaced target layer pattern and a mask pattern are provided, wherein the target layer pattern and the mask pattern have the same shape, and each side of the target layer pattern is within the range represented by the mask pattern and can move freely within that range; In the model-based OPC correction process, no mask design rules are set, allowing the target layer graphic to move freely within the range represented by the mask graphic until the expected simulation size is reached, and a target mask graphic is selected, wherein the target mask graphic is a graphic that violates the mask design rules; The target mask pattern is decornered, and the decornered target mask is measured to evaluate whether it violates the mask design rules. If it violates the mask design rules, the decornering process continues. If it does not violate the mask design rules, the target mask is simulated and its size is evaluated to determine whether it meets the expected simulation size of the target layer pattern. The mask design rules include the minimum critical size and the minimum spacing of the mask analysis. If the critical size of the target mask pattern is smaller than the minimum critical size of the mask analysis, and its spacing is smaller than the minimum spacing of the mask analysis, it violates the mask design rules.

2. The OPC correction method according to claim 1, characterized in that, The target layer pattern and the mask pattern are square shapes, and the target layer pattern is used to form through holes on the wafer.

3. The OPC correction method according to claim 2, characterized in that, The densely interleaved target layer graphics and mask graphics are arranged in multiple rows and columns, with the target layer graphics / mask graphics in the next row and the target layer graphics / mask graphics in the previous row on the same diagonal line.

4. The OPC correction method according to claim 3, characterized in that, The spacing between the mask pattern described in the next row and the mask pattern in the previous row adjacent to it is less than 20 nm.

5. The OPC correction method according to claim 1, characterized in that, If the mask design rules are violated, the methods for continuing the dekeratinization process include: The decornening size is increased in increments of 1 nm to obtain a new decornening size, and the target mask is processed with the new decornening size. The decornening process of the target mask involves removing the four corners of the target mask, and the removed corners are isosceles triangles with the length of the side containing the vertex being the decornening size.

6. The OPC correction method according to claim 1, characterized in that, The mask design rules are determined by the process nodes.

7. The OPC correction method according to claim 6, characterized in that, For the 14nm process node, the minimum critical dimension of the mask resolution is 18nm, and the minimum spacing of the mask resolution is 12nm.

8. The OPC correction method according to claim 1, characterized in that, For a target mask pattern that meets the mask design rules, perform model simulation and check whether the simulation contour, PVband, and Meef meet the requirements. If they do, the final target mask pattern and its corresponding decornering dimensions are obtained.

9. The OPC correction method according to claim 1, characterized in that, Model-based OPC correction involves multiple iterative loop operations.

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