Grating bias control circuit

Abstract

The invention discloses a gate bias control circuit which is connected to the gate end of a PWN tube and comprises a phase inverter, an M1 tube, an M2 tube, an M3 tube, an M4 tube, an M5 tube, an M6 tube, a B1 tube, an M7 tube, a resistor R1 and a resistor R2. Wherein the M2 tube, the M4 tube, the M6 tube and the M7 tube are NMOS (N-channel metal oxide semiconductor) tubes, the M1 tube, the M3 tube and the M5 tube are PMOS (P-channel metal oxide semiconductor) tubes, and the B1 tube is a triode; the drain electrode of the M1 tube, the drain electrode of the M2 tube, the emitting electrode of the B1 tube, the source electrode of the M7 tube and the source electrode of the M5 tube are connected in parallel and then connected to the grid end of the PNW tube to serve as the grid bias voltage of the PNW tube. The PNW gate bias control circuit has the advantages that compared with a general VCCA power supply voltage serving as a PNW gate bias control circuit, the PNW gate bias control circuit adopts a PNW gate bias control circuit structure, and the delay problem of signal output waveforms under all conditions and the maximum rate problem of signal transmission under all conditions are solved.

Description

Technical Field

[0001] The invention relates to a gate bias control circuit. Background Art

[0002] In various signal processing systems, commonly used communication protocols include RS-232, RS-422, RS-485, I²C and other standard protocols. The I²C communication protocol is a bidirectional two-wire synchronous serial transmission protocol with a simple structure that only needs two wires to transmit information between devices connected to the bus. Therefore, the I²C communication protocol and communication interface are widely used in engineering fields such as serial AD in the field of data acquisition, camera configuration in the field of image processing, and X-ray tube configuration in the field of industrial control. The schematic diagram of the I²C communication protocol application is shown in the figure below. Figure 1 As shown in Figure 1, data transmission between different devices requires the use of the I²C communication interface. The general I²C signal transmission interface structure diagram is shown in Figure 1. Figure 2 As shown, the signal is transmitted by turning on or off the PWN tube, and the Oneshot module realizes fast pull-up when the signal jumps. The specific working process is as follows: when the A end transmits a low level to the B end, when the A end changes from a high level to a low level, the PWN tube is turned on, and the B end is pulled to a low level through the PWN tube; when the A end transmits a high level to the B end, when the A end changes from a low level to a high level, the PWN is initially in the on state, and the B end rises together with the A end voltage through the PWN tube, and the Oneshot function is triggered during the rise of the A end, so that the B end is pulled up quickly; when the A end rises to a certain voltage, the PWN tube is turned off; the B end is kept at a high level by the pull-up resistor. The same is true for transmission from the B end to the A end. From the above working principle, it can be seen that under certain extreme conditions, when the signal changes from a low level to a high level, the PWN tube will be cut off before the Oneshot function is triggered. This will cause a period of time when the output signal is pulled up only by the pull-up resistor during its rise. In this case, the transmission delay and the output rise time will increase; the maximum operating frequency will decrease; and the waveform will become uneven.

[0003] Under certain extreme conditions, since the PWN tube is cut off before the oneshot function is triggered, there will be a period of pull-up only by the pull-up resistor during the output signal rising process, which will deteriorate the switching characteristics, such as Figure 3 shown. Summary of the invention

[0004] The technical problem to be solved by the present invention is that: under certain extreme conditions, between the known I²C communication protocol and the interface, since the PWN tube is cut off before the oneshot function is triggered, a period of time during the output signal rising process when the output signal is pulled up only by the pull-up resistor will occur, thereby deteriorating the switching characteristics.

[0005] In order to solve the above technical problem, the present invention proposes a gate bias control circuit. The present invention uses a gate voltage control circuit introduced into a PWN tube to solve the technical problem.

[0006] The technical solutions adopted are as follows: A gate bias control circuit is connected to the gate end of a PWN tube. The gate bias control circuit includes an inverter, an M1 tube, an M2 tube, an M3 tube, an M4 tube, an M5 tube, an M6 tube, a B1 tube, an M7 tube, a resistor R1 and a resistor R2. The external input enable signal OE is connected to the inverter input, the inverter output is connected to the gates of the M1 and M2 tubes, the source of the M1 tube is connected to the VCCB voltage, the source of the M2 tube is connected to the ground potential; the drain of the M1 tube is connected to the drain of the M2 tube; A pulse of the enable signal OE that has just been valid is connected to the base of the B1 tube and the gate of the M7 tube. The collector of the B1 tube is connected to the VCCB power supply through the resistor R1, and the drain of the M7 tube is connected to the VCCB power supply through the resistor R2; the gate of the M5 tube is connected to the gate and drain of the M3 tube and the drain of the M4 tube, the source of the M3 tube is connected to the VCCA power supply, and the source of the M4 tube is grounded; the drain of the M5 tube is connected to the gate of the M4 tube and the gate and drain of the M6 ​​tube, and the source of the M6 ​​tube is grounded; The drain of M1 tube, the drain of M2 tube, the emitter of B1 tube, the source of M7 tube and the source of M5 tube are connected in parallel and connected to the gate end of PNW tube as the gate bias of PNW tube; the gate bias of PWN tube = VCCA + vgs5-vgs3, where vgs5 is the gate-source voltage of M5 tube, and vgs3 is the gate-source voltage of M3 tube.

[0007] In a further preferred embodiment of the technical solution of the present invention, the enable signal OE rises and a pulse is generated on the chip.

[0008] In a further preferred embodiment of the technical solution of the present invention, the M3 tube, the M4 tube, and the M6 ​​tube are all VCCA voltage domain devices.

[0009] In a further preferred embodiment of the technical solution of the present invention, the VCCA voltage domain device is usually 3.3V, and the M3 tube, the M4 tube, and the M6 ​​tube are all 3.3V NMOS tubes.

[0010] In a further preferred embodiment of the technical solution of the present invention, the tube M1 is an inverse ratio tube. The inverse ratio tube is used here because the current is small, which can reduce the power consumption of this part of the circuit.

[0011] In a further preferred embodiment of the technical solution of the present invention, the M5 tube is a VCCB voltage domain device.

[0012] In a further preferred embodiment of the technical solution of the present invention, the VCCB voltage domain device is usually 5V, and the M5 tube is a 5V PMOS tube.

[0013] In a further preferred embodiment of the technical solution of the present invention, the width-to-length ratio of the M5 tube is adjusted to achieve the adjustment of the gate bias of the PWN tube.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. Compared with the general VCCA power supply voltage as the PNW tube gate bias circuit, the gate bias control circuit of the present invention adopts a PNW gate bias control circuit structure to improve the delay problem of the signal output waveform under all conditions; specifically: under certain extreme conditions, when the signal changes from a low level to a high level, the PWN tube will be cut off before the Oneshot function is triggered, which will cause a period of pull-up only by the pull-up resistor during the output signal rising process. The present patent adopts a PNW gate bias control circuit structure to increase the gate voltage of the PWN tube, thereby ensuring that the PWN tube is cut off after the oneshot function is triggered, and there will be no period of pull-up only by the pull-up resistor (the resistor is a weak pull-up and very slow).

[0015] 2. Compared with the general VCCA power supply voltage as the PNW tube gate bias circuit, the gate bias control circuit of the present invention adopts a PNW gate bias control circuit structure to improve the maximum signal transmission rate problem under all conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of I²C signal transmission; Figure 2 This is the circuit schematic diagram of a universal I²C interface chip; Figure 3 This is the waveform diagram of the traditional VCCA power supply as the PNW tube gate voltage output; Figure 4 This is a PNW tube grid bias control circuit diagram of the present invention; Figure 5 This is a good output waveform of the present invention using PNW gate bias control. DETAILED DESCRIPTION

[0017] The technical solution of the present invention is described in detail below, but the protection scope of the present invention is not limited to the embodiments.

[0018] To make the content of the present invention more clearly understood, the following Figure 1 -Attached Figure 5 The specific implementation manner is further described.

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] like Figure 4 As shown, this embodiment provides a gate bias control circuit, which is connected to the gate end of the PWN tube. Figure 2 and 4 shown.

[0021] like Figure 4 As shown, the gate bias control circuit includes an inverter, an M1 tube, an M2 tube, an M3 tube, an M4 tube, an M5 tube, an M6 tube, a B1 tube, an M7 tube, a resistor R1 and a resistor R2; wherein, the M2 tube, the M4 tube, the M6 ​​tube and the M7 tube are NMOS tubes, the M1 tube, the M3 tube and the M5 tube are PMOS tubes, and the B1 tube is a triode.

[0022] like Figure 4 As shown, the external input enable signal OE is connected to the inverter input, the inverter output is connected to the gates of the M1 tube and the M2 tube, the source of the M1 tube is connected to the VCCB voltage, and the source of the M2 tube is connected to the ground potential; the drain of the M1 tube is connected to the drain of the M2 tube; A pulse of the enable signal OE that has just been valid is connected to the base of the B1 tube and the gate of the M7 tube. The collector of the B1 tube is connected to the VCCB power supply through the resistor R1, and the drain of the M7 tube is connected to the VCCB power supply through the resistor R2; the gate of the M5 tube is connected to the gate and drain of the M3 tube and the drain of the M4 tube, the source of the M3 tube is connected to the VCCA power supply, and the source of the M4 tube is grounded; the drain of the M5 tube is connected to the gate of the M4 tube and the gate and drain of the M6 ​​tube, and the source of the M6 ​​tube is grounded; The drain of M1 tube, the drain of M2 tube, the emitter of B1 tube, the source of M7 tube and the source of M5 tube are connected in parallel and connected to the gate end of PNW tube as the gate bias of PNW tube; the gate bias of PWN tube = VCCA + vgs5-vgs3, where vgs5 is the gate-source voltage of M5 tube, and vgs3 is the gate-source voltage of M3 tube.

[0023] In the gate bias control circuit of this embodiment, the M3 transistor, the M4 transistor, and the M6 ​​transistor are all 3.3V NMOS transistors, and the M1 transistor is an inverse ratio transistor.

[0024] In the gate bias control circuit of this embodiment, the width-to-length ratio of the M5 tube is adjusted to achieve the adjustment of the gate bias of the PWN tube.

[0025] When the gate bias control circuit of this patent is used, when the external input enable signal OE just rises, a pulse is generated to act on the base of the B1 tube, and the emitter voltage of the B1 tube, that is, the gate bias of the PWN tube, rises rapidly; the generated pulse also acts on the gate of the M7 tube, turning on the M6 ​​tube.

[0026] When the external input enable signal OE rises, the M1 tube is turned on, the M2 tube is turned off, the M5 tube and the M6 ​​tube are all turned on, and the weak current passes through the M1 tube through the M5 tube to the M6 ​​tube to obtain the PWN tube gate bias. The PWN tube gate bias = VCCA + vgs5-vgs3, where vgs5 is the gate-source voltage of the M5 tube, and vgs3 is the gate-source voltage of the M3 tube.

[0027] In the gate bias control circuit of this embodiment, the PWN gate bias is adjusted by using the difference between the gate-source voltage of the 3.3V NMOS tube and the 5V PMOS tube.

[0028] Further preferably, the width-to-length ratio of the M5 tube is adjusted by a trimming unit to achieve control and adjustment of the PWN gate bias. The trimming unit is used to adjust the width-to-length ratio of the M5 tube. This is a technology known to those skilled in the art.

[0029] The gate bias control circuit of the PWN tube of this patent can make the gate bias of the PWN tube higher than the VCCA power supply, but it should be noted that when adjusting the width-to-length ratio of M5 to increase the gate bias of the PWN tube, it cannot be so high that the PWN tube is turned on when the high level is transmitted. The increase of the gate bias of the PWN tube is beneficial to shorten the intermediate state between the PWN tube cutoff and the oneshot function triggering under extreme conditions, making the waveform smooth, reducing the delay, and increasing the maximum transmission rate; the good output waveform of the circuit of this patent is as follows Figure 5 shown.

[0030] The parts not involved in the present invention are the same as the prior art or can be implemented by using the prior art.

[0031] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes in form and details may be made without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A gate bias control circuit, characterized in that: The gate bias control circuit is connected to the gate end of the PWN tube, and the gate bias control circuit includes an inverter, an M1 tube, an M2 tube, an M3 tube, an M4 tube, an M5 tube, an M6 tube, a B1 tube, an M7 tube, a resistor R1 and a resistor R2. The external input enable signal OE is connected to the inverter input, the inverter output is connected to the gates of the M1 and M2 tubes, the source of the M1 tube is connected to the VCCB voltage, the source of the M2 tube is connected to the ground potential; the drain of the M1 tube is connected to the drain of the M2 tube; A pulse of the enable signal OE that has just been valid is connected to the base of the B1 tube and the gate of the M7 tube. The collector of the B1 tube is connected to the VCCB power supply through the resistor R1, and the drain of the M7 tube is connected to the VCCB power supply through the resistor R2; the gate of the M5 tube is connected to the gate and drain of the M3 tube and the drain of the M4 tube, the source of the M3 tube is connected to the VCCA power supply, and the source of the M4 tube is grounded; the drain of the M5 tube is connected to the gate of the M4 tube and the gate and drain of the M6 ​​tube, and the source of the M6 ​​tube is grounded; The drain of M1 tube, the drain of M2 tube, the emitter of B1 tube, the source of M7 tube and the source of M5 tube are connected in parallel and connected to the gate end of PNW tube as the gate bias of PNW tube; the gate bias of PWN tube = VCCA + vgs5-vgs3, where vgs5 is the gate-source voltage of M5 tube, and vgs3 is the gate-source voltage of M3 tube.

2. The gate bias control circuit according to claim 1, characterized in that: The enable signal OE rises and a pulse is generated on the chip.

3. The gate bias control circuit according to claim 1, characterized in that: The M3, M4, and M6 tubes are all VCCA voltage domain devices.

4. The gate bias control circuit according to claim 3, characterized in that: VCCA voltage domain devices are usually 3.3v, and M3, M4, and M6 tubes are all 3.3V NMOS tubes.

5. The gate bias control circuit according to claim 1, characterized in that: The M1 tube is an inverse ratio tube.

6. The gate bias control circuit according to claim 1, characterized in that: The M5 tube is a VCCB voltage domain device.

7. The gate bias control circuit according to claim 6, characterized in that: The VCCB voltage domain devices are usually 5V, and the M5 tube is a 5V PMOS tube.

8. The gate bias control circuit according to claim 1, characterized in that: Adjust the width-to-length ratio of the M5 tube to adjust the gate bias of the PWN tube.

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