Segmented compensation band-gap reference voltage source

Abstract

The invention belongs to the field of analog integrated circuit design, and particularly relates to a segmented compensation band-gap reference voltage source. Comprising a first-order compensation band-gap reference circuit, a segmented compensation circuit and a bias circuit, the first-order compensation band-gap reference circuit is connected with the segmented compensation circuit, the segmented compensation circuit is connected with the bias circuit, the first-order compensation band-gap reference circuit is used for providing band-gap reference voltage for eliminating a first-order temperature coefficient, and the first-order compensation band-gap reference circuit is used for providing band-gap reference voltage for eliminating a second-order temperature coefficient. The first-order compensation band-gap reference circuit is used for providing band-gap reference voltage, the segmented compensation circuit is used for providing temperature characteristic voltage for the band-gap reference voltage, the voltage curve of the temperature characteristic voltage is a parabola with an upward opening, and the bias circuit provides bias voltage for the first-order compensation band-gap reference circuit and the segmented compensation circuit. According to the band-gap reference voltage source, the voltage with the parabola temperature characteristic and the opening facing upwards is provided through the segmented compensation circuit and used for compensating the high-order temperature coefficient of VBE, and the temperature drift of the band-gap reference voltage source can be reduced.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design, and in particular relates to a segmented compensation bandgap reference voltage source. Background Art

[0002] Bandgap reference voltage source is a common voltage source in the field of analog integrated circuit design. It is widely used in various DAC, ADC, power management chips, sensor chips and other chips. Its most prominent feature is that it has high accuracy and is independent of power supply voltage and temperature. Bandgap reference voltage source is generally used as a module to provide reference voltage. Its accuracy determines the accuracy of the entire circuit. With the continuous improvement of market requirements for circuit accuracy, the design of bandgap reference with excellent temperature characteristics has become an important topic of concern for integrated circuit designers.

[0003] Bandgap reference voltage sources have a variety of traditional structures, but their basic principles are basically the same. Generally, a voltage with a positive temperature coefficient with adjustable weight is added to a voltage with a negative temperature coefficient to achieve the purpose of eliminating the first-order voltage temperature coefficient. The positive temperature coefficient voltage usually selects the thermal voltage VT, and the negative temperature coefficient voltage generally uses the base-emitter voltage VBE of the transistor.

[0004] In actual situations, since VBE is not an ideal first-order negative temperature coefficient voltage and has a high-order curvature, under the traditional structure, the output bandgap reference voltage will have a second-order or higher temperature coefficient, affecting the accuracy of the circuit. In this case, to further improve the circuit accuracy, it is necessary to design a compensation circuit for the second-order or higher temperature coefficient. Summary of the invention

[0005] The present invention provides a segmented compensated bandgap reference voltage source, which solves the defects of the traditional first-order compensation circuit mentioned in the background technology, performs segmented compensation for high-order temperature coefficients, and reduces the temperature drift of the bandgap reference voltage source.

[0006] The technical solution of the present invention is as follows: a segmented compensated bandgap reference voltage source, comprising: a first-order compensated bandgap reference circuit, a segmented compensation circuit and a bias circuit, wherein the first-order compensated bandgap reference circuit is connected to the segmented compensation circuit, and the segmented compensation circuit is connected to the bias circuit. The first-order compensated bandgap reference circuit is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient, and the segmented compensation circuit is used to provide a temperature characteristic voltage for the bandgap reference voltage, and the voltage curve of the temperature characteristic voltage is an upward-opening parabola, and the bias circuit provides a bias voltage for the first-order compensated bandgap reference circuit and the segmented compensation circuit.

[0007] Furthermore, the first-order compensated bandgap reference circuit includes a common-source common-gate current mirror and a bipolar reference output circuit, the common-source common-gate current mirror is connected to the power supply voltage and the bipolar reference output circuit, the common-source common-gate current mirror is used to copy the power supply voltage to the bipolar reference output circuit, and the bipolar reference output circuit is used to generate a bandgap reference voltage that eliminates the first-order temperature coefficient based on the power supply voltage.

[0008] Further, the common-source common-gate current mirror includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, and a first NMOS tube MN1, the sources of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the power supply voltage, the gates of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the drain of the fourth PMOS tube MP4, the drain of the first PMOS tube MP1 is connected to the source of the third PMOS tube MP3, the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, the drain of the third PMOS tube MP3 is connected to the gate of the first NMOS tube MN1, the drain of the second PMOS tube MP2 is connected to the source of the fourth PMOS tube MP4, the drain of the fourth PMOS tube MP4 is connected to the drain of the first NMOS tube MN1, and the gate of the first NMOS tube MN1 is connected to the segmented compensation circuit.

[0009] Further, the bipolar reference output circuit includes: a first transistor QN1, a second transistor QN2, a second resistor R2 and a first resistor R1, the collector of the first transistor QN1 is connected to the gate of the first NMOS transistor MN1, the base of the first transistor QN1 is connected to the base of the second transistor QN2, the collector of the second transistor QN2 is connected to the source of the first NMOS transistor MN1, the emitter of the first transistor QN1 is connected to one end of the first resistor R1, the emitter of the second transistor QN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the signal ground, and the bases of the first transistor QN1 and the second transistor QN2 output a bandgap reference voltage that eliminates the first-order temperature coefficient.

[0010] Further, the segmented compensation circuit includes: a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third transistor QN3, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0011] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage, the gate of the fifth PMOS transistor MP5 is connected to the first-order compensation bandgap reference circuit, the drain of the fifth PMOS transistor MP5 is connected to the collector and base of the third transistor QN3 and the base of the fifth transistor QN5, the emitter of the collector of the third transistor QN3 is connected to the collector and base of the fourth transistor QN4, the emitter of the fourth transistor QN4 is connected to the signal ground, the collector of the fifth transistor QN5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient, the emitter of the fifth transistor QN5 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the emitter of the sixth transistor QN6 and one end of the fourth resistor R4, The other end of the fourth resistor R4 is connected to the signal ground, the collector of the sixth transistor QN6 is connected to the power supply voltage, the base of the sixth transistor QN6 is connected to the bias circuit, the drain of the second NMOS transistor MN2 is connected to the power supply voltage, the gate of the second NMOS transistor MN2 is connected to the first-order compensation bandgap reference circuit, the source of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient and the collector of the seventh transistor QN7, the base of the seventh transistor QN7 is connected to the bias circuit, the emitter of the seventh transistor QN7 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the signal ground.

[0012] Further, the bias circuit includes: an eighth PMOS tube MP8, a ninth PMOS tube MP9, a seventh resistor R7, an eighth resistor R8, an eighth transistor QN8, a ninth resistor R9, and a tenth resistor R10;

[0013] The source of the eighth PMOS tube MP8 and the gate and source of the ninth PMOS tube MP9 are connected to the power supply voltage, the gate of the eighth PMOS tube MP8 is connected to the first-order compensation bandgap reference circuit, the drain of the eighth PMOS tube MP8 is connected to one end of the seventh resistor R7 and provides the second bias voltage VB2, the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and provides the third bias voltage VB3, the other end of the ninth resistor R9 is connected to the signal ground, the drain of the ninth PMOS tube MP9 is connected to the collector of the eighth transistor QN8 and provides the first bias voltage VB1, the base of the eighth transistor QN8 is connected to one end of the eighth resistor R8 and the emitter of the eighth transistor QN8, the emitter of the eighth transistor QN8 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the signal ground.

[0014] Beneficial effects of the present invention: The present invention provides a voltage with an upwardly opening parabolic temperature characteristic through a segmented compensation circuit, which is used to compensate for the high-order temperature coefficient of VBE. The present invention can reduce the temperature drift of the bandgap reference voltage source. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of the present invention.

[0016] Figure 2 It is a schematic diagram of voltage characteristics of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. The described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0018] In the technical solution of the present invention, Figure 1 is a structural schematic diagram of a specific structure of a segmented compensation bandgap reference voltage source according to the present invention, such as Figure 1 As shown, the present invention includes: a first-order compensated bandgap reference circuit 1, a segmented compensation circuit 2 and a bias circuit 3, wherein the first-order compensated bandgap reference circuit 1 is connected to the segmented compensation circuit 2, and the segmented compensation circuit 2 is connected to the bias circuit. The first-order compensated bandgap reference circuit 1 is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient, and the segmented compensation circuit 2 is used to provide a temperature characteristic voltage for the bandgap reference voltage, and the voltage curve of the temperature characteristic voltage is an upward-opening parabola, and the bias circuit 3 provides a bias voltage for the first-order compensated bandgap reference circuit 1 and the segmented compensation circuit 2.

[0019] In one embodiment of the present invention, the first-order compensated bandgap reference circuit 1 includes a common-source common-gate current mirror and a bipolar reference output circuit, the common-source common-gate current mirror is connected to the power supply voltage and the bipolar reference output circuit, the common-source common-gate current mirror is used to copy the power supply voltage to the bipolar reference output circuit, and the bipolar reference output circuit is used to generate a bandgap reference voltage that eliminates the first-order temperature coefficient based on the power supply voltage.

[0020] In one embodiment of the present invention, the common-source common-gate current mirror includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, and a first NMOS tube MN1. The sources of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the power supply voltage, the gates of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the drain of the fourth PMOS tube MP4, the drain of the first PMOS tube MP1 is connected to the source of the third PMOS tube MP3, the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, the drain of the third PMOS tube MP3 is connected to the gate of the first NMOS tube MN1, the drain of the second PMOS tube MP2 is connected to the source of the fourth PMOS tube MP4, the drain of the fourth PMOS tube MP4 is connected to the drain of the first NMOS tube MN1, and the gate of the first NMOS tube MN1 is connected to the segmented compensation circuit 2.

[0021] In one embodiment of the present invention, the bipolar reference output circuit includes: a first transistor QN1, a second transistor QN2, a second resistor R2 and a first resistor R1, the collector of the first transistor QN1 is connected to the gate of the first NMOS transistor MN1, the base of the first transistor QN1 is connected to the base of the second transistor QN2, the collector of the second transistor QN2 is connected to the source of the first NMOS transistor MN1, the emitter of the first transistor QN1 is connected to one end of the first resistor R1, the emitter of the second transistor QN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the signal ground, and the bases of the first transistor QN1 and the second transistor QN2 output a bandgap reference voltage that eliminates the first-order temperature coefficient.

[0022] In one embodiment of the present invention, the segmented compensation circuit 2 includes: a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third transistor QN3, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0023] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage, the gate of the fifth PMOS transistor MP5 is connected to the first-order compensation bandgap reference circuit 1, the drain of the fifth PMOS transistor MP5 is connected to the collector and base of the third transistor QN3 and the base of the fifth transistor QN5, the emitter of the collector of the third transistor QN3 is connected to the collector and base of the fourth transistor QN4, the emitter of the fourth transistor QN4 is connected to the signal ground, the collector of the fifth transistor QN5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient, the emitter of the fifth transistor QN5 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the emitter of the sixth transistor QN6 and one end of the fourth resistor R4, The other end of the fourth resistor R4 is connected to the signal ground, the collector of the sixth transistor QN6 is connected to the power supply voltage, the base of the sixth transistor QN6 is connected to the bias circuit 3, the drain of the second NMOS transistor MN2 is connected to the power supply voltage, the gate of the second NMOS transistor MN2 is connected to the first-order compensation bandgap reference circuit 1, the source of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient and the collector of the seventh transistor QN7, the base of the seventh transistor QN7 is connected to the bias circuit 3, the emitter of the seventh transistor QN7 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the signal ground.

[0024] In one embodiment of the present invention, the bias circuit 3 includes: an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a seventh resistor R7, an eighth resistor R8, an eighth transistor QN8, a ninth resistor R9, and a tenth resistor R10;

[0025] The source of the eighth PMOS tube MP8 and the gate and source of the ninth PMOS tube MP9 are connected to the power supply voltage, the gate of the eighth PMOS tube MP8 is connected to the first-order compensation bandgap reference circuit 1, the drain of the eighth PMOS tube MP8 is connected to one end of the seventh resistor R7 and provides a first bias voltage VB1, the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and provides a third bias voltage VB3, the other end of the ninth resistor R9 is connected to the signal ground, the drain of the ninth PMOS tube MP9 is connected to the collector of the eighth transistor QN8, the base of the eighth transistor QN8 is connected to one end of the eighth resistor R8 and the emitter of the eighth transistor QN8, the emitter of the eighth transistor QN8 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the signal ground.

[0026] The working principle of the present invention is as follows:

[0027] In the first-order bandgap reference circuit 1, NPN transistors QN1 and QN2 and resistors R1 and R2 form a traditional Brokaw reference structure. PMOS transistors MP1, MP2, MP3, and MP4 form a common source and common gate current mirror to ensure that the currents flowing through NPN transistors QN1 and QN2 are basically the same. NMOS transistor MN1 plays an isolation role to prevent VB4 from being pulled down during startup, causing a transient large current to appear in the reference.

[0028] According to circuit analysis, the output of the first-order bandgap reference circuit (1) is

[0029]

[0030] For VBE1,

[0031]

[0032] Among them, V G0 (T r ) is the silicon bandgap voltage at reference temperature T r The value below, V T is the thermal voltage, η is a process-related constant, ζ is the order of the transistor collector current-temperature characteristic. When the current flowing through the transistor is PTAT, this term is 1, when a negative temperature coefficient current flows, this term is -1, and when a temperature-independent current flows, this term is 0. From the above formula, it can be seen that the temperature function of VBE consists of a constant term, a first-order term, and a high-order term. After first-order compensation, the voltage has another Part, the temperature-voltage image of this part is similar to the function y=-xlnx, which is a parabola with an opening facing downward. Therefore, it is only necessary to use a voltage of a temperature-voltage curve with a parabolic image with an opening facing upward and add it to a first-order bandgap reference to obtain a bandgap reference with a smaller temperature drift. In the present invention, this function is realized by the segmented compensation circuit 2.

[0033] In the segmented compensation circuit 2, the PMOS transistor MP5, the NPN transistors QN3, QN4, QN5, the resistors R3, R4 form one branch, and the NMOS transistor QN7 and the resistor R6 form another branch. These two branches provide current for segmented compensation. The NMOS transistor MN2 and the resistor R5 convert the segmented compensation current into a compensation voltage, which is superimposed on the output of the first-order bandgap reference 1.

[0034] Let the current flowing through R5 be I1, the current flowing through QN5 and R3 be I11, the current flowing through QN7 and R6 be I12, and the current flowing through QN6 be I2. Let the saturation conduction voltage of transistors QN5 and QN6 be VBE0. First, analyze I12. When the temperature is too low, due to the negative temperature characteristic of VBE, the voltage VBE0 required for conduction at this time > the bias voltage VB3, and the transistor is not conducting, and the current is approximately 0. When the temperature rises and VBE0 < VB3, an equation can be listed for I12 at this time as follows Since the temperature coefficient of R6 is small and will cancel out the temperature coefficient of R5, the influence of R6 can be ignored. Since the temperature coefficient of -VBE7 is positive, overall, I12 is a positive temperature coefficient current with a certain concave higher-order curvature; then analyze I11. When the temperature is too high, due to the negative temperature characteristic of VBE, VBE1 + VBE6 < VBE0 + V3 + V4, and transistor QN5 is not conducting, and the current is approximately 0. When the temperature decreases and VBE1 + VBE6 rises to make transistor QN5 conducting, an equation can be listed for the circuit as follows:

[0035]

[0036] The solution of the equation is

[0037]

[0038] Among them, VBE all have negative temperature coefficients. By selecting appropriate sizes for transistors QN3, QN5, QN5, and QN6, it is possible to make V BE3 +V BE4 +V BE6 -V BE5 In this, the temperature coefficients of QN3, QN4, and QN6 are greater than the temperature coefficient of QN5, and this voltage is generally a negative temperature coefficient voltage with a certain convex higher-order curvature. The magnitude of VB2 is the reference voltage plus the voltage of R7. Since the current flowing through R7 is a mirror image of the reference PTAT, the current flowing through R7 has a first-order positive temperature coefficient, and thus VB2 also has a first-order positive temperature coefficient. Overall, at this time, I11 can be regarded as the sum of two negative temperature coefficient currents, and its property is a negative temperature coefficient current with a certain convex higher-order curvature. Since the temperature coefficient of R3 is small and will cancel out the temperature coefficient of R5, the influence of R3 can be ignored.

[0039] Let the turn-on temperature of QN6 be T1 and the turn-on temperature of QN7 be T2. By adjusting the ratio of resistors R8 and R9 and the sizes of transistors QN3 and QN4, the values of T1 and T2 can be adjusted such that T1 < T2. From the circuit, it can be seen that I1 is the sum of the two branch currents I11 and I12. At this time, the temperature characteristic of I1 is: when T < T1, it is a negative temperature coefficient current; when T1 < T < T2, the current is approximately 0; when T2 < T, it is a positive temperature coefficient current. The overall current-temperature graph is approximately a parabola opening upwards.

[0040] The overall output of the circuit is

[0041]

[0042] Among them, the second term compensates for the first-order temperature coefficient of VBE1. In the third term, I1 is the segmented compensation current, R5 is a resistor with a low temperature coefficient, and the voltage across R5 is the product of these two terms, which is used to compensate for the high-order curvature of the circuit. The final compensation process is as Figure 2 shown. Figure 2 In the first curve graph in, it is the first-order compensation result after the cancellation of the first and second terms in Equation (5), and the overall performance is a parabola waveform opening upwards. Figure 2 In the second curve graph in, it is a schematic diagram of the third term in Equation (5), and overall it is approximately a parabola image opening downwards. Finally, the fluctuation of the overall compensated bandgap reference voltage is as Figure 2 shown in the third curve graph in. The temperature graph of the bandgap reference voltage is similar to a cubic function, and the temperature drift is reduced.

[0043] In the bias circuit 3, the PMOS transistor MP9, the NPN transistor QN8, and the resistor R10 provide a bias voltage for the cascode current mirror. The PMOS transistor MP3, and the resistors R7, R8, and R9 provide a bias voltage for the segmented compensation circuit.

[0044] Finally, it should be noted that the above specific implementation manners are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A segmented compensated bandgap reference voltage source, characterized in that: include: A first-order compensation bandgap reference circuit (1), a segmented compensation circuit (2) and a bias circuit (3), wherein the first-order compensation bandgap reference circuit (1) is connected to the segmented compensation circuit (2), and the segmented compensation circuit (2) is connected to the bias circuit. The first-order compensation bandgap reference circuit (1) is used to provide a bandgap reference voltage that eliminates a first-order temperature coefficient, and the segmented compensation circuit (2) is used to provide a temperature characteristic voltage for the bandgap reference voltage, wherein the voltage curve of the temperature characteristic voltage is an upwardly opening parabola, and the bias circuit (3) provides a bias voltage for the first-order compensation bandgap reference circuit (1) and the segmented compensation circuit (2).

2. The segmented compensated bandgap reference voltage source according to claim 1, characterized in that: The first-order compensated bandgap reference circuit (1) comprises a common-source common-gate current mirror and a bipolar reference output circuit, wherein the common-source common-gate current mirror is connected to a power supply voltage and the bipolar reference output circuit, the common-source common-gate current mirror is used to copy the power supply voltage to the bipolar reference output circuit, and the bipolar reference output circuit is used to generate a bandgap reference voltage that eliminates a first-order temperature coefficient according to the power supply voltage.

3. The segmented compensated bandgap reference voltage source according to claim 2, characterized in that: The cascode current mirror comprises: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, and a first NMOS tube MN1. The sources of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to a power supply voltage, the gates of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the drain of the fourth PMOS tube MP4, the drain of the first PMOS tube MP1 is connected to the source of the third PMOS tube MP3, the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, the drain of the third PMOS tube MP3 is connected to the gate of the first NMOS tube MN1, the drain of the second PMOS tube MP2 is connected to the source of the fourth PMOS tube MP4, the drain of the fourth PMOS tube MP4 is connected to the drain of the first NMOS tube MN1, and the gate of the first NMOS tube MN1 is connected to a segmented compensation circuit (2).

4. The segmented compensated bandgap reference voltage source according to claim 3, characterized in that: The bipolar reference output circuit includes: a first transistor QN1, a second transistor QN2, a second resistor R2 and a first resistor R1, the collector of the first transistor QN1 is connected to the gate of the first NMOS transistor MN1, the base of the first transistor QN1 is connected to the base of the second transistor QN2, the collector of the second transistor QN2 is connected to the source of the first NMOS transistor MN1, the emitter of the first transistor QN1 is connected to one end of the first resistor R1, the emitter of the second transistor QN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the signal ground, and the bases of the first transistor QN1 and the second transistor QN2 output a bandgap reference voltage that eliminates the first-order temperature coefficient.

5. The segmented compensated bandgap reference voltage source according to claim 1, characterized in that: The segmented compensation circuit (2) comprises: a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third transistor QN3, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; The source of the fifth PMOS transistor MP5 is connected to the power supply voltage, the gate of the fifth PMOS transistor MP5 is connected to the first-order compensation bandgap reference circuit (1), the drain of the fifth PMOS transistor MP5 is connected to the collector and base of the third transistor QN3 and the base of the fifth transistor QN5, the emitter of the collector of the third transistor QN3 is connected to the collector and base of the fourth transistor QN4, the emitter of the fourth transistor QN4 is connected to the signal ground, the collector of the fifth transistor QN5 is connected to the bandgap reference voltage for eliminating the first-order temperature coefficient, the emitter of the fifth transistor QN5 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the emitter of the sixth transistor QN6 and one end of the fourth resistor R4, and the emitter of the fifth transistor QN5 is connected to the first-order compensation bandgap reference circuit (1). The other end of the four resistors R4 is connected to the signal ground, the collector of the sixth transistor QN6 is connected to the power supply voltage, the base of the sixth transistor QN6 is connected to the bias circuit (3), the drain of the second NMOS transistor MN2 is connected to the power supply voltage, the gate of the second NMOS transistor MN2 is connected to the first-order compensation bandgap reference circuit (1), the source of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the bandgap reference voltage for eliminating the first-order temperature coefficient and the collector of the seventh transistor QN7, the base of the seventh transistor QN7 is connected to the bias circuit (3), the emitter of the seventh transistor QN7 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the signal ground.

6. The segmented compensated bandgap reference voltage source according to claim 1, characterized in that: The bias circuit (3) comprises: an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a seventh resistor R7, an eighth resistor R8, an eighth transistor QN8, a ninth resistor R9, and a tenth resistor R10; The source of the eighth PMOS transistor MP8 and the gate and source of the ninth PMOS transistor MP9 are connected to the power supply voltage, the gate of the eighth PMOS transistor MP8 is connected to the first-order compensation bandgap reference circuit (1), the drain of the eighth PMOS transistor MP8 is connected to one end of the seventh resistor R7 and provides a second bias voltage VB2, the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and provides a third bias voltage VB3, the other end of the ninth resistor R9 is connected to the signal ground, the drain of the ninth PMOS transistor MP9 is connected to the collector of the eighth transistor QN8 and provides a first bias voltage VB1, the base of the eighth transistor QN8 is connected to one end of the eighth resistor R8 and the emitter of the eighth transistor QN8, the emitter of the eighth transistor QN8 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the signal ground.

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