A data path system, method, apparatus, and medium based on a hard-soft fusion engine

Abstract

The application provides a data channel system, method, device and medium based on a hard-soft fusion engine, and belongs to the technical field of solid state disks.The system comprises a command self-analysis module, a cooperative data transmission module, an adaptive flash block management module and an abnormal power-off cooperative processing module.The system is powered on and initialized;host commands are acquired;the command self-analysis module performs command legality checking according to a set threshold;the cooperative data transmission module calculates data transmission volume, automatically acquires a cache block, analyzes and acquires a PRP address entry and starts dma transmission;the adaptive flash block management module provides a space block and flash programming and updates a logical-physical address mapping table;when an abnormal power-off is detected, the abnormal power-off cooperative processing module cancels the command automatic takeover function, writes current cache content to NAND, updates the logical-physical mapping table, outputs current block information to control software and completes power-off.The application makes the data transmission process more efficient and reduces the loss of data transmission in the channel.

Description

TECHNICAL FIELD

[0001] The application relates to a data channel system, method, device and medium based on a soft and hard fusion engine and belongs to the technical field of solid state disks. BACKGROUND

[0002] With the wide application of new generation information technologies such as cloud computing, big data, artificial intelligence and 5G communication, data presents a massive and explosive growth, and some application scenarios have more stringent requirements on the timeliness of data access, and upper-layer businesses have higher performance requirements for data center storage systems. As a core component of modern data center storage systems, the performance of a solid state disk (SSD) is directly related to the access efficiency of data and user experience of upper-layer applications. However, the latency of the SSD to read and write access requests becomes an important technical index for performance improvement of a flash memory storage master chip, and this latency directly affects the transmission speed and storage efficiency of data.

[0003] Traditional SSD master designs have many bottlenecks in command processing and data transmission, such as low command analysis efficiency, high data transmission latency, insufficient utilization of hardware resources and the like, which limit the improvement of the performance of the SSD. Therefore, the industry has carried out extensive research and exploration on how to reduce the command processing and data transmission latency in the SSD master, improve the data transmission efficiency and meet the application requirements of high performance and high reliability. SUMMARY

[0004] The application aims to provide a data channel system, method, device and medium based on a soft and hard fusion engine, which improves the resource allocation efficiency of a data transmission engine, realizes automatic cooperative processing of commands, reduces the processing latency and processing time of the commands, guarantees the quality of service and meets the application requirements of high performance and high reliability under the premise of meeting the queue priority.

[0005] To achieve the above-mentioned purpose, the application is implemented by the following technical scheme:

[0006] A data channel system based on a soft and hard fusion engine comprises:

[0007] A command self-analysis module automatically analyzes the command format after reading the command from a host and automatically checks each command code in the command according to a configured error checking condition;

[0008] The cooperative data transmission module is configured to configure a resource pool during power-on initialization, automatically allocate a buffer in the resource pool to receive host data during processing of a write command, and automatically update a corresponding offset in the DDR cache after the host data transmission is completed; automatically obtain a PRP address and start DMA data transmission, and send a completion message to the FIFO interacting with the NAND control module after the transmission is completed; and dynamically allocate DMA according to the load of each DMA engine;

[0009] The adaptive flash block management module is configured to provide a free writable NAND flash block in real time, perform flash block recycling, erasing, and changing a logical-physical mapping table operation according to a software-set free block threshold, and process a message in the interaction FIFO, and start a write programming action to the NAND flash block when new data is obtained from the interaction FIFO, and update the logical-physical address mapping table after the write is completed.

[0010] The abnormal power-off cooperative processing module is configured to close the automatic management function of the flash free block when an abnormal power-off interrupt is sensed, timely flush the data in the cache to the NAND flash, and output the current block information.

[0011] Preferably, the command self-parsing module further automatically checks the command according to a software-configured error checking condition after reading the command from the host, and the error checking condition is a field legal value range, including a legal range of a logical address.

[0012] Preferably, the resource pool in the cooperative data transmission module is configured during power-on initialization, and is used to store data to be processed, and improves the data transmission efficiency by automatically allocating a buffer and synchronously updating the DDR cache.

[0013] Preferably, the adaptive flash block management module is further configured to dynamically adjust the allocation of the flash block according to the set free block threshold, so as to optimize the storage performance.

[0014] Preferably, the automatic parsing of the command format includes automatic acquisition, parsing, and format checking of the command.

[0015] Preferably, the resource pool corresponds to a plurality of sram buffers, and the granularity of the buffer is 4224 bytes.

[0016] Preferably, the automatic allocation of the buffer in the resource pool to receive the host data is implemented by applying a cache from the resource pool, and the cache application processing logic is as follows: a command request requiring cache application is put into a first-in-first-out FIFO, and if the cache application of the current command fails, the processing request of the command is reinserted into the FIFO to wait for the release of the resource.

[0017] A data path system using method based on a soft and hard fusion engine, comprising:

[0018] The system is powered on, the boundary value of the command check field and the threshold value of the idle block number are initialized;

[0019] The host command is obtained, and the command self-analysis module performs command legality checking according to the set threshold value;

[0020] The data transmission module calculates the data transmission amount, automatically obtains the cache block, analyzes and obtains the PRP address entry, and starts the dma transmission;

[0021] The adaptive flash block management module provides a space block and flash programming, and updates the logical-physical address mapping table;

[0022] When an abnormal power-off is detected, the abnormal power-off cooperative processing module cancels the command automatic takeover function, and writes the current cache content to the NAND;

[0023] The logical-physical mapping table is updated, the current block information is output to the control software, the software completes the log and mapping table saving, and the power-off is completed.

[0024] A data path device based on a soft and hard fusion engine, comprising a processor and a memory storing program instructions, the processor is configured to execute the program instructions when running, and the data path method based on the soft and hard fusion engine is executed.

[0025] A computer readable storage medium, which stores a computer program, the program is executed by a processor to realize the data path method based on the soft and hard fusion engine.

[0026] The advantages of the present application are that the present application reduces the intervention of software functions as much as possible through the design of the soft and hard fusion engine, so that the data transmission process is more efficient, and the loss of data transmission in the path is reduced. This improvement not only improves the data transmission speed, but also optimizes the resource utilization efficiency.

[0027] The abnormal power-off protection mechanism designed by the present application can quickly respond when an abnormal power-off interruption is sensed, automatically close the automatic management function of the flash idle block, and write the data in the cache to the NAND flash in time, thereby minimizing the risk of data loss. This mechanism not only enhances the reliability of data, but also reduces the design difficulty of the standby power circuit, making the overall system more stable and reliable.

[0028] The method of the present application not only supports the traditional LBA access mode, but also can adapt to new access modes such as ZNS, showing strong flexibility and applicability. This design makes the present application better meet the needs of different application scenarios, improving its market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0030] Figure 1 Schematic diagram of the process of the present invention.

[0031] Figure 2 A schematic diagram of the system usage structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0033] Example 1

[0034] A data path system based on a hardware-software fusion engine improves the resource allocation efficiency of the data transmission engine while meeting queue priorities through the hardware-software fusion engine and scheduling algorithm design, realizes automatic collaborative processing of commands, reduces command processing delay and processing time, ensures service quality, and meets high-performance and high-reliability application requirements. The system includes: a command self-parsing module, a collaborative data transmission module, an adaptive flash memory block management module, and an abnormal power-off collaborative processing module.

[0035] The command self-parsing module is coupled to the command acquisition unit. After reading the command back from the host, it calculates the logical address according to the number of namespaces and automatically checks each command code in the command according to the configured error checking conditions.

[0036] As a refinement of the above embodiment, this module is used to automatically acquire, parse, and format commands. It also rearranges the original commands sent by the host according to the requirements of the collaborative data transmission module, facilitating the data transmission module's calculation of the data transmission volume. The command format check is performed based on the legal value range of the fields configured by the software. If any of the values ​​do not meet the requirements, command processing is terminated and an error code is returned to the host.

[0037] The cooperative data transmission module is configured with a resource pool during power-on initialization, automatically allocates a buffer in the resource pool to receive host data when processing a write command, and automatically synchronously updates a copy of the host data to a corresponding offset in the DDR cache after the host data transmission is completed; automatically acquires a PRP address and starts DMA data transmission, and sends a completion message to the FIFO interacting with the NAND control module after the transmission is completed; and dynamically allocates DMA according to the load of each DMA engine.

[0038] As a refinement of the above embodiment, the data cooperative transmission module is the key to the design of the software and hardware cooperative transmission engine. The cooperative data transmission module automatically calculates the data transmission amount according to the command format output by the command self-analysis module, and applies for occupying the corresponding cache from the software-configured resource pool to receive host data. The design logic of applying for the cache is to design a first-in-first-out FIFO, and put the command request that needs to apply for the cache into the FIFO. If the cache application of the current command fails, the processing request of the command is reinserted into the FIFO to wait for the release of the resource. The second function of the cooperative data transmission module is to automatically acquire a PRP address and start DMA data transmission. This process does not require software participation. After the host data transmission is completed, a copy of the host data is automatically synchronously updated to the corresponding offset in the DDR cache for data recovery, and a completion message is sent to the FIFO interacting with the adaptive flash block management module. When scheduling the DMA engine for data transmission, the working pressure between the DMAs is coordinated according to the working state of the DMA engine to avoid the problem of unbalanced load of the DMA.

[0039] The resource pool corresponds to a plurality of sram buffers, and the granularity of the buffer is 4224 bytes.

[0040] The automatic allocation of the buffer in the resource pool to receive the host data is implemented by applying for the cache from the resource pool. The application cache processing logic is as follows: the command request that needs to apply for the cache is put into a first-in-first-out FIFO. If the cache application of the current command fails, the processing request of the command is reinserted into the FIFO to wait for the release of the resource.

[0041] The adaptive flash block management module is used to provide a free writable NAND flash block in real time, perform flash block recycling, erasing, and changing logical-physical mapping table operations according to a software-set free block threshold, and process messages in the interaction FIFO. When new data is written from the interaction FIFO, a write programming action to the NAND flash block is started, and the logical address-physical address mapping table is updated after the writing is completed.

[0042] As a refinement of the above embodiment, this module is mainly responsible for writing the data in the previous-level data collaborative transmission cache into the flash memory, including the flash memory block automatic management algorithm and the cache automatic save function. The flash memory block automatic management algorithm refers to providing free writable flash memory blocks in real time according to the free block threshold set by the software, and automatically recovering, erasing and changing the logical-physical mapping table of the flash memory blocks. The cache automatic save function refers to sending a message according to the data collaborative transmission module. When new data is obtained from the interactive fifo, the write programming action to the flash memory block is started, and after the write is completed, the logical address-physical address mapping table is updated.

[0043] The abnormal power-off collaborative processing module is used to disable the automatic management function of the flash memory free blocks when an abnormal power-off interruption is sensed, and at the same time, the data in the cache is promptly flushed to the NAND flash memory and the current block information is output.

[0044] As a refinement of the above embodiment, the abnormal power-off collaborative processing module can automatically turn off the automatic management function of the flash memory free blocks when it senses an abnormal power-off interruption, and at the same time flush the data in the cache to the NAND in a timely manner, update the mapping table, output the currently used physical block information, and hand it over to the software for management, and the software triggers functions such as log saving and mapping table flushing.

[0045] It should be noted that compared with traditional designs, this method minimizes software intervention and reduces data transmission losses. Furthermore, the designed power-off protection mechanism minimizes time consumption and reduces the difficulty of backup circuit design. Furthermore, this method supports both traditional LBA access methods and new access methods such as ZNS, making the design more flexible and highly applicable.

[0046] like Figure 2 As shown in the figure, its complete functional implementation also requires the basic hardware units of the SSD, including the main control chip (SoC), NAND FLASH flash memory, DDR cache, SRAM, power chip, and PCIe gold finger. The main control chip is the core of the SSD controller and is composed of modules such as the MCU, PCIe module, NVMe controller, and NAND flash controller.

[0047] Example 2

[0048] like Figure 1 As shown, a method for using a data path system based on a software and hardware fusion engine includes:

[0049] S1: The system is powered on and the initialization command checks the boundary value of the field and the threshold of the number of free blocks;

[0050] S2: Obtain host commands, and the command self-analysis module performs command validity checks based on the set threshold;

[0051] S3: The cooperative data transmission module calculates data transmission volume, automatically acquires a cache block, parses and acquires a PRP address entry, and starts a dma transmission;

[0052] S4: The self-adaptive flash block management module provides a space block and a flash programming, and updates a logical-physical address mapping table;

[0053] S5: An abnormal power-off is detected, an abnormal power-off cooperative processing module cancels a command automatic takeover function, and flushes current cache content to the NAND;

[0054] S6: A logical-physical mapping table is updated, current block information is output to control software, software completes log and mapping table saving, and power-off is completed.

[0055] The embodiment of the disclosure further provides a data path device based on a soft and hard fusion engine, including a processor and a memory. Optionally, the device can further include a communication interface and a bus. Wherein, the processor, the communication interface, and the memory can complete mutual communication through the bus. The communication interface can be used for information transmission. The processor can call logical instructions in the memory to execute the data path method based on the soft and hard fusion engine of the above-mentioned embodiment.

[0056] In addition, the logical instructions in the memory described above can be realized in the form of a software function unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0057] The memory as a computer readable storage medium can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the disclosure. The processor executes the program instructions / modules stored in the memory, thereby executing function applications and data processing, that is, realizing the data path method based on the soft and hard fusion engine in the above-mentioned embodiment.

[0058] The memory can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory.

[0059] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that the technical solutions described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalent ones. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data path system based on a soft and hard fusion engine, characterized by, Comprise: The command self-analysis module automatically analyzes the command format after reading the command from the host, and automatically checks each command code in the command according to the configured error checking conditions; The cooperative data transmission module is used for configuring a resource pool during power-on initialization, automatically allocating a buffer in the resource pool to receive host data during processing of a write command, and automatically synchronously updating a DDR cache corresponding to an offset after host data transmission is completed; automatically obtaining a PRP address and starting DMA data transmission, and sending a completion message to a fifo interacting with the NAND control module after transmission is completed; dynamically allocating DMA according to the load of each DMA engine; The adaptive flash block management module is used for providing a free writable NAND flash block in real time, performing flash block recycling, erasing, and changing logical-physical mapping table operations according to a free block threshold set by software, and processing messages in the interaction fifo, and starting a write programming action to the NAND flash block when new data is obtained from the interaction fifo, and updating the logical address-physical address mapping table after writing is completed; The abnormal power-off cooperative processing module is used for closing the automatic management function of the flash free block when an abnormal power-off interrupt is sensed, timely flushing the data in the cache to the NAND flash, and outputting the current block information.

2. The soft and hard fusion engine based data path system of claim 1, wherein, The command self-analysis module further automatically checks the command according to the error checking conditions configured by software after reading the command from the host, and the error checking conditions are field legal value intervals, including a legal range of logical addresses.

3. The soft and hard fusion engine based data path system of claim 1, wherein, The resource pool in the cooperative data transmission module is configured during power-on initialization, and is used for storing data to be processed, and improves data transmission efficiency by automatically allocating a buffer and synchronously updating a DDR cache.

4. The soft and hard fusion engine based data path system of claim 1, wherein, The adaptive flash block management module is also used for dynamically adjusting the allocation of the flash block according to the set free block threshold, so as to optimize the storage performance.

5. The soft and hard fusion engine based data path system of claim 1, wherein, The automatic analysis of the command format includes automatic acquisition, analysis, and format checking of the command.

6. The soft and hard fusion engine based data path system of claim 1, wherein, The resource pool corresponds to a plurality of sram buffers, and the granularity of the buffer is 4224 bytes.

7. The soft and hard fusion engine based data path system of claim 1 or 6, wherein, The automatic allocation of the buffer in the resource pool to receive host data is implemented by applying a cache from the resource pool, and the cache application processing logic is as follows: a command request requiring cache application is put into a fifo in a first-in-first-out manner, and if the cache application of the current command fails, the processing request of the command is reinserted into the fifo, and waits for the release of the resource.

8. A method of using the system of any one of claims 1-7, wherein, Comprise: System power-on, initialize the boundary value of the command checking field and the threshold value of the free block number; Obtain the host command, and the command self-analysis module performs command legality checking according to the set threshold value; The cooperative data transmission module calculates the data transmission amount, automatically obtains a cache block, parses and obtains a PRP address entry, and starts dma transmission; The adaptive flash block management module provides a space block and flash programming, and updates a logical-physical address mapping table; When an abnormal power-off is detected, the abnormal power-off cooperative processing module cancels the automatic takeover function, and flushes the current cache content to the NAND; The update logic-physical mapping table, output the current block information to the control software, software complete log and mapping table save, complete power-off.

9. A data path device based on a soft-hard fusion engine, comprising a processor and a memory having stored therein program instructions, the device being characterized by: The processor is configured to execute the use method as claimed in claim 8 when running the program instructions.

10. A computer-readable storage medium, characterized in that, A computer program is stored thereon, which is executed by a processor to realize the use method as claimed in claim 8.

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