Data migration method, device, equipment and medium

Abstract

The embodiment of the present application provides a data migration method, device, equipment and medium, which relates to the field of computer technology. The method includes: obtaining a first migration instruction and a second migration instruction, the first migration instruction includes a first identifier and a first address, the second migration instruction includes a second identifier and a second address, the first identifier corresponds to a first register, the second identifier corresponds to a second register, the first address is the storage address of the target data to be migrated in the first register; the second address is the write address of the target data in the second register; according to the first migration instruction, the target data at the first address in the first register is written to the implicit register; according to the second migration instruction, the target data in the implicit register is written to the second address in the second register. Applying the technical solution provided by the embodiment of the present application can simplify the migration operation at the bit level and reduce the instruction space occupied by the migration operation.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data migration method, device, equipment and medium. Background Art

[0002] The fifth-generation Reduced Instruction Set Computing V (RISC-V) is an open source instruction set architecture (ISA) based on the Reduced Instruction Set Computing (RISC) principle. RISC-V provides a standard basic instruction set and a series of optional extended instruction sets. Developers can customize processors suitable for their own application scenarios as needed.

[0003] Currently, RISC-V includes bit operation extension instructions, which can implement corresponding bit-level operations, such as fast index address calculation, bit statistics, bit extension, circular shift, etc. However, RISC-V lacks bit-level migration instructions. If bit-level migration operations are to be implemented, a large number of instructions are required, and the way to implement migration operations is relatively complex, occupying more instruction space. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a data migration method, apparatus, device and medium to simplify the bit-level migration operation and reduce the instruction space occupied by the migration operation. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a data migration method, the method comprising:

[0006] Obtain a first migration instruction and a second migration instruction, wherein the first migration instruction includes a first identifier and a first address, and the second migration instruction includes a second identifier and a second address, wherein the first identifier corresponds to a first register, and the second identifier corresponds to a second register, and the first address is a storage address of target data to be migrated in the first register; and the second address is a write address of the target data in the second register;

[0007] Writing the target data at the first address in the first register into a shadow register according to the first migration instruction;

[0008] According to the second migration instruction, the target data in the implicit register is written into the second address in the second register.

[0009] In some embodiments, the first migration instruction further includes a data length; the first address is the bit where the target data to be migrated is located in the first register;

[0010] The step of writing the target data at the first address in the first register into an implicit register according to the first migration instruction comprises:

[0011] Reading target data at a source position in the first register, the source position corresponding to the first address of the data length included in the first migration instruction;

[0012] The target data is written into an implicit register.

[0013] In some embodiments, the step of reading the target data at the source location in the first register includes:

[0014] Reading source data stored in the first register;

[0015] Shifting the data at the source position in the source data to the least significant bit;

[0016] The valid bit data of the lowest data length in the shifted source data is intercepted as the target data.

[0017] In some embodiments, the first migration instruction further includes a first module identifier, and the step of writing the target data into an implicit register includes:

[0018] Performing a processing operation corresponding to the first module identifier on the target data;

[0019] Write the processed target data to the implicit register.

[0020] In some embodiments, the first migration instruction further includes a data length; the first address is a starting offset of the target data to be migrated in the first register;

[0021] The step of writing the target data at the first address in the first register into an implicit register according to the first migration instruction comprises:

[0022] Read target data between the first address and the third address in the first register, where the length from the first address to the third address is the data length;

[0023] The target data is written into an implicit register.

[0024] In some embodiments, the step of reading target data between the first address and the third address in the first register includes:

[0025] Reading source data stored in the first register;

[0026] Shifting the data between the first address and the third address in the source data to the least significant bit;

[0027] The valid bit data of the lowest data length in the shifted source data is intercepted as the target data.

[0028] In some embodiments, the second migration instruction further includes a data length; the second address is a bit in the second register where the target data is written;

[0029] The step of writing the target data in the implicit register to the second address in the second register according to the second migration instruction comprises:

[0030] Reading the target data from the implicit register;

[0031] The target data is written into a destination position in the second register, where the destination position corresponds to the data length second address included in the second migration instruction.

[0032] In some embodiments, the step of writing the target data to a destination location in the second register includes:

[0033] Shifting each bit of the target data to a corresponding destination position;

[0034] Merging the shifted target data and the destination data to obtain migrated data, wherein the destination data is the data stored in the second register;

[0035] The migrated data is written into the second register.

[0036] In some embodiments, the second migration instruction further includes a second module identifier; and the step of writing the target data to the destination position in the second register includes:

[0037] Performing a processing operation corresponding to the second module identifier on the target data;

[0038] The processed target data is written into the destination position in the second register.

[0039] In some embodiments, the second migration instruction further includes a data length; the second address is a starting offset for writing the target data in the second register;

[0040] The step of writing the target data in the implicit register to the second address in the second register according to the second migration instruction comprises:

[0041] Reading the target data from the implicit register;

[0042] The target data is written into the interval from the second address to the fourth address in the second register, and the length from the second address to the fourth address is the data length.

[0043] In some embodiments, the step of writing the target data into the interval from the second address to the fourth address in the second register includes:

[0044] Shifting the target data to the interval between the second address and the fourth address;

[0045] Merging the shifted target data and the destination data to obtain migrated data, wherein the destination data is the data stored in the second register;

[0046] The migrated data is written into the second register.

[0047] In some embodiments, the step of reading the target data from the implicit register comprises:

[0048] Reading implicit data stored in the implicit register;

[0049] The target data is obtained by extracting the least significant bit data of the data length from the implicit data.

[0050] In some embodiments, the first migration instruction and the second migration instruction further include an operation code and an instruction function code, the operation code indicates the migration instruction, and the instruction function code indicates that the migration instruction is the first migration instruction or the second migration instruction;

[0051] The operation code is located at a first preset position in the first migration instruction and the second migration instruction;

[0052] The instruction function code is located at a second preset position in the first migration instruction and the second migration instruction;

[0053] The first identifier is located at a third preset position in the first migration instruction;

[0054] The second identifier is located at a fourth preset position in the second migration instruction;

[0055] The first migration instruction and the second migration instruction further include reserved bits, and the reserved bits are used to carry other function codes.

[0056] In a second aspect, an embodiment of the present application provides a data migration device, the device comprising:

[0057] an acquisition module, configured to acquire a first migration instruction and a second migration instruction, wherein the first migration instruction includes a first identifier and a first address, and the second migration instruction includes a second identifier and a second address, wherein the first identifier corresponds to a first register, and the second identifier corresponds to a second register, and the first address is a storage address of target data to be migrated in the first register; and the second address is a write address of the target data in the second register;

[0058] A first writing module, configured to write target data at the first address in the first register into an implicit register according to the first migration instruction;

[0059] The second writing module is used to write the target data in the implicit register into the second address in the second register according to the second migration instruction.

[0060] In some embodiments, the first migration instruction further includes a data length; the first address is a bit where the target data to be migrated in the first register is located; and the first writing module is specifically used to:

[0061] The target data at the source position in the first register is read, the source position corresponding to the first address of the data length included in the first migration instruction; and the target data is written into the implicit register.

[0062] In some embodiments, the first writing module is specifically used to:

[0063] Read the source data stored in the first register; shift the data at the source position in the source data to the least significant bit; and intercept the least significant bit data of the data length in the shifted source data as the target data.

[0064] In some embodiments, the first migration instruction further includes a first module identifier, and the first writing module is specifically configured to:

[0065] Performing a processing operation corresponding to the first modulus identifier on the target data; and writing the processed target data into an implicit register.

[0066] In some embodiments, the first migration instruction further includes a data length; the first address is a starting offset of the target data to be migrated in the first register; and the first writing module is specifically used to:

[0067] Read target data between the first address and the third address in the first register, where the length from the first address to the third address is the data length; and write the target data into an implicit register.

[0068] In some embodiments, the first writing module is specifically used to:

[0069] Read the source data stored in the first register; shift the data between the first address to the third address in the source data to the least significant bit; and intercept the least significant bit data of the data length in the shifted source data as the target data.

[0070] In some embodiments, the second migration instruction further includes a data length; the second address is a bit in the second register where the target data is written; and the second writing module is specifically configured to:

[0071] The target data is read from the implicit register; and the target data is written into a destination position in the second register, where the destination position corresponds to the data length second address included in the second migration instruction.

[0072] In some embodiments, the second writing module is specifically used to:

[0073] Shifting each bit of the target data to a corresponding destination position; merging the shifted target data and the destination data to obtain migrated data, wherein the destination data is the data stored in the second register; and writing the migrated data into the second register.

[0074] In some embodiments, the second migration instruction further includes a second module identifier; and the second writing module is specifically configured to:

[0075] Performing a processing operation corresponding to the second modulus identifier on the target data; and writing the processed target data into a destination position in the second register.

[0076] In some embodiments, the second migration instruction further includes a data length; the second address is a starting offset for writing the target data into the second register; and the second writing module is specifically configured to:

[0077] The target data is read from the implicit register; and the target data is written into the interval from the second address to the fourth address in the second register, where the length from the second address to the fourth address is the data length.

[0078] In some embodiments, the second writing module is specifically used to:

[0079] The target data is shifted to the interval between the second address and the fourth address; the shifted target data and the destination data are combined to obtain migrated data, where the destination data is the data stored in the second register; and the migrated data is written into the second register.

[0080] In some embodiments, the second writing module is specifically used to:

[0081] The implicit data stored in the implicit register is read; and the valid bit data of the lowest data length is intercepted from the implicit data to obtain the target data.

[0082] In some embodiments, the first migration instruction and the second migration instruction further include an operation code and an instruction function code, the operation code indicates the migration instruction, and the instruction function code indicates that the migration instruction is the first migration instruction or the second migration instruction;

[0083] The operation code is located at a first preset position in the first migration instruction and the second migration instruction;

[0084] The instruction function code is located at a second preset position in the first migration instruction and the second migration instruction;

[0085] The first identifier is located at a third preset position in the first migration instruction;

[0086] The second identifier is located at a fourth preset position in the second migration instruction;

[0087] The first migration instruction and the second migration instruction further include reserved bits, and the reserved bits are used to carry other function codes.

[0088] In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0089] Memory, used to store computer programs;

[0090] The processor is used to implement any method described in the first aspect when executing a program stored in the memory.

[0091] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any method described in the first aspect is implemented.

[0092] An embodiment of the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any method described in the first aspect of the above embodiments.

[0093] Beneficial effects of the embodiments of the present application:

[0094] In the technical solution provided in the embodiment of the present application, a bit-level migration instruction is constructed, and a first migration instruction for reading target data and a second migration instruction for writing target data are used to migrate the target data from the source register to the destination register, so as to achieve the migration of one data using two instructions, thereby reducing the number of instructions used for the migration operands, simplifying the bit-level migration operation, and reducing the instruction resources occupied by the migration operation. In addition, an implicit register is used during the execution of the instruction, which further saves the occupied instruction space and facilitates the implementation of more flexible and complex bit-level operations.

[0095] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0097] Figure 1 A schematic diagram of the instruction format of the RISC-V basic instruction set;

[0098] Figure 2 A schematic diagram of an opcode mapping table;

[0099] Figure 3 A schematic diagram of a flow chart of a data migration method provided in an embodiment of the present application;

[0100] Figure 4 A schematic diagram of a first format of a first migration instruction provided in an embodiment of the present application;

[0101] Figure 5 A schematic diagram of a second format of a first migration instruction provided in an embodiment of the present application;

[0102] Figure 6 A schematic diagram of a first format of a second migration instruction provided in an embodiment of the present application;

[0103] Figure 7 A schematic diagram of a second format of a second migration instruction provided in an embodiment of the present application;

[0104] Figure 8 A first detailed schematic diagram of step S32 provided in an embodiment of the present application;

[0105] Figure 9a A first schematic diagram of data migration provided in an embodiment of the present application;

[0106] Figure 9b A second schematic diagram of data migration provided in an embodiment of the present application

[0107] Fig.10 A detailed schematic diagram of step S81 provided in an embodiment of the present application;

[0108] Fig.11a A third schematic diagram of data migration provided in an embodiment of the present application;

[0109] Fig.11b A fourth schematic diagram of data migration provided in an embodiment of the present application;

[0110] Fig.12 A second detailed schematic diagram of step S32 provided in an embodiment of the present application;

[0111] Fig.13 A fifth schematic diagram of data migration provided in an embodiment of the present application;

[0112] Fig.14 A detailed schematic diagram of step S121 provided in an embodiment of the present application;

[0113] Fig.15 A sixth schematic diagram of data migration provided in an embodiment of the present application;

[0114] Fig.16 A first detailed schematic diagram of step S33 provided in an embodiment of the present application;

[0115] Fig.17a A seventh schematic diagram of data migration provided in an embodiment of the present application;

[0116] Fig.17b An eighth schematic diagram of data migration provided in an embodiment of the present application;

[0117] Fig.18 A detailed schematic diagram of step S161 provided in an embodiment of the present application;

[0118] Fig.19 A detailed schematic diagram of step S162 provided in an embodiment of the present application;

[0119] Fig.20a A ninth schematic diagram of data migration provided in an embodiment of the present application;

[0120] Fig.20b A tenth schematic diagram of data migration provided in an embodiment of the present application;

[0121] Fig.21 A second detailed schematic diagram of step S33 provided in an embodiment of the present application;

[0122] Fig. 22 An eleventh schematic diagram of data migration provided in an embodiment of the present application;

[0123] Fig.23 A detailed schematic diagram of step S212 provided in an embodiment of the present application;

[0124] Fig.24 A twelfth schematic diagram of data migration provided in an embodiment of the present application;

[0125] Fig.25 A schematic diagram of an instruction implementation provided in an embodiment of the present application;

[0126] Fig.26 A schematic diagram of the structure of a data migration device provided in an embodiment of the present application;

[0127] Fig. 27 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0128] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0129] RISC-V is an open source instruction set architecture based on the RISC principle, with the following features: 1) Open and modular: RISC-V provides a standard basic instruction set and a series of optional extended instruction sets, developers can customize the processor suitable for their own application scenarios as needed. 2) Simple and efficient: Based on the RISC principle, RISC-V is committed to achieving efficient data processing through fewer and simpler instructions to achieve the goal of increasing processing speed and reducing energy consumption. 3) Easy to expand. 4) Widely used: It can cover all kinds of computing devices. 5) Ecosystem support: There is currently a relatively complete ecosystem, including software tool chains, operating systems, hardware design and tools.

[0130] The standard RISC-V instruction set has the following characteristics: concise (helps to reduce chip area), fast calculation, not affected by architecture, etc. The RISC-V basic instruction set can include six types of instructions: R-type, I-type, S-type, B-type, U-type and J-type. The format of each basic instruction is as follows: Figure 1In the RISC-V basic instruction set, the length of an instruction is 32 bits (bits), and the instruction may include an operation code (opcode) field, a function code (func) field, a source register (rs) field, a destination register (rd) field, and an immediate value (imm) field.

[0131] The opcode field is used to carry the attribute function of the instruction and the type of instruction executed to distinguish different instructions. The length of the opcode field is 7 bits, such as the [6:0] bit field of each instruction.

[0132] The func field is used to carry the function code to further distinguish instructions. According to the field length, the func field can be divided into a 3-bit function code (funct3) field and a 7-bit function code (funct7) field. The length of the funct3 field is 3 bits, such as the [14:12] bit field of R-type instructions, I-type instructions, S-type instructions, and B-type instructions. The length of the funct7 field is 7 bits, such as the [31:25] bit field of R-type instructions.

[0133] The rs field is used to carry the source register identifier. The length of the rs field is 5 bits. An instruction may include one or more rs fields. For example, R-type instructions, S-type instructions, and B-type instructions include 2 rs fields, namely, the [19:15] bit field (rs1 field) of R-type instructions, S-type instructions, and B-type instructions, and the [24:20] bit field (rs2 field) of R-type instructions, S-type instructions, and B-type instructions. An I-type instruction includes 1 rs field, namely, the [19:15] bit field (rs1 field) of the I-type instruction.

[0134] The rd field is used to carry the destination register identifier. The length of the rd field is 5 bits, such as the [11:7] bit field of R-type instructions, I-type instructions, U-type instructions, and J-type instructions.

[0135] The imm field is used to carry unsigned or signed constants (i.e., immediate values) of any length. The length of the imm field is not fixed, such as the 12-bit [31:20]-bit field in I-type instructions, the 5-bit [11:6]-bit field and the 7-bit [31:25]-bit field in S-type instructions, the 1-bit [7]-bit field, the 4-bit [11:8]-bit field, the 6-bit [30:25]-bit field, and the 1-bit

[31] -bit field in B-type instructions, the 20-bit [31:12]-bit field in U-type instructions, the 8-bit [19:12]-bit field, the 1-bit

[20] -bit field, the 10-bit [30:21]-bit field, and the 1-bit

[31] -bit field in J-type instructions.

[0136] Figure 1 The characteristics of the instruction format in the basic instruction set shown are: 1) The content is simple and unified, and the instruction only includes the opcode field, rs1 field, rs2 field, rd field, func field and imm field; 2) The format is unified, and the segment fields of all rs1 fields, rs2 fields, rd fields, opcode fields and func fields are consistent; 3) All bits are regarded as illegal instructions with 0, which is conducive to debugging; 4) All instructions are 32 bits.

[0137] Currently, a large amount of remaining encoding space is reserved in RISC-V for the supplement of future extended instructions.

[0138] like Figure 2 The opcode map shown shows the correspondence between opcodes and different instruction types. Figure 2 In the example, the first row indicates the value of the bit position [4:2] of the instruction (inst), that is, the value of the opcode field [4:2]; the first column indicates the value of the bit position [6:5] of inst, that is, the value of the opcode field [6:5]. In the basic ISA, the values ​​of the 0th and 1st bits of all 32-bit instructions are 1, so the value of the bit position [1:0] of inst is 11, that is, the value of the opcode field [1:0] is 11. Figure 2 Omitted.

[0139] Each bit of the opcode field takes different values, corresponding to different instructions. For example, when inst[4:2] takes the value of 000 and inst[6:5] takes the value of 00, the opcode is 0000011, and the corresponding instruction function is load (LOAD); when inst[4:2] takes the value of 000 and inst[6:5] takes the value of 10, the opcode is 1000011, and the corresponding instruction function is floating-point multiply-add (MADD); when inst[4:2] takes the value of 010 and inst[6:5] takes the value of 00, the opcode is 0001011, which is a user-defined opcode (custom-1); when inst[4:2] takes the value of 101 and inst[6:5] takes the value of 10, the opcode is 1010111, which is an undefined / reserved opcode (reserved). For details on each opcode and the corresponding instruction function, please refer to the relevant documents of RISC-V, which will not be described in detail here.

[0140] like Figure 2 As shown, the opcode mapping table includes 4 user-defined opcodes and 3 undefined opcodes. These 7 opcodes can be used as opcodes for extended instructions.

[0141] In addition, standard RISC-V supports variable-length encoding of extended instructions. In the extended instructions of the optional compressed 16-bit instruction set, the value of the bit position [1:0] of inst is 00, 01, or 10. In the extended instructions of the standard instruction set with more than 32 bits of encoding, the value of the bit position [1:0] of inst is 11, and when the value of inst[4:2] is 111, the corresponding instruction length is greater than 32 bits (32b); when the value of inst[5] is 0, the corresponding instruction length is 48 bits (48b); when the value of inst[6:5] is 01, the corresponding instruction length is 64 bits (64b); when the value of inst[6:5] is 11, the corresponding instruction length is greater than or equal to 80 bits (≥80b). For details on the standard RISC-V instruction length encoding convention, please refer to the relevant documents of RISC-V, which will not be described in detail here.

[0142] Currently, RISC-V includes bit-manipulation extension instructions (also known as B extension instructions), which include four extension subsets. Among them, Zba is an address generation instruction, which is used to implement fast index address calculation. The overall operation is a base address plus index operation, and the index supports a maximum shift of 3 bits; Zbb is a basic bit-manipulation instruction, which is used to implement basic bit operations such as bit statistics, bit extension, and circular shift; Zbc is a carry-less multiplication instruction, which is used to implement carry-less multiplication in a polynomial ring on the Galois Field (GF) (2); Zbs is a single-bit instruction, which is used to implement single-bit extraction, setting, clearing, and negation operations.

[0143] The above B extension instructions lack bit-level migration instructions. If you want to implement bit-level migration operations, you need to use a large number of instructions to implement it. For example, if you need to move the data at bit0, bit2, bit4, and bit6 in the source register x5 to bit0, bit1, bit2, and bit3 in the destination register x31, then use the standard B extension instructions, and at least execute the following instructions 1 to 10:

[0144] Instruction 1: bext x28, x5, 6, which writes the data at bit 6 in register x5 to bit 0 in register x28;

[0145] Instruction 2: slli x28, x28, 3, which means to shift the data in register x28 to the left by 3 bits, so as to shift the data at bit 0 in register x28 to bit 3.

[0146] Instruction 3: bext x29, x5, 4, which writes the data at bit 4 in register x5 to bit 0 in register x29;

[0147] Instruction 4: slli x29, x29, 2, which means to shift the data in register x29 to the left by 2 bits, so as to shift the data at bit 0 in register x28 to bit 2.

[0148] Instruction 5: bext x30, x5, 2, which writes the data at bit 2 in register x5 to bit 0 in register x30;

[0149] Instruction 6: slli x30, x30, 1, which means to shift the data in register x30 to the left by 1 bit, so as to shift the data at bit 0 in register x28 to bit 1.

[0150] Instruction 7: bext x31, x5, 0, which writes the data at bit 0 in register x5 to bit 0 in register x31.

[0151] Instruction 8: or x29, x28, x29, that is, the data in register x28 and register x29 are logically ORed and written to register x29;

[0152] Instruction 9: or x30, x29, x30, which performs a logical OR operation on the data in register x29 and register x30 and writes the result to register x30.

[0153] Instruction 10: or x31, x30, x31, which performs a logical OR operation on the data in register x30 and register x31 and writes the data into register x31.

[0154] By executing the above instructions 1 to 10, bit-level data migration is achieved.

[0155] In the above data migration process, 10 instructions were used to migrate 4 bits of data, and an average of 2.5 instructions were required to migrate one bit of data. The method for implementing the migration operation is relatively complex and occupies more instruction space.

[0156] In order to solve the above problems, the embodiments of the present application provide a data migration method, which can be applied to electronic devices with processors such as computers and servers. For the convenience of description, the electronic devices are used as the execution subjects in the following, which is not a limitation. Figure 3 , is a flow chart of a data migration method provided in an embodiment of the present application, and the data migration method includes the following steps S31 to S33.

[0157] Step S31, obtain the first migration instruction and the second migration instruction, the first migration instruction includes a first identifier and a first address, the second migration instruction includes a second identifier and a second address, the first identifier corresponds to the first register, the second identifier corresponds to the second register, the first address is the storage address of the target data to be migrated in the first register; the second address is the write address of the target data in the second register.

[0158] Step S32: writing the target data at the first address in the first register into the implicit register according to the first migration instruction.

[0159] Step S33: write the target data in the implicit register into the second address in the second register according to the second migration instruction.

[0160] In the technical solution provided in the embodiment of the present application, a bit-level migration instruction is constructed, and a first migration instruction for reading target data and a second migration instruction for writing target data are used to migrate the target data from the source register to the destination register, so as to achieve the migration of one data using two instructions, thereby reducing the number of instructions used for the migration operands, simplifying the bit-level migration operation, and reducing the instruction resources occupied by the migration operation. In addition, an implicit register is used during the execution of the instruction, which further saves the occupied instruction space and facilitates the implementation of more flexible and complex bit-level operations.

[0161] In the above step S31, the first migration instruction is an instruction for reading the data to be migrated from the source register. The first migration instruction includes a source operand, such as a first identifier, one or more first addresses, wherein the first identifier is an identifier, an address, etc. of the source register, the source register is the source of the data to be migrated, the first address is the storage address of the data to be migrated in the source register, the first address can indicate a single bit in the source register, or can indicate the starting offset of a continuous bit interval in the source register, and the value range of the first address is <0~31> bit.

[0162] In the embodiment of the present application, the first migration instruction may include a first identification field and a first address field, which are used to carry the first identification and the first address respectively.

[0163] The first migration instruction may further include an operation code for distinguishing the instruction type, wherein the operation code indicating the migration instruction may be Figure 2Any user-defined opcode or undefined opcode in. For example, opcode 0001011 indicates a first migration instruction where the first address indicates a single bit, and opcode 110111 indicates a first migration instruction where the first address indicates a starting offset of a continuous bit interval. In the embodiment of the present application, the first migration instruction may include an opcode field that carries the opcode.

[0164] The first migration instruction may also include an instruction function code (func) to further distinguish the instruction type. In the case where the instruction function code is included in the first migration instruction, the operation codes included in different first migration instructions may be the same. For example, the operation code 0001011 represents the first migration instruction in which the first address indicates a single bit, and also represents the first migration instruction in which the first address indicates the starting offset of a continuous bit interval. The instruction function code in the first migration instruction is 001, indicating that the first migration instruction is a migration instruction in which the first address indicates a single bit. The instruction function code in the first migration instruction is 010, indicating that the first migration instruction is a migration instruction in which the first address indicates the starting offset of a continuous bit interval. In an embodiment of the present application, the first migration instruction may include a func field that carries the instruction function code. Using this instruction function code to further distinguish the instruction type can reduce the occupied operation code and facilitate decoding processing.

[0165] The first migration instruction may also include a data length (sz) and a modulus (mod) identifier (such as a first modulus identifier). The data length indicates the number of bits (i.e., the number of bits) of the data to be migrated. The data length belongs to the control function code and may be a single-bit function code or a multi-bit function code. The modulus identifier indicates a preset processing operation to be performed on the data to be migrated. The modulus identifier belongs to the control function code and may be a single-bit function code or a multi-bit function code. One modulus identifier corresponds to one first address. If the first migration instruction includes multiple first addresses, the first migration instruction includes multiple corresponding modulus identifiers. For example, the modulus identifier may have values ​​of 00, 01, 10, and 11. When the modulus identifier has a value of 00 (i.e., mod=0), the corresponding processing operation may be to keep the data unchanged; when the modulus identifier has a value of 01 (i.e., mod=1), the corresponding processing operation may be to invert the data; when the modulus identifier has a value of 10 (i.e., mod=2), the corresponding processing operation may be to set the data to 0; when the modulus identifier has a value of 11 (i.e., mod=3), the corresponding processing operation may be to set the data to 1. The processing operation corresponding to the modulus identifier is not limited here. In the embodiment of the present application, the first migration instruction may include an sz field carrying the data length and a mod field carrying the modulus identifier.

[0166] In the embodiment of the present application, the first migration instruction may further include a reserved bit (R), which is located at any position in the first migration instruction that does not conflict with other fields, and the reserved bit may be used to carry other function codes such as clear, addition or subtraction. The reserved bit facilitates further expansion of the migration instruction.

[0167] In order to facilitate the implementation of the instruction and reduce the impact on the existing instruction system, the positions of the operation code, instruction function code and first identifier included in the first migration instruction are fixed, such as the operation code is located at the first preset position in the first migration instruction; the instruction function code is located at the second preset position in the first migration instruction; the first identifier is located at the third preset position in the first migration instruction. The first preset position, the second preset position and the third preset position can be set according to actual needs.

[0168] For example, Figure 4 The first migration instruction shown in the figure, the first row indicates the first migration instruction of a single bit indicated by the first address, and the second row indicates the first migration instruction of the starting offset of a continuous bit interval indicated by the first address. In these two first migration instructions, the [6:0] bit field is the opcode field carrying the operation code, the [14:12] bit field is the func field carrying the instruction function code, and the [19:15] bit field is the rs1 field carrying the first identifier.

[0169] In the first line of instructions, the [24:20] bit field is the first field carrying the first address (i.e., the SRC_POS1 field), the [29:25] bit field is the second field carrying the first address (i.e., the SRC_POS2 field), the [7] bit field is the sz field carrying the data length, the [9:8] bit field is the first mod field carrying the mod identifier (i.e., the mod1 field), and the mod1 field corresponds to the SRC_POS1 field, and the [11:10] bit field is the second mod field carrying the mod identifier (i.e., the mod2 field), and the mod2 field corresponds to the SRC_POS2 field. In the second line of instructions, the [24:20] bit field is the field carrying the first address (i.e., the SRC_OFS field), and the [29:25] bit field is the sz field carrying the data length.

[0170] The other fields in the first and second lines of instructions are reserved bits, namely, R fields.

[0171] Figure 4 The first migration instruction shown is only an example, and the first migration instruction can also be implemented in other formats, such as Figure 5 As shown, the first row represents a first migration instruction in which the first address indicates a single bit, and the second row represents a first migration instruction in which the first address indicates a starting offset of a continuous bit interval. Figure 5 The two first migration instructions shown are Figure 4 The two first migration instructions shown are similar, except that Figure 5 In the two first migration instructions shown, the [11:7] bit field is the sz field carrying the data length, and in the second row of instructions, the [29:25] bit field is the R field. In the embodiment of the present application, the specific structure of the first migration instruction is not limited.

[0172] also, Figure 4 In the example, the first migration instruction includes at most two first addresses. The first migration instruction can also include more first addresses, as long as the information length included in the first migration instruction is less than the instruction length specified by RISC-V (such as the standard 32 bits or the extended 48 bits, 64 bits).

[0173] The second migration instruction is an instruction for writing the data to be migrated into the destination register. The second migration instruction includes a destination operand, such as a second identifier, one or more second addresses, wherein the second identifier is an identifier, an address, etc. of the destination register, the destination register is the destination of the data to be migrated, the second address is the write address of the data to be migrated in the destination register, the second address can indicate a single bit in the destination register, or the starting offset of a continuous bit interval in the destination register, and the value range of the second address is <0~31> bit.

[0174] In the embodiment of the present application, the second migration instruction may include a second identification field and a second address field, which are used to carry the second identification and the second address, respectively.

[0175] The second migration instruction may further include an operation code for distinguishing the instruction type, wherein the operation code indicating the migration instruction may be Figure 2 For example, the operation code 0001011 indicates a second migration instruction where the second address indicates a single bit, and the operation code 110111 indicates a second migration instruction where the second address indicates a starting offset of a continuous bit interval.

[0176] The opcode of the second migration instruction may be the same as or different from the opcode of the first migration instruction. For example, the opcode 0001011 represents the second migration instruction, and the opcode 110111 represents the first migration instruction; or, the first migration instruction and the second migration instruction are both represented by the opcode 0001011. In the embodiment of the present application, the second migration instruction may include an opcode field that carries the opcode.

[0177] The second migration instruction may also include an instruction function code (func) to further distinguish the instruction type. In the case where the second migration instruction includes an instruction function code, the operation codes included in different second migration instructions may be the same. For example, the operation code 0001011 represents a second migration instruction in which the second address indicates a single bit, and also represents a second migration instruction in which the second address indicates a starting offset of a continuous bit interval. The instruction function code in the second migration instruction is 001, indicating that the second migration instruction is a migration instruction in which the second address indicates a single bit. The instruction function code in the second migration instruction is 010, indicating that the second migration instruction is a migration instruction in which the second address indicates a starting offset of a continuous bit interval. In an embodiment of the present application, the second migration instruction may include a func field that carries the instruction function code.

[0178] In the case where the first migration instruction and the second migration instruction include an instruction function code, the operation codes included in different first migration instructions and different second migration instructions may be the same. For example, the operation code 0001011 indicates a second migration instruction where the second address indicates a single bit, indicates a second migration instruction where the second address indicates a starting offset of a continuous bit interval, indicates a first migration instruction where the first address indicates a single bit, and also indicates a first migration instruction where the first address indicates a starting offset of a continuous bit interval; the instruction function code in the migration instruction is 001, indicating that the migration instruction is a first migration instruction where the first address indicates a single bit; the instruction function code in the migration instruction is 010, indicating that the migration instruction is a first migration instruction where the first address indicates a starting offset of a continuous bit interval; the instruction function code in the migration instruction is 011, indicating that the migration instruction is a second migration instruction where the second address indicates a single bit; the instruction function code in the migration instruction is 100, indicating that the migration instruction is a second migration instruction where the second address indicates a starting offset of a continuous bit interval.

[0179] This instruction function code is used to further distinguish instruction types, which can reduce the occupied operation codes and facilitate decoding processing.

[0180] The second migration instruction may also include a data length (sz) and a modulus (mod) identifier (such as a second modulus identifier). The data length indicates the number of bits (i.e., the number of bits) of the data to be migrated. To ensure the correctness of the data migration, the data length included in the second migration instruction is less than or equal to the data length included in the first migration instruction. The modulus identifier indicates a preset processing operation to be performed on the data to be migrated. The modulus identifier belongs to a control function code, which may be a single-bit function code or a multi-bit function code. One modulus identifier corresponds to one second address. If the second migration instruction includes multiple second addresses, the second migration instruction includes multiple corresponding modulus identifiers. The specific value of the modulus identifier and the processing operation corresponding to the modulus identifier can be found in the above-mentioned related description. In an embodiment of the present application, the second migration instruction may include an sz field carrying the data length and a mod field carrying the modulus identifier.

[0181] In the embodiment of the present application, the second migration instruction may further include a reserved bit (R), which is located at any position in the second migration instruction that does not conflict with other fields, and the reserved bit may be used to carry other function codes such as clear, addition or subtraction. The reserved bit facilitates further expansion of the migration instruction.

[0182] To facilitate the implementation of the instruction and reduce the impact on the existing instruction system, the positions of the operation code, instruction function code and second identifier included in the second migration instruction are fixed, such as the operation code is located at the first preset position in the second migration instruction; the instruction function code is located at the second preset position in the second migration instruction; the second identifier is located at the fourth preset position in the second migration instruction. The first preset position, the second preset position and the fourth preset position can be set according to actual needs.

[0183] For example, Figure 6 The second migration instructions shown in the figure, the first row indicates the second migration instruction of a single bit indicated by the second address, and the second row indicates the second migration instruction of the starting offset of a continuous bit interval indicated by the second address. In these two types of second migration instructions, the [6:0] bit field is the opcode field carrying the operation code, the [14:12] bit field is the func field carrying the instruction function code, and the [11:7] bit field is the rd field carrying the second identifier.

[0184] In the first line of instructions, the [24:20] bit field is the first field carrying the second address (i.e., the DST_POS1 field), the [29:25] bit field is the second field carrying the second address (i.e., the DST_POS2 field), the

[15] bit field is the sz field carrying the data length, the [17:16] bit field is the first mod field carrying the mod identifier (i.e., the mod1 field), and the mod1 field corresponds to the DST_POS1 field, the [19:18] bit field is the second mod field carrying the mod identifier (i.e., the mod2 field), and the mod2 field corresponds to the DST_POS2 field. In the second line of instructions, the [24:20] bit field is the field carrying the second address (i.e., the DST_OFS field), and the [29:25] bit field is the sz field carrying the data length.

[0185] The other fields in the first and second lines of instructions are reserved bits, namely, R fields.

[0186] Figure 6 The second migration instruction shown is only an example, and the second migration instruction can also be implemented in other formats, such as Figure 7 As shown, the first row indicates a second migration instruction in which the second address indicates a single bit, and the second row indicates a second migration instruction in which the second address indicates a starting offset of a continuous bit interval. Figure 7 The two second migration instructions shown are Figure 6 The two second migration instructions shown are similar except that Figure 7 In the two second migration instructions shown, the [19:15] bit field is the sz field carrying the data length, and in the second row of instructions, the [29:25] bit field is the R field. In the embodiment of the present application, the specific structure of the second migration instruction is not limited.

[0187] also, Figure 6 In the example, the second migration instruction includes at most two second addresses. The second migration instruction can also include more second addresses, as long as the information length included in the second migration instruction is less than the instruction length specified by RISC-V (such as the standard 32 bits or the extended 48 bits, 64 bits).

[0188] In the embodiment of the present application, when performing data migration, the electronic device obtains a migration instruction for reading the data to be migrated (i.e., the target data), i.e., the first migration instruction, and obtains a migration instruction for writing the data to be migrated (i.e., the target data), i.e., the second migration instruction. The number of the first migration instructions may be one or more, and the number of the second migration instructions may be one or more.

[0189] To ensure accurate data migration, the electronic device can first obtain the first migration instruction, then obtain the second migration instruction, and execute the first migration instruction and the second migration instruction in a pipeline manner, that is, first execute step S32; after the first migration instruction is executed, execute step S33 to improve instruction processing efficiency and accuracy.

[0190] Before obtaining the first migration instruction and the second migration instruction, the electronic device first uses a compiler to compile the first migration instruction and the second migration instruction together. After that, the electronic device first obtains the compiled first migration instruction, and then obtains the compiled second migration instruction. Then, after executing the first migration instruction, the electronic device will execute the second migration instruction instead of other instructions, thereby improving the efficiency of data migration.

[0191] In the above steps S32 and S33, the implicit register is a fixed register pre-bound to the first migration instruction and the second migration instruction. The length of the implicit register can be the same as the length of the first register and the second register, such as 32 bits. After the electronic device obtains the first migration instruction, it can decode the first migration instruction, that is, extract the values ​​of all fields from the first migration instruction, identify the operation code and instruction function code included in the first migration instruction, and determine that the first migration instruction is a migration instruction for migrating data from the source register to the implicit register.

[0192] The electronic device determines the first register (ie, the source register) based on the extracted first identifier, and obtains the data at the first address from the first register based on the extracted first address, and the data is the target data. The electronic device writes the obtained target data into the implicit register.

[0193] After the electronic device obtains the second migration instruction, it can decode the second migration instruction, that is, extract the values ​​of all fields from the second migration instruction, identify the operation code and instruction function code included in the second migration instruction, and determine that the second migration instruction is a migration instruction for migrating data from an implicit register to a destination register.

[0194] The electronic device obtains the target data to be migrated from the implicit register, determines the second register (ie, the destination register) based on the extracted second identifier, and writes the obtained target data to the second address in the second register based on the extracted second address.

[0195] The execution of the first migration instruction and the second migration instruction are respectively described below.

[0196] (1) First migration instruction.

[0197] In an embodiment of the present application, according to the different types of the first address included in the first migration instruction, the first migration instruction can be divided into a first migration instruction for migrating discrete data (such as a movbittoshad instruction) and a first migration instruction for migrating continuous data (such as a movbitstoshad instruction).

[0198] 1) movbittoshad instruction.

[0199] The movbittoshad instruction may include a first identifier, a first address, and a data length. In the movbittoshad instruction, the first address is the bit in the first register where the target data to be migrated is located, that is, the first address indicates a single bit in the source register. Figure 4 Taking the first line of instructions shown as an example, the first address carried by the SRC_POS1 field is 00110, indicating that the first bit of target data is at bit 6 in the first register; the first address carried by the SRC_POS2 field is 00010, indicating that the second bit of target data is at bit 2 in the first register.

[0200] In this case, if Figure 8 As shown, the above step S32 can be implemented by the following steps:

[0201] Step S81, reading target data at a source position in a first register, where the source position corresponds to a first address of the first data length included in a first migration instruction;

[0202] Step S82, writing the target data into the implicit register.

[0203] In an embodiment of the present application, the electronic device can directly read the target data at the source position from the first register, and write the read target data into the implicit register starting from the least significant bit (such as bit0).

[0204] Still Figure 4 Taking the first line of instruction as an example, the first address carried by the SRC_POS1 field is 00110, which is the bit6 position in the first register, and the first address carried by the SRC_POS2 field is 00010, which is the bit2 position in the first register. The value carried by the sz field is 0, indicating that the data length is 1; the value carried by the sz field is 1, indicating that the data length is 2. The data stored in the first register is as follows Figure 9a and Figure 9b shown.

[0205] When the data length is 1, the source position corresponds to the first address, that is, 00110 carried by the SRC_POS1 field; the electronic device directly reads the data "1" (target data) at the bit6 position (source position) in the first register; and writes "1" to the bit0 of the implicit register, such as Figure 9a shown.

[0206] When the data length is 2, the source position corresponds to the first two first addresses, that is, 00110 carried by the SRC_POS1 field and 00010 carried by the SRC_POS2 field; the electronic device directly reads the data "1" (target data) at the bit6 position (source position) in the first register and the data "0" (target data) at the bit2 position (source position); writes "1" and "0" to bit0 and bit1 of the implicit register, such as Figure 9b shown.

[0207] In the embodiment of the present application, the electronic device can read only the target data from the first register, the amount of data read by the electronic device is small, and the data reading efficiency is high.

[0208] In the present application embodiment, Fig.10 As shown, the electronic device can also implement the above step S81 through the following steps:

[0209] Step S101, reading source data stored in a first register;

[0210] Step S102, shifting the data at the source position in the source data to the least significant bit;

[0211] Step S103, intercepting the valid bit data with the lowest data length in the shifted source data as the target data.

[0212] In an embodiment of the present application, the electronic device reads all the data in the first register to obtain the source data. If the length of the first register is 32 bits, the electronic device obtains 32 bits of source data. Based on the source data, the electronic device sequentially shifts the target data at each source position to the least significant bit to obtain the shifted source data. The electronic device can intercept data with a length of the data length starting from the least significant bit of the source data based on the data length, and the intercepted valid bit data is the target data. The electronic device writes the target data into the implicit register.

[0213] In the embodiment of the present application, in order to ensure that the target data is accurately written into the implicit register and reduce the interference of other data, the electronic device can generate a mask according to the data length, and the length of the mask is the same as the length of the implicit register, such as 32 bits. The valid bit of the lowest data length in the mask is 1, and the other bits are 0. When writing the read target data into the implicit register, the electronic device can perform a logical AND operation on the shifted source data and the mask to obtain the target data.

[0214] Still Figure 4Taking the first line of instructions shown in the figure as an example, the first address carried by the SRC_POS1 field is 00110, and the first address carried by the SRC_POS2 field is 00010. The data stored in the first register is as follows Fig.11a and Fig.11b shown.

[0215] When the data length is 1, the source position corresponds to the first address, that is, 00110 carried by the SRC_POS1 field (corresponding to the bit6 position); the electronic device reads all the data stored in the first register (that is, the source data), and shifts the data "1" at the read bit6 position to the least significant bit bit0; the electronic device generates a mask with bit0 as 1 and other bits as 0 according to the data length, and performs a logical AND operation on the shifted source data and the mask to obtain the target data, such as Fig.11a As shown, the target data is written into the implicit register. At this time, the value at bit 0 of the implicit register is "1", and the values ​​at other bits are 0.

[0216] When the data length is 2, the source position corresponds to the first two first addresses, that is, 00110 (corresponding to the bit6 position) carried by the SRC_POS1 field, and 00010 (corresponding to the bit2 position) carried by the SRC_POS2 field; the electronic device reads all the data stored in the first register (that is, the source data), shifts the data "1" at the read bit6 position to the least significant bit bit0, and shifts the data "0" at the read bit2 position to the second least significant bit bit1; the electronic device generates a mask with bit0~bit1 as 1 and other bits as 0 according to the data length, performs a logical AND operation on the shifted source data and the mask to obtain the target data, such as Fig.11b As shown, the target data is written into the implicit register. At this time, the value at bit0 of the implicit register is "1", the value at bit1 is "0", and the values ​​at other bits are 0.

[0217] In an embodiment of the present application, after reading the source data, the electronic device may also copy one or more copies of the source data according to the data length, and shift the copied one or more copies of the source data to obtain the shifted source data and target data.

[0218] For example, when the data length is 2, after reading the source data, the electronic device can copy 2 copies of the source data. In the first copy of the source data, the data "1" at the read bit6 position is shifted to the least significant bit bit0, and the other bits are cleared. In the second copy of the source data, the data "0" at the read bit2 position is shifted to the second least significant bit bit1, and the other bits are cleared. The electronic device performs a logical OR operation on the shifted first copy of the source data and the shifted second copy of the source data to obtain the shifted source data; the electronic device generates a mask with bit0~bit1 as 1 and other bits as 0 according to the data length, and performs a logical AND operation on the shifted source data and the mask to obtain the target data.

[0219] The electronic device can also generate a mask with a value of 1 at the source position and values ​​of 0 at other bits according to the data length and the source position, perform a logical AND operation on the source data and the mask, and then shift the data at the source position after the AND operation to the least significant bit to obtain the shifted data as the target data. The method for the electronic device to obtain the target data is not limited here.

[0220] In the embodiment of the present application, the electronic device can read all the source data from the first register and obtain the target data based on the source data. The processing logic executed by the electronic device is simpler and easy to implement instructions.

[0221] In some embodiments, the first migration instruction may further include a module identifier, namely a first module identifier, indicating a preset processing operation to be performed on the target data. On this basis, the above step S82 may be implemented by the following steps: performing the processing operation corresponding to the first module identifier on the target data; and writing the processed target data into the implicit register.

[0222] After the electronic device reads the target data, it can determine the processing operation that needs to be performed on the target data based on the value of the first module identifier, and then perform the determined processing operation on the target data to obtain the processed target data, and write the processed target data into the least significant bit of the implicit register.

[0223] For example, the data length is 2, and the source position corresponds to the first two addresses. The electronic device reads the target data "01", where "0" corresponds to the modulus identifier mod2, mod2=1, that is, the processing operation corresponding to mod2 is to set the data to 0, then the electronic device sets "0" to 0 to obtain "0", and "1" corresponds to the modulus identifier mod1, mod1=1, that is, the processing operation corresponding to mod2 is to invert the data, then the electronic device inverts "1" to obtain "0", and then the electronic device obtains the processed target data "00".

[0224] In the embodiment of the present application, the electronic device can process the read target data based on the preset module identifier, thereby providing richer functions while realizing bit-level data migration.

[0225] Still Figure 4 Taking the first line of instructions shown as an example, the first migration instruction can be in the form of: movbittoshad rs1 (corresponding to the rs1 field), src_pos1 (corresponding to the SRC_POS1 field), src_pos2 (corresponding to the SRC_POS2 field), mod1 (corresponding to the mod1 field), mod2 (corresponding to the mod2 field), size (corresponding to the sz field). The order of the fields is not limited here, as long as the electronic device can recognize the value of the corresponding field.

[0226] 2) movbitstoshad instruction.

[0227] The movbitstoshad instruction may include a first identifier, a first address, and a data length. In the movbitstoshad instruction, the first address is the starting offset of the target data to be migrated in the first register, that is, the first address indicates the starting offset of the continuous bit interval in the source register. Figure 4 Taking the second line of instructions shown as an example, the first address carried by the SRC_OFS field is 00011, indicating that the starting offset of the target data is at bit 3 in the first register, and the value carried by the sz field is 00010, indicating that the data length is 3, that is, the length of the target data is 3, the first bit of the target data is at bit 3 in the first register, the second bit of the target data is at bit 4 in the first register, and the last bit of the target data is at bit 5 in the first register. For ease of description, the bit where the last bit of the target data is located in the first register is referred to as the third address. In the above example, the third address is 00101.

[0228] In this case, if Fig.12 As shown, the above step S32 can also be implemented by the following steps:

[0229] Step S121, read the target data between the first address and the third address in the first register, where the length from the first address to the third address is the data length;

[0230] Step S122, writing the target data into the implicit register.

[0231] The electronic device can determine the third address according to the data length and the first address, and directly read the target data between the first address and the third address from the first register, and write the read target data into the implicit register starting from the least significant bit (such as bit0).

[0232] Still Figure 4 Taking the second line of instruction as an example, the first address carried by the SRC_OFS field is 00011, that is, the bit 3 position in the first register, and the value carried by the sz field is 00010, that is, the data length is 3. The data stored in the first register is as follows Fig.13 shown.

[0233] The electronic device determines the third address as 00101, i.e., bit 5 in the first register, based on the data length and the first address, and directly reads the data "010" (target data) at bit 3 to bit 5 in the first register; writes "010" to bit 0 to bit 2 of the implicit register, such as Fig.13 shown.

[0234] In the embodiment of the present application, the electronic device executes the first migration instruction to realize the migration of multiple continuous data, further increasing the amount of data that can be migrated at one time, and the read target data is stored in sequence in the implicit register, so that when the second migration instruction is subsequently executed, the target data can be written to the corresponding position. In addition, the electronic device only reads the target data from the first register, the amount of data read is small, and the data reading efficiency is high.

[0235] In the present application embodiment, Fig.14 As shown, the electronic device can also implement the above step S121 through the following steps:

[0236] Step S141, reading source data stored in the first register;

[0237] Step S142, shifting the data between the first address to the third address in the source data to the least significant bit;

[0238] Step S143, intercepting the valid bit data with the lowest data length in the shifted source data as the target data.

[0239] In an embodiment of the present application, the electronic device reads all the data in the first register to obtain the source data. If the length of the first register is 32 bits, the electronic device obtains 32 bits of source data. Based on the source data, the electronic device shifts the target data between the first address and the third address to the least significant bit to obtain the shifted source data. Based on the data length, the electronic device can intercept data with a length of the data length starting from the least significant bit of the source data, and the intercepted valid bit data is the target data. The electronic device writes the target data into the implicit register.

[0240] In the embodiment of the present application, in order to ensure that the target data is accurately written into the implicit register and reduce the interference of other data, the electronic device can generate a mask with the minimum data length and the effective bit value of 1 and the other bits of 0 according to the data length, and perform a logical AND operation on the shifted source data and the mask to obtain the target data. Fig.10 Some descriptions about masks.

[0241] Still Figure 4 Taking the second line of instructions as an example, the first address carried by the SRC_OFS field is 00011 (corresponding to bit3 position), and the data stored in the first register is as follows Fig.15 shown.

[0242] The electronic device reads all the data (i.e., source data) stored in the first register, determines the third address to be 00101 (corresponding to bit5) according to the data length and the first address, and shifts the data "010" at the read bit3 position to bit5 position to bit0 to bit2, that is, shifts the data "0" at the read bit3 position to the least significant bit bit0, shifts the data "1" at the read bit4 position to the second least significant bit bit1, and shifts the data "0" at the read bit5 position to the third least significant bit bit2; the electronic device generates a mask with bit0 to bit2 as 1 and other bits as 0 according to the data length, performs a logical AND operation on the shifted source data and the mask to obtain the target data, such as Fig.15 As shown, the target data is written into the implicit register. At this time, the values ​​of bit0~bit2 of the implicit register are "0", "1" and "0" respectively, and the values ​​of other bits are 0.

[0243] The electronic device may also generate a mask with the bit value between the first address and the third address being 1 and the other bits being 0 according to the data length and the first address, perform a logical AND operation on the source data and the mask, and then shift the data between the first address and the third address after the AND operation to the least significant bit, and obtain the shifted data as the target data. The manner in which the electronic device obtains the target data is not limited here.

[0244] In the embodiment of the present application, the electronic device can read all the source data from the first register and obtain the target data based on the source data. The processing logic executed by the electronic device is simpler and easy to implement instructions.

[0245] Still Figure 4Taking the second line of instructions shown as an example, the first migration instruction can be in the form of: movbitstoshadrs1 (corresponding to the rs1 field), src_pos (corresponding to the SRC_OFS field), size (corresponding to the sz field). The order of the fields is not limited here, as long as the electronic device can recognize the value of the corresponding field.

[0246] (2) Second migration instruction.

[0247] In an embodiment of the present application, according to the different types of the second address included in the second migration instruction, the second migration instruction can be divided into a second migration instruction for migrating discrete data (such as a movbitfrshad instruction) and a second migration instruction for migrating continuous data (such as a movbitsfrshad instruction).

[0248] 1) movbitfrshad instruction.

[0249] The movbitfrshad instruction may include a second identifier, a second address, and a data length. In the movbitfrshad instruction, the second address is the bit in the second register where the target data is written, that is, the second address indicates a single bit in the destination register. Figure 6 Taking the first line of instructions shown as an example, the second address carried by the DST_POS1 field is 00011, indicating that the first bit of target data is written to bit 3 in the second register; the second address carried by the DST_POS2 field is 00001, indicating that the second bit of target data is written to bit 1 in the second register.

[0250] In this case, if Fig.16 As shown, the above step S33 can be implemented by the following steps:

[0251] Step S161, reading target data from the implicit register;

[0252] Step S162, writing the target data into a destination position in the second register, where the destination position corresponds to a second address of the first data length included in the second migration instruction.

[0253] In the embodiment of the present application, the electronic device may read the target data of the data length starting from the least significant bit (such as bit 0) of the implicit register, and write the read target data into the destination position of the second register.

[0254] Still Figure 6Taking the first line of instruction as an example, the second address carried by the DST_POS1 field is 00011, which is the bit3 position in the second register, and the second address carried by the DST_POS2 field is 00001, which is the bit1 position in the second register. The value carried by the sz field is 0, which means the data length is 1; the value carried by the sz field is 1, which means the data length is 2. The data stored in the implicit register is as follows Fig.17a and Fig.17b shown.

[0255] When the data length is 1, the destination position corresponds to the first second address, that is, 00011 carried by the DST_POS1 field; the electronic device directly reads the data "1" (target data) at the least significant bit 0 in the implicit register; and writes "1" to the bit 3 position (destination position) in the second register, such as Fig.17a shown.

[0256] When the data length is 2, the destination position corresponds to the first two second addresses, namely 00011 carried by the DST_POS1 field and 00001 carried by the DST_POS2 field; the electronic device directly reads the data "1" (target data) at the least significant bit bit0 in the implicit register and the data "0" (target data) at the second least significant bit bit1; writes "1" to the bit3 position (destination position) in the second register and writes "0" to the bit1 position (destination position) in the second register, such as Fig.17b shown.

[0257] In the embodiment of the present application, the electronic device executes the second migration instruction to achieve the migration of multiple data from the implicit register to the second register. Combined with the first migration instruction, the electronic device can achieve the migration of multiple data. When the data length is 2, the electronic device can migrate 2 data by executing the first migration instruction and the second migration instruction. On average, one instruction is used to migrate one data, which greatly reduces the number of instructions used in the migration operation. In addition, the electronic device can read only the target data from the implicit register, the amount of data read by the electronic device is small, and the data reading efficiency is high.

[0258] In the present application embodiment, Fig.18 As shown, the electronic device can also implement the above step S161 through the following steps:

[0259] Step S181, reading implicit data stored in the implicit register;

[0260] Step S182, extracting the valid bit data of the minimum data length from the implicit data to obtain the target data.

[0261] The electronic device reads all the data in the implicit register to obtain the implicit data. For example, if the length of the implicit register is 32 bits, the electronic device obtains 32 bits of implicit data. Based on the data length, the electronic device can intercept data with a length equal to the data length starting from the least significant bit of the implicit data. The intercepted valid bit data is the target data. By obtaining all the implicit data and intercepting the target data, the processing logic of the electronic device during the instruction execution process is simplified, which facilitates the instruction implementation.

[0262] In an embodiment of the present application, the electronic device may also generate a mask with the valid bit value of the minimum data length being 1 and the other bits being 0 according to the data length, and perform a logical AND operation on the implicit data and the mask to obtain the target data.

[0263] In the present application embodiment, Fig.19 As shown, the electronic device can also implement the above step S162 through the following steps:

[0264] Step S191, shifting each bit of the target data to the corresponding destination position;

[0265] Step S192, merging the shifted target data and the destination data to obtain the migrated data, where the destination data is the data stored in the second register;

[0266] Step S193, writing the migrated data into the second register.

[0267] In the embodiment of the present application, the electronic device can read all the data in the second register to obtain the target data. For example, if the length of the second register is 32 bits, the electronic device obtains 32 bits of target data. The electronic device sequentially shifts each target data read from the implicit register to the corresponding target position to obtain the shifted target data.

[0268] After obtaining the target data and the shifted target data, the electronic device can use the shifted target data to replace the data at the corresponding target position in the target data to obtain the shifted data. The electronic device writes the shifted data into the second register.

[0269] In an embodiment of the present application, in order to ensure that the target data is accurately written into the implicit register and to reduce interference from other data, the electronic device may generate a mask having a length that is the same as the length of the second register, such as 32 bits, based on the destination position. The value at the destination position in the mask is 0, and the values ​​of other bits are 1. When merging the shifted target data and the destination data, the electronic device may first perform a logical AND operation on the destination data and the mask, and perform a logical OR operation on the destination data after the AND operation and the shifted target data to obtain the migrated data. In this way, in the migrated data, the data at the destination position is the same as the shifted target data, and the data at other bits is the same as the destination data. The order in which the electronic device generates the mask and shifts the target data is not limited here.

[0270] Still Figure 6 Taking the first line of instructions shown in the figure as an example, the second address carried by the DST_POS1 field is 00011, and the second address carried by the DST_POS2 field is 00001. The data stored in the second register is as follows Fig.20a and Fig.20b shown.

[0271] When the data length is 1, the destination position corresponds to the first second address, that is, 00011 carried by the DST_POS1 field (corresponding to the bit3 position); the electronic device reads all the data stored in the second register (that is, the destination data), and generates a mask with bit3 as 0 and other bits as 1, performs a logical AND operation on the destination data and the mask to obtain the destination data after the AND operation; reads the target data from the implicit register, shifts the data "1" at the read bit0 to the bit3 position, and obtains the shifted target data; performs a logical OR operation on the destination data after the AND operation and the shifted target data to obtain the migrated data, such as Fig.20a As shown, the target data is written into the second register. At this time, the value at bit 3 of the second register is "1", and the values ​​at other bits remain unchanged.

[0272] When the data length is 2, the destination position corresponds to the first two second addresses, namely 00011 (corresponding to the bit3 position) carried by the DST_POS1 field, and 00001 (corresponding to the bit1 position) carried by the DST_POS2 field; the electronic device reads all the data stored in the second register (i.e., the destination data), and generates a mask with bit3 being 0, bit1 being 0, and other bits being 1, performs a logical AND operation on the destination data and the mask to obtain the destination data after the AND operation; reads the target data from the implicit register, shifts the data "1" at the read bit0 to the bit3 position, and shifts the data "0" at the read bit1 to the bit1 position to obtain the shifted target data; performs a logical OR operation on the destination data after the AND operation and the shifted target data to obtain the migrated data, such as Fig.20b As shown, the target data is written into the second register. At this time, the value at bit3 of the second register is "1", the value at bit1 is "0", and the values ​​at other bits remain unchanged.

[0273] In an embodiment of the present application, after obtaining the target data, the electronic device can also copy one or more copies of the target data according to the data length, and shift each bit of data in the copied one or more copies of the target data to the corresponding destination position to obtain the shifted target data.

[0274] For example, when the data length is 2, after the electronic device reads the target data from the implicit register, it can copy 2 copies of the target data. In the first copy of the target data, the data "1" at the read bit0 is shifted to the bit3 position, and the other bits are cleared. In the second copy of the source data, the data "0" at the read bit1 is shifted to the bit1 position, and the other bits are cleared. The electronic device performs a logical OR operation on the first shifted target data and the second shifted target data to obtain the shifted target data; the electronic device performs a logical OR operation on the target data after the AND operation and the shifted target data to obtain the migrated data. The way in which the electronic device obtains the migrated data is not limited here.

[0275] In the embodiment of the present application, the electronic device can read all the target data from the second register, replace the data at the corresponding position according to the target data, and then write it into the second register, which simplifies the processing logic during the execution of the electronic device and facilitates instruction implementation.

[0276] In some embodiments, the second migration instruction may further include a module identifier, namely a second module identifier, indicating a preset processing operation to be performed on the target data. On this basis, the above step S162 may be implemented by the following steps: performing the processing operation corresponding to the second module identifier on the target data; and writing the processed target data to the destination position in the second register.

[0277] After the electronic device reads the target data, it can determine the processing operation that needs to be performed on the target data according to the value of the second module identifier, and then perform the determined processing operation on the target data to obtain the processed target data, and write the processed target data to the destination location in the second register. For details, please refer to the above description of the first module identifier, which will not be described in detail here. In an embodiment of the present application, the electronic device can process the target data based on a preset module identifier, and provide richer functions while realizing bit-level data migration.

[0278] Still Figure 6 Taking the first line of instructions shown as an example, the second migration instruction can be in the form of: movbitfrshad rd (corresponding to the rd field), dst_pos1 (corresponding to the DST_POS1 field), dst_pos2 (corresponding to the DST_POS2 field), mod1 (corresponding to the mod1 field), mod2 (corresponding to the mod2 field), size (corresponding to the sz field). The order of the fields is not limited here, as long as the electronic device can recognize the value of the corresponding field.

[0279] 2) movbitsfrshad instruction.

[0280] The movbitstoshad instruction may include a second identifier, a second address, and a data length. In the movbitstoshad instruction, the second address is the starting offset of writing the target data in the second register, that is, the second address indicates the starting offset of the continuous bit interval in the destination register. Figure 6 Taking the second line of instructions shown as an example, the second address carried by the DST_OFS field is 00010, indicating that the starting offset of writing the target data is at bit 2 in the second register, and the value carried by the sz field is 00010, indicating that the data length is 3, that is, the length of the target data is 3, the first bit of target data is written to bit 2 in the second register, the second bit of target data is written to bit 3 in the second register, and the last bit of target data is written to bit 4 in the second register. For ease of description, the bit where the last bit of target data is written to the second register is referred to as the fourth address. In the above example, the fourth address is 00100.

[0281] In this case, if Fig.21 As shown, the above step S33 can also be implemented by the following steps:

[0282] Step S211, reading target data from the implicit register;

[0283] Step S212, writing the target data into the interval from the second address to the fourth address in the second register, where the length from the second address to the fourth address is the data length.

[0284] The electronic device can start from the least significant bit (such as bit0) of the implicit register, read the target data with a length equal to the data length, and determine the fourth address based on the data length and the second address, and write the read target data between the second address and the fourth address of the second register.

[0285] Still Figure 6 Taking the second line of instruction as an example, the second address carried by the DST_OFS field is 00010, that is, the bit 2 position in the second register, and the value carried by the sz field is 00010, indicating that the data length is 3. The data stored in the implicit register is as follows Fig. 22 shown.

[0286] The electronic device directly reads the data "010" (target data) at bit0~bit2 in the implicit register, and determines the fourth address as 00100, i.e., bit4 in the second register, based on the data length and the second address; writes the read "010" to bit2~bit4 of the second register, such as Fig. 22 shown.

[0287] In the embodiment of the present application, the electronic device executes the second migration instruction to realize the migration of multiple continuous data. Combined with the first migration instruction, the amount of data that can be migrated at one time is further increased, the number of instructions used in the migration operation is greatly reduced, and the instruction space is saved. In addition, the electronic device only reads the target data from the first register, the amount of data read is small, and the data reading efficiency is high.

[0288] Electronic devices can also use the above Fig.18 The steps shown in the figure implement the above step S211. For details, please refer to the above Fig.18 The relevant description of some parts will not be elaborated here.

[0289] In the present application embodiment, Fig.23 As shown, the electronic device can also implement the above step S212 through the following steps:

[0290] Step S231, shifting the target data to the interval between the second address and the fourth address;

[0291] Step S232, merging the shifted target data and the destination data to obtain the migrated data, where the destination data is the data stored in the second register;

[0292] Step S233, writing the migrated data into the second register.

[0293] In the embodiment of the present application, the electronic device can read all the data in the second register to obtain the target data. The electronic device can shift the target data read from the implicit register to between the second address and the fourth address to obtain the shifted target data.

[0294] After obtaining the target data and the shifted target data, the electronic device may use the shifted target data to replace the data between the second address and the fourth address in the target data, obtain the migrated data, and write the migrated data into the second register.

[0295] In an embodiment of the present application, in order to ensure that the target data is accurately written into the implicit register and to reduce interference from other data, the electronic device can generate a mask in which the bit value between the second address and the fourth address is 0 and the other bit values ​​are 1 according to the data length and the second address (that is, the second address and the fourth address). When merging the shifted target data and the destination data, the electronic device can perform a logical AND operation on the destination data and the mask, and perform a logical OR operation on the destination data after the AND operation and the shifted target data to obtain the migrated data. In this way, in the migrated data, the data between the second address and the fourth address is the same as the shifted target data, and the data at other positions is the same as the destination data. The order in which the electronic device generates the mask and shifts the target data is not limited here.

[0296] Still Figure 6 Taking the second line of instructions shown in the figure as an example, the second address carried by the DST_OFS field is 00010 (corresponding to bit2 position), and the data stored in the second register is as follows Fig.24 shown.

[0297] The electronic device reads all the data stored in the second register (i.e., the target data), and generates a mask with bit2 to bit4 being 0 and other bits being 1, performs a logical AND operation on the target data and the mask to obtain the target data after the AND operation; shifts the data "010" at the read bit0 to the bit2 position to the bit4 position to obtain the shifted target data; performs a logical OR operation on the target data after the AND operation and the shifted target data to obtain the migrated data, such as Fig.24 As shown, the target data is written into the second register. At this time, the values ​​at bit2 to bit4 of the second register are "010", and the values ​​at other bits remain unchanged.

[0298] Still Figure 6Taking the second line of instructions shown as an example, the second migration instruction can be in the form of: movbitsfrshad rd (corresponding to the d field), dst_ofs (corresponding to the DST_OFS field), size (corresponding to the sz field). The order of the fields is not limited here, as long as the electronic device can recognize the value of the corresponding field.

[0299] Below through Fig.25 The data migration method provided in the embodiment of the present application is described.

[0300] The embodiment of the present application provides a self-extended instruction set for data migration, including the above four instructions (movbittoshad instruction, movbitstoshad instruction, movbitfrshad instruction and movbitsfrshad instruction). The instruction function design of the self-extended instruction set can be divided into two parts: the opcode from the 0th to the 6th bit and the custom content from the 7th to the 31st bit. The instructions in the self-extended instruction set use the same opcode and do not conflict with the existing instruction set; similar instruction formats are used, such as Figure 4~Figure 7 The instructions shown; have similar functions to realize discrete or continuous data migration; the units for processing instructions are the same, that is, all instructions are processed by the acquisition unit, decoding unit, execution unit and write-back unit included in the electronic device to realize data migration; the execution cycle is the same (single-cycle instruction), that is, the execution unit executes each instruction in a single cycle.

[0301] like Fig.25 A schematic diagram of an instruction implementation shown in FIG. 1 shows that the acquisition unit acquires instruction 1 (such as the first migration instruction) and sends the acquired instruction 1 to the decoding unit. The decoding unit decodes instruction 1, extracts the values ​​of all fields from instruction 1, and acquires source data (such as the first register) from the source register in the register file. Fig.25 The execution unit executes instruction 1 and obtains the data to be written into the implicit register based on the values ​​of all fields and the source data. For details, see the above Figure 8~Figure 15 The execution unit executes instruction 1 in a single cycle and sends the data to the write-back unit. The write-back unit writes the data to the corresponding implicit register (such as Fig.25 Process b).

[0302] After the acquisition unit sends instruction 1 to the decoding unit, the acquisition unit can acquire instruction 2 (such as the second migration instruction). After decoding instruction 1, the decoding unit continues to decode instruction 2, extracts the values ​​of all fields from instruction 2, and obtains implicit data from implicit registers (such as Fig.25In process c), the destination data is obtained from the destination register (i.e., the second register) in the register file and sent to the execution unit. After executing instruction 1, the execution unit continues to execute instruction 2, and obtains the data to be written to the destination register based on the values ​​of all fields, implicit data, and destination data. For details, see the above Figure 16~Figure 24 The execution unit executes instruction 2 in a single cycle and sends the data to the write-back unit. The write-back unit writes the data to the corresponding destination register (such as Fig.25 Process d).

[0303] In the technical solution provided in the embodiment of the present application, the above four instructions are used in combination to realize continuous or discrete data migration more quickly and flexibly. Specifically, the functional requirements of the following multiple scenarios can be realized.

[0304] (1) One-to-one migration.

[0305] 1) Use the movbitstoshad and movbitsfrshad instructions to move continuous multi-bit (or single-bit) data in the source register to any continuous position in the destination register.

[0306] 2) Use the movbitstoshad and movbitfrshad instructions to migrate continuous multi-bit (or single-bit) data in the source register to any discrete position in the destination register.

[0307] 3) Use the movbittoshad and movbitsfrshad instructions to migrate discrete multi-bit (or single-bit) data in the source register to any continuous position in the destination register.

[0308] 4) Use the movbittoshad and movbitfrshad instructions to move discrete multi-bit (or single-bit) data in the source register to any discrete position in the destination register.

[0309] For example, if you need to move the data at bit0, bit2, bit4 and bit6 in the source register x5 to bit0, bit1, bit2 and bit3 in the destination register x31, you can use the movbittoshad instruction and the movbitfrshad instruction to achieve the migration. Execute the following instructions 1 to 4:

[0310] Instruction 1: movbittoshad x5(rs1), 0(src_pos1), 2(src_pos2), 00(mod1), 00(mod2), 1(size=2bit), which reads the data at bit0 and bit2 in register x5, keeps the data unchanged, and writes them to bit0 and bit1 in the implicit register respectively;

[0311] Instruction 2: movbitfrshad x31(rd), 0(dst_pos1), 1(dst_pos2), 00(mod1), 00(mod2), 1(size=2bit), which reads the data at bit0 and bit1 in the implicit register, keeps the data unchanged, and writes them to bit0 and bit1 in register x31 respectively;

[0312] Instruction 3: movbittoshad x5, 4, 6, 00, 00, 1, which reads the data at bit4 and bit6 of register x5, keeps the data unchanged, and writes them to bit0 and bit1 of the implicit register respectively;

[0313] Instruction 4: movbitfrshad x31, 2, 3, 00, 00, 1, which reads the data at bit0 and bit1 in the implicit register, keeps the data unchanged, and writes it to bit2 and bit3 in register x31 respectively.

[0314] By executing the above four instructions, the electronic device realizes the bit-level migration of four data. On average, one instruction migrates one bit of data. Compared with using the B extended instruction to migrate data, a large number of instructions are saved.

[0315] In addition, when using the movbittoshad instruction and the movbitfrshad instruction to migrate data, you can select only one of the instructions to define the mod field without repeating the definition.

[0316] (2) One-to-many migration, that is, migrating data in a source register to multiple destination registers.

[0317] 1) Use the movbitstoshad and movbitsfrshad instructions to move continuous multi-bit (or single-bit) data in the source register to continuous locations in multiple destination registers. For example, if you need to move the data at bit0 to bit2 in the source register x5 to bit3 to bit5 in the destination register x30 and bit6 to bit8 in the destination register x31, you can execute the following instructions:

[0318] Instruction 1: movbitstoshad x5, 0, 10 (size=3bit), which writes the data at bit0~bit2 in register x5 to bit0~bit2 in the implicit register;

[0319] Instruction 2: movbitsfrshad x30, 3, 10, which writes the data at bit0~bit2 in the implicit register to bit3~bit5 in register x30;

[0320] Instruction 3: movbitsfrshad x31, 6, 10, which writes the data at bit0~bit2 in the implicit register to bit6~bit8 in register x31.

[0321] 2) Use the movbitstoshad and movbitfrshad instructions to migrate continuous multi-bit (or single-bit) data in the source register to discrete locations in multiple destination registers.

[0322] 3) Use the movbittoshad and movbitsfrshad instructions to migrate discrete multi-bit (or single-bit) data in the source register to consecutive locations in multiple destination registers.

[0323] 4) Use the movbittoshad and movbitfrshad instructions to move discrete multi-bit (or single-bit) data in the source register to discrete locations in multiple destination registers. For example, if you need to move the data at bit0 and bit2 in the source register x5 to bit4 and bit6 in the destination register x30, and bit8 and bit10 in the destination register x31, you can execute the following instructions:

[0324] Instruction 1: movbittoshad x5, 0, 2, 1, which writes the data at bit0 and bit2 in register x5 to bit0 and bit1 in the implicit register respectively;

[0325] Instruction 2: movbitfrshad x30, 4, 6, 00, 00, 1, which reads the data at bit0 and bit1 in the implicit register, keeps the data unchanged, and writes it to bit4 and bit6 in register x30 respectively;

[0326] Instruction 3: movbitfrshad x31, 8, 10, 00, 00, 1, which reads the data at bit0 and bit1 in the implicit register, keeps the data unchanged, and writes it to bit8 and bit10 in register x31 respectively.

[0327] In this scenario, the mod field can be defined in the movbitfrshad instruction to perform different operations on the data written to different destination registers. In this case, the mod field can be omitted in the movbittoshad instruction.

[0328] (3) Data replication, that is, migrating data in a source register to multiple locations in a destination register. In this scenario, the number of instructions used = the number of replications + 1.

[0329] 1) Use the movbitstoshad and movbitsfrshad instructions to move continuous multi-bit (or single-bit) data in the source register to multiple continuous locations in a destination register. For example, if you need to copy the data at bit0 to bit7 in the source register x5 to bit0 to bit7, bit8 to bit15, bit16 to bit23, and bit24 to bit31 in the destination register x31, you can execute the following instructions:

[0330] Instruction 1: movbitstoshad x5, 0, 111 (size=8bit), which writes the data at bit0~bit7 in register x5 to bit0~bit7 in the implicit register;

[0331] Instruction 2: movbitsfrshad x31, 0, 111, which writes the data at bit0 to bit7 in the implicit register to bit0 to bit7 in register x31;

[0332] Instruction 3: movbitsfrshad x31, 8, 111, which writes the data at bit0~bit7 in the implicit register to bit8~bit15 in register x31;

[0333] Instruction 4: movbitsfrshad x31, 16, 111, which writes the data at bit0 to bit7 in the implicit register to bit16 to bit23 in register x31;

[0334] Instruction 5: movbitsfrshad x31, 24, 111, which writes the data at bit0~bit7 in the implicit register to bit24~bit31 in register x31.

[0335] 2) Use the movbitstoshad and movbitfrshad instructions to move continuous multi-bit (or single-bit) data in the source register to multiple discrete locations in a destination register. For example, if you need to copy the data at bit2~bit3 in the source register x5 to bit0 and bit2, bit4 and bit6, and bit8 and bit10 in the destination register x31, you can execute the following instructions:

[0336] Instruction 1: movbitstoshad x5, 2, 1, which writes the data at bit 2 and bit 3 in register x5 to bit 0 and bit 1 in the implicit register;

[0337] Instruction 2: movbitfrshad x31, 0, 2, 00, 00, 1, which writes the data at bit0 and bit1 in the implicit register to bit0 and bit2 in register x31;

[0338] Instruction 3: movbitfrshad x31, 4, 6, 00, 00, 1, which writes the data at bit0 and bit1 in the implicit register to bit4 and bit6 in register x31;

[0339] Instruction 4: movbitfrshad x31, 8, 10, 00, 00, 1, writes the data at bit0 and bit1 in the implicit register to bit8 and bit10 in register x31.

[0340] 3) Use the movbittoshad and movbitsfrshad instructions to move discrete multi-bit (or single-bit) data in the source register to multiple consecutive locations in a destination register. For example, if you need to copy the data at bit0 and bit2 in the source register x5 to bit0 and bit1, bit8 and bit9, bit16 and bit17, and bit24 and bit25 in the destination register x31, you can execute the following instructions:

[0341] Instruction 1: movbittoshad x5, 0, 2, 00, 00, 1, which writes the data at bit0 and bit2 in register x5 to bit0 and bit1 in the implicit register respectively;

[0342] Instruction 2: movbitsfrshad x31, 0, 1, which writes the data at bit0 and bit1 in the implicit register to bit0 and bit1 in register x31 respectively;

[0343] Instruction 3: movbitsfrshad x31, 8, 1, which writes the data at bit0 and bit1 in the implicit register to bit8 and bit9 in register x31 respectively;

[0344] Instruction 4: movbitsfrshad x31, 16, 1, which writes the data at bit0 and bit1 in the implicit register to bit16 and bit17 in register x31 respectively;

[0345] Instruction 5: movbitsfrshad x31, 24, 1, which writes the data at bit0 and bit1 in the implicit register to bit24 and bit25 in register x31 respectively.

[0346] 4) Use the movbittoshad and movbitfrshad instructions to move discrete multi-bit (or single-bit) data in the source register to multiple discrete locations in a destination register. For example, if you need to copy the data at bit0 in the source register x5 to bit0, bit8, bit16, and bit24 in the destination register x31, you can execute the following instructions:

[0347] Instruction 1: movbittoshad x5, 0, 00, 0 (size=1), which writes the data at bit 0 in register x5 to bit 0 in the implicit register;

[0348] Instruction 2: movbitfrshad x31, 0, 00, 0, which writes the data at bit 0 in the implicit register to bit 0 in register x31;

[0349] Instruction 3: movbitfrshad x31, 8, 00, 0, which writes the data at bit 0 in the implicit register to bit 8 in register x31;

[0350] Instruction 4: movbitfrshad x31, 16, 00, 0, which writes the data at bit 0 in the implicit register to bit 16 in register x31;

[0351] Instruction 5: movbitfrshad x31, 24, 00, 0, which writes the data at bit 0 in the implicit register to bit 24 in register x31.

[0352] (4) Data integration, that is, migrating data from multiple source registers to one destination register. In this scenario, the number of instructions used = 2 × the number of source registers.

[0353] 1) Use the movbittoshad instruction and the movbitfrshad instruction (or movbitsfrshad instruction) to migrate the discrete multi-bit (or single-bit) data in multiple source registers to discrete (or continuous) locations in a destination register. For example, if you need to migrate the data at bit0 in source register x5, the data at bit0 in source register x6, and the data at bit0 in source register x7 to bit0~bit2 in destination register x31, you can execute the following instruction:

[0354] Instruction 1: movbittoshad x5, 0, 00, 0, which writes the data at bit 0 in register x5 to bit 0 in the implicit register;

[0355] Instruction 2: movbitfrshad x31, 0, 00, 0, which writes the data at bit 0 in the implicit register to bit 0 in register x31;

[0356] Instruction 3: movbittoshad x6, 0, 00, 0, which writes the data at bit 0 in register x6 to bit 0 in the implicit register;

[0357] Instruction 4: movbitfrshad x31, 1, 00, 0, which writes the data at bit 0 in the implicit register to bit 1 in register x31;

[0358] Instruction 5: movbittoshad x7, 0, 00, 0, which writes the data at bit 0 in register x7 to bit 0 in the implicit register;

[0359] Instruction 6: movbitfrshad x31, 2, 00, 0, which writes the data at bit 0 in the implicit register to bit 2 in register x31.

[0360] In this scenario, the mod field can be defined in the movbittoshad instruction to perform different operations on the data read from different source registers. In this case, the mod field can be omitted in the movbitfrshad instruction.

[0361] 2) Use the movbitstoshad instruction and the movbitfrshad instruction (or movbitsfrshad instruction) to migrate continuous multi-bit (or single-bit) data in multiple source registers to discrete (or continuous) locations in a destination register. For example, if you need to migrate the data at bit16 to bit23 in source register x5 and the data at bit24 to bit31 in source register x6 to bit0 to bit15 in destination register x31, you can execute the following instructions:

[0362] Instruction 1: movbitstoshad x5, 16, 111, which writes the data at bit16 to bit23 in register x5 to bit0 to bit7 in the implicit register;

[0363] Instruction 2: movbitsfrshad x31, 0, 111, which writes the data at bit0 to bit7 in the implicit register to bit0 to bit7 in register x31;

[0364] Instruction 3: movbitstoshad x6, 24, 111, which writes the data at bit24 to bit31 in register x6 to bit0 to bit7 in the implicit register;

[0365] Instruction 4: movbitsfrshad x31, 8, 111, which writes the data at bit0~bit7 in the implicit register to bit8~bit15 in register x31.

[0366] The self-expandable instruction set provided in the embodiments of the present application can be used to realize functional requirements in more scenarios and achieve more flexible, complex and efficient bit operations, which will not be elaborated here.

[0367] Corresponding to the above data migration method, the present application embodiment also provides a data migration device, such as Fig.26 As shown, the above-mentioned data migration device includes:

[0368] The acquisition module 261 is used to acquire a first migration instruction and a second migration instruction, the first migration instruction includes a first identifier and a first address, and the second migration instruction includes a second identifier and a second address, the first identifier corresponds to a first register, the second identifier corresponds to a second register, the first address is a storage address of target data to be migrated in the first register; the second address is a write address of the target data in the second register;

[0369] A first writing module 262, configured to write target data at a first address in a first register into an implicit register according to a first migration instruction;

[0370] The second writing module 263 is used to write the target data in the implicit register into the second address in the second register according to the second migration instruction.

[0371] In the technical solution provided in the embodiment of the present application, a bit-level migration instruction is constructed, and a first migration instruction for reading target data and a second migration instruction for writing target data are used to migrate the target data from the source register to the destination register, so as to achieve the migration of one data using two instructions, thereby reducing the number of instructions used for the migration operands, simplifying the bit-level migration operation, and reducing the instruction resources occupied by the migration operation. In addition, an implicit register is used during the execution of the instruction, which further saves the occupied instruction space and facilitates the implementation of more flexible and complex bit-level operations.

[0372] In some embodiments, the first migration instruction may further include a data length; the first address is the bit where the target data to be migrated is located in the first register; the first writing module 262 may be specifically used to:

[0373] The target data at the source position in the first register is read, the source position corresponds to the first address of the first data length included in the first migration instruction; and the target data is written into the implicit register.

[0374] In some embodiments, the first writing module 262 may be specifically used for:

[0375] The source data stored in the first register is read; the data at the source position in the source data is shifted to the least significant bit; and the valid bit data of the lowest data length in the shifted source data is intercepted as the target data.

[0376] In some embodiments, the first migration instruction may further include a first module identifier, a first writing module 262, which may be specifically used to:

[0377] Perform a processing operation corresponding to the first modulus identifier on the target data; and write the processed target data into the implicit register.

[0378] In some embodiments, the first migration instruction may further include a data length; the first address is a starting offset of the target data to be migrated in the first register; and the first writing module 262 may be specifically used to:

[0379] Read the target data between the first address and the third address in the first register, where the length from the first address to the third address is the data length; and write the target data into the implicit register.

[0380] In some embodiments, the first writing module 262 may be specifically used for:

[0381] The source data stored in the first register is read; the data between the first address and the third address in the source data is shifted to the least significant bit; and the valid bit data of the lowest data length in the shifted source data is intercepted as the target data.

[0382] In some embodiments, the second migration instruction may further include a data length; the second address is a bit in the second register where the target data is written; and the second writing module 263 may be specifically used to:

[0383] The target data is read from the implicit register; and the target data is written into a destination position in the second register, where the destination position corresponds to a second address of the first data length included in the second migration instruction.

[0384] In some embodiments, the second writing module 263 may be specifically used for:

[0385] Shift each bit of the target data to the corresponding destination position; merge the shifted target data and the destination data to obtain the migrated data, where the destination data is the data stored in the second register; and write the migrated data into the second register.

[0386] In some embodiments, the second migration instruction may further include a second module identifier; the second writing module 263 may be specifically used to:

[0387] Perform a processing operation corresponding to the second modulus identifier on the target data; and write the processed target data into a destination position in the second register.

[0388] In some embodiments, the second migration instruction may further include a data length; the second address is a starting offset for writing the target data in the second register; and the second writing module 263 may be specifically used for:

[0389] Read the target data from the implicit register; write the target data into the interval from the second address to the fourth address in the second register, where the length from the second address to the fourth address is the data length.

[0390] In some embodiments, the second writing module 263 may be specifically used for:

[0391] Shift the target data to the interval between the second address and the fourth address; merge the shifted target data and the destination data to obtain migrated data, where the destination data is the data stored in the second register; and write the migrated data into the second register.

[0392] In some embodiments, the second writing module 263 may be specifically used for:

[0393] Read the implicit data stored in the implicit register; extract the valid bit data of the lowest data length from the implicit data to obtain the target data.

[0394] In some embodiments, the first migration instruction and the second migration instruction may further include an operation code and an instruction function code, the operation code indicating the migration instruction, and the instruction function code indicating whether the migration instruction is the first migration instruction or the second migration instruction;

[0395] The operation code may be located at a first predetermined position in the first migration instruction and the second migration instruction;

[0396] The instruction function code may be located at a second preset position in the first migration instruction and the second migration instruction;

[0397] The first identifier may be located at a third preset position in the first migration instruction;

[0398] The second identifier may be located at a fourth preset position in the second migration instruction;

[0399] The first migration instruction and the second migration instruction may further include reserved bits, and the reserved bits may be used to carry other function codes.

[0400] The present application also provides an electronic device, such as Fig. 27 As shown, it includes a processor 271, a communication interface 272, a memory 273 and a communication bus 274, wherein the processor 271, the communication interface 272 and the memory 273 communicate with each other through the communication bus 274;

[0401] Memory 273, for storing computer programs;

[0402] The processor 271 is used to implement the steps of any of the above-mentioned data migration methods when executing the program stored in the memory 273.

[0403] The communication bus mentioned in the above device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0404] The communication interface is used for communication between the above electronic device and other devices.

[0405] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0406] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0407] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data migration methods are implemented.

[0408] In another embodiment provided by the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any of the data migration methods in the above embodiments.

[0409] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0410] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0411] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, computer-readable storage medium, and computer program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0412] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A data migration method, characterized in that: The method comprises: Obtain a first migration instruction and a second migration instruction, wherein the first migration instruction includes a first identifier and a first address, and the second migration instruction includes a second identifier and a second address, wherein the first identifier corresponds to a first register, and the second identifier corresponds to a second register, and the first address is a storage address of target data to be migrated in the first register; and the second address is a write address of the target data in the second register; writing the target data at the first address in the first register into an implicit register according to the first migration instruction; According to the second migration instruction, the target data in the implicit register is written into the second address in the second register.

2. The method according to claim 1, characterized in that The first migration instruction also includes a data length; the first address is the bit where the target data to be migrated in the first register is located; The step of writing the target data at the first address in the first register into an implicit register according to the first migration instruction comprises: Reading target data at a source position in the first register, the source position corresponding to the first address of the data length included in the first migration instruction; The target data is written into an implicit register.

3. The method according to claim 2, characterized in that The step of reading the target data at the source position in the first register comprises: Reading source data stored in the first register; Shifting the data at the source position in the source data to the least significant bit; The valid bit data of the lowest data length in the shifted source data is intercepted as the target data.

4. The method according to claim 2, characterized in that: The first migration instruction further includes a first module identifier, and the step of writing the target data into an implicit register includes: Performing a processing operation corresponding to the first module identifier on the target data; Write the processed target data to the implicit register.

5. The method according to claim 1, characterized in that The first migration instruction also includes a data length; the first address is a starting offset of the target data to be migrated in the first register; The step of writing the target data at the first address in the first register into an implicit register according to the first migration instruction comprises: Read target data between the first address and the third address in the first register, where the length from the first address to the third address is the data length; The target data is written into an implicit register.

6. The method according to claim 5, characterized in that The step of reading target data between the first address and the third address in the first register includes: Reading source data stored in the first register; Shifting the data between the first address and the third address in the source data to the least significant bit; The valid bit data of the lowest data length in the shifted source data is intercepted as the target data.

7. The method according to claim 1, characterized in that The second migration instruction also includes a data length; the second address is a bit in the second register where the target data is written; The step of writing the target data in the implicit register to the second address in the second register according to the second migration instruction comprises: Reading the target data from the implicit register; The target data is written into a destination position in the second register, where the destination position corresponds to the data length second address included in the second migration instruction.

8. The method according to claim 7, characterized in that The step of writing the target data into the destination position in the second register comprises: Shifting each bit of the target data to a corresponding destination position; Merging the shifted target data and the destination data to obtain migrated data, wherein the destination data is the data stored in the second register; The migrated data is written into the second register.

9. The method according to claim 7, characterized in that: The second migration instruction further includes a second module identifier; the step of writing the target data to the destination position in the second register includes: Performing a processing operation corresponding to the second module identifier on the target data; The processed target data is written into the destination position in the second register.

10. The method according to claim 1, characterized in that The second migration instruction also includes a data length; the second address is a starting offset for writing the target data into the second register; The step of writing the target data in the implicit register to the second address in the second register according to the second migration instruction comprises: Reading the target data from the implicit register; The target data is written into the interval from the second address to the fourth address in the second register, and the length from the second address to the fourth address is the data length.

11. The method according to claim 10, characterized in that The step of writing the target data into the interval from the second address to the fourth address in the second register comprises: Shifting the target data to the interval between the second address and the fourth address; Merging the shifted target data and the destination data to obtain migrated data, wherein the destination data is the data stored in the second register; The migrated data is written into the second register.

12. The method according to any one of claims 7 or 10, characterized in that: The step of reading the target data from the implicit register comprises: Reading implicit data stored in the implicit register; The target data is obtained by extracting the least significant bit data of the data length from the implicit data.

13. The method according to any one of claims 1 to 11, characterized in that: The first migration instruction and the second migration instruction further include an operation code and an instruction function code, the operation code indicates the migration instruction, and the instruction function code indicates that the migration instruction is the first migration instruction or the second migration instruction; The operation code is located at a first preset position in the first migration instruction and the second migration instruction; The instruction function code is located at a second preset position in the first migration instruction and the second migration instruction; The first identifier is located at a third preset position in the first migration instruction; The second identifier is located at a fourth preset position in the second migration instruction; The first migration instruction and the second migration instruction further include reserved bits, and the reserved bits are used to carry other function codes.

14. A data migration device, characterized in that: The device comprises: an acquisition module, configured to acquire a first migration instruction and a second migration instruction, wherein the first migration instruction includes a first identifier and a first address, and the second migration instruction includes a second identifier and a second address, wherein the first identifier corresponds to a first register, and the second identifier corresponds to a second register, and the first address is a storage address of target data to be migrated in the first register; and the second address is a write address of the target data in the second register; A first writing module, configured to write target data at the first address in the first register into an implicit register according to the first migration instruction; The second writing module is used to write the target data in the implicit register into the second address in the second register according to the second migration instruction.

15. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-13 when executing a program stored in a memory.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 13 is implemented.

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