Storage method, system, device and medium based on memory durability

Abstract

The present disclosure provides a storage method, system, device and medium based on memory durability. The storage method includes: obtaining the unit margin of the target data address in the first storage area; in response to the unit margin being lower than the preset margin threshold, writing the unit data in the target data address to the backup data address in the second storage area; writing the target data address or the backup data address to the corresponding mapping address in the third storage area; storing the mapping relationship of the target data address or the backup data address in the third storage area in the register; in response to the instruction hitting the target data address, reading the mapping relationship in the register and replacing the target data address with the backup data address. By monitoring the degree of wear of the storage unit, when the wear of the storage unit reaches a critical level, the backup process is automatically started, and the number of erasable times of the user's high-frequency write area is doubled without the user's perception.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor integrated circuits, and in particular to a storage method, system, device and medium based on memory durability. Background Art

[0002] As modern electronic devices continue to increase their requirements for data storage, the durability of EEPROM and NOR flash memory has become a key factor. Especially in the fields of IoT, smart metering, smart home and automotive electronics, the demand for the number of erasable and rewritable times has increased significantly. Users expect to be able to update the stored data frequently without sacrificing the reliability and service life of the memory.

[0003] The erasable number of times of traditional EEPROM is usually between 10,000 and 1,000,000 times, while the erasable number of times of NOR flash memory is between 10,000 and 100,000 times. However, with the popularity of data-intensive applications, the durability of traditional memory is no longer sufficient. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defect of insufficient durability of the memory in the prior art and to provide a storage method, system, device, medium and program product based on memory durability.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] In a first aspect, a storage method based on memory durability is provided, wherein the memory includes a first storage area, a second storage area, a third storage area and a register; the first storage area, the second storage area and the third storage area are independent of each other, and the storage method includes:

[0007] Acquire a cell margin of a target data address in the first storage area;

[0008] In response to the cell margin being lower than a preset margin threshold, writing the cell data in the target data address to a backup data address in the second storage area;

[0009] Writing the target data address or the backup data address into a corresponding mapping address in the third storage area;

[0010] storing a mapping relationship between the target data address or the backup data address in the third storage area in a register;

[0011] In response to an instruction hitting the target data address, the mapping relationship in the register is read, and the target data address is replaced with the backup data address.

[0012] Preferably, the storage unit further comprises a sensitive amplifier with deep margin sensing, and the step of obtaining the cell margin of the target data address in the first storage area comprises:

[0013] Obtaining original data in the target data address;

[0014] The original data is read with a windowed bias using the sensitive amplifier with deep margin perception to obtain a cell margin of the target data address.

[0015] Preferably, the step of writing the unit data in the target data address into the backup data address of the second storage area comprises:

[0016] In response to the new data written in the target data address, determining the data amount of the new data;

[0017] In response to the data volume of the new data being greater than or equal to the capacity of the target data address, writing the new data written in the target data address into the backup data address of the second storage area;

[0018] In response to the data volume of the new data being smaller than the capacity of the target data address, all data in the target data address including the new data are written into the backup data address of the second storage area.

[0019] Preferably, after writing the unit data in the target data address to the backup data address of the second storage area, the method further includes:

[0020] Mark the backup data address;

[0021] The flag information of the backup data address is stored in a register.

[0022] Preferably, the step of obtaining the cell margin of the target data address in the first storage area includes:

[0023] In response to receiving a write instruction, a read instruction, a power-on self-test instruction, or a timed self-test instruction, a cell margin of a target data address in the first storage area is obtained.

[0024] Preferably, the storage method further comprises:

[0025] A cell margin of the target data address is checked.

[0026] In a second aspect, a storage system based on memory durability is provided, wherein the memory includes a first storage area, a second storage area, a third storage area and a register; the first storage area, the second storage area and the third storage area are independent of each other, and the storage system includes a cell margin acquisition unit, a data backup unit, a data mapping unit, a data storage unit and a data replacement unit;

[0027] The cell margin acquisition unit is used to acquire the cell margin of the target data address in the first storage area;

[0028] The data backup unit is configured to write the unit data in the target data address to the backup data address in the second storage area in response to the unit margin being lower than a preset margin threshold;

[0029] The data mapping unit is used to write the target data address or the backup data address into a corresponding mapping address in the third storage area;

[0030] The data register unit is used to store the mapping relationship between the target data address or the backup data address in the third storage area into a register;

[0031] The data replacement unit is used for reading the mapping relationship in the register in response to an instruction hitting the target data address, and replacing the target data address with the backup data address.

[0032] In a third aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, wherein when the processor executes the computer program, the storage method based on memory durability as described in the first aspect is implemented.

[0033] According to a fourth aspect, a computer storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the storage method based on memory durability as described in the first aspect is implemented.

[0034] According to a fifth aspect, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the storage method based on memory durability as described in the first aspect.

[0035] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0036] The positive and progressive effect of the present disclosure is that by monitoring the degree of wear of the storage unit, when the wear of the storage unit reaches a critical point, the backup process is automatically started, and the number of erasable times of the user's high-frequency writing area is multiplied without the user's perception. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A flowchart of a storage method based on memory durability provided by an exemplary embodiment of the present disclosure;

[0038] Figure 2 A flowchart of step S101 in a storage method based on memory durability provided by an exemplary embodiment of the present disclosure;

[0039] Figure 3 A flowchart of step S201 in a storage method based on memory durability provided by an exemplary embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of a module of a storage system based on memory durability provided by an exemplary embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram of the hardware structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0043] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0044] Endurance: Durability, reflecting the ability of non-volatile memory to withstand repeated erasure and writing;

[0045] Cyle: the write cycle inside the EEPROM;

[0046] Cyling: cumulative number of write cycles;

[0047] Sense Amplifier: Sensitive amplifier;

[0048] Wear-leveling: Wear leveling is a technique used to extend the life of flash memory.

[0049] ECC (Error-Correcting Code): Error correction coding.

[0050] Example 1

[0051] This embodiment provides a storage method based on memory durability, wherein the memory includes a first storage area, a second storage area, a third storage area and a register; the first storage area, the second storage area and the third storage area are independent of each other, such as Figure 1 As shown, the storage method includes:

[0052] S101, obtaining a cell margin of a target data address in the first storage area;

[0053] S102, in response to the cell margin being lower than a preset margin threshold, writing the cell data in the target data address to a backup data address in the second storage area;

[0054] S103, writing the target data address or the backup data address into a corresponding mapping address in the third storage area;

[0055] S104, storing a mapping relationship between the target data address or the backup data address in the third storage area into a register;

[0056] S105 . In response to an instruction hitting the target data address, reading the mapping relationship in the register, and replacing the target data address with the backup data address.

[0057] In step S101, frequent write and erase operations will affect the data unit margin of the storage unit. As the number of erase and write times increases, the data unit margin will gradually decrease. In the memory, data is stored in the form of binary "0" and "1". The "1" unit margin curve and the "0" unit margin curve represent the changes in the signal level relative to various interference factors (such as noise, process deviation, aging, etc.) when the storage unit stores "1" and "0", respectively. The "1" unit margin curve and the "0" unit margin curve show the margin between the signal level of storing "1" or "0" and the ideal signal level under different working conditions or time processes. When any one of the "1" unit margin curve or the "0" unit margin curve intersects with the Sense Amp Level (sensitivity amplifier reference level), the data can no longer be reliably read. By obtaining the unit margin of the target data address, the reliability of the target data address can be accurately determined.

[0058] In step S102, if the cell margin is lower than a preset margin threshold, it indicates that the target data address is not reliable, the data stored in the target data address is not stable enough, and the data in the target data address needs to be backed up. In one embodiment, the first storage area is used as a main storage area, the second storage area is used as a redundant storage area, and the third storage area is used as a sub-storage area.

[0059] In step S103, the target data address can be written into the corresponding first mapping address in the third storage area, wherein the first mapping address and the backup data address have a one-to-one correspondence; or the backup data address can be written into the corresponding second mapping address in the third storage area, wherein the target data address and the second mapping address have a one-to-one correspondence.

[0060] In step S104, the memory includes a storage control unit, and the storage control unit includes a register. When the storage control unit is powered on or receives a new instruction, the mapping relationship between the target data address, the backup data address and the mapping address in step S103 is read from the third storage area, and the mapping relationship is stored in the register.

[0061] In step S105, the instruction hitting the target data address includes the storage control unit performing a global read of the data address in the first storage area during power-on, hitting the target data address during the instruction reading process, or the storage control unit receiving a new instruction hitting the target data address. When the instruction hits the target data address, the automatic backup process is implemented by replacing the target data address with the backup data address.

[0062] In this solution, by monitoring the degree of wear of the storage unit, when the wear of the storage unit reaches a critical point, the backup process is automatically started, and the number of erasable times of the user's high-frequency writing area is multiplied without the user's awareness.

[0063] As an implementable manner, the storage unit further includes a sensitive amplifier with deep margin sensing, such as Figure 2 As shown, step S101 includes:

[0064] S1011, obtaining the original data in the target data address;

[0065] S1012: Using the sensitive amplifier with depth margin perception, read the original data with window bias to obtain a cell margin of the target data address.

[0066] In this solution, the Sense Amplifier with deep margin sensing, compared to the traditional sense amplifier, can only simply determine whether the signal in the storage cell is above or below a certain threshold to distinguish between "0" and "1". The Sense Amplifier with deep margin sensing can accurately measure the signal margin, that is, not only know whether the signal is "0" or "1", but also know the difference between the signal level and the critical level. The original data of the target data address can be read with window deviation to achieve in-depth signal margin detection. The Sense Amplifier with deep margin sensing has the ability to bidirectionally or unidirectionally deflect the Sense Amp Level or the current and voltage curve of the storage cell under the control of the storage control unit. The deviation can be current deviation or voltage deviation. In one embodiment, the original address in the target data address is read by bidirectional deviation and current deviation. Potential problems can be detected before serious failures occur in the storage cell, and accurate evaluation of memory durability can be achieved.

[0067] As a feasible approach, Figure 3 As shown, the step of writing the unit data in the target data address to the backup data address of the second storage area in step S102 includes:

[0068] S1021, in response to the new data written into the target data address, determining the data amount of the new data;

[0069] S1022: In response to the data volume of the new data being greater than or equal to the capacity of the target data address, writing the new data written in the target data address into the backup data address of the second storage area;

[0070] S1023: In response to the data volume of the new data being smaller than the capacity of the target data address, all data in the target data address including the new data are written into the backup data address of the second storage area.

[0071] In this solution, when it is determined that the target data address is not reliable, when an instruction to write new data is received, all data in the target address is written to the backup data address for backup based on the capacity of the target data address occupied by the new instruction to meet the storage reliability of the new data.

[0072] As an implementable manner, after writing the unit data in the target data address to the backup data address of the second storage area, the method further includes:

[0073] Mark the backup data address;

[0074] The flag information of the backup data address is stored in a register.

[0075] In this solution, by marking the backup data address that has been occupied, the storage controller determines whether the backup data address in the second storage area is occupied by reading the flag in the register. On the one hand, the mapping relationship between the target data address and the backup data address is determined based on the flag information. On the other hand, after all the backup data addresses in the second storage area are used, no new data backup process is triggered.

[0076] As an implementable manner, the step of obtaining the cell margin of the target data address in the first storage area includes:

[0077] In response to receiving a write instruction, a read instruction, a power-on self-test instruction, or a timed self-test instruction, a cell margin of a target data address in the first storage area is obtained.

[0078] In this solution, by receiving the four command moments of write command, read command, power-on self-test command or timed self-test command, the unit margin detection of the target data address is triggered to achieve real-time monitoring of the durability of the storage unit, so as to find out in advance whether the storage unit has a signal margin reduction due to various factors (such as aging, electromagnetic interference, process deviation, etc.). It helps to take timely measures, such as data backup, error correction or adjustment of the working parameters of the storage system, so as to ensure reliable storage and reading of data.

[0079] Performing a cell margin test before writing new data can ensure that the storage unit is in good condition before the write operation. The write parameters can be adjusted dynamically according to the results of the cell margin test. Testing the cell margin before the read operation can determine in advance whether the data of the storage unit can be reliably read. The test before each read operation can timely discover the performance changes of the storage unit. The power-on self-test is an important part of the system startup process. At this time, performing a cell margin test on the target data address can conduct a comprehensive initial status assessment of the storage system. The test triggered by the timed self-test instruction can realize the periodic health monitoring of the storage system. This regular inspection can discover the performance change trend of the storage unit during long-term operation.

[0080] In one embodiment, for cost-sensitive storage systems, it is preferred to trigger detection when a read instruction or a timed self-check instruction is received. Detection at the time of a read instruction can ensure the accuracy of data reading and reduce the cost of data retransmission or recovery caused by read errors; detection at the time of a timed self-check instruction can effectively detect the aging and potential failures of storage units, reasonably arrange the replacement or maintenance of storage units, and reduce overall operating costs.

[0081] As an achievable manner, the storage method further includes:

[0082] A cell margin of the target data address is checked.

[0083] In this solution, the reliability of the read data of the Sense Amplifier with deep margin perception is verified. In one embodiment, the verification is performed by a check code, and the check code is stored in a memory. The check code can use ECC, CRC, parity check, etc., or a universal check code, and the reliability of the read data of the Sense Amplifier with deep margin perception is judged based on the verification result of the check code; or, the read cell margin is compared with the preset reference data, and the reliability of the read data of the Sense Amplifier with deep margin perception is judged based on the comparison result.

[0084] The storage method based on memory durability provided in this embodiment monitors the degree of wear of the storage unit. When the wear of the storage unit reaches a critical level, the backup process is automatically started. The number of erasable times of the user's high-frequency writing area is multiplied without the user's awareness.

[0085] Example 2

[0086] This embodiment provides a storage system 100 based on memory durability, wherein the memory includes a first storage area, a second storage area, a third storage area and a register; the first storage area, the second storage area and the third storage area are independent of each other, such as Figure 4 As shown, the storage system 100 includes a unit margin acquisition unit 101, a data backup unit 102, a data mapping unit 103, a data storage unit 104 and a data replacement unit 105;

[0087] The cell margin acquisition unit 101 is used to acquire the cell margin of the target data address in the first storage area;

[0088] The data backup unit 102 is configured to write the unit data in the target data address to the backup data address in the second storage area in response to the unit margin being lower than a preset margin threshold;

[0089] The data mapping unit 103 is used to write the target data address or the backup data address into a corresponding mapping address in the third storage area;

[0090] The data register unit 104 is used to store the mapping relationship between the target data address or the backup data address in the third storage area into a register;

[0091] The data replacement unit 105 is configured to read the mapping relationship in the register in response to an instruction hitting the target data address, and replace the target data address with the backup data address.

[0092] As an implementable manner, the memory further includes a sensitive amplifier with deep margin perception, and the unit margin acquisition unit 101 is further used to obtain the original data in the target data address;

[0093] The cell margin acquisition unit 101 is further used to read the original data with a windowed bias using the sensitive amplifier with deep margin perception to obtain the cell margin of the target data address.

[0094] As an implementable manner, the data backup unit 102 is further configured to determine the data volume of the new data in response to the new data written into the target data address;

[0095] The data backup unit 102 is further configured to write the new data written in the target data address into the backup data address of the second storage area in response to the data volume of the new data being greater than or equal to the capacity of the target data address;

[0096] The data backup unit 102 is further configured to write all data in the target data address including the new data into the backup data address of the second storage area in response to the data volume of the new data being smaller than the capacity of the target data address.

[0097] As an implementable manner, the data backup unit 102 is further used to mark the backup data address;

[0098] The data storage unit 104 is further used to store the flag information of the backup data address into a register.

[0099] As an implementable manner, the cell margin acquisition unit 101 is further configured to acquire the cell margin of the target data address in the first storage area in response to receiving a write instruction, a read instruction, a power-on self-test instruction or a timed self-test instruction.

[0100] As an implementable manner, the storage system further includes a margin checking unit:

[0101] The margin checking unit is used to check the unit margin of the target data address.

[0102] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0103] The storage system based on memory durability provided in this embodiment monitors the degree of wear of the storage unit. When the wear of the storage unit reaches a critical level, the backup process is automatically started. The number of erasable times of the user's high-frequency writing area is multiplied without the user's awareness.

[0104] Example 3

[0105] Figure 5 This is a structural diagram of an electronic device shown in an example embodiment of the present disclosure, wherein the electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and when the processor executes the computer program, the storage method based on memory durability of any of the above embodiments is implemented. Figure 5 The electronic device 90 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0106] like Figure 5 As shown, the electronic device 90 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 90 may include, but are not limited to: at least one processor 91, at least one memory 92, and a bus 93 connecting different system components (including the memory 92 and the processor 91).

[0107] The bus 93 includes a data bus, an address bus, and a control bus.

[0108] The memory 92 may include a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read only memory (ROM) 923 .

[0109] The memory 92 may also include a program tool 925 (or utility) having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0110] The processor 91 executes various functional applications and data processing by running computer programs stored in the memory 92, such as the storage method based on memory durability provided in any of the above embodiments.

[0111] The electronic device 90 may also communicate with one or more external devices 94 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 95. Furthermore, the electronic device 90 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 96. As shown, the network adapter 96 communicates with other modules of the electronic device 90 via a bus 93. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 90, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0112] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0113] Example 4

[0114] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the storage method based on memory durability provided by any of the above embodiments is implemented.

[0115] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0116] Example 5

[0117] An embodiment of the present disclosure further provides a computer program product, including a computer program, which implements any of the above-mentioned storage methods based on memory durability when executed by a processor.

[0118] Among them, the program code for executing the computer program product of the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.

[0119] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A storage method based on memory durability, characterized in that: The memory includes a first storage area, a second storage area, a third storage area and a register; The first storage area, the second storage area and the third storage area are independent of each other, and the storage method includes: Acquire a cell margin of a target data address in the first storage area; In response to the cell margin being lower than a preset margin threshold, writing the cell data in the target data address to a backup data address in the second storage area; Writing the target data address or the backup data address into a corresponding mapping address in the third storage area; storing a mapping relationship between the target data address or the backup data address in the third storage area in a register; In response to an instruction hitting the target data address, the mapping relationship in the register is read, and the target data address is replaced with the backup data address.

2. The storage method based on memory durability according to claim 1, characterized in that: The storage unit further includes a sensitive amplifier with deep margin sensing, and the step of obtaining the cell margin of the target data address in the first storage area includes: Obtaining original data in the target data address; The original data is read with a windowed bias using the sensitive amplifier with deep margin perception to obtain a cell margin of the target data address.

3. The storage method based on memory durability according to claim 1, characterized in that: The step of writing the unit data in the target data address into the backup data address of the second storage area comprises: In response to the new data written in the target data address, determining the data amount of the new data; In response to the data volume of the new data being greater than or equal to the capacity of the target data address, writing the new data written in the target data address into the backup data address of the second storage area; In response to the data volume of the new data being smaller than the capacity of the target data address, all data in the target data address including the new data are written into the backup data address of the second storage area.

4. The storage method based on memory durability according to claim 1, characterized in that: After writing the unit data in the target data address into the backup data address of the second storage area, the method further includes: Mark the backup data address; The flag information of the backup data address is stored in a register.

5. The storage method based on memory durability according to claim 1, characterized in that: The step of obtaining the cell margin of the target data address in the first storage area comprises: In response to receiving a write instruction, a read instruction, a power-on self-test instruction, or a timed self-test instruction, a cell margin of a target data address in the first storage area is obtained.

6. The storage method based on memory durability according to claim 2, characterized in that: The storage method further comprises: A cell margin of the target data address is checked.

7. A storage system based on memory durability, characterized in that: The memory includes a first storage area, a second storage area, a third storage area and a register; the first storage area, the second storage area and the third storage area are independent of each other, and the storage system includes a unit margin acquisition unit, a data backup unit, a data mapping unit, a data storage unit and a data replacement unit; The cell margin acquisition unit is used to acquire the cell margin of the target data address in the first storage area; The data backup unit is configured to write the unit data in the target data address to the backup data address in the second storage area in response to the unit margin being lower than a preset margin threshold; The data mapping unit is used to write the target data address or the backup data address into a corresponding mapping address in the third storage area; The data register unit is used to store the mapping relationship between the target data address or the backup data address in the third storage area into a register; The data replacement unit is used for reading the mapping relationship in the register in response to an instruction hitting the target data address, and replacing the target data address with the backup data address.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, characterized in that: When the processor executes the computer program, the storage method based on memory durability as claimed in any one of claims 1 to 6 is implemented.

9. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the storage method based on memory durability as claimed in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the storage method based on memory durability as claimed in any one of claims 1 to 6 is implemented.

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