A two-way dual-redundancy 1553B bus circuit

Abstract

The present invention proposes a two-way dual-redundancy 1553B bus circuit, which belongs to the field of 1553B bus. The circuit includes a SOC processor with two independent 1553B bus channels, each channel having BC, RT, and MT functions of the 1553B bus, and two 1553B bus transceiver modules; the two 1553B bus transceiver modules are respectively connected to the SOC processor to form a complementary and non-interfering two-way communication channel, and the operating voltage of the two 1553B bus transceiver modules is consistent with that of the SOC processor; any 1553B bus transceiver module includes two independent isolation transformers, one of which is connected to a receiver for converting a differential signal of the 1553B bus into a Manchester coded signal and transmitting it to the SOC processor, and the other isolation transformer is connected to a transmitter for converting a Manchester coded signal of the SOC processor into a differential signal and transmitting it to the 1553B bus. Compared with the prior art 1553B bus circuit, the number of components is greatly reduced, the volume of the circuit is reduced, and on the basis of the reduced volume, the stable operation of the equipment can be ensured.

Description

Technical Field

[0001] The present application relates to the field of 1553B bus, and in particular to a two-way dual-redundancy 1553B bus circuit. Background Art

[0002] The 1553B bus is a broadcast distributed processing computer network with the advantages of high reliability, high transmission rate and mature technology. It is very suitable for measurement and control networks in the fields of aviation, aerospace, etc.

[0003] The 1553B bus circuit in the prior art is as follows Figure 1 As shown, the BU61580 chip is used to implement the 1553B bus function. The circuit includes a DSP processor chip for data solution, an FPGA chip for completing the logic control of the BU61580 chip, a level converter for improving the driving ability of the FPGA chip, two 1553B bus control modules for receiving and sending 1553B data, a 5V level input clock, four isolation transformers and four impedance matching resistors. The circuit structure is complex, the number of components required is large, and it is difficult to adapt to the development requirements of miniaturization. Summary of the invention

[0004] The purpose of the present application is to provide a two-way dual-redundancy 1553B bus circuit, which can reduce the number of components required for the 1553B bus, so as to reduce the overall volume of the 1553B bus circuit.

[0005] This application is implemented as follows:

[0006] The present application provides a two-way dual-redundancy 1553B bus circuit, comprising:

[0007] A SOC processor with two independent 1553B bus channels, each channel having BC, RT, and MT functions of the 1553B bus, and two 1553B bus transceiver modules;

[0008] Two 1553B bus transceiver modules are respectively connected to the SOC processor to form a complementary and non-interfering two-way communication channel, and the operating voltage of the 1553B bus transceiver module is consistent with that of the SOC processor;

[0009] Any 1553B bus transceiver module includes two independent isolation transformers, one of which is connected to the receiver to convert the differential signal of the 1553B bus into a Manchester coded signal for transmission to the SOC processor, and the other isolation transformer is connected to the transmitter to convert the Manchester coded signal of the SOC processor into a differential signal for transmission to the 1553B bus.

[0010] Furthermore, the SOC processor includes a TMS320C6713 chip and two 1553B bus control modules connected to each other, and the two 1553B bus transceiver modules are correspondingly connected to the two 1553B bus control modules.

[0011] Furthermore, the operating voltages of the 1553B bus transceiver module and the SOC processor are both 3.3V, and the power supply terminal of the 1553B bus transceiver module is directly connected to the power supply terminal of the processor.

[0012] Furthermore, it also includes an impedance matching resistor, which is arranged between the 1553B bus and the 1553B bus transceiver module.

[0013] Furthermore, the 1553B bus includes a BUSA bus and a BUSB bus. The BUSA bus is connected to one of the isolation transformers of the first 1553B bus transceiver module via an impedance matching resistor, and the BUSB bus is connected to another isolation transformer of the first 1553B bus transceiver module via an impedance matching resistor; the BUSA bus is also connected to one of the isolation transformers of the second 1553B bus transceiver module via an impedance matching resistor, and the BUSB bus is also connected to another isolation transformer of the second 1553B bus transceiver module via an impedance matching resistor.

[0014] Furthermore, the isolation transformer in the first 1553B bus transceiver module is connected to the receiver via the BUSA_0_IN pin and the BUSB_0_IN pin, and the receiver is connected to the receiver via the RXA_0 pin, pin, RXB_0 pin and The pin is connected to the first 1553B bus control module, and the first 1553B bus control module is connected to the first 1553B bus control module through the TXA_0 pin, pin, TXB_0 pin and The pin is connected to the transmitter, and the transmitter is connected to the isolation transformer through the BUSA_0_OUT pin and the BUSB_0_OUT pin;

[0015] The isolation transformer in the second 1553B bus transceiver module is connected to the receiver through the BUSA_1_IN pin and the BUSB_1_IN pin, and the receiver is connected to the receiver through the RXA_1 pin, pin, RXB_1 pin and The pin is connected to the second 1553B bus control module, and the second 1553B bus control module is connected to the second 1553B bus control module through the TXA_1 pin, pin, TXB_1 pin and The pin is connected to the transmitter, and the transmitter is connected to the isolation transformer through the BUSA_1_OUT pin and the BUSB_1_OUT pin.

[0016] Beneficial Effects

[0017] Compared with the prior art, the present invention has at least the following advantages or beneficial effects:

[0018] 1. The operating voltage of the 1553B bus transceiver module is consistent with that of the SOC processor. The 1553B bus transceiver module can be directly connected to the power pin of the processor without the need for an additional level converter, which simplifies the structure of the 1553B bus circuit and reduces the number of components in the 1553B bus circuit.

[0019] 2. Two independent isolation transformers are integrated inside the 1553B bus transceiver module. The two independent isolation transformers cooperate with the receiver and transmitter respectively. When directly coupled, there is no need for an external conversion circuit between the 1553B bus differential signal and the complementary CMOS format Manchester coded signal, which further reduces the number of components in the 1553B bus circuit and reduces the overall size of the 1553B bus circuit.

[0020] 3. The SOC processor chip with two independent 1553B bus channels integrated inside and each channel having BC, RT and MT functions of the 1553B bus is used to complete the processing of the 2-way 1553B protocol controller, which can realize the initialization of the 2-way 1553B bus, the reception and transmission of data, and the interrupt service. When a channel fails, it can automatically switch to another channel, which can ensure the stable operation of the equipment on the basis of reducing the overall volume of the 1553B bus circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a structural diagram of the prior art 1553B bus circuit;

[0023] Figure 2 This is a schematic diagram of the structure of a two-way dual-redundancy 1553B bus circuit of the present application;

[0024] Figure 3 A schematic diagram of the receiving voltage of a 1553B bus transceiver module in a two-way dual-redundancy 1553B bus circuit of the present application;

[0025] Figure 4 This is a schematic diagram of the transmission voltage of a 1553B bus transceiver module in a two-way dual-redundancy 1553B bus circuit of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0028] Example

[0029] After long-term research and practice, the applicant found that the circuit structure of the 1553B bus circuit in the prior art is complex and difficult to adapt to the development requirements of miniaturization and high reliability of inertial system products. Figure 1 As shown, the circuit includes a DSP processor chip, an FPGA chip, two level converters, two 1553B bus control modules, a 5V level input clock, four isolation transformers and four impedance matching resistors, requiring a total of 15 components. The number of components required is large and the structure is quite complex.

[0030] In view of this, an embodiment of the present application provides a two-way dual-redundancy 1553B bus circuit, which can simplify the structure of the 1553B bus circuit to reduce the overall volume of the 1553B bus circuit.

[0031] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a two-way dual-redundancy 1553B bus circuit of the present application. The 1553B bus circuit includes:

[0032] A SOC processor with two independent 1553B bus channels, each channel having BC, RT, and MT functions of the 1553B bus, and two 1553B bus transceiver modules;

[0033] Specifically, BC stands for Bus Controller, which is the node responsible for initializing data transmission and managing communications on the bus. RT stands for Remote Terminal, which is a device that receives commands from BC and responds to these commands. MT stands for Bus Monitor, which is used to monitor data transmission on the bus. SOC processor refers to a System on Chip processor, which integrates all the necessary circuits and logic to implement the above functions. The SOC processor integrates two 1553B buses internally, supports the standard functions of the 1553B bus, supports dual-clock transmission, and can support a bus rate of 1M / 4Mbps, meeting the 1553B bus BC (bus controller), RT (remote terminal) and MT (bus monitor) functions, and is compatible with BU61580.

[0034] Two 1553B bus transceiver modules are respectively connected to the SOC processor to form a complementary and non-interfering two-way communication channel, and the operating voltage of the 1553B bus transceiver module is consistent with that of the SOC processor;

[0035] Specifically, two 1553B bus transceiver modules are connected to the SOC processor respectively to form two communication channels. The two communication channels are independent of each other when working, and the activity of one channel will not affect the activity of the other channel. This helps to ensure the stability and reliability of data communication. Since the operating voltage of the 1553B bus transceiver module and the SOC processor is consistent, they can be directly connected through the interface pins without the use of an additional level conversion chip. The 1553B bus transceiver module and the SOC processor are electrically compatible. This compatibility is important to ensure the stability of the system, and this direct connection simplifies the hardware design of the system, reduces the number of components used, and improves the reliability of the system.

[0036] Any 1553B bus transceiver module includes two independent isolation transformers, one of which is connected to the receiver to convert the differential signal of the 1553B bus into a Manchester coded signal for transmission to the SOC processor, and the other isolation transformer is connected to the transmitter to convert the Manchester coded signal of the SOC processor into a differential signal for transmission to the 1553B bus.

[0037] Specifically, the 1553B bus uses differential signaling for communication, which means that the signal is transmitted over a pair of wires with a higher voltage on one wire than the other to represent a specific logic state (such as 1 or 0). Figure 3 , Figure 3The schematic diagram of the receiving voltage of the 1553B bus transceiver module. The role of the isolation transformer connected to the receiver is to convert these differential signals into Manchester coded signals. Manchester coding is a binary coding scheme in which each bit period is divided into two equal half periods, and the logic state is represented by changing the polarity of the signal. The converted Manchester coded signal is then transmitted to the SOC processor for further processing. Manchester coded signals have the advantages of signal synchronization, DC component elimination, error detection capability, simple coding, support for multi-level signals, and strong anti-interference performance. Please refer to Figure 4 , Figure 4 The schematic diagram of the transmission voltage of the 1553B bus transceiver module is shown in Figure 1. The isolation transformer connected to the transmitter is used to convert the Manchester coded signal back to a differential signal for transmission on the 1553B bus. Differential signal transmission has the advantages of strong anti-interference ability and long transmission distance, and is suitable for industrial communications and aerospace. Through such a design, the stability and reliability of the signal during transmission are ensured.

[0038] In summary, the components used in a two-way dual-redundancy 1553B bus circuit of the present application are only one SOC processor, two 1553B bus transceiver modules and four impedance matching resistors, and only 7 separate components. The prior art 1553B bus circuit includes a DSP processor chip, an FPGA chip, two level converters, two 1553B bus control modules, a 5V level input clock, four isolation transformers and four impedance matching resistors, requiring a total of 15 separate components. The 1553B bus circuit of the present application reduces 8 separate components compared to the 1553B bus circuit of the prior art. It can be seen that the 1553B bus circuit of the present application greatly reduces the number of components compared to the prior art through a clever structural layout design, so that the overall volume of the 1553B bus circuit is reduced. Moreover, on the basis of the overall volume reduction of the 1553B bus circuit, the stable operation of the equipment can be ensured.

[0039] Preferably, the SOC processor includes a TMS320C6713 chip and two 1553B bus control modules connected to each other, and the two 1553B bus transceiver modules are correspondingly connected to the two 1553B bus control modules.

[0040] Specifically, TMS320C6713 is a high-performance digital signal processor (DSP) produced by Texas Instruments, which is used to process complex digital signal algorithms. It can meet the performance requirements of inertial system floating-point operations, processing frequency, etc. The 1553B bus control module is a hardware component used to manage and control 1553B bus communications. The SOC processor includes two independent 1553B bus control modules, which can support two independent 1553B bus communication channels at the same time. The two independent 1553B bus transceiver modules are respectively connected to the two 1553B bus control modules. This connection method enables each 1553B bus control module to communicate with the 1553B bus through the corresponding transceiver module.

[0041] Furthermore, the operating voltages of the 1553B bus transceiver module and the SOC processor are both 3.3V, and the power supply terminal of the 1553B bus transceiver module is directly connected to the power supply terminal of the processor.

[0042] Specifically, the 1553B bus transceiver module and the SOC processor have the same operating voltage and can be directly connected to provide electrical compatibility. This direct connection simplifies power management because no additional power conversion or distribution circuits are required to match the voltage requirements of different components. At the same time, it also ensures that the 1553B bus transceiver module and the SOC processor can receive the same and stable power supply voltage.

[0043] Furthermore, it also includes an impedance matching resistor, which is arranged between the 1553B bus and the 1553B bus transceiver module.

[0044] Specifically, an impedance matching resistor is a component used to match the impedance between a signal source and a signal load. It can ensure that the signal is transmitted on the transmission line with minimal reflection and distortion. The impedance matching resistor is set between the 1553B bus (i.e., the signal transmission line) and the 1553B bus transceiver module (i.e., the sending and receiving end of the signal). It ensures that the impedance of the signal is continuous and matched during the signal transmission from the bus to the transceiver module, thereby minimizing the reflection and distortion of the signal.

[0045] Furthermore, the 1553B bus includes a BUSA bus and a BUSB bus. The BUSA bus is connected to one of the isolation transformers of the first 1553B bus transceiver module via an impedance matching resistor, and the BUSB bus is connected to another isolation transformer of the first 1553B bus transceiver module via an impedance matching resistor; the BUSA bus is also connected to one of the isolation transformers of the second 1553B bus transceiver module via an impedance matching resistor, and the BUSB bus is also connected to another isolation transformer of the second 1553B bus transceiver module via an impedance matching resistor.

[0046] Specifically, the BUSA bus first passes through an impedance matching resistor, which ensures impedance matching of the signal during transmission and reduces signal reflection and distortion. Then, the signal enters the first 1553B bus transceiver module through an isolation transformer. The isolation transformer is used to achieve electrical isolation and protect the transceiver module from high voltage or current shocks on the bus. The same is true for the BUSA bus. The BUSA and BUSB buses are connected to the two 1553B bus transceiver modules through impedance matching resistors and isolation transformers, respectively, to achieve signal transmission and electrical isolation.

[0047] The specific connection method includes: the isolation transformer in the first 1553B bus transceiver module is connected to the receiver through the BUSA_0_IN pin and the BUSB_0_IN pin, and the receiver is connected to the receiver through the RXA_0 pin, pin, RXB_0 pin and The pin is connected to the first 1553B bus control module, and the first 1553B bus control module is connected to the first 1553B bus control module through the TXA_0 pin, pin, TXB_0 pin and The pin is connected to the transmitter, and the transmitter is connected to the isolation transformer through the BUSA_0_OUT pin and the BUSB_0_OUT pin;

[0048] The isolation transformer in the second 1553B bus transceiver module is connected to the receiver through the BUSA_1_IN pin and the BUSB_1_IN pin, and the receiver is connected to the receiver through the RXA_1 pin, pin, RXB_1 pin and The pin is connected to the second 1553B bus control module, and the second 1553B bus control module is connected to the second 1553B bus control module through the TXA_1 pin, pin, TXB_1 pin and The pin is connected to the transmitter, and the transmitter is connected to the isolation transformer through the BUSA_1_OUT pin and the BUSB_1_OUT pin. The first 1553B bus control module is connected to the isolation transformer through the TXA_0 pin, pin, TXB_0 pin and The pins are connected to the transmitter and these pins are used to send the differential signals to be transmitted to the 1553B bus.

[0049] Specifically, the isolation transformer in the first 1553B bus transceiver module receives signals from the 1553B bus through the BUSA_0_IN pin and the BUSB_0_IN pin, and transmits these signals to the receiver. These two pins correspond to the BUSA bus and the BUSB bus of the 1553B bus, respectively. The receiver receives the signals through the RXA_0 pin, pin, RXB_0 pin and The pin is connected to the first 1553B bus control module to transmit the received differential signals of the BUSA bus and the BUSB bus. The transmitter outputs the processed signal to the isolation transformer through the BUSA_0_OUT pin and the BUSB_0_OUT pin, and then the isolation transformer transmits it to the 1553B bus. The connection method of the second 1553B bus transceiver module is similar to the first module, except that the pin numbering is different, and different pin numbers are used to distinguish two independent channels.

[0050] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A two-way dual-redundancy 1553B bus circuit, characterized in that: include: A SOC processor with two independent 1553B bus channels, each channel having BC, RT, and MT functions of the 1553B bus, and two 1553B bus transceiver modules; The two 1553B bus transceiver modules are respectively connected to the SOC processor to form a complementary and non-interfering two-way communication channel, and the operating voltage of the two 1553B bus transceiver modules is consistent with that of the SOC processor; Any of the 1553B bus transceiver modules includes two independent isolation transformers, one of which is connected to the receiver to convert the differential signal of the 1553B bus into a Manchester coded signal for transmission to the SOC processor, and the other is connected to the transmitter to convert the Manchester coded signal of the SOC processor into a differential signal for transmission to the 1553B bus.

2. A two-way dual-redundancy 1553B bus circuit according to claim 1, characterized in that: The SOC processor includes a TMS320C6713 chip and two 1553B bus control modules. The two 1553B bus control modules are used for correspondingly connecting with two 1553B bus transceiver modules.

3. A two-way dual-redundancy 1553B bus circuit according to claim 2, characterized in that: The operating voltages of the 1553B bus transceiver module and the SOC processor are both 3.3V, and the power supply terminal of the 1553B bus transceiver module is directly connected to the power supply terminal of the processor.

4. A two-way dual-redundancy 1553B bus circuit according to claim 2, characterized in that: It also includes an impedance matching resistor, which is arranged between the 1553B bus and the 1553B bus transceiver module.

5. A two-way dual-redundancy 1553B bus circuit according to claim 4, characterized in that: The 1553B bus includes a BUSA bus and a BUSB bus. The BUSA bus is connected to one of the isolation transformers of the first 1553B bus transceiver module via an impedance matching resistor, and the BUSB bus is connected to another isolation transformer of the first 1553B bus transceiver module via an impedance matching resistor; the BUSA bus is also connected to one of the isolation transformers of the second 1553B bus transceiver module via an impedance matching resistor, and the BUSB bus is also connected to another isolation transformer of the second 1553B bus transceiver module via an impedance matching resistor.

6. A two-way dual-redundancy 1553B bus circuit according to claim 5, characterized in that: The isolation transformer in the first 1553B bus transceiver module is connected to the receiver through the BUSA_0_IN pin and the BUSB_0_IN pin, and the receiver is connected to the receiver through the RXA_0 pin, pin, RXB_0 pin and The pin is connected to the first 1553B bus control module, and the first 1553B bus control module is connected to the first 1553B bus control module through the TXA_0 pin, pin, TXB_0 pin and The pin is connected to the transmitter, and the transmitter is connected to the isolation transformer through the BUSA_0_OUT pin and the BUSB_0_OUT pin; The isolation transformer in the second 1553B bus transceiver module is connected to the receiver through the BUSA_1_IN pin and the BUSB_1_IN pin, and the receiver is connected to the receiver through the RXA_1 pin, pin, RXB_1 pin and The pin is connected to the second 1553B bus control module, and the second 1553B bus control module is connected to the second 1553B bus control module through the TXA_1 pin, pin, TXB_1 pin and The pin is connected to the transmitter, and the transmitter is connected to the isolation transformer through the BUSA_1_OUT pin and the BUSB_1_OUT pin.

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