A high-speed bus configuration circuit, configuration method and communication method
By adopting new circuit design and software control methods in high-speed bus communication, the slave selection signal line is removed, and the problems of traditional communication efficiency and difficult hardware design are solved, and more efficient communication and more flexible equipment expansion are achieved.
Patent Information
- Application Number
- CN202411929808.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-04
AI Technical Summary
In traditional high-speed bus communication, the communication efficiency between the host device and the slave device is low, especially when the number of slaves is not fixed, which leads to increased difficulty in hardware circuit design and limited number of slaves in the system.
By providing a high-speed bus configuration circuit, adopting a new circuit design idea, the slave selection signal lines are removed, and the signal line configuration between the devices is controlled using software to realize normal communication between the host device and the slave device. The circuit design includes a master device and N slave devices, sequentially connected via GPIO pins, and clamps the high-level signal of the slave device through a pull-up circuit.
This design simplifies circuit design, reduces the use of GPIO pins of the host device MCU, optimizes the PCB layout, shortens communication time by 50%, improves communication efficiency, and supports the expansion of any number of slave devices.
Smart Images
Figure CN119759824A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data communication, and in particular to a high-speed bus configuration circuit, a configuration method and a communication method. Background Art
[0002] The high-speed bus is a synchronous serial bus, which is a synchronous serial port for communication between the microprocessor unit and peripheral devices. The high-speed bus system can be directly connected to a variety of standard peripheral devices produced by various manufacturers. Generally, the normal communication of the high-speed bus requires 4 signal lines, including the slave selection signal line SET, the serial clock signal line SCLK, the host transmit data line TX, and the host receive data line RX.
[0003] In the traditional mode, there is a SET signal line between the host device and each slave device. The host device selects which slave device to communicate with through the SET signal. As the number of slave devices in the system increases, the number of SET signal lines also increases. As the number of slaves increases, the use of the host device MCU pins will increase, which increases the difficulty of hardware circuit design and PCB layout; therefore, when the number of slaves is not fixed, the number of SET signal lines connected to the host device cannot be determined. In actual applications, there are some scenarios where the number of slaves is not fixed, and the device processor MCU pins are limited, which leads to certain disadvantages in the traditional method and limits the number of slaves in the system.
[0004] The host device starts the clock signal to initiate communication, and the slave device passively receives and sends data according to the clock signal provided by the host device. In the traditional communication mechanism, the host needs to start the clock signal to send a frame of message first, and the slave device prepares to respond after receiving the message. Then the host starts the clock signal for the second time to send a frame of message. The slave device receives the clock signal and synchronously sends the response message to the host device. In a system with one master and multiple slaves, two communications are required when switching slaves. The host device needs to start two requests to communicate with a slave device. The slave device replies with response data at the second request. The communication time between the master and slave devices is long and the communication efficiency is low. Summary of the invention
[0005] In view of the deficiencies in the prior art, the present invention provides a high-speed bus configuration circuit, configuration method and communication method, which optimize the circuit design and ensure that when the host device starts the clock signal and sends the request data, the slave device returns the response data synchronously. Compared with the master-slave one-to-one communication mechanism in the traditional full-duplex communication mode, the communication time is shortened by 50%, thereby improving the communication efficiency.
[0006] The present invention is achieved through the following technical solutions: Provided is a high-speed bus configuration circuit, comprising a host device and N slave devices, wherein the host device and the N slave devices are all connected to a bus consisting of a clock signal line SCK, a host data transmission signal line TX and a slave data transmission signal line RX; the host device is configured with an output pin GPIOa to provide an enable signal for the slave device; each slave device is configured with two GPIO pins, one is an input pin GPIO1, which is a local enable receiving pin, and the other is an output pin GPIO2, which is an enable output pin, which provides an enable signal for the next slave device, and the host device and the N slave devices are sequentially connected through the GPIO pins; a 10Ω resistor is connected in series at the RX interface of each slave device to match the impedance, and a pull-up circuit formed by connecting a 1kΩ resistor to a 3.3V positive voltage clamps a high-level signal sent by the slave device to a high level.
[0007] Furthermore, the output pin GPIOa of the host device is connected to the input pin GPIO1 of the first slave device, and the output pin GPIO2 of the i-th slave device is connected to the input pin GPIO1 of the (i+1)-th slave device.
[0008] A configuration method for a high-speed bus configuration circuit comprises the following steps: P1, the host device outputs a negative level to the GPIOa pin to enable the first slave device, at this time i=1; P2, the GPIO1 input pin of the i-th slave device detects a level jump, and enables the high-speed bus transceiver function of the i-th slave device through the internal control of the i-th slave device, waiting to receive the configuration information sent by the host device; P3. The host device sends a configuration information message of the i-th slave device through the TX signal line. The configuration information message includes the address of the i-th slave device, where the address number of the configured i-th slave device is i; P4, the i-th slave device receives and parses the configuration information message in step P3, writes the address number assigned by the host device into the local memory, and writes the information reply message containing the local device type into the sending buffer, and waits for the host device to start data access next time and then sends the information reply message to the host device; P5. The host device again sends the configuration information message described in step P3 to the i-th slave device through the TX signal line, and synchronously receives the information reply message in step P4 sent by the i-th slave device through the RX signal line; P6. If the host device receives the information reply message described in step P5, it prepares to write the configuration completion confirmation message into the host sending buffer, and waits for the next clock start to execute step P7; if the host device does not receive the information reply message described in step P5, it returns to execute step P5, and records the number of times m of returning to execute step P5. When m>D, the host device assumes that all slave devices have been configured, and the configuration ends here, and D>1; P7, the host device sends a configuration completion confirmation message to the i-th slave device through the TX signal; P8, after the i-th slave device receives the configuration completion confirmation message described in step P7, after ensuring that the bus is idle, the i-th slave device internally controls to enable the high-speed bus transceiver function of the slave device i, and outputs a negative level to the GPIO2 pin; P9, the i+1th slave device detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i+1th slave device through the internal control of the i+1th slave device, and waits to receive the configuration information sent by the host device; P10. Increase i by 1 and execute steps P3-P9 in sequence.
[0009] Furthermore, during the configuration of the slave device by the host device, at most one slave device has its high-speed bus transceiver function enabled at any one time, so as to prevent other slave devices from sending data to the RX signal line and interfering with the host receiving data.
[0010] A high-speed bus communication method using a high-speed bus configuration method, wherein after the slave device configuration is completed, the normal access phase is entered, and the process of the host accessing the slave device includes the following steps: T1: The host device starts the timer at a timing interval of 50μs, and sends data to the outside through the TX signal line in the timer interrupt to access the slave device. The order of accessing the slave device is from small to large according to the configured address number; T2: The host device outputs a negative level to the GPIOa pin to notify the i-th slave device that the host is about to access the i-th slave device, at this time i=1; T3: The i-th slave device detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i-th slave device through the internal control of the i-th slave device, and waits to receive the request data message sent by the host device; T4: The host device enters the timer interrupt and sends a request data message to the i-th slave device through the TX signal line; T5: After the i-th slave device receives the request data message sent by the host through the TX bus, it parses the data and prepares to write the response data message into the cache, and waits for the clock signal to start in the next timer cycle of the host to be sent to the host device; at the same time, the i-th slave device outputs a negative level to the GPIO2 pin; T6: The i+1th slave device detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i+1th slave device through the internal control of the i+1th slave device, and waits to receive the request data message sent by the host device; T7: The host device enters the timer interrupt and sends a request data message to the i+1th slave device through the TX signal line; T8: The i-th slave device sends the response data described in step T5 to the host device through the RX signal line while the host device sends the request data message to the i+1-th slave device. After waiting for the sending to be completed, the internal control enables the high-speed bus transceiver function of the i-th slave device. T9: Increase i by 1. When i≤N, execute steps T5-T8 in sequence; when i>N, execute step T2.
[0011] Furthermore, during normal communication, two slave devices are enabled with the high-speed bus transceiver function, and the two slave devices simultaneously receive data messages sent by the host, but only one slave device synchronously sends a response message to the host device.
[0012] Beneficial effects of the present invention: 1. The present invention abandons the traditional hardware circuit design idea and provides a new circuit design idea, removes the slave selection signal line used in the communication process, simplifies the circuit design, and realizes the configuration and communication of the high-speed bus through the control of the configuration signal line between each device by software. In the design process, the SET signal interface is completely abandoned, and the normal communication between the host device and the slave device is realized through another configuration signal line and the software mechanism of the slave device. In this way, in a bus system with one master and multiple slaves, the use of the GPIO pins of the host device MCU is greatly reduced, and the circuit design is simplified, the PCB layout is optimized, and the PCB size is reduced; at the same time, the expansion of any number of slave devices within the distance range allowed by the bus can be realized.
[0013] 2. In the present invention, through the optimized design of the high-speed bus communication hardware circuit, during the process of the host device configuring the slave device, the signal control of the configuration input and output pins between the host device and the slave device and between the slave devices is realized, thereby realizing data interaction between the host device and the only slave device during the configuration process.
[0014] 3. The master device communicates with the only slave device to ensure that there is no possibility of interference due to other slaves participating in the communication, thereby ensuring successful configuration. The master-slave one-to-one communication prevents signal interference caused by other slaves replying.
[0015] Fourth, the host device accesses the slave devices in sequence according to the pre-configured slave device addresses 1~N, in the order of distance from the host device from near to far, and after starting the communication, the i-th and i+1-th slave devices simultaneously enable the high-speed bus transceiver function, and control the normal communication process to have only one host device and two slave devices connected to each other simultaneously enable the high-speed bus data transceiver function, and ensure that when the host device starts the clock signal, the request data is sent synchronously with the slave device returning the response data. Compared with the master-slave one-to-one communication mechanism in the traditional full-duplex communication mode, the communication time is shortened by 50%, and the communication efficiency is improved. In the present invention, the host device sends request data to 1 slave device for the first time, and 1 slave does not reply at this time. Then, when the host sends data to 2 slaves, 1 slave replies. Similarly, when the host sends data to N slaves, N-1 slave replies. In this way, the time for the host to access N slaves can be shortened by 50%. The host sends request data once, and the slave replies with response data once, which shortens the communication time between the master and slave devices and improves the communication efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a simplified diagram of the hard-wire connection of the high-speed bus communication in the present invention.
[0017] Figure 2 The invention discloses a high-speed bus communication RX signal processing clamping circuit diagram of a slave device.
[0018] Figure 3 This is a flow chart of configuring the slave in the present invention.
[0019] Figure 4 It is a schematic diagram of communication between a host device and a slave device in the present invention.
[0020] In the figure: 1. Host device, 2. Slave device. DETAILED DESCRIPTION
[0021] In order to clearly illustrate the technical features of this solution, this solution is described below through a specific implementation method.
[0022] like Figure 1 As shown, a high-speed bus configuration circuit includes a host device 1 and N slave devices 2, wherein the host device 1 and the N slave devices 2 are all connected to a bus consisting of a clock signal line SCK, a host transmit data signal line TX and a slave transmit data signal line RX. The host device 1 is configured with one output pin GPIOa to provide an enable signal for the slave device 2; each slave device 2 is configured with two GPIO pins, one is an input pin GPIO1, which is the local enable reception pin, and the other is an output pin GPIO2, which is an enable output pin and provides an enable signal for the next slave device 2. The host device 1 and N slave devices 2 are sequentially connected through the GPIO pins; specifically: the output pin GPIOa of the host device 1 is connected to the input pin GPIO1 of the first slave device 2, and the output pin GPIO2 of the i-th slave device 2 is connected to the input pin GPIO1 of the i+1-th slave device 2.
[0023] A 10Ω resistor is connected in series at the RX interface of each slave device 2 to match the impedance, and a pull-up circuit formed by connecting a 1kΩ resistor to a 3.3V positive voltage clamps the high-level signal sent by the slave device to a high level. Figure 2 As shown, specifically: a 10Ω current limiting resistor is connected in series to the RX interface of the slave device 2, and a 1kΩ pull-up resistor is used to achieve a clamping effect. The current limiting resistor is connected in series to the pin externally to prevent damage to the device caused by excessive current, and it also has the function of matching impedance; then a pull-up circuit is formed by directly connecting the resistor to the 3.3V positive voltage to ensure the output high level value, so that the high level signal sent by the slave can be clamped to a high level, thereby ensuring that the data sent by the enabled slave can be correctly received by the host.
[0024] like Figure 3 As shown, a configuration method of a high-speed bus configuration circuit includes the following steps: P1, host device 1 outputs a negative level to GPIOa pin to enable the first slave device 2, at this time i=1; P2, the GPIO1 input pin of the i-th slave device 2 detects a level jump, and enables the high-speed bus transceiver function of the i-th slave device 2 through the internal control of the i-th slave device 2, waiting to receive the configuration information sent by the host device 1; P3, the host device 1 sends the configuration information message of the i-th slave device 2 through the TX signal line. The configuration information message includes a 1-byte slave address number, 7 bytes of 0x00 and a 2-byte CRC check code, where the address number of the configured i-th slave device 2 is i; P4. The i-th slave device 2 receives and parses the configuration information message in step S3, writes the address number assigned by the host device 1 into the local memory, and writes the information reply message containing the local device type into the sending buffer, and waits for the host device 1 to start data access next time and then send the information reply message to the host device 1, wherein the information reply message includes 1 byte of slave address number, 1 byte of slave type, 6 bytes of 0x00 and 2 bytes of CRC check code.
[0025] P5. The host device 1 again sends the configuration information message described in step S3 to the i-th slave device 2 through the TX signal line, and synchronously receives the information reply message in step S4 sent by the i-th slave device 2 through the RX signal line.
[0026] P6. If the host device 1 receives the information reply message described in step S5, it prepares to write the configuration completion confirmation message into the host sending buffer, and waits for the next clock start to execute step S7; if the host device 1 does not receive the information reply message described in step S5, it returns to execute step S5, and records the number of times m that it returns to execute step S5. When m>D, the host device 1 assumes that all slave devices 2 have been configured, and the configuration is ended, and D>1.
[0027] P7. The host device 1 sends a configuration completion confirmation message to the i-th slave device 2 through a TX signal, wherein the configuration completion confirmation message includes a 1-byte address number, a 1-byte type of the i-th slave, 6 bytes of 0x00 and a 2-byte CRC check code.
[0028] P8. After the i-th slave device 2 receives the configuration completion confirmation information message described in step S7, after ensuring that the bus is idle, the i-th slave device 2 internally controls the i-th slave device 2 to enable the high-speed bus transceiver function of the slave device i, and outputs a negative level to the GPIO2 pin.
[0029] P9, the i+1th slave device 2 detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i+1th slave device 2 through the internal control of the i+1th slave device 2, and waits to receive the configuration information sent by the host device 1.
[0030] P10. Increase i by 1 and execute steps P3-P9 in sequence.
[0031] During the configuration process of the host device 1 to the slave device 2, at most one slave device 2 has its high-speed bus transceiver function enabled at any time, so as to prevent other slave devices 2 from sending data to the RX signal line and interfering with the host receiving data.
[0032] A high-speed bus communication method using a configuration method of a high-speed bus configuration circuit, wherein the slave device 2 is configured and enters a normal access phase, and the process in which the host accesses the slave device 2 includes the following steps: T1: Host device 1 starts the timer at a timing interval of 50μs, and sends data outward through the TX signal line in the timer interrupt to access slave device 2. The order of accessing slave device 2 is cyclically accessed in ascending order according to the configured address number.
[0033] T2: The host device 1 outputs a negative level to the GPIOa pin to notify the i-th slave device 2 that the host is about to access the i-th slave device 2, and at this time i=1.
[0034] T3: The i-th slave device 2 detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i-th slave device 2 through the internal control of the i-th slave device 2, and waits to receive the request data message sent by the host device 1.
[0035] T4: Master device 1 enters the timer interrupt and sends a request data message to the i-th slave device 2 through the TX signal line; the request data message includes a 1-byte address number of slave device 2, a 1-byte slave device type, 6 bytes of data, and a 2-byte CRC check code.
[0036] T5: After the i-th slave device 2 receives the request data message sent by the host through the TX bus, it parses the data and prepares to write the response data message into the cache, waiting for the clock signal to start in the next timer cycle of the host to be sent to the host device 1; at the same time, the i-th slave device 2 outputs a negative level to the GPIO2 pin.
[0037] T6: The i+1th slave device 2 detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i+1th slave device 2 through the internal control of the i+1th slave device 2, and waits to receive the request data message sent by the host device 1.
[0038] T7: Master device 1 enters the timer interrupt and sends a request data message to the i+1th slave device 2 through the TX signal line.
[0039] T8: The i-th slave device 2 sends the response data described in step T5 to the host device 1 through the RX signal line while the host device 1 sends the request data message to the i+1-th slave device 2. After waiting for the sending to be completed, the internal control enables the high-speed bus transceiver function of the i-th slave device 2.
[0040] T9: Increase i by 1. When i≤N, execute steps T5-T8 in sequence; when i>N, execute step T2.
[0041] During normal communication, only one host device and two slave devices connected in front and behind enable the high-speed bus data receiving and sending function at the same time, ensuring that when the host device sends request data, the slave device returns response data synchronously. Compared with the traditional full-duplex master-slave device one-to-one communication mode, the communication time is shortened by 50%, which improves the communication efficiency.
[0042] Of course, the above description is not limited to the above examples. Technical features not described in the present invention can be achieved by or by using existing technologies, which will not be described here. The above embodiments and drawings are only used to illustrate the technical scheme of the present invention and are not limitations of the present invention. The present invention is described in detail with reference to the preferred implementation methods. Ordinary technicians in this field should understand that changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention do not depart from the purpose of the present invention, and should also fall within the scope of protection of the claims of the present invention.
Claims
1. A high-speed bus configuration circuit, characterized in that: The invention comprises a host device and N slave devices, wherein the host device and the N slave devices are connected to a bus composed of a clock signal line SCK, a host data transmission signal line TX and a slave data transmission signal line RX; the host device is configured with an output pin GPIOa to provide an enable signal for the slave device; each slave device is configured with two GPIO pins, one is an input pin GPIO1, which is a local enable receiving pin, and the other is an output pin GPIO2, which is an enable output pin, and provides an enable signal for the next slave device, and the host device and the N slave devices are sequentially connected through the GPIO pins; a 10Ω resistor is connected in series at the RX interface of each slave device to match the impedance, and a pull-up circuit formed by connecting a 1kΩ resistor to a 3.3V positive voltage clamps the high level and uncertain level signals sent by the slave device to a high level.
2. The high-speed bus configuration circuit according to claim 1, characterized in that: The output pin GPIOa of the host device is connected to the input pin GPIO1 of the first slave device, and the output pin GPIO2 of the i-th slave device is connected to the input pin GPIO1 of the i+1-th slave device.
3. A configuration method for a high-speed bus configuration circuit according to claim 1, characterized in that: The following steps are involved: P1, the host device outputs a negative level to the GPIOa pin to enable the first slave device, at this time i=1; P2, the GPIO1 input pin of the i-th slave device detects a level jump, and enables the high-speed bus transceiver function of the i-th slave device through the internal control of the i-th slave device, waiting to receive the configuration information sent by the host device; P3. The host device sends a configuration information message of the i-th slave device through the TX signal line. The configuration information message includes the address of the i-th slave device, where the address number of the configured i-th slave device is i; P4, the i-th slave device receives and parses the configuration information message in step P3, writes the address number assigned by the host device into the local memory, and writes the information reply message containing the local device type into the sending buffer, and waits for the host device to start data access next time and then sends the information reply message to the host device; P5. The host device again sends the configuration information message described in step P3 to the i-th slave device through the TX signal line, and synchronously receives the information reply message in step P4 sent by the i-th slave device through the RX signal line; P6. If the host device receives the information reply message described in step P5, it prepares to write the configuration completion confirmation message into the host sending buffer, and waits for the next clock start to execute step P7; if the host device does not receive the information reply message described in step P5, it returns to execute step P5, and records the number of times m of returning to execute step P5. When m>D, the host device assumes that all slave devices have been configured, and the configuration ends here, and D>1; P7, the host device sends a configuration completion confirmation message to the i-th slave device through the TX signal; P8, after the i-th slave device receives the configuration completion confirmation message described in step P7, after ensuring that the bus is idle, the i-th slave device internally controls to enable the high-speed bus transceiver function of the slave device i, and outputs a negative level to the GPIO2 pin; P9, the i+1th slave device detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i+1th slave device through the internal control of the i+1th slave device, and waits to receive the configuration information sent by the host device; P10. Increase i by 1 and execute steps P3-P9 in sequence.
4. The configuration method of the high-speed bus configuration circuit according to claim 3, characterized in that: During the configuration process of the master device to the slave device, at most one slave device's high-speed bus transceiver function is enabled at any one time.
5. A high-speed bus communication method using the configuration method of claim 3, characterized in that: The slave device configuration is completed and enters the normal access stage. The process of the host accessing the slave device The following steps are involved: T1: The host device starts the timer at a timing interval of 50μs, and sends data to the outside through the TX signal line in the timer interrupt to access the slave device. The order of accessing the slave device is from small to large according to the configured address number; T2: The host device outputs a negative level to the GPIOa pin to notify the i-th slave device that the host is about to access the i-th slave device, at this time i=1; T3: The i-th slave device detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i-th slave device through the internal control of the i-th slave device, and waits to receive the request data message sent by the host device; T4: The host device enters the timer interrupt and sends a request data message to the i-th slave device through the TX signal line; T5: After the i-th slave device receives the request data message sent by the host through the TX bus, it parses the data and prepares to write the response data message into the cache, and waits for the clock signal to start in the next timer cycle of the host to be sent to the host device; at the same time, the i-th slave device outputs a negative level to the GPIO2 pin; T6: The i+1th slave device detects the level jump of the GPIO1 input pin, enables the high-speed bus transceiver function of the i+1th slave device through the internal control of the i+1th slave device, and waits to receive the request data message sent by the host device; T7: The host device enters the timer interrupt and sends a request data message to the i+1th slave device through the TX signal line; T8: The i-th slave device sends the response data described in step T5 to the host device through the RX signal line while the host device sends the request data message to the i+1-th slave device. After waiting for the sending to be completed, the internal control enables the high-speed bus transceiver function of the i-th slave device. T9: Increase i by 1. When i≤N, execute steps T5-T8 in sequence; when i>N, execute step T2.
6. The high-speed bus communication method according to claim 1, characterized in that: During normal communication, two slave devices are enabled with the high-speed bus transceiver function. The two slave devices simultaneously receive the data message sent by the host, but only one slave device synchronously sends a response message to the host device.