Cascade processing method, data transmission interface, device and medium of millimeter wave chip

Abstract

The application discloses a cascaded processing method of a millimeter wave chip, a data transmission interface, equipment and a medium. The method comprises the following steps: obtaining target data from a front-stage chip or a rear-stage chip, and storing the target data into a data storage unit; determining a target data transmission mode based on a chip type of the rear-stage chip; adjusting target enabling modes of a data signal line, an effective flag signal line, a clock signal line and a reset signal line respectively based on the target data transmission mode through a register management unit, and enabling each signal line in a physical IO interface based on the corresponding target enabling mode, so as to transmit the target data to the rear-stage chip or the front-stage chip. According to the scheme provided in the embodiment of the application, the actual data transmission requirements of different rear-stage chip types are different, the target enabling modes of each signal line of the data transmission interface are adaptively adjusted based on the rear-stage chip type, and therefore the application flexibility of the millimeter wave cascaded chip is improved.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the field of millimeter wave chip technology, and in particular to a cascade processing method, data transmission interface, device, and medium for millimeter wave chips. Background Art

[0002] Existing millimeter-wave chips are mainly divided into two categories: RF chips and SOC chips. RF chips generally only output intermediate frequency signals after detection, and the specific sampling and subsequent data processing are completed by the main control. SOC chips, on the other hand, integrate RF, sampling, and data processing functions. The data transmission interfaces are basically integrated with existing conventional IP cores, such as SPI, UART, Ethernet, etc. The cost of integrating these interfaces is high. Based on this, the application of cascaded chips has been proposed. For example, multiple SOC chips of the same type are cascaded and work together to improve data processing performance while avoiding the use of higher-configuration chips to reduce costs. However, when chips are cascaded, the data transmission method is relatively limited. Data can only be transmitted according to the fixed architecture and protocol of the chip. For example, the transmission between the front-stage chip and the back-stage chip must be maintained at the same clock and cannot be changed according to actual application requirements. Summary of the Invention

[0003] The embodiments of the present application provide a cascade processing method, data transmission interface, device, and medium for a millimeter wave chip, which adaptively configures the data transmission interface connected to the cascade chip according to actual data transmission requirements, thereby improving the application flexibility of the millimeter wave cascade chip.

[0004] In a first aspect, an embodiment of the present application provides a cascade processing method for a millimeter wave chip, which is applied to a data transmission interface, wherein the data transmission interface is electrically connected to a preceding chip and a succeeding chip, respectively, and the preceding chip is a millimeter wave chip. The data transmission interface includes a physical IO interface, a data storage unit, and a register management unit. The physical IO interface includes a data signal line, a valid flag signal line, a clock signal line, and a reset signal line. The method includes:

[0005] Acquire target data from the preceding chip or the succeeding chip, and store the target data in the data storage unit;

[0006] Determining a chip type of the subsequent chip, and determining a target data transmission mode based on the chip type, wherein the target data transmission mode is a full-duplex transmission mode or a half-duplex transmission mode;

[0007] Based on the target data transmission mode, the target enable modes of the data signal line, the valid flag signal line, the clock signal line and the reset signal line are respectively adjusted by the register management unit, and each signal line in the physical IO interface is enabled based on the corresponding target enable mode to transmit the target data to the subsequent chip or the previous chip.

[0008] In some embodiments, determining the chip type of the subsequent chip and determining the target data transmission mode based on the chip type includes:

[0009] When the chip type indicates that the subsequent chip is an FPGA chip, half-duplex transmission mode is determined as the target data transmission mode;

[0010] When the chip type indicates that the subsequent chip is a millimeter wave chip, the full-duplex transmission mode is determined as the target data transmission mode.

[0011] In some embodiments, when the chip type indicates that the subsequent chip is an FPGA chip, the half-duplex transmission mode includes a half-duplex receiving mode and a half-duplex transmitting mode, the clock signal line includes a clock input signal line and a clock output signal line, and based on the target data transmission mode, the target enable modes of the data signal line, the valid flag signal line, the clock signal line, and the reset signal line are respectively adjusted by the register management unit, and each signal line in the physical IO interface is enabled based on the corresponding target enable mode, including:

[0012] When the target enable mode is the half-duplex transmission mode, the clock output signal line is enabled, the data signal line is enabled, the input and output direction of the data signal line is determined to be output, and the valid flag signal line and the reset signal line are enabled;

[0013] or,

[0014] When the target enable mode is the half-duplex receiving mode, the clock input signal line is enabled, the data signal line is enabled, and the input / output direction of the data signal line is determined to be input, and the valid flag signal line and the reset signal line are enabled.

[0015] In some embodiments, when the chip type characterizes that the subsequent chip is a millimeter wave chip, the data transmission interface includes a first transmission interface and a second transmission interface, the first transmission interface includes a first IO interface, the second transmission interface includes a second IO interface, the first transmission interface is electrically connected to the previous chip, and the second transmission interface is electrically connected to the subsequent chip, the first IO interface includes a first data signal line, a first clock output signal line, a first clock input signal line, a first valid flag signal line and a first reset signal line, the second IO interface includes a second data signal line, a second clock output signal line, a second clock input signal line, a second valid flag signal line and a second reset signal line, the first clock output signal The physical IO interface comprises: a first clock input signal line electrically connected to the second clock input signal line, a first clock input signal line electrically connected to the second clock output signal line, a first data signal line electrically connected to the second data signal line, a plurality of first data signal lines and a plurality of second data signal lines, a first valid flag signal line electrically connected to the second valid flag signal line, and a first reset signal line electrically connected to the second reset signal line; and based on the target data transmission mode, adjusting target enable modes of the data signal line, the valid flag signal line, the clock signal line, and the reset signal line respectively by the register management unit, and enabling each signal line in the physical IO interface based on the corresponding target enable mode, including:

[0016] enabling the first clock output signal line, the second clock output signal line, the first clock input signal line, and the second clock input signal line;

[0017] enabling all first data signal lines, determining the input / output directions of a third number of first data signal lines as output, and determining the input / output directions of the remaining fourth number of first data signal lines as input;

[0018] enabling all of the second data signal lines, determining the input and output directions of the third number of second data signal lines as input, and determining the input and output directions of the remaining fourth number of second data signal lines as output;

[0019] The first reset signal line, the second reset signal line, the first valid flag signal line, and the second valid flag signal line are enabled.

[0020] In some embodiments, when the chip type characterizes that the subsequent chip is an FPGA chip, the method further includes:

[0021] When the target data comes from the previous chip, determining a first number of data signal lines that meet current data transmission requirements according to the data volume of the target data, and when the first number is less than the total number of the data signal lines, calculating a first difference between the total number and the first number, and turning off enable signals of the data signal lines whose number is equal to the first difference;

[0022] or,

[0023] When the target data comes from the subsequent chip, the second number of data signal lines that meet the current data reception requirements is determined based on the data volume of the target data; when the second number is less than the total number of the data signal lines, the second difference between the total number and the second number is calculated, and the enable signals of the data signal lines whose number is the second difference are turned off.

[0024] In some embodiments, the first transmission interface includes a first register management unit and a first data storage unit storing first target data, and the second transmission interface includes a second register management unit and a second data storage unit storing second target data. When the chip type characterizes that the subsequent chip is a millimeter wave chip, the method further includes:

[0025] Acquire a first data volume of the first target data and a second data volume of the second target data;

[0026] Based on the first data amount and the second data amount, the first register management unit in combination with the second register management unit updates the third quantity and the fourth quantity of the first data signal lines, and updates the third quantity and the fourth quantity of the second data signal lines.

[0027] In some embodiments, the method further comprises:

[0028] Determining a transmission rate requirement for the target data;

[0029] Based on the transmission rate requirement, the clock output frequency of the clock signal line is adjusted by the register management unit.

[0030] In a second aspect, an embodiment of the present application provides a control device comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the cascade processing method of the millimeter wave chip as described in the first aspect.

[0031] In a third aspect, an embodiment of the present application further provides an electronic device comprising the control device of the second aspect.

[0032] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the cascade processing method of the millimeter wave chip as described in the first aspect.

[0033] The embodiment of the present application provides a cascade processing method, data transmission interface, device, and medium for millimeter wave chips, the method comprising: obtaining target data from the preceding chip or the succeeding chip, and storing the target data in the data storage unit; determining the chip type of the succeeding chip, and determining the target data transmission mode based on the chip type, wherein the target data transmission mode is a full-duplex transmission mode or a half-duplex transmission mode; based on the target data transmission mode, adjusting the target enable modes of the data signal line, the valid flag signal line, the clock signal line, and the reset signal line respectively through the register management unit, and enabling each signal line in the physical IO interface based on the corresponding target enable mode to transmit the target data to the succeeding chip or the preceding chip. According to the solution provided in the embodiment of the present application, the actual data transmission requirements of different succeeding chip types are different, and the target enable modes of each signal line of the data transmission interface are adaptively adjusted based on the succeeding chip type, thereby improving the application flexibility of the millimeter wave cascade chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a flowchart of the steps of the cascade processing method of the millimeter wave chip provided by one embodiment of the present application;

[0035] Figure 2 This is a module diagram of a data transmission interface provided by another embodiment of the present application;

[0036] Figure 3 This is a schematic diagram of another embodiment of the present application providing a millimeter wave chip and an FPGA chip cascaded via a data transmission interface;

[0037] Figure 4 is a schematic diagram of two millimeter wave chips cascaded via a data transmission interface provided by another embodiment of the present application;

[0038] Figure 5 This is a structural diagram of a control device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0040] It is understood that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and the like in the specification, claims, or accompanying drawings are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0041] Existing millimeter-wave chips are mainly divided into two categories: RF chips and SOC chips. RF chips generally only output intermediate frequency signals after detection, and the specific sampling and subsequent data processing are completed by the main control. SOC chips, on the other hand, integrate RF, sampling, and data processing functions. The data transmission interfaces are basically integrated with existing conventional IP cores, such as SPI, UART, Ethernet, etc. The cost of integrating these interfaces is high. Based on this, the application of cascaded chips has been proposed. For example, multiple SOC chips of the same type are cascaded and work together to improve data processing performance while avoiding the use of higher-configuration chips to reduce costs. However, when chips are cascaded, the data transmission method is relatively limited. Data can only be transmitted according to the fixed architecture and protocol of the chip. For example, the transmission between the front-stage chip and the back-stage chip must be maintained at the same clock and cannot be changed according to actual application requirements.

[0042] In order to solve the above-mentioned problems, the embodiments of the present application provide a cascade processing method, data transmission interface, device, and medium for millimeter wave chips, the method comprising: obtaining target data from the preceding chip or the succeeding chip, and storing the target data in the data storage unit; determining the chip type of the succeeding chip, and determining the target data transmission mode based on the chip type, wherein the target data transmission mode is a full-duplex transmission mode or a half-duplex transmission mode; based on the target data transmission mode, adjusting the target enable modes of the data signal line, the valid flag signal line, the clock signal line, and the reset signal line respectively through the register management unit, and enabling each signal line in the physical IO interface based on the corresponding target enable mode to transmit the target data to the succeeding chip or the preceding chip. According to the solution provided in the embodiments of the present application, the actual data transmission requirements of different succeeding chip types are different, and the target enable modes of each signal line of the data transmission interface are adaptively adjusted based on the succeeding chip type, thereby improving the application flexibility of the millimeter wave cascade chip.

[0043] The embodiments of the present application are further described below with reference to the accompanying drawings.

[0044] refer to Figure 1 , Figure 1This is a flowchart of a cascade processing method for millimeter wave chips provided by an embodiment of the present application. The embodiment of the present application provides a cascade processing method for millimeter wave chips, which is applied to Figures 2 to 4 The data transmission interface 300 shown is electrically connected to the front-stage chip 100 and the back-stage chip. The back-stage chip can be as follows: Figure 3 The FPGA chip 210 shown, or the Figure 4 The chip type shown is a millimeter wave chip rear-stage chip 220, the front-stage chip 100 is a millimeter wave chip, the data transmission interface 300 includes a physical IO interface, a data storage unit 302 and a register management unit 301, the physical IO interface includes a data signal line 304, a valid flag signal line 303, a clock signal line and a reset signal line 307, and the method includes but is not limited to the following steps:

[0045] Step S10 , acquiring target data from a previous chip or a subsequent chip, and storing the target data in a data storage unit.

[0046] Specifically, refer to Figure 2 The data transmission interface 300 of this embodiment includes a data storage unit 302, which is used to store target data from the previous chip 100 or the next chip 210 / 220 before determining the data transmission mode between the previous and next chips.

[0047] Specifically, if Figure 2 As shown, the data transmission interface 300 of this embodiment also includes a working clock, which is provided by the previous-stage chip 100 to the data transmission interface 300 module for operation. The data storage unit 302, the register management unit 301 and the working clock unit are all electrically connected to the chip core of the previous-stage chip 100, and the physical IO interface of the data transmission interface 300 is electrically connected to the chip Pad of the subsequent-stage chip.

[0048] Step S20 , determining the chip type of the subsequent chip, and determining a target data transmission mode based on the chip type, the target data transmission mode being a full-duplex transmission mode or a half-duplex transmission mode.

[0049] Specifically, this embodiment does not limit the specific chip type of the subsequent chip. It can be the same as the previous chip 100, a millimeter wave chip, or an FPGA chip, etc., and those skilled in the art can choose according to actual needs.

[0050] Specifically, in one embodiment, Figure 1 Step S20 includes but is not limited to the following steps:

[0051] Step S21: When the chip type characterization indicates that the subsequent chip is an FPGA chip, the half-duplex transmission mode is determined as the target data transmission mode;

[0052] Step S22 : When the chip type characterization indicates that the subsequent chip is a millimeter wave chip, the full-duplex transmission mode is determined as the target data transmission mode.

[0053] Specifically, the specific method for determining the target data transmission mode of the data transmission interface of this embodiment is based on considerations such as hardware compatibility, signal processing and power consumption, and application requirements between the front-stage chip 100 and the back-stage chip. For example, when the back-stage chip is an FPGA chip, considering that the FPGA chip requires additional signal processing circuits and power consumption when processing millimeter-wave signals, and the half-duplex transmission mode can reduce the complexity and power consumption of signal processing, the half-duplex transmission mode is more suitable for data transmission between the FPGA chip and the millimeter-wave chip; and considering that there is a high bandwidth requirement between millimeter-wave chips, and the millimeter-wave chip has a built-in module that supports the full-duplex transmission mode, therefore, when the front-stage and back-stage chips in the cascade chip are both millimeter-wave chips, the use of the full-duplex transmission mode can maximize the utilization of bandwidth resources and improve data transmission efficiency and reliability.

[0054] Step S30, based on the target data transmission mode, adjust the target enable modes of the data signal line, valid flag signal line, clock signal line and reset signal line respectively through the register management unit, and enable each signal line in the physical IO interface based on the corresponding target enable mode to transmit the target data to the subsequent chip or the previous chip.

[0055] It can be understood that the data transmission interface applied to cascade chips in this embodiment can adjust the target data transmission mode based on the hardware characteristics of the previous and next chips and the transmission requirements of the target data, determine the target enable mode of each signal line in the physical IO interface corresponding to the target data transmission mode, and configure and enable each signal line in the physical IO interface through the register management unit based on the target enable mode to realize data transmission between the previous and next chips. Compared with the existing data transmission interface that can only transmit data in a fixed transmission mode, this embodiment can improve the application flexibility and versatility of the data transmission interface, while enabling the millimeter wave chip to have large data throughput and high frame rate, thereby improving the transmission performance between millimeter wave cascade chips.

[0056] Additionally, in some embodiments, reference Figure 2 and Figure 3 In the case where the chip type characterizes that the subsequent chip is an FPGA chip, the half-duplex transmission mode includes a half-duplex receiving mode and a half-duplex transmitting mode, and the clock signal line includes a clock input signal line 306 and a clock output signal line 305. In this case, Figure 1In step S30, based on the target data transmission mode, the target enable modes of the data signal line, the valid flag signal line, the clock signal line, and the reset signal line are respectively adjusted by the register management unit, and each signal line in the physical IO interface is enabled based on the corresponding target enable mode, including but not limited to the following steps:

[0057] Step S31, when the target enable mode is half-duplex transmission mode, enable the clock output signal line, enable the data signal line, and determine the input and output direction of the data signal line as output, enable the valid flag signal line and the reset signal line;

[0058] or,

[0059] Step S32, when the target enable mode is half-duplex receiving mode, enable the clock input signal line, enable the data signal line, and determine the input and output direction of the data signal line as input, enable the valid flag signal line and the reset signal line.

[0060] Specifically, in this embodiment, the valid flag signal line is enabled by default and used as an output. In the valid flag signal transmitted by the valid flag signal line, the data transmission of the target data starts from the timestamp corresponding to the rising edge and ends from the timestamp corresponding to the falling edge. The register management unit can also be configured to start the data transmission of the target data from the timestamp corresponding to the falling edge and end the data transmission from the timestamp corresponding to the rising edge. No restrictions will be imposed here.

[0061] It is understandable that when the chip type characterization post-stage chip is an FPGA chip, reference Figure 3 In this embodiment, the target enable mode of the data transmission interface is a half-duplex transmission mode, and the half-duplex transmission mode corresponds to a half-duplex sending mode and a half-duplex receiving mode. Specifically, when the target enable mode is the half-duplex sending mode, the clock output signal line is enabled, the data signal line is enabled, and the input and output direction of the data signal line is determined to be output, and the valid flag signal line and the reset signal line are enabled; and when the target enable mode is the half-duplex receiving mode, the clock input signal line is enabled, the data signal line is enabled, and the input and output direction of the data signal line is determined to be input, and the valid flag signal line and the reset signal line are enabled. That is to say, the data transmission interface 300 of this embodiment can adaptively and dynamically configure the target enable modes of different signal lines in the physical IO interface according to different half-duplex requirements, thereby improving the application flexibility of the interface.

[0062] In addition, in some embodiments, when the chip type characterization post-stage chip is an FPGA chip, the cascade processing method of the millimeter wave chip in the embodiment of the present application further includes but is not limited to the following steps:

[0063] Step S311: When target data comes from a previous chip, a first number of data signal lines that meet current data transmission requirements is determined based on the amount of the target data. When the first number is less than the total number of data signal lines, a first difference between the total number and the first number is calculated, and enable signals for the data signal lines whose number is equal to the first difference are turned off.

[0064] or,

[0065] Step S321, when the target data comes from the subsequent chip, determine the second number of data signal lines that meet the current data receiving requirements based on the data volume of the target data; when the second number is less than the total number of data signal lines, calculate the second difference between the total number and the second number, and turn off the enable signal of the data signal lines whose number is the second difference.

[0066] It is understandable that this embodiment also adjusts the number of enabled data signal lines according to the amount of target data currently received or to be sent, specifically: Figure 3 When the target data comes from the front-stage chip 100, the first number of data signal lines 304 that meet the current data sending requirements is determined according to the data volume of the target data. When the first number is less than the total number of data signal lines 304, the first difference between the total number and the first number is calculated, and the enable signal of the data signal lines 304 whose number is the first difference is turned off; when the target data comes from the back-stage chip 210 (i.e., the FPGA chip), the second number of data signal lines 304 that meet the current data receiving requirements is determined according to the data volume of the target data. When the second number is less than the total number of data signal lines 304, the second difference between the total number and the second number is calculated, and the enable signal of the data signal lines 304 whose number is the second difference is turned off. While enhancing flexibility, it can effectively save hardware resources, reduce the overall power consumption of the system, improve transmission efficiency, and reduce the maintenance cost of the signal transmission line.

[0067] Specifically, this embodiment does not involve improvements to the millimeter wave chip. For example, Figure 3 and Figure 4 The front-stage chip 100 of this embodiment includes a radio frequency unit 110, an ADC sampling unit (i.e., a digital-to-analog interface 120), and an algorithm unit 130 including a 1-dimensional FFT operation unit, a 2-dimensional FFT operation unit, a 3-dimensional FFT operation unit, and a CFAR operation unit. Starting from the digital-to-analog interface 120, the output data can be sent out through the data transmission interface 300 of the embodiment of the present application. At the same time, the data received by the data transmission interface 300 from the rear-stage chip can be sent to the front-stage chip 100 and processed again by the core processor 140 of the front-stage chip 100.

[0068] Specifically, in one embodiment, referring to Figure 3In the case where the front-stage chip 100 is a millimeter wave chip and the back-stage chip is an FPGA chip 210, half-duplex is mainly used in this application to transmit large packet data. After the front-stage chip 100 completes ADC sampling or 1-dimensional FFT operation or 2-dimensional FFT operation or 3-dimensional FFT operation or CFAR operation through the digital-analog interface 120 and the algorithm unit 130 to obtain the target data, the target data is sent to the FPGA chip through the data transmission interface 300. After the FPGA chip receives the data and performs further processing, it can choose to directly provide result feedback or transmit it back to the front-stage chip 100 through the data transmission interface 300, and the front-stage chip 100 will perform further processing or feedback the result. The advantage of this method is that when the hardware algorithm unit 130 integrated in the front-stage chip 100 cannot meet the application requirements, the algorithm can be secondary developed through the external FPGA chip 210 to meet the needs of the application scenario.

[0069] In addition, in some embodiments, when the chip type characterization post-stage chip is a millimeter wave chip, reference Figure 4 The data transmission interface 300 includes a first transmission interface 310 and a second transmission interface 320. The first transmission interface 310 includes a first IO interface, and the second transmission interface 320 includes a second IO interface. The first transmission interface 310 is electrically connected to the front-stage chip 100, and the second transmission interface 320 is electrically connected to the back-stage chip 210. The first IO interface includes a first data signal line 311, a first clock output signal line 313, a first clock input signal line 314, a first valid flag signal line 315 and a first reset signal line 316. The second IO interface includes a second data signal line 321, a second clock output signal line 323, a first valid flag signal line 315 and a first reset signal line 316. The first clock input signal line 324, the second valid flag signal line 325, and the second reset signal line 326 are electrically connected. The first clock output signal line 313 is electrically connected to the second clock input signal line 324, the first clock input signal line 314 is electrically connected to the second clock output signal line 323, the first data signal line 311 is electrically connected to the second data signal line 321, the number of the first data signal line 311 and the second data signal line 321 is the same and the number is multiple, the first valid flag signal line 315 is electrically connected to the second valid flag signal line 325, and the first reset signal line 316 is electrically connected to the second reset signal line 326. In this case, Figure 1 In step S30, based on the target data transmission mode, the target enable modes of the data signal line, the valid flag signal line, the clock signal line, and the reset signal line are respectively adjusted by the register management unit, and each signal line in the physical IO interface is enabled based on the corresponding target enable mode, including but not limited to the following steps:

[0070] Step S33, enabling the first clock output signal line, the second clock output signal line, the first clock input signal line, and the second clock input signal line;

[0071] Step S34, enabling all first data signal lines, determining the input / output direction of a third number of first data signal lines as output, and determining the input / output direction of the remaining fourth number of first data signal lines as input;

[0072] Step S35, enabling all second data signal lines, determining the input and output directions of the third number of second data signal lines as input, and determining the input and output directions of the remaining fourth number of second data signal lines as output;

[0073] Step S36 , enabling the first reset signal line, the second reset signal line, the first valid flag signal line, and the second valid flag signal line.

[0074] Understandably, the reference Figure 4 As described in the above embodiment, when the front-stage chip 100 and the back-stage chip are both millimeter wave chips, two transmission interfaces need to be set, namely the first transmission interface 310 and the second transmission interface 320. The first transmission interface 310 and the second transmission interface 320 are connected one-to-one through the corresponding physical IO interface. The first clock output signal line 313 is electrically connected to the second clock input signal line 324, the first clock input signal line 314 is electrically connected to the second clock output signal line 323, the first data signal line 311 is electrically connected to the second data signal line 321, the number of the first data signal line 311 and the second data signal line 321 is the same and the number is multiple, the first valid flag signal line 315 is electrically connected to the second valid flag signal line 325, and the first reset signal line 316 is electrically connected to the second reset signal line 326. On this hardware basis, by enabling the first clock output signal Line 313, the second clock output signal line 323, the first clock input signal line 314 and the second clock input signal line 324; enable all the first data signal lines, determine the input and output directions of the third number of first data signal lines 311 as output, and determine the input and output directions of the remaining fourth number of first data signal lines 312 as input; enable all the second data signal lines, determine the input and output directions of the third number of second data signal lines 321 as input, and determine the input and output directions of the remaining fourth number of second data signal lines 322 as output; enable the first reset signal line 316, the second reset signal line 326, the first valid flag signal line 315 and the second valid flag signal line 325 to realize full-duplex data transmission between the front-stage chip 100 and the back-stage chip 210, so as to improve the transmission rate between the front-stage chip 100 and the back-stage chip 210.

[0075] In addition, in some embodiments, when the chip type characterization post-stage chip is a millimeter wave chip, the first transmission interface includes a first register management unit and a first data storage unit storing first target data, and the second transmission interface includes a second register management unit and a second data storage unit storing second target data. The cascade processing method of the millimeter wave chip in the embodiment of the present application further includes but is not limited to the following steps:

[0076] Step S37, obtaining a first data volume of the first target data and a second data volume of the second target data;

[0077] Step S38 : Based on the first data amount and the second data amount, the first register management unit in combination with the second register management unit updates the third and fourth quantities of the first data signal lines and updates the third and fourth quantities of the second data signal lines.

[0078] Specifically, since the chip type characterizes that the rear-stage chip 210 is a millimeter wave chip, data transmission between the front- and rear-stage chips is realized through the first transmission interface 310 and the second transmission interface 320. This embodiment adjusts the number of data signal lines used as input and output by determining the first data amount and the second data amount. For example, this embodiment includes N data signal lines, and the third number (for example, the 1st to N / 2nd) of data signal lines are configured as outputs through the register unit, and the remaining fourth number of data signal lines, that is, the (N / 2+1)th to Nth data signal lines are configured as inputs; or the number of data bits is changed, and the 1st to N / 4th data signal lines are configured as outputs, and the remaining (N / 4+1)th to Nth data signal lines are configured as inputs. Those skilled in the art adjust the specific number of data signal lines 304 and the specific configuration of the input and output directions of the data signal lines according to actual conditions.

[0079] It is understood that, in one embodiment, Figure 4As shown, in the millimeter wave cascade chip, when the front-stage chip 100 and the back-stage chip are both millimeter wave chips, full-duplex mode is mainly used to transmit data. At this time, the first data signal line 311 of the first transmission interface 310 connected to the front-stage chip 100 is configured so that the number of output signal lines is far greater than the number of input signal lines. For example, the front-stage chip 100 outputs 24 signal lines and inputs 8 signal lines; accordingly, the second data signal line of the second transmission interface 320 connected to the back-stage chip 210 is configured as 8 output signal lines and 24 input signal lines; the front-stage and back-stage chips are connected, and the first valid flag signal line 315 connected to the first transmission interface 310 of the front-stage chip 100 is configured as output, and the second valid flag signal line 325 connected to the second transmission interface 320 of the back-stage chip 210 is configured as output; the first clock output signal line 313 of the front-stage chip 100 is connected to the back-stage chip The second clock input signal line 324 of the chip 210 is electrically connected, and the first clock input signal line 314 of the front-stage chip 100 is electrically connected to the second clock output signal line 323 of the back-stage chip 210; after the front-stage chip 100 completes ADC sampling at the digital-to-analog interface 120, or completes 1-dimensional FFT operation, 2-dimensional FFT operation, 3-dimensional FFT operation or CFAR operation in the algorithm unit 130, the obtained first target data is sent to the back-stage chip through the data output signal line, and the back-stage chip 210 completes subsequent processing. Subsequent processing refers to the secondary processing result of the result of the FFT operation or the result of the CFAR operation performed by the algorithm unit 221 of the back-stage chip 210 in combination with the core processor 222. The amount of result information data is much smaller than the amount of data sent by the front-stage chip, so at the same valid flag bit effective time, only a small number of data bits are needed to complete data transmission. Moreover, since the transmission clocks of the front-end and rear-end chips are independent, the data transmission time of the front-end chip 100 is used as the basis, and the data transmission rate of the rear-end chip can be individually configured according to actual application requirements (adjusting the number of inputs and outputs) to ensure that the information transmitted by the rear-end chip can be completed when the same valid flag takes effect.

[0080] In this way, this embodiment adjusts the enable mode of each signal line in the physical IO module of the data transmission interface based on actual data transmission requirements, such as adjusting the number of data bits used to transmit target data, thereby enhancing flexibility and effectively improving transmission efficiency.

[0081] In addition, in some embodiments, the cascade processing method of the millimeter wave chip provided in the embodiments of the present application includes but is not limited to the following steps:

[0082] Step S41, determining the transmission rate requirement of the target data;

[0083] Step S42: Based on the transmission rate requirement, the clock output frequency of the clock signal line is adjusted by the register management unit.

[0084] It can be understood that this embodiment adjusts the clock output frequency of the clock signal line through the register management unit based on the transmission rate requirement of the target data, and can adjust the configuration of the data transmission interface based on the actual data transmission requirement, thereby enhancing the flexibility of interface application.

[0085] like Figure 5 As shown, Figure 5 : is a structural diagram of a control device provided in one embodiment of the present application. The present invention also provides a control device 500, comprising:

[0086] The processor 510 may be implemented as a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0087] The memory 520 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 520 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 520 and is called by the processor 510 to execute the cascade processing method of the millimeter wave chip in the embodiments of this application;

[0088] Input / output interface 530, used to implement information input and output;

[0089] Communication interface 540, used to implement communication interaction between the apparatus and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.);

[0090] bus 550 , which transmits information between various components of the device (e.g., processor 510 , memory 520 , input / output interface 530 , and communication interface 540 );

[0091] The processor 510 , the memory 520 , the input / output interface 530 and the communication interface 540 are connected to each other in communication within the device via a bus 550 .

[0092] In addition, an embodiment of the present application further provides an electronic device, including the control device 500 of the above embodiment.

[0093] In addition, an embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the cascade processing method of the millimeter wave chip described above is implemented.

[0094] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory optionally includes a memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of the above-mentioned networks include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0095] Those skilled in the art will appreciate that all or some of the steps and systems in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include computer storage media (or non-transitory media) and communication media (or temporary media). As known to those skilled in the art, the term computer storage media is included in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data) and is volatile and non-volatile, removable, and non-removable. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0096] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above implementation. Those skilled in the art can also make various equivalent modifications or substitutions under the shared conditions that do not violate the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A cascade processing method for millimeter wave chips, characterized in that: Applied to a data transmission interface, the data transmission interface is electrically connected to a front-stage chip and a back-stage chip respectively, the front-stage chip is a millimeter wave chip, the data transmission interface includes a physical IO interface, a data storage unit and a register management unit, the physical IO interface includes a data signal line, a valid flag signal line, a clock signal line and a reset signal line, the method includes: Acquire target data from the preceding chip or the succeeding chip, and store the target data in the data storage unit; Determining the chip type of the subsequent chip; when the chip type indicates that the subsequent chip is an FPGA chip, determining the half-duplex transmission mode as the target data transmission mode; when the chip type indicates that the subsequent chip is a millimeter wave chip, determining the full-duplex transmission mode as the target data transmission mode; When the chip type indicates that the subsequent chip is a millimeter wave chip: The data transmission interface includes a first transmission interface and a second transmission interface, the first transmission interface includes a first IO interface, the second transmission interface includes a second IO interface, the first transmission interface is electrically connected to the front-stage chip, the second transmission interface is electrically connected to the back-stage chip, the first IO interface includes a first data signal line, a first clock output signal line, a first clock input signal line, a first valid flag signal line and a first reset signal line, the second IO interface includes a second data signal line, a second clock output signal line, a second clock input signal line, a second valid flag signal line and a second reset signal line, the first clock output signal line is electrically connected to the second clock input signal line, the first clock input signal line is electrically connected to the second clock output signal line, the first data signal line is electrically connected to the second data signal line, the first data signal line and the second data signal line are electrically connected The number of data signal lines is the same and there are multiple of them, the first valid flag signal line is electrically connected to the second valid flag signal line, and the first reset signal line is electrically connected to the second reset signal line; the first clock output signal line, the second clock output signal line, the first clock input signal line, and the second clock input signal line are enabled; all the first data signal lines are enabled, the input and output directions of the third number of first data signal lines are determined to be output, and the input and output directions of the remaining fourth number of first data signal lines are determined to be input; all the second data signal lines are enabled, the input and output directions of the third number of second data signal lines are determined to be input, and the input and output directions of the remaining fourth number of second data signal lines are determined to be output; the first reset signal line, the second reset signal line, the first valid flag signal line, and the second valid flag signal line are enabled; The first transmission interface includes a first register management unit and a first data storage unit storing first target data, and the second transmission interface includes a second register management unit and a second data storage unit storing second target data, obtaining a first data amount of the first target data and a second data amount of the second target data; based on the first data amount and the second data amount, updating the third quantity and the fourth quantity of the first data signal line and updating the third quantity and the fourth quantity of the second data signal line by the first register management unit in combination with the second register management unit; When the chip type indicates that the subsequent chip is an FPGA chip: When the target data comes from the front-stage chip, the first number of data signal lines that meet the current data sending requirements is determined according to the data volume of the target data; when the first number is less than the total number of the data signal lines, the first difference between the total number and the first number is calculated, and the enable signals of the data signal lines whose number is the first difference are turned off; or, when the target data comes from the back-stage chip, the second number of data signal lines that meet the current data receiving requirements is determined according to the data volume of the target data; when the second number is less than the total number of the data signal lines, the second difference between the total number and the second number is calculated, and the enable signals of the data signal lines whose number is the second difference are turned off.

2. The cascade processing method of the millimeter wave chip according to claim 1, characterized in that: The method further comprises: In the case where the chip type characterizes that the subsequent chip is an FPGA chip, the half-duplex transmission mode includes a half-duplex receiving mode and a half-duplex transmitting mode, and the clock signal line includes a clock input signal line and a clock output signal line. When the target enable mode is the half-duplex transmitting mode, the clock output signal line is enabled, the data signal line is enabled, and the input and output direction of the data signal line is determined to be output, and the valid flag signal line and the reset signal line are enabled; or, when the target enable mode is the half-duplex receiving mode, the clock input signal line is enabled, the data signal line is enabled, and the input and output direction of the data signal line is determined to be input, and the valid flag signal line and the reset signal line are enabled.

3. The cascade processing method of millimeter wave chips according to claim 1, characterized in that: The method further comprises: Determining a transmission rate requirement for the target data; Based on the transmission rate requirement, the clock output frequency of the clock signal line is adjusted by the register management unit.

4. A control device, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the cascade processing method of the millimeter wave chip as described in any one of claims 1 to 3.

5. A data transmission interface, characterized in that: Comprising the control device according to claim 4.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the cascade processing method of the millimeter wave chip according to any one of claims 1 to 3.

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