A time delay calculation method, electronic device and storage medium

Abstract

The application discloses a time delay calculation method, an electronic device and a storage medium, and comprises the following steps: constructing a reduced-order model of an interconnection line corresponding to a driver model and a receiver model, wherein the reduced-order model is provided with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; determining a driver output voltage waveform by using a preset step length and the impedance function; taking the driver output voltage waveform as input, determining a receiver input voltage waveform by using a preset time delay voltage threshold and the transfer function; determining an input conversion time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and then determining a time delay calculation result; that is, the application determines the corresponding driver output voltage waveform and the corresponding receiver input voltage waveform by using transient analysis combined with a composite current source model, and then analyzes and accurately calculates the time delay, so that the accuracy of the time delay calculation result can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a delay calculation method, an electronic device and a storage medium. BACKGROUND

[0002] In the static timing analysis of integrated circuits, accurate and fast delay calculation is crucial. When performing delay calculation, the timing path is usually divided into multiple stages, each stage including a driving unit, an RC network of a unit output end and a pin capacitance of a network load end. By establishing corresponding driver models, RC models and receiver models, unit delay and line delay calculation is performed.

[0003] In practice, the present application found that the current technology only performs simple segmentation on the driver output voltage interval when calculating the effective capacitance, and commonly uses delay voltage thresholds, transition minimum voltage thresholds and transition maximum voltage thresholds to divide three intervals. However, when using a composite current source model, the driver output waveform is used to calculate the receiver input waveform, and after obtaining the receiver transition time, the pin capacitance is updated through a lookup table. The driver output waveform obtained by using simple segmentation still has differences with the real waveform, which further leads to distortion of the calculated receiver input waveform, inaccuracy of the pin capacitance obtained from the lookup table, and inaccuracy of the delay result obtained after final iteration and convergence. When the supply voltage decreases, the driver output waveform is more nonlinear, and the resulting error is more obvious. That is, the waveform obtained by simple segmentation cannot accurately represent the distortion of the driver output waveform, thereby leading to inaccurate analysis results of the delay calculation. SUMMARY

[0004] The technical problem solved by the present application is to provide a delay calculation method, an electronic device and a storage medium, which can accurately represent the driver output voltage waveform and the receiver input voltage waveform, and improve the accuracy of the analysis results of the delay calculation.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a delay calculation method, comprising: constructing a reduced-order model of an interconnection line corresponding to a driver model and a receiver model, wherein the reduced-order model is provided with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; determining a driver output voltage waveform corresponding to the driver model by using a preset step size and the impedance function; determining a receiver input voltage waveform corresponding to the receiver model by using a preset delay voltage threshold and the transfer function, with the driver output voltage waveform as input; and determining an input transition time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and further determining a delay calculation result.

[0006] In some embodiments, the constructing the reduced-order model of the interconnect line corresponding to the driver model and the receiver model comprises: determining the driver model and the receiver model according to timing information provided by a preset first file; and establishing the reduced-order model of the interconnect line according to parasitic parameter information provided by a preset second file, the driver model and the receiver model.

[0007] In some embodiments, the establishing the reduced-order model of the interconnect line according to parasitic parameter information provided by a preset second file, the driver model and the receiver model comprises: establishing first and second circuit equations corresponding to a driver output current and a driver output voltage according to interconnect line information provided by the preset second file; establishing third and fourth circuit equations corresponding to the driver output voltage and a receiver input voltage; performing Laplace transform on the first and second circuit equations to determine the impedance function; performing Laplace transform on the third and fourth circuit equations to determine the transfer function; and composing the reduced-order model with the transfer function and the impedance function.

[0008] In some embodiments, the impedance function comprises a first impedance function and a second impedance function; and the determining the driver output voltage waveform corresponding to the driver model using a preset step size and the impedance function comprises: determining a current curve and a corresponding voltage curve corresponding to each load using a preset output load interval to establish a current curve set and a voltage curve set of the driver output; determining an interpolation coefficient and a corresponding starting time according to a preset starting capacitance, and saving a starting point of an output current waveform of the current curve set and a starting point of an output voltage waveform of the voltage curve set; determining a current voltage using a preset voltage change value and a starting voltage, and determining a current time and a corresponding voltage change rate using the current voltage and the interpolation coefficient, and determining a current current according to the current time; increasing the current time by a preset step size, and determining an output voltage using a recursive convolution method through the output current waveform and the first impedance function or the second impedance function to determine the driver output voltage waveform corresponding to the driver model.

[0009] In some embodiments, the current time is used to determine the current current, including: using the first voltage curve and the second voltage curve corresponding to the two endpoints of the output load interval to determine the first time and the second time corresponding to the current voltage, and using the first current curve and the second current curve corresponding to the two endpoints of the output load interval to determine the first current corresponding to the first time and the second current corresponding to the second time; then determine the time difference ratio of the first time difference between the current time and the first time and the second time difference between the second time and the first time, and determine the current difference value of the second current and the first current, and determine the current according to the product of the time difference ratio and the current difference value, and the first current, and save the current voltage and the current current to the corresponding output voltage waveform and output current waveform.

[0010] In some embodiments, the output voltage is determined using a recursive convolution method, including: obtaining the first zero pole and the second zero pole of the first impedance function or the second impedance function, and obtaining the output voltage of the previous time step; based on the preset step, the first zero pole, the second zero pole, the current corresponding to the output current waveform and the order of the reduced order model, the output voltage is determined by a recursive convolution method.

[0011] In some embodiments, it further includes: judging the size relationship between the current time and the first time and the second time corresponding to the current voltage; if the current time is between the first time and the second time, the current current is determined by using the current time; if the current time is outside the first time and the second time, the two endpoints of the output load interval are adjusted so that the adjusted current time is between the first time and the second time, and then the current current is determined by using the adjusted current time.

[0012] In some embodiments, it further includes: numerical detection is performed on the current voltage, current and voltage change rate; when the numerical value is normal, the change rate difference value of the voltage change rate corresponding to the current step and the voltage change rate corresponding to the previous step is calculated; the local truncation error is calculated using the change rate difference value, and then the preset step is adjusted through the first relationship between the local truncation error and the preset error tolerance and the size of the voltage change rate; if the numerical abnormality occurs, the solution of the current step is marked as invalid, and the rollback processing is performed.

[0013] In some embodiments, further comprising: judging the current voltage by using a delay voltage threshold; switching the first impedance function or the second impedance function in the reduced order model to the second impedance function or the first impedance function when the current voltage of the previous step is less than the delay voltage threshold and the current voltage of the current step is greater than the delay voltage threshold; if the delay voltage threshold is outside the current voltage of the previous step and the current voltage of the current step, judging the current voltage by using an end voltage threshold, wherein the delay voltage threshold and the end voltage threshold are in a multiple relationship; and re-performing the solving of the output voltage when the current voltage is less than the end voltage threshold.

[0014] In some embodiments, the transfer function comprises a first transfer function and a second transfer function; and determining the receiver input voltage waveform corresponding to the receiver model by using the preset delay voltage threshold and the transfer function comprises: obtaining third and fourth zero poles of the first transfer function or the second transfer function by using the driver output voltage waveform as input; and determining the receiver input voltage waveform by recursive convolution based on a preset step, the third and fourth zero poles, point information corresponding to the driver output voltage waveform, and an order of the reduced order model.

[0015] In some embodiments, determining the input conversion time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and further determining the delay calculation result comprises: obtaining a delay threshold voltage, a first conversion threshold voltage, and a second conversion threshold voltage, and obtaining a reference time corresponding to a current curve in a current curve set; determining a unit delay by using a first time corresponding to the driver output voltage waveform and the delay threshold voltage, and further determining the unit delay by using the first time and the reference time; determining a second time by using the driver output voltage waveform and the first conversion threshold voltage, determining a third time by using the driver output voltage waveform and the second conversion threshold voltage, and further determining the unit output conversion time by using the second time and the third time; determining an interconnection line delay by using a fourth time corresponding to the driver output voltage waveform and the delay threshold voltage, and a fifth time corresponding to the receiver input voltage waveform and the delay threshold voltage; and determining a lower unit input conversion time by using a sixth time corresponding to the receiver input voltage waveform and the second conversion threshold voltage, and a seventh time corresponding to the receiver input voltage waveform and the first conversion threshold voltage.

[0016] In some embodiments, further comprising: comparing absolute and relative changes of the input conversion time corresponding to the current iteration and the previous iteration; if not convergent, updating a preset output load interval by using the input conversion time of the current iteration, and further recalculating the driver output waveform.

[0017] To solve the above technical problems, the application further provides an electronic device, comprising a memory and a processor coupled with the memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to implement the method as described above.

[0018] To solve the above technical problems, the application further provides a storage medium, the storage medium having at least one program, the at least one program being loaded and executed by a processor to implement the method as described above.

[0019] Distinguishing from the prior art, the delay calculation method provided by the application comprises: constructing a reduced-order model of an interconnection line corresponding to a driver model and a receiver model, wherein the reduced-order model is provided with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model; determining a driver output voltage waveform corresponding to the driver model by using a preset step size and the impedance function; determining a receiver input voltage waveform corresponding to the receiver model by using a preset delay voltage threshold and the transfer function; and determining an input conversion time corresponding to the receiver model by using the driver output voltage waveform and the receiver input voltage waveform, and then determining a delay calculation result. That is, the application determines the corresponding driver output voltage waveform, i.e., the corresponding receiver input voltage waveform, by using transient analysis combined with a composite current source model (the driver model and the receiver model), and then analyzes and accurately calculates the delay, which can effectively improve the accuracy of the delay calculation result. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor. Among them:

[0021] Figure 1 is a flowchart of an embodiment of the delay calculation method in the application;

[0022] Figure 2 is a structural schematic diagram of the model in the application;

[0023] Figure 3 is a flowchart of an embodiment of step S20 in the application;

[0024] Figure 4 is a schematic diagram of the driver output voltage waveform in the application;

[0025] Figure 5 is a structural schematic diagram of an embodiment of the electronic device in the application;

[0026] Figure 6 Figure 1 is a structural schematic diagram of an embodiment of the storage medium in the present application. DETAILED DESCRIPTION

[0027] The application will be further described below in conjunction with the drawings and embodiments. It is particularly pointed out that the following embodiments are only for illustrating the application, but not for limiting the scope of the application. Similarly, the following embodiments are only part of the embodiments of the application, but not all the embodiments of the application, and all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the application.

[0028] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. Those skilled in the art will appreciate that embodiments described herein can be combined with other embodiments.

[0029] In static timing analysis of integrated circuits, it is important to perform accurate and fast delay calculation. In performing delay calculation, a timing path is usually divided into stages, each stage including a driver, an RC network at the output of the cell, and a pin capacitance at the load of the network. Cell delay and wire delay are calculated by establishing corresponding driver model, RC model, and receiver model. For designs using advanced technology, the RC model is modeled by appropriate model order reduction techniques. The driver and receiver models use composite current source (CCS) models.

[0030] When the load at the output includes interconnect resistance, an equivalent load capacitance is usually found such that the timing at the output of the original design matches that of a design with the equivalent load capacitance. This equivalent load capacitance is called "effective capacitance", which depends on the input impedance of the driver and its load. Through the effective capacitance and the input slew time, the delay and slew time of the cell are looked up and calculated in a lookup table.

[0031] In existing delay calculation techniques based on composite current source models, a more accurate method is to segment the driver output voltage interval, and calculate the delay by interpolation at the segmented voltage threshold. The effective capacitance corresponding to each interval is updated according to the delay calculation result, and the driver output voltage waveform and the receiver input voltage waveform are obtained through multiple iterations and convergence.

[0032] The prior art only simply segments the driver output voltage interval when calculating the effective capacitance, and commonly uses delay voltage thresholds, conversion minimum voltage thresholds and conversion maximum voltage thresholds to divide three intervals. However, when using a composite current source model, the receiver input waveform is calculated through the driver output waveform, the receiver conversion time is obtained, and the pin capacitance is updated through a lookup table. The driver output waveform obtained by using simple segmentation still has differences from the real waveform, which further leads to distortion of the calculated receiver input waveform, inaccuracy of the pin capacitance obtained from the lookup table, and inaccuracy of the delay result obtained after final iteration and convergence. When the power supply voltage decreases, the driver output waveform is more nonlinear, and the error is more obvious.

[0033] In addition, when signal integrity analysis is involved, a more complete and real waveform is needed to represent the influence of the coupling capacitance, and the waveform obtained by simple segmentation cannot accurately represent the distortion of the driver output waveform, which leads to inaccurate analysis results.

[0034] Therefore, the present application proposes a delay calculation method, which uses transient analysis combined with a composite current source model (driver model and receiver model) to determine the corresponding driver output voltage waveform, i.e., the corresponding receiver input voltage waveform, and then performs accurate analysis and delay calculation, which can effectively improve the accuracy of the delay calculation result.

[0035] Please refer to Figure 1 , Figure 1 which is a flowchart of an embodiment of the delay calculation method in the present application. It should be noted that the method of the present application is not limited to the order of the flowchart shown in Figure 1 .

[0036] As shown in Figure 1 , the delay calculation method in the present application includes the following steps:

[0037] S10, constructing a reduced-order model of the interconnection line corresponding to the driver model and the receiver model, wherein the reduced-order model is provided with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model.

[0038] The transfer function is a frequency domain matrix transfer function obtained by Laplace transform of a circuit equation with driver output voltage and receiver input voltage as input and output; the impedance function is a transfer function obtained by Laplace transform of a circuit equation with driver output current and driver output voltage as input and output, also known as impedance function; the reduced-order model is a correlation model of the interconnection line established according to the parasitic parameter information corresponding to the driver model and the receiver model; the driver model provides a current curve varying with time, and the receiver model provides an input capacitance with a delay threshold as a boundary.

[0039] Specifically, a driver model and a receiver model of the composite current source model are determined, and a reduced-order model of the interconnection line is established according to parasitic parameter information corresponding to the preset driver model and the receiver model.

[0040] S20, a driver output voltage waveform corresponding to the driver model is determined by using a preset step length and an impedance function.

[0041] The preset step length is a step length added to the current time in the transient analysis process.

[0042] Specifically, the starting capacitor is used to determine the starting time to obtain the starting point of the driver output voltage waveform, and to determine the point of the driver output voltage waveform corresponding to the current voltage and the current current corresponding to the current time; then a preset step length is added for analysis, and the point of the driver output voltage waveform corresponding to the preset step length is determined again by combining the impedance function, and the driver output voltage waveform corresponding to the driver model is determined.

[0043] S30, the driver output voltage waveform is taken as input, and a receiver input voltage waveform corresponding to the receiver model is determined by using a preset delay voltage threshold and a transfer function.

[0044] The preset delay voltage threshold is provided by the receiver model.

[0045] Specifically, the driver output voltage waveform determined in the above step is taken as input, and the receiver input voltage waveform is solved by using the transfer function through the recursive convolution method, wherein the switching point of the transfer function is taken as the preset delay voltage threshold. The time value of each point of the receiver input voltage waveform corresponds to the point of the driver output waveform one by one, and the complete receiver input voltage waveform can be determined.

[0046] S40, the input conversion time corresponding to the receiver model is determined by using the driver output voltage waveform and the receiver input voltage waveform, and the delay calculation result is determined.

[0047] The input conversion time corresponding to the receiver model is determined according to the delay voltage threshold and the conversion voltage threshold.

[0048] Specifically, after the driver output voltage waveform and the receiver input voltage waveform are determined, the delay threshold provided by the receiver model, such as the delay voltage threshold and the conversion voltage threshold, can be used to determine the input conversion time corresponding to the receiver model, and the delay calculation result can be determined according to the change of the input conversion time of the previous iteration and the current iteration.

[0049] In the embodiment, the corresponding driver output voltage waveform, i.e., the corresponding receiver input voltage waveform, is determined by using the transient analysis combined with the composite current source model (the driver model and the receiver model), and then the analysis and the accurate calculation of the delay are performed, so that the accuracy of the delay calculation result can be effectively improved.

[0050] In some embodiments, the reading of the timing information provided by the first file and the parasitic parameter information provided by the second file, i.e., the interconnection line information, is further included before the construction of the reduced-order model.

[0051] The step S10 can further include the following steps:

[0052] The preset first file and the preset second file are read.

[0053] The preset first file is a cell library file, and the cell library file provides the driver model and the receiver model of the composite current source model. The driver model provides a current curve changing with time, and the receiver model provides a plurality of input capacitances divided by a delay voltage threshold, such as a first input capacitance 1 and a second input capacitance 2. The preset second file is a parasitic parameter file.

[0054] Specifically, various types of files required by the static timing analysis are read in, and the specific types of files include a cell library file containing cell timing information created by using a timing library format, and a parasitic parameter file containing interconnection line parasitic parameter information described by using a standard parasitic exchange format.

[0055] Further, a third file and a fourth file can also be read in. The third file is a netlist file describing the circuit function written by using a hardware description language, and the fourth file is a design constraint file providing timing constraint information.

[0056] The driver model and the receiver model are determined according to the timing information provided by the preset first file.

[0057] The driver model and the receiver model of the composite current source model can be determined according to the cell timing information included in the cell library file, because the cell library file as the first file contains the timing information, such as the cell timing information.

[0058] Referring to Figure 2 , Figure 2 is a structural schematic diagram of the model in the present application.

[0059] As Figure 2 shown, the driver model and the receiver model of the composite current source model are connected with the reduced-order model, respectively.

[0060] The reduced-order model of the interconnection line is established according to the parasitic parameter information provided by the preset second file, the driver model and the receiver model.

[0061] The parasitic parameter information provided by the second file is information of resistance, capacitance, etc. of the interconnection line provided by the parasitic parameter file.

[0062] Further, the reduced-order model of the interconnection line is established according to the driver model and the receiver model and the parasitic parameter information provided by the parasitic parameter file.

[0063] In some embodiments, the step of establishing the reduced-order model of the interconnection line can further include the following steps.

[0064] According to the interconnection line information provided by the preset second file, i.e. the parasitic parameter information, including resistance, capacitance, etc. of the interconnection line, the first circuit equation and the second circuit equation corresponding to the driver output current and the driver output voltage are established.

[0065] The first circuit equation and the second circuit equation can be established by using the modified nodal analysis (MNA).

[0066] Specifically, the resistance and capacitance information of the interconnection line provided in the parasitic parameter file, such as the driver output current and the driver output voltage, is used to establish the corresponding first circuit equation and the second circuit equation by the modified nodal analysis.

[0067] The first circuit equation is:

[0068]

[0069] The second circuit equation is:

[0070] u drv (t)=L T x.

[0071] Wherein, i drv is the driver output current; u drv is the driver output voltage; G and C are n x n conductance and energy storage element matrices, x is an n-dimensional MNA variable vector, i drv (t) is an N i dimensional input excitation vector, B is an n x N o connection matrix, L is an n x N drv probe matrix, u o (t) is an N o dimensional output vector.

[0072] And the third circuit equation and the fourth circuit equation corresponding to the driver output voltage and the receiver input voltage are established.

[0073] Specifically, the resistance and capacitance information of the interconnection line provided in the parasitic parameter file, such as the driver output voltage and the receiver input voltage, are used to establish corresponding third and fourth circuit equations by improving the node method.

[0074] The third circuit equation is:

[0075]

[0076] The fourth circuit equation is:

[0077] u rec (t)=L T x.

[0078] wherein u rec is the receiver input voltage, u drv (t) is an N rec dimensional input excitation vector, and u o (t) is an N T dimensional output vector.

[0079] The Laplace transform is performed on the first and second circuit equations to determine the impedance function, and the Laplace transform is performed on the third and fourth circuit equations to determine the transfer function.

[0080] The third and fourth circuit equations with the driver output voltage and the receiver input voltage as the input and output are subjected to the Laplace transform to obtain the transfer function corresponding to the frequency domain matrix.

[0081] The transfer function is:

[0082] H(s)=L T (G+sC) -1 B.

[0083] wherein s is an independent variable.

[0084] The first and second circuit equations with the driver output current and the driver output voltage as the input and output are subjected to the Laplace transform to also obtain the corresponding transfer function, and the transfer function corresponding to the first and second circuit equations is taken as the impedance function.

[0085] That is, the impedance function is:

[0086] Z(s)=L T (G+sC) -1 B.

[0087] wherein s is an independent variable.

[0088] Further, the transfer function and the impedance function are used to form a reduced-order model of the interconnection line.

[0089] In some embodiments, it is also required to obtain the zero-pole form of each term in the transfer function.

[0090] Specifically, the block matrix of the transfer matrix can be obtained by an iterative algorithm, a projection method, specifically, the Arnoldi method, and the projection method combined with the Krylov subspace, and then the zero-pole form of each term in the transfer function of the matrix is determined by matrix matching.

[0091] The calculation formula of the zero-pole form is as follows:

[0092]

[0093] where q is the order of the reduced order model, k m and p m are the zero-pole of the impedance function, respectively.

[0094] The time-domain output response corresponding to the given input can be obtained by the transfer function and the Laplace inverse transform.

[0095] Then, when the composite current source receiver model is used, the impedance function corresponding to the circuit equation with the driver output current and the driver output voltage as the input and output can be obtained, in some embodiments, the impedance function can include the first impedance function z1(t) and the second impedance function z2(t), which are used for subsequent switching; the transfer function corresponding to the circuit equation with the driver output voltage and the receiver input voltage as the input and output can also be obtained, in some embodiments, the transfer function can include the first transfer function h1(t) and the second transfer function h2(t), which are used for subsequent switching; wherein the first impedance function z1(t) and the first transfer function h1(t) correspond to the first input capacitance 1, and the second impedance function z2(t) and the second transfer function h2(t) correspond to the second input capacitance 2.

[0096] Then, step 20 is performed to determine the driver output voltage waveform corresponding to the driver model by using the preset step size and the impedance function.

[0097] Specifically, an embodiment of step S20 can include the following steps:

[0098] The current curve and the corresponding voltage curve corresponding to each load are determined by using the preset output load interval, and then the current curve set and the voltage curve set of the driver output are established.

[0099] The preset output load interval is the output load region corresponding to the driver model, because each load has a corresponding current curve, and the voltage curve corresponding to the current curve of each load can be calculated, therefore, the current curve set and the voltage curve set of the driver output can be established.

[0100] Specifically, a preset output load interval is acquired, and then a current curve corresponding to each load segment point is determined according to the preset output load interval, and then a corresponding voltage curve is calculated, and then a driver output current curve set is established by using all the current curves corresponding to the load segment points, and a driver output voltage curve set is established by using all the voltage curves corresponding to the load segment points.

[0101] In some embodiments, the preset output load interval can be provided as a cell library file of the first file; in addition, according to a driver input transition time given by a fourth file, i.e., a design constraint file, the driver input transition time and the output load interval are combined, and then the current curve corresponding to each load segment point is found out, and the corresponding voltage curve is calculated.

[0102] Then, an interpolation coefficient and a corresponding start time are determined according to the preset start capacitance, and an output current waveform start point of the corresponding current curve set and an output voltage waveform start point of the voltage curve set are saved.

[0103] The start capacitance can be a minimum capacitance value in the output load interval; the endpoints of the output load interval include a first endpoint C1 and a second endpoint C2, and the initial times of the current curves corresponding to the first endpoint C1 and the second endpoint C2 can include a first initial time 1 and a second initial time 2.

[0104] Specifically, the minimum capacitance in the output load interval is acquired as the start capacitance, and the first endpoint C1 and the second endpoint C2 of the output load interval are acquired, and the first initial time 1 and the second initial time 2 corresponding to the first endpoint C1 and the second endpoint C2 are acquired, and then the interpolation coefficient is determined according to the start capacitance, the first endpoint C1 and the second endpoint C2, for example, the interpolation coefficient is determined by the ratio of the first ratio of the start capacitance to the first endpoint to the second ratio of the second endpoint to the first endpoint.

[0105] The interpolation coefficient is calculated as follows:

[0106] k = (C init -C1) / (C2-C1).

[0107] The start capacitance C init is the start capacitance, and k is the interpolation coefficient.

[0108] In some embodiments, the start voltage can be updated by the calculation method of the effective capacitance.

[0109] Then, the start time corresponding to the start capacitance is determined by interpolating the time with the first initial time, the second initial time and the interpolation coefficient; for example, a first product is determined by the product of the difference between the second initial time and the first initial time and the interpolation coefficient, and then the start time is determined by the sum of the first product and the first initial time.

[0110] The start time is calculated as follows:

[0111] t init = t c1 + k(t c2 - t c1 ).

[0112] where t init is the start time.

[0113] In some embodiments, the start voltage is 0 or vdd, and the start current is 0, thereby saving the start point of the output voltage waveform and the start point of the output current waveform.

[0114] Further, the current voltage is determined using the preset voltage change value and the start voltage, and the current time and the corresponding voltage change rate are determined using the current voltage and the interpolation coefficient, and the current current is determined according to the current time.

[0115] where the preset voltage change value is a selected small voltage change value.

[0116] Specifically, a small voltage change value is selected, and then the current voltage can be obtained according to the start voltage and the voltage change value; then the first voltage curve and the second voltage curve corresponding to the first endpoint and the second endpoint of the output load interval are used to find the first time corresponding to the current voltage on the first voltage curve, and the second time corresponding to the current voltage on the second voltage curve, and then the current time after the voltage change is calculated using interpolation; then the start step is determined using the difference between the start time and the current time, and the voltage change rate is determined. In addition, the first current and the second current are found in the first current curve and the second current curve corresponding to the first endpoint and the second endpoint of the output load interval, respectively, and then the first time difference between the current time and the first time, the second time difference between the second time and the first time, and the current difference between the second current and the first current are determined, and then the product of the time difference ratio and the current difference is determined, and the current current is determined according to the first current, and the current voltage and the current current are saved in the corresponding output voltage waveform and output current waveform.

[0117] For example, a small voltage change value is selected, and then the current voltage v out is obtained according to the start voltage and the voltage change value, and then the first time 1 corresponding to the current voltage v out is found through the first endpoint C1 of the output load interval, and the second time 2 corresponding to the current voltage v out is found through the second endpoint C2 of the output load interval, and then the current time after the voltage change is calculated using the difference.

[0118] The current time is calculated as follows:

[0119] t now = t1+ k(t2- t1).

[0120] where t now is the current time.

[0121] And the initial step is calculated as follows:

[0122] t step = t now - t init .

[0123] where t step is the initial step, and t init is the initial time.

[0124] In addition, the voltage rate of change is / , where is the time-varying value.

[0125] And by outputting the first current curve corresponding to the first endpoint of the load and the second current curve corresponding to the second endpoint of the load, the first current 1 and the second current 2 corresponding to the first time and the second time are found, respectively.

[0126] Then the current current is calculated as follows:

[0127]

[0128] where i out is the current current.

[0129] Further, the current voltage point (t now , v out ) and the current current point (t now , i out ) are saved in the output voltage waveform and the output current waveform, respectively.

[0130] Next, a preset step is added to the current time, and the output voltage is determined using the recursive convolution method by outputting the current waveform and the first impedance function or the second impedance function, and then the driver output voltage waveform corresponding to the driver model is determined.

[0131] Where the impedance function includes the first impedance function and the second impedance function, one of which can be used first, and the other can be switched according to the change of the output voltage.

[0132] Specifically, on the basis of the current time t now , a preset step is added, that is, an initial step t step is added., and the output voltage can be solved by using the recursive convolution method based on the output current waveform and the first impedance function z1(t) or the second impedance function z1(t) obtained in the foregoing.

[0133] In some embodiments, the first zero pole and the second zero pole of the impedance function can also be obtained by a calculation formula in the form of zero poles, and the output voltage of the previous time step can be obtained; and then the output voltage can be determined by using the recursive convolution method based on the preset step, the first zero pole, the second zero pole, the current corresponding to the output current waveform, and the order of the reduced-order model.

[0134] The output voltage calculation process is as follows:

[0135]

[0136] wherein v out is the output voltage, k m is the first zero pole of the impedance function, p m is the second zero pole of the impedance function, t step is the preset step, i out is the current, and q is the order of the reduced-order model. prev

[0137] Further, the size relationship between the current time and the first time and the second time corresponding to the current voltage can be determined, and then the first endpoint and the second endpoint of the output load interval can be adjusted according to the size relationship, so that the current time is between the first time and the second time, and the value of the current corresponding to the current time is determined by using the adjusted current time.

[0138] For example, the first voltage curve corresponding to the first endpoint C1 of the output load and the second voltage curve corresponding to the second endpoint C2 of the output load are used to find the first time 1 and the second time 2 corresponding to the current voltage v out , and then the size relationship between the current time t now and the first time 1 and the second time 2 is determined; if the current time t now is between the first time 1 and the second time 2, the current can be determined by using the current time; if the current time t now is outside the first time 1 and the second time 2, the two endpoints of the output load interval, i.e., the first endpoint C1 and the second endpoint C2, need to be adjusted, so that the adjusted current time t now is between the first time 1 and the second time 2, and then the current is determined by using the adjusted current time t now .

[0139] ​Further, the preset step length of the transient analysis can also be adjusted.

[0140] Specifically, the values of the current voltage, the current current and the voltage rate of change are detected to determine whether the values are normal; when the values are normal, the rate of change difference between the voltage rate of change corresponding to the current step length and the voltage rate of change corresponding to the previous step length is calculated; the preset step length is adjusted by using the rate of change difference, the first relationship between the local truncation error and the preset error tolerance, and the size of the voltage rate of change; if the values are abnormal, the solving of the current step length is marked as invalid, and a rollback process is performed.

[0141] For example, it is checked whether the values of the current voltage v out , the current current and the voltage rate of change dv / dt are normal, i.e., whether they are in a reasonable range, which can be set according to actual conditions.

[0142] When the values are detected to be abnormal, the preset step length, i.e., the initial step length t step , is reduced, the solving corresponding to this step length is marked as invalid, and the values of the current voltage v out and the current current are rolled back; when the values are detected to be normal, the rate of change difference Δv / dt between the voltage rate of change dv / dt corresponding to the current step length and the voltage rate of change dv / dt corresponding to the previous step length is calculated, and then the preset step length, i.e., the initial step length t step , is adjusted by using the rate of change difference Δv / dt, the first relationship between the local truncation error and the preset error tolerance, and the size of the voltage rate of change dv / dt, so that the values of the current voltage v out and the current current calculated after the initial step length is adjusted are in the reasonable range.

[0143] Further, the current voltage can also be judged by using a delay voltage threshold value; if the current voltage passes the delay voltage threshold value, the first impedance function or the second impedance function is switched to the second impedance function or the first impedance function; otherwise, it is further judged whether the current voltage reaches an end voltage threshold value, and the calculation process is ended when the current voltage reaches the end voltage threshold value.

[0144] Specifically, when the current voltage of the previous step length is less than the delay voltage threshold value and the current voltage of the current step length is greater than the delay voltage threshold value, the first impedance function or the second impedance function is switched to the second impedance function or the first impedance function; that is, the corresponding reduced-order model is switched to the corresponding reduced-order model; if the delay voltage threshold value is outside the current voltage of the previous step length and the current voltage of the current step length, the current voltage is judged by using the end voltage threshold value, wherein the delay voltage threshold value and the end voltage threshold value are in a multiple relationship; when the current voltage is less than the end voltage threshold value, the solving of the output voltage is performed again.

[0145] For example, the delay voltage threshold is 0.5vdd, and the current voltage v out If the current voltage is less than 0.5vdd and the current voltage of the current step is greater than or equal to 0.5vdd, the first impedance function z1(t) is switched to the second impedance function z2(t). If the current voltage does not pass through the delay voltage threshold, it is determined whether the current voltage reaches the end voltage threshold vdd. If the current voltage reaches the end voltage threshold vdd, the calculation process is ended. If the current voltage does not reach the end voltage threshold vdd, the current voltage v out is calculated.

[0146] In order to more clearly represent the operation process of step S20, the following is described in combination with the drawings.

[0147] Referring to Figure 3 , Figure 3 FIG. 4 is a flowchart of an embodiment of step S20 in the present application.

[0148] As Figure 3 shown, step S20 can include:

[0149] S31, establishing an output current curve set and a voltage curve set.

[0150] That is, according to the output load interval, the current curve corresponding to each load segment point is found, and the corresponding voltage curve is calculated, and then the driver output current curve set and the driver output voltage curve set are established.

[0151] S32, transient analysis initialization.

[0152] That is, through the starting capacitance, the interpolation coefficient is calculated, and the starting time is determined, and the starting point corresponding to the output voltage waveform and the output current waveform is saved with the corresponding starting voltage and starting current.

[0153] S33, transient analysis start.

[0154] That is, a voltage change value is selected, the current voltage is obtained according to the starting voltage and the voltage change value, and the first time and the second time corresponding to the current voltage are determined through the two endpoints of the load interval, and the current time is obtained through interpolation calculation, and the corresponding starting step and voltage change rate are obtained. Through the two endpoints of the output load interval, the first current and the second current corresponding to the first time and the second time are determined, and then the current current is determined.

[0155] S34, transient analysis single-step solution.

[0156] That is, the current time is increased by a preset step, that is, the starting step, and the output voltage is solved through the output current waveform and the impedance function.

[0157] S35, adjust the transient analysis step.

[0158] That is, check whether the current voltage, current, and voltage rate of change are within a reasonable range. If the values are not abnormal, adjust the preset step size.

[0159] S36, determine whether to back up.

[0160] If the values in step S35 are abnormal, perform a back-up process and return to step S34 for single-step solving.

[0161] S37, save the single-step solving result.

[0162] That is, save the current voltage point and current current point to the output voltage waveform and output current waveform.

[0163] S38, determine whether the critical threshold point has been reached.

[0164] That is, determine whether the current voltage change has reached the delay voltage threshold, that is, whether the current voltage has passed the delay voltage threshold. If so, perform step S39. Otherwise, determine whether the end voltage threshold has been reached. If so, end. Otherwise, return to step S34 for single-step solving.

[0165] S39, switch the reduced-order model.

[0166] That is, when the current voltage change passes the delay voltage threshold, switch the reduced-order model from the one corresponding to the first impedance function to the one corresponding to the second impedance function.

[0167] Next, perform the operation of step S40 to determine the input conversion time corresponding to the receiver model using the driver output voltage waveform and the receiver input voltage waveform, and further determine the delay calculation result.

[0168] Referring to Figure 4 , Figure 4 is a schematic diagram of the driver output voltage waveform in this application.

[0169] As shown in Figure 4 , each time the driver output voltage waveform is solved, a corresponding waveform graph is obtained. Taking the fourth-order solving as an example, the time range is 0ns-1ns and the voltage range is 0vdd-1vdd. The waveform corresponding to the first solving is iter1, the waveform corresponding to the second solving is iter2, the waveform corresponding to the third solving is iter3, and the waveform corresponding to the fourth solving is iter4.

[0170] Next, perform the operation process of step S30 to determine the receiver input voltage waveform corresponding to the receiver model using the preset delay voltage threshold and the transfer function with the driver output voltage waveform as input.

[0171] Step S30 can include the following operations:

[0172] The third zero point and the fourth zero point of the first transfer function or the second transfer function are obtained by using the driver output voltage waveform as input.

[0173] Wherein, because the driver output voltage waveform is used as input, the receiver input voltage waveform is solved by using the first transfer function and the second transfer function through recursive convolution, and the switching point of the first transfer function and the second transfer function is the delay voltage threshold 0.5vdd, at this time, the time value of each point of the receiver input voltage waveform corresponds to the point of the driver output voltage waveform one by one, therefore, the third zero point corresponds to the first zero point, and the fourth zero point corresponds to the second zero point.

[0174] Based on the preset step, the third zero point, the fourth zero point, the point information corresponding to the driver output voltage waveform, and the order of the reduced-order model, the receiver input voltage waveform is determined through recursive convolution.

[0175] Specifically, the potential information corresponding to the delay voltage threshold and the conversion voltage threshold is solved by using the iteration method to obtain the complete receiver input voltage waveform.

[0176] The calculation process can use the calculation process of the output voltage, as follows:

[0177]

[0178] Wherein, v out is the output voltage, k m is the first zero point of the impedance function, that is, the third zero point of the transfer function; p m is the second zero point of the impedance function, that is, the fourth zero point of the transfer function; t step is a preset step, which can also be a starting step; i out is the current; q is the order of the reduced-order model; v prev is the output voltage of the previous time step.

[0179] Step S40 can include the following operation process:

[0180] The delay voltage threshold, the first conversion voltage threshold, and the second conversion voltage threshold are obtained, and the reference time corresponding to the current curve in the current curve set is obtained.

[0181] Wherein, when solving the driver output voltage waveform and the receiver input voltage waveform, the delay voltage threshold and the conversion voltage threshold can be obtained at the same time, and the conversion voltage threshold includes the first conversion voltage threshold and the second conversion voltage threshold; the reference time is the reference time corresponding to the current curve in the current curve set of the composite current source model.

[0182] In some embodiments, the delay voltage threshold can be 0.5vdd, the first transition voltage threshold can be 0.3vdd, and the second transition voltage threshold can be 0.7vdd.

[0183] The third time corresponding to the delay voltage threshold and the driver output voltage waveform is used to determine the cell delay based on the third time and the reference time.

[0184] The third time is the time corresponding to the delay voltage threshold in the driver output voltage waveform.

[0185] Specifically, the time corresponding to the delay voltage threshold in the driver output voltage waveform is used as the third time, and the difference between the third time and the reference time is used as the cell delay.

[0186] The delay is calculated as follows:

[0187] = 05-.

[0188] The 05 is the third time, the is the reference time, and the is the cell delay.

[0189] Next, the fourth time corresponding to the first transition voltage threshold and the driver output voltage waveform is determined, and the fifth time corresponding to the second transition voltage threshold and the driver output voltage waveform is determined, and then the cell output transition time is determined based on the fourth time and the fifth time.

[0190] The fourth time is the time corresponding to the first transition voltage threshold in the driver output voltage waveform, and the fifth time is the time corresponding to the second transition voltage threshold in the driver output voltage waveform.

[0191] Specifically, the time corresponding to the first transition voltage threshold in the driver output voltage waveform is used as the fourth time, and the time corresponding to the second transition voltage threshold in the driver output voltage waveform is used as the fifth time, and then the difference between the fourth time and the fifth time is used as the cell output transition time.

[0192] The cell output transition time is calculated as follows:

[0193] - = 07-03.

[0194] The 07 is the fourth time, the 03 is the fifth time, and the is the cell output transition time.

[0195] Next, the interconnect line delay is determined based on the third time and the sixth time corresponding to the delay voltage threshold and the receiver input voltage waveform.

[0196] The sixth time is the time corresponding to the delay voltage threshold in the receiver input voltage waveform.

[0197] Specifically, the corresponding time in the receiver input voltage waveform is found by using the delay voltage threshold as the sixth time, and the difference between the third time and the sixth time is taken as the interconnection line delay.

[0198] The interconnection line delay is calculated as follows:

[0199] = 05-05.

[0200] Wherein, 05 is the sixth time, and 05 is the interconnection line delay.

[0201] Then, the seventh time corresponding to the receiver input voltage waveform and the second conversion voltage threshold, and the eighth time corresponding to the receiver input voltage waveform and the first conversion voltage threshold, are used to determine the lower unit input conversion time.

[0202] Wherein, the seventh time is the time corresponding to the second conversion voltage threshold in the receiver input voltage waveform, and the eighth time is the time corresponding to the first conversion voltage threshold in the receiver input voltage waveform.

[0203] Specifically, the corresponding time in the receiver input voltage waveform is found by using the second conversion voltage threshold as the seventh time, and the corresponding time in the receiver input voltage waveform is found by using the first conversion voltage threshold as the eighth time, and the difference between the seventh time and the eighth time is taken as the lower unit input conversion time.

[0204] The lower unit input conversion time is calculated as follows:

[0205] - = 07-03.

[0206] Wherein, 07 is the seventh time, 03 is the eighth time, and - is the lower unit input conversion time.

[0207] Further, the absolute change and the relative change of the input conversion time corresponding to the current iteration and the last iteration can also be compared; and then it is judged whether the lower unit output conversion time converges according to the absolute change and the relative change; if it converges, the delay calculation is ended; if it does not converge, the preset output load interval is updated by using the input conversion time of the current iteration, and then the driver output waveform is recalculated.

[0208] Specifically, when the absolute change is less than the first change threshold and / or the relative change is less than the second change threshold, it is considered to converge, and the delay calculation is ended.

[0209] When the absolute change is greater than the first change threshold and / or the relative change is greater than the second change threshold, it is considered that there is no convergence, the preset output load interval is updated, and the driver output waveform is recalculated; also, according to the updated input conversion time in the current iteration, the receiver load values, such as the first receiver load value 1 and the second receiver load value 2, are found in the receiver model in the composite current source model, and the reduced-order model of the interconnection line is updated; and the effective capacitance corresponding to the voltage change value of the driver output voltage is calculated in combination with the Pi model, to serve as the starting capacitance for the next iteration.

[0210] In this embodiment, the transient analysis is combined with the composite current source model (driver model and receiver model) to determine the corresponding driver output voltage waveform, i.e., the corresponding receiver input voltage waveform, and then to analyze and accurately calculate the delay, which can effectively improve the accuracy of the delay calculation result.

[0211] Further, the present application also provides an electronic device.

[0212] Referring to Figure 5 , Figure 5 is a structural schematic diagram of an embodiment of the electronic device in the present application.

[0213] As Figure 5 shown, the electronic device 500 includes a memory 510 and a processor 520 coupled with the memory, the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the foregoing delay calculation method.

[0214] Further, the present application also provides a storage medium.

[0215] Referring to Figure 6 , Figure 6 is a structural schematic diagram of an embodiment of the storage medium in the present application.

[0216] As Figure 6 shown, the storage medium 600 has at least one program 610, and the at least one program is loaded and executed to implement the foregoing delay calculation method; wherein the storage medium is a computer readable storage medium.

[0217] In several embodiments provided by the present application, it should be understood that the disclosed system, apparatus and method can be implemented in other manners. For example, the apparatus embodiments described above are merely schematic. For example, the division of the modules or units is merely logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0218] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0219] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0220] The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0221] The above description is merely an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation made by using the content of the present application specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A method of delay computation, characterized by, The method comprises the following steps: constructing a reduced-order model of the interconnection line corresponding to the driver model and the receiver model, wherein the reduced-order model is provided with an impedance function corresponding to the driver model and a transfer function corresponding to the driver model and the receiver model, the transfer function is a frequency domain matrix transfer function obtained by Laplace transform of a circuit equation with driver output voltage and receiver input voltage as input and output, and the impedance function is a function obtained by Laplace transform of a circuit equation with driver output current and driver output voltage as input and output; determining a driver output voltage waveform corresponding to the driver model by using a preset step size and the impedance function; determining a receiver input voltage waveform corresponding to the receiver model by using a preset delay voltage threshold and the transfer function with the driver output voltage waveform as input; determining an input conversion time corresponding to the receiver model and then determining a delay calculation result by using the driver output voltage waveform and the receiver input voltage waveform.

2. The method of claim 1, wherein the step of constructing a reduced-order model of the interconnection line corresponding to the driver model and the receiver model comprises: determining the driver model and the receiver model according to timing information provided by a preset first file; establishing the reduced-order model of the interconnection line according to parasitic parameter information provided by a preset second file, the driver model and the receiver model.

3. The method of claim 2, wherein the step of establishing the reduced-order model of the interconnection line according to parasitic parameter information provided by a preset second file, the driver model and the receiver model comprises: establishing first and second circuit equations corresponding to driver output current and driver output voltage according to interconnection line information provided by the preset second file, and establishing third and fourth circuit equations corresponding to driver output voltage and receiver input voltage; determining the impedance function by performing Laplace transform on the first and second circuit equations, and determining the transfer function by performing Laplace transform on the third and fourth circuit equations; composing the reduced-order model with the transfer function and the impedance function.

4. The method of claim 1, wherein the impedance function comprises a first impedance function and a second impedance function, and the step of determining a driver output voltage waveform corresponding to the driver model by using a preset step size and the impedance function comprises: determining a current curve and a corresponding voltage curve corresponding to each load by using a preset output load interval, thereby establishing a current curve set and a voltage curve set of driver output; determining an interpolation coefficient and a corresponding starting time according to a preset starting capacitance, and saving an output current waveform starting point of the current curve set and an output voltage waveform starting point of the voltage curve set corresponding to the interpolation coefficient and the starting time. ​ ​ ​ ​ determining a current voltage by using a preset voltage variation value and a starting voltage, and determining a current time and a corresponding voltage variation rate by using the current voltage and the interpolation coefficient, and determining a current current by using the current time; adding a preset step length to the current time, and determining an output voltage by using a recursive convolution method through the output current waveform and the first impedance function or the second impedance function, and further determining the driver output voltage waveform corresponding to the driver model.

5. The method of claim 4, wherein the determining the current current by using the current time comprises: determining a first time and a second time corresponding to the current voltage by using a first voltage curve and a second voltage curve corresponding to two endpoints of an output load interval, and determining a first current corresponding to the first time and a second current corresponding to the second time by using a first current curve and a second current curve corresponding to the two endpoints of the output load interval; further determining a time difference ratio of a first time difference between the current time and the first time and a second time difference between the second time and the first time, and determining a current difference value of the second current and the first current, and determining the current current by using a product of the time difference ratio and the current difference value and the first current, and saving the current voltage and the current current into the corresponding output voltage waveform and output current waveform.

6. The method of claim 4, wherein the determining the output voltage by using the recursive convolution method comprises: obtaining a first zero pole and a second zero pole of the first impedance function or the second impedance function, and obtaining an output voltage of a previous time step length; determining the output voltage by using a recursive convolution method based on the preset step length, the first zero pole, the second zero pole, a current current corresponding to the output current waveform, and an order of the reduced order model. further comprising: determining a size relationship between the current time and a first time and a second time corresponding to the current voltage; 7. The method of claim 5, wherein, if the current time is between the first time and the second time, determining the current current by using the current time; if the current time is outside the first time and the second time, adjusting two endpoints of the output load interval so that an adjusted current time is between the first time and the second time, and further determining the current current by using the adjusted current time. further comprising: performing numerical detection on the current voltage, the current current, and the voltage variation rate; 8. The method of claim 5, wherein, if the numerical value is normal, calculating a variation rate difference value of a voltage variation rate corresponding to the current step length and a voltage variation rate corresponding to a previous step length; calculating a local truncation error by using the variation rate difference value, and further adjusting the preset step length by using a first relationship between the local truncation error and a preset error tolerance and a size of the voltage variation rate; if a numerical abnormality occurs, marking a solution of the current step length as invalid, and performing a rollback process. further comprising: performing a time delay voltage threshold value on the current voltage.

9. The method of claim 5, wherein, ​ ​ switching the first impedance function or the second impedance function to the second impedance function or the first impedance function when the current voltage of the current step is less than the delay voltage threshold and the current voltage of the current step is greater than the delay voltage threshold; if the delay voltage threshold is outside the current voltage of the previous step and the current voltage of the current step, judging the current voltage by using an end voltage threshold, wherein the delay voltage threshold and the end voltage threshold are in a multiple relationship; renewing the solving of the output voltage when the current voltage is less than the end voltage threshold.

10. The method of claim 1, wherein the transfer function comprises a first transfer function and a second transfer function; and the determining of the receiver input voltage waveform corresponding to the receiver model comprises: obtaining a third zero pole and a fourth zero pole of the first transfer function or the second transfer function by using the driver output voltage waveform as input; and determining the receiver input voltage waveform by using a recursive convolution method based on a preset step, the third zero pole, the fourth zero pole, point information corresponding to the driver output voltage waveform, and an order of the reduced order model.

11. The method of claim 1, wherein the determining of the input conversion time corresponding to the receiver model based on the driver output voltage waveform and the receiver input voltage waveform, and the determining of the delay calculation result comprises: obtaining a delay voltage threshold, a first conversion voltage threshold, and a second conversion voltage threshold, and obtaining a reference time corresponding to a current curve in a current curve set; determining a unit delay by using a third time corresponding to the driver output voltage waveform and the delay voltage threshold, and determining the input conversion time by using the third time and the reference time; determining a fourth time by using the driver output voltage waveform and the first conversion voltage threshold, and determining a fifth time by using the driver output voltage waveform and the second conversion voltage threshold, and determining the output conversion time by using the fourth time and the fifth time; determining an interconnection line delay by using the third time and a sixth time corresponding to the receiver input voltage waveform and the delay voltage threshold; and determining the input conversion time of a lower unit corresponding to the receiver model by using a seventh time corresponding to the receiver input voltage waveform and the second conversion voltage threshold, and an eighth time corresponding to the receiver input voltage waveform and the first conversion voltage threshold. The method further comprises: comparing an absolute change and a relative change of the input conversion time corresponding to the current iteration and the previous iteration; and determining whether the output conversion time converges based on the absolute change and the relative change; and if the output conversion time does not converge, updating a preset output load interval by using the input conversion time of the current iteration, and recalculating the driver output waveform. ​ ​ ​ ​ ​ ​ 12. The method of claim 11, wherein, ​ ​ ​ ​ 13. An electronic device, comprising: The electronic device includes a memory and a processor coupled to the memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to implement the method of any one of claims 1-12.

14. A storage medium, characterized by The storage medium has at least one program, the at least one program being loaded and executed by the processor to implement the method of any one of claims 1-12.

Images