A method for preparing a quantum state and related apparatus

Abstract

The application discloses a quantum state preparation method and a related device, and the method comprises the following steps: determining each partial component of a target quantum state to be prepared, each partial component comprising one ground state of the target quantum state and an amplitude of the ground state; constructing a plurality of target matrices based on the amplitudes of the partial components, and performing SVD decomposition on the target matrices to obtain a unitary matrix, determining a disentanglement quantum logic gate based on the unitary matrix, and applying a plurality of disentanglement quantum logic gates on a quantum bit with an initial state being the target quantum state to obtain a disentanglement quantum circuit; inversely deriving the target quantum circuit from the disentanglement quantum circuit, wherein the target quantum circuit has a target quantum logic gate, and the target quantum logic gate is determined based on a conjugate transpose matrix of the unitary matrix. (logn) The application discloses a quantum state preparation method and a related device, and the method comprises the following steps: determining each partial component of a target quantum state to be prepared, each partial component comprising one ground state of the target quantum state and an amplitude of the ground state; constructing a plurality of target matrices based on the amplitudes of the partial components, and performing SVD decomposition on the target matrices to obtain a unitary matrix, determining a disentanglement quantum logic gate based on the unitary matrix, and applying a plurality of disentanglement quantum logic gates on a quantum bit with an initial state being the target quantum state to obtain a disentanglement quantum circuit; inversely deriving the target quantum circuit from the disentanglement quantum circuit, wherein the target quantum circuit has a target quantum logic gate, and the target quantum logic gate is determined based on a conjugate transpose matrix of the unitary matrix. (logn) The application discloses a quantum state preparation method and a related device, and the method comprises the following steps: determining each partial component of a target quantum state to be prepared, each partial component comprising one ground state of the target quantum state and an amplitude of the ground state; constructing a plurality of target matrices based on the amplitudes of the partial components, and performing SVD decomposition on the target matrices to obtain a unitary matrix, determining a disentanglement quantum logic gate based on the unitary matrix, and applying a plurality of disentanglement quantum logic gates on a quantum bit with an initial state being the target quantum state to obtain a disentanglement quantum circuit

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum computing, and in particular to a quantum state preparation method and related device. BACKGROUND

[0002] Quantum computing is a new computing mode that regulates quantum information units to perform calculations according to the laws of quantum mechanics. Unlike classical computing, quantum computing follows the laws of quantum mechanics, which is a new computing mode that can break through the bottleneck of classical computing power. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have the ability to process mathematical problems more efficiently than ordinary computers, for example, they can accelerate the time to break RSA keys from hundreds of years to hours, so they have become a key technology under research.

[0003] In quantum computing, quantum state encoding is crucial, as it is the key step in converting classical information into quantum states, enabling quantum computers to process and manipulate this information and thus take advantage of the performance of quantum computing. Common quantum state encoding methods include ground state encoding, amplitude encoding, angle encoding, and MPS (Matrix Product State) encoding. Among them, MPS encoding is an effective method for representing quantum states, which can effectively prepare and represent quantum states by decomposing quantum states in the form of known wave functions into a series of local tensor products. MPS encoding can effectively prepare and represent quantum states, especially those with local entanglement properties.

[0004] Therefore, if a more general quantum state amplitude preparation can be achieved based on the encoding method of matrix product state, it undoubtedly has great research prospects and practical value. SUMMARY

[0005] The purpose of the present application is to provide a quantum state preparation method and related device to solve the technical problems in the prior art, which can more efficiently prepare the amplitude of the quantum state.

[0006] In a first aspect, the present application provides a quantum state preparation method, comprising:

[0007] determining each partial component of a target quantum state to be prepared, each partial component comprising a ground state of the target quantum state and an amplitude of the ground state;

[0008] A plurality of target matrices are constructed based on the amplitudes of the partial components, and SVD decomposition is performed on the target matrices to obtain unitary matrices, and the unitary matrices are used to determine disentangling quantum logic gates, and the disentangling quantum logic gates are applied to quantum bits in an initial state of a target quantum state to obtain a disentangling quantum circuit, wherein the relationship between the disentangling quantum logic gates and the quantum bits in a later layer of action timing is determined by the relationship between the disentangling quantum logic gates and the quantum bits in a previous layer of action timing.

[0009] An inverse circuit of the disentangling quantum circuit is determined as a target quantum circuit.

[0010] The target quantum circuit is run to prepare the target quantum state.

[0011] The method described above, wherein preferably the relationship between the target quantum logic gates and the quantum bits in a previous layer of action timing is determined by the relationship between the target quantum logic gates and the quantum bits in a later layer of action timing, includes:

[0012] In each layer of action timing, the quantum bits are re-grouped to form a plurality of quantum bit pairs, each quantum bit pair including a first bit quantum bit and a second bit quantum bit, the first bit quantum bit being lower than the second bit quantum bit, and each quantum bit pair being acted on by a target quantum logic gate in each layer of action timing.

[0013] In the last layer of action timing, the quantum bits are sequentially grouped from the lowest bit to the highest bit, and each two adjacent quantum bits form a quantum bit pair.

[0014] In other layers of action timing, a plurality of quantum bits are re-grouped according to the relationship between the target quantum logic gates and the quantum bits in a later layer of action timing to form a quantum bit set, the quantum bits in the quantum bit set being from the first bit quantum bit or the second bit quantum bit in each quantum bit pair, and the quantum bits in the quantum bit set being sequentially grouped from the lowest bit to the highest bit to form the quantum bit pairs.

[0015] The method described above, wherein preferably the plurality of quantum bits are re-grouped according to the relationship between the target quantum logic gates and the quantum bits in a later layer of action timing to form a quantum bit set, includes:

[0016] The set of qubits includes a first set of qubits and a second set of qubits, the qubits in the first set of qubits are from the first bit qubit in each subsequent qubit pair, the qubits in the first set of qubits are sequentially grouped from low bit to high bit to form the qubit pair; the qubits in the second set of qubits are from the second bit qubit in each subsequent qubit pair, the qubits in the second set of qubits are sequentially grouped from low bit to high bit to form the qubit pair.

[0017] The method as described above, preferably, the constructing of the plurality of target matrices based on the amplitudes of the partial components comprises:

[0018] Determining the number of qubits for preparing the target quantum state based on the number of basis states of the target quantum state, the number of qubits n satisfies 2 n-1 N≤2 n , N is the number of basis states of the target quantum state.

[0019] The method as described above, preferably, the constructing of the plurality of target matrices based on the amplitudes of the partial components comprises: for each of the action time sequences, rearranging the amplitudes of the plurality of partial components into a 2 2 ×2 n-2 matrix based on the number of target qubits of the target quantum logic gate action, to obtain the plurality of target matrices.

[0020] The method as described above, preferably, the rearranging of the amplitudes of the plurality of partial components into a 2 2 ×2 n-2 matrix based on the number of target qubits of the target quantum logic gate action comprises:

[0021] Rearranging the amplitudes of a plurality of basis states corresponding to positions of the qubit pair as | 00>, | 01>, | 10>, | 11) in sequence as the 1st, 2nd, 3rd, and 4th rows of a matrix, to obtain the 2 2 ×2 n-2 matrix; wherein the 2 n-2 amplitudes in each row are arranged based on the binary representation order of the corresponding basis state.

[0022] The method as described above, preferably, the SVD decomposition of the target matrix to obtain a unitary matrix comprises:

[0023] For each of the target matrices, the target matrix is subjected to SVD decomposition to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and the left singular vector matrix is taken as the unitary matrix.

[0024] In a second aspect, the present application provides a quantum state preparation device, the device comprising:

[0025] An acquisition module is configured to determine each partial component of a target quantum state to be prepared, wherein each partial component comprises one ground state of the target quantum state and an amplitude of the ground state.

[0026] A disentanglement quantum circuit construction module is configured to construct a disentanglement quantum circuit, obtain a plurality of target matrices based on the amplitudes of the partial components, and perform SVD decomposition on the target matrices to obtain a unitary matrix, determine a disentanglement quantum logic gate based on the unitary matrix, and apply a plurality of disentanglement quantum logic gates to quantum bits with an initial state of the target quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gate and the quantum bit in a later layer action timing sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in a previous layer action timing sequence.

[0027] A target quantum circuit construction module is configured to determine that the inverse circuit of the disentanglement quantum circuit is a target quantum circuit.

[0028] A running module is configured to run the target quantum circuit to prepare the target quantum state.

[0029] In a third aspect, the present application provides a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to implement the method described above when running.

[0030] In a fourth aspect, the present application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the method described above.

[0031] Compared with the prior art, the quantum state preparation method provided by the present application only needs O(1ogn) layers of quantum circuit depth, compresses the running time of the quantum computer by an exponential level, and can more efficiently prepare the amplitudes of the quantum states. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a network block diagram of a quantum circuit construction system provided by an embodiment of the present application;

[0033] Figure 2 is a flowchart of a quantum state preparation method provided by an embodiment of the present application;

[0034] Figure 3 A structural schematic diagram of a target quantum circuit provided for an embodiment of the present application is shown in FIG. 6.

[0035] Figure 4 A structural schematic diagram of a target quantum circuit provided for an embodiment of the present application is shown in FIG. 6.

[0036] Figure 5 A flowchart of an SVD decomposition method provided for an embodiment of the present application is shown in FIG. 7.

[0037] Figure 6 A structural schematic diagram of a quantum state preparation device provided for an embodiment of the present application is shown in FIG. 8. DETAILED DESCRIPTION

[0038] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be explained as a limitation of the present application.

[0039] Structure of quantum circuit construction system

[0040] Figure 1 A network block diagram of a quantum circuit construction system provided for an embodiment of the present application is shown in FIG. 1. The quantum circuit construction system can include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and can also include additional storage, classical processors, quantum processors and other devices not shown.

[0041] The network 110 is a medium for providing communication links between various devices and computers connected together in the quantum circuit construction system, including but not limited to the Internet, an intranet, a local area network, a mobile communication network and combinations thereof, and the connection mode can adopt wired, wireless communication links or optical fiber cables, etc.

[0042] The server 120 and the client 140 are conventional data processing systems, which can contain data and have application programs or software tools for performing conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smartphone, a tablet, a notebook computer, a smart wearable device, etc. The storage unit 150 can include a database 151, which can be configured to store quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0043] The classical processing system 160 (quantum processing system 170) can include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data), which can be a boot file, an operating system image, and an application program 162 (application program 173), which can be used to implement a quantum algorithm compiled by a quantum circuit construction method according to an embodiment of the present application.

[0044] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed thereby can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0045] It should be noted that a real quantum computer is a hybrid structure, which includes at least two parts: a classical processing system 160 responsible for performing classical computation and control; and a quantum processing system 170 responsible for running a quantum program to implement quantum computation. Figure 1

[0046] The classical processing system 160 and the quantum processing system 170 described above can be integrated in one device or distributed in two different devices. For example, a first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, and storage and network services required by quantum application programs are also provided. A user develops a quantum application program through the quantum application development tools and services thereon, and sends a quantum program to a second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by a quantum computer control system, and the quantum processor 170 implements a quantum algorithm corresponding to the quantum program according to the instructions.

[0047] In a classical processing system 160 based on a silicon chip, the unit of the classical processor 161 is a CMOS tube, and such a computing unit is not limited by time and coherence, i.e., such a computing unit is not limited by the length of use and is available at any time. In addition, in a silicon chip, the number of such computing units is also sufficient, and the number of computing units in a classical processor is currently in the thousands. The number of computing units is sufficient and the computing logic of the CMOS tube is fixed, for example: AND logic. When operating with CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the effect of operation.

[0048] ​Unlike the logical units in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. It is a key problem of quantum computing to fully use the quantum bit within the available use time of the quantum bit. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of the quantum computer, and each quantum bit realizes a computing function through a logically configured function, and given the limited number of quantum bits and the diversified logical functions in the field of quantum computing, such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, and the like. In quantum computing, the operation effect needs to be achieved by combining the limited quantum bits with the diversified logical functions.

[0049] Based on these differences, the design of the logical function acting on the quantum bit (including the design of whether to use the quantum bit and the design of the use efficiency of each quantum bit) is the key to improving the operation performance of the quantum computer, and special design is required. The above design for quantum bits is a technical problem that ordinary computing devices do not need to consider and face.

[0050]

Quantum state preparation method

[0051] In the field of quantum computing, amplitude encoding is a method of encoding classical data into quantum state amplitudes. In amplitude encoding, a given n quantum bits can represent a number of quantum states (i.e., the number of states that can be amplitude encoded) of 2 n For n quantum bits, all possible quantum states they can represent is a 2 n -dimensional complex vector space. Specifically, the number of all basis states that n quantum bits can represent is 2 n , which can be written as |0>, |1>, |2>,..., |2 n -1> or in binary form, such as the basis state of 6 quantum bits represented as |000000>, |000001),..., |111111>, etc., which is not specifically limited here.

[0052] First, define the quantum state amplitude on n quantum bits First, reorganize the amplitude into four rows, which is to correspond to the four-order unitary matrix of the double quantum gate. The matrix composed of four rows is as follows:

[0053]

[0054] SVD decomposition is performed on the 4x2 n-2 matrix, and SVD (Singular Value Decomposition) is a widely used matrix decomposition technique in numerical linear algebra, which reveals many important properties of the original matrix by decomposing the matrix into the product of three matrices.

[0055] When a target matrix A is subjected to SVD decomposition, left singular vector matrix U, singular value matrix S and right singular vector matrix V can be obtained. The left singular vector matrix U is an orthogonal matrix, and its column vectors are the left singular vectors of the target matrix A, representing the direction after the target matrix A acts on the standard orthogonal vectors. In an embodiment, the left singular vector matrix U can be used as the unitary matrix, so that the corresponding unitary matrix of the disentangling quantum logic gate can evolve the target quantum state | ψ> into | 0> n .

[0056] By performing SVD decomposition on the aforementioned fourth-order unitary matrix, the unitary matrix U 12 and S can be obtained. The SVD decomposition has a low rank property, that is, the last two diagonal elements of the diagonal matrix S can be negligible compared to the first two diagonal elements. At this time, the last two singular values are truncated, and at this time, U1 acts on the quantum circuit, and the remaining quantum state SV can be regarded as a rearrangement of the quantum state as a 4x2 n-2 matrix. Due to the low rank property of S, the last two rows can be completely regarded as 0, and the information is concentrated in the first two rows. The first two rows only exist in | 00> and | 01>, which means that the first quantum bit can be directly regarded as | 0> state without considering it.

[0057] The above operation uses the first two quantum bits as indices to rearrange the quantum state amplitude. For other quantum bits, the same method can also be used to rearrange the quantum state, for example, the 3rd and 4th bits as subscripts, and the quantum state is rearranged as |··00…>, |··01…>, |··10…>, and |··11…>. Then, the unitary matrix U 34 can be obtained by performing SVD decomposition on the rearranged amplitude, and at this time, the third quantum bit can be approximated as |0> state.

[0058] The embodiments provided by the present application assume that the initial state of a certain disentangling quantum circuit is the target quantum state Therefore, by unentanglement and approximate truncation of the target quantum state |ψ>, we can obtain the quantum circuit that evolves the target quantum state |ψ> to the |0> state. The above steps are classical processing procedures that can be implemented using a quantum simulator.

[0059] Furthermore, the inverse circuit of the above-mentioned unentangled quantum circuit can be constructed to obtain the target quantum circuit. The target quantum circuit is then run and applied to a qubit with an initial state of |0>, thereby achieving the approximate preparation of the target quantum state |ψ> on a real quantum chip.

[0060] In one feasible implementation, refer to Figure 2 As shown, the present invention provides a method for preparing quantum states, comprising the following steps:

[0061] Step S101: Determine the components of the target quantum state to be prepared. Each component includes a ground state of the target quantum state and the amplitude of the ground state.

[0062] The target quantum state to be prepared is For example, it includes 2 n Each component comprises a ground state |x> of the target quantum state |ψ> and the amplitude α corresponding to that ground state. x That is, the number N of the ground states of the target quantum state |ψ> satisfies N=2 n The sum of the squares of the amplitudes of each ground state is 1, i.e.

[0063] Step S102: Based on the amplitude of some components, multiple target matrices are constructed and the target matrices are decomposed by SVD to obtain unitary matrices. Based on the unitary matrices, the unentangled quantum logic gates are determined. The multiple unentangled quantum logic gates are applied to the qubits whose initial state is the target quantum state to obtain unentangled quantum circuits. The interaction relationship between the unentangled quantum logic gates and the qubits in the later layer interaction sequence is determined by the interaction relationship between the unentangled quantum logic gates and the qubits in the previous layer interaction sequence.

[0064] Specifically, the deentanglement quantum logic gates are determined based on the unitary matrix obtained from the decomposition. Multiple deentanglement quantum logic gates are applied to qubits whose initial state is the target quantum state, resulting in a deentanglement quantum circuit. This deentanglement quantum circuit is used to evolve the target quantum state into |0> n state.

[0065] Specifically, based on the idea of ​​deentanglement, the amplitudes of the components determined in the above steps can be rearranged to construct multiple target matrices. Each target matrix contains the amplitude information of the target quantum state to be prepared, |ψ>. Then, for each target matrix, SVD decomposition can be performed to obtain its corresponding unitary matrix.

[0066] Since each target matrix in the embodiment includes part of the amplitude information of the target quantum state due to the target matrix being obtained based on the amplitude rearrangement of the ground state of the target quantum state, the entanglement of the target quantum state is not required to be strictly implemented in the order of the quantum bits from high to low, and thus the multiple quantum logic gates without shared quantum bits can be operated in parallel.

[0067] In the disentanglement quantum circuit, each disentanglement quantum logic gate acts on two preset quantum bits, which can be two quantum bits of adjacent positions or two quantum bits of spaced positions, and can be determined according to the setting of the circuit, which is not limited herein. Along the action time sequence, the multiple disentanglement quantum logic gates are distributed in multiple layers, each layer of disentanglement quantum logic gates includes at least one disentanglement quantum logic gate, and the disentanglement quantum logic gates in the same layer of disentanglement quantum logic gates act on the same action time sequence.

[0068] In the disentanglement quantum circuit, the disentanglement quantum logic gate plays a role of disentangling two quantum bits. After the disentanglement quantum circuit acts on the two quantum bits, the disentanglement of the two quantum bits is completed. After each quantum bit of the target quantum state passes through the action time sequence of each layer of disentanglement quantum logic gates, part of the quantum bits are disentangled with each other, until after passing through all the action time sequences, the target quantum state is approximately |0> n .

[0069] Further, in the disentanglement quantum circuit, the action relationship between the disentanglement quantum logic gate in the next layer of action time sequence and the quantum bit is determined by the action relationship between the disentanglement quantum logic gate in the previous layer of action time sequence and the quantum bit. The parameters of the unitary matrix of the disentanglement quantum logic gate in the first layer of action time sequence and the quantum bits acted on by the disentanglement quantum logic gate are obtained by referring to the amplitude of the target quantum state. After passing through the first layer of action time sequence, part of the quantum bits complete disentanglement and change the target quantum state. The parameters of the unitary matrix of the disentanglement quantum logic gate in the second layer of action time sequence and the quantum bits acted on by the disentanglement quantum logic gate are obtained by referring to the amplitude of the changed target quantum state. By analogy, the parameters of the unitary matrix of the disentanglement quantum logic gate in all layers of action time sequence and the quantum bits acted on by the disentanglement quantum logic gate are obtained.

[0070] Step S103: inversely deriving the target quantum circuit from the disentanglement quantum circuit, the target quantum circuit having a target quantum logic gate, the target quantum logic gate being determined based on a conjugate transpose matrix of a unitary matrix, wherein the action relationship between the target quantum logic gate in the previous layer of action time sequence and the quantum bit is determined by the action relationship between the target quantum logic gate in the next layer of action time sequence and the quantum bit.

[0071] In this context, the inverse of the unentangled quantum circuit is the target quantum circuit. The number of target quantum logic gates in the target quantum circuit is the same as the number of unentangled quantum logic gates in the unentangled quantum circuit. However, the execution timing of multiple target quantum logic gates is the reverse of that of multiple unentangled quantum logic gates. The unentangled quantum logic gates of the unentangled quantum circuit are determined based on the unitary matrix obtained from the decomposition, while the target quantum logic gates of the target quantum circuit are determined based on the conjugate transpose of the unitary matrix. Multiple target quantum logic gates acting on qubits with an initial state of |0>n can evolve to obtain the target quantum state.

[0072] The target quantum circuit is obtained by reverse engineering the deentangled quantum circuit. In the target quantum circuit, each target quantum logic gate acts on two preset qubits. These two qubits can be two adjacent qubits or two qubits at intervals, depending on the circuit settings. No limitation is made here. Along the action sequence, multiple target quantum logic gates are distributed in multiple layers. Each layer of target quantum logic gates includes at least one target quantum logic gate. Target quantum logic gates in the same layer of target quantum logic gates all act on the same action sequence.

[0073] In the target quantum circuit, the target quantum logic gate functions to create a predetermined entangled state between two qubits, with the initial state being |0> n After each quantum bit passes through a target quantum logic gate, some of the quantum bits become entangled with each other until the target quantum state is obtained after all the interaction sequences.

[0074] Furthermore, in the target quantum circuit, the interaction relationship between the target quantum logic gate and the qubit in the previous layer's interaction timing is determined by the interaction relationship between the target quantum logic gate and the qubit in the next layer's interaction timing. Referring to the aforementioned construction of the unentangled quantum circuit, the execution timing of multiple target quantum logic gates is the opposite of that of multiple unentangled quantum logic gates. The target quantum logic gate is determined by the conjugate transpose of the unitary matrix of the unentangled quantum logic at the corresponding position.

[0075] Step S104: Run the target quantum circuit to prepare the target quantum state. In the specific preparation process, first obtain the target quantum circuit, and then run the quantum operation corresponding to the target quantum circuit on the quantum chip to prepare the target quantum state.

[0076] Based on the quantum state preparation method provided in the above embodiment, without determining the wave function of the target quantum state to be prepared in advance, the target quantum circuit is constructed based on the idea of disentanglement, first, the partial components of the target quantum state to be prepared are determined, each partial component includes a ground state of the target quantum state and the amplitude of the ground state. Further, a plurality of target matrices can be constructed based on the amplitudes of the partial components, and the target matrices are subjected to SVD decomposition to obtain unitary matrices (i.e. disentanglement quantum logic gates), and the disentanglement quantum logic gates corresponding to the plurality of unitary matrices obtained by decomposition are collectively acted on to evolve the target quantum state into | 0> n state, by constructing the conjugate transpose matrix of the plurality of unitary matrices (target quantum logic gate), and acting on the quantum bit with the initial state |0>n, the target quantum circuit can be obtained, running the target quantum circuit to prepare the target quantum state, the depth of the target quantum circuit only needs O(log n) layers, which can compress the running time of the quantum computer exponentially, and can more efficiently prepare the amplitude of the quantum state.

[0077] Further, in each layer of the disentanglement quantum circuit, the specific method for determining the action relationship between the disentanglement quantum logic gate and the quantum bit in the next layer of the action time sequence from the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer of the action time sequence is:

[0078] Each quantum bit in the disentanglement quantum circuit needs to be uniquely identified, so each quantum bit is assigned a unique number to distinguish different quantum bits, in the embodiments provided by the present application, the quantum bits in the disentanglement quantum circuit are numbered from the lowest bit to the highest bit, for example, as shown in Figure 3 , the disentanglement quantum circuit has 8 quantum bits, and the numbers of the 8 quantum bits are arranged in sequence from 1 to 8, the first quantum bit is located at the top of the diagram, which is the lowest bit quantum bit, and the eighth quantum bit is located at the bottom of the diagram, which is the highest bit quantum bit.

[0079] In each layer of the action time sequence, the quantum bits are re-grouped to form a plurality of quantum bit pairs, the quantum bits included in different quantum bit pairs are different, each quantum bit pair includes a first bit quantum bit and a second bit quantum bit, the first bit quantum bit is lower than the second bit quantum bit, and each quantum bit pair is acted on by a disentanglement quantum logic gate in each layer of the action time sequence.

[0080] In the first layer of action timing, the qubits from the lowest bit to the highest bit are sequentially grouped, and every two adjacent qubits form a qubit pair. The qubits from the lowest bit to the highest bit are each subjected to a disentangling quantum logic gate, so as to disentangle the two qubits. After the disentangling quantum logic gate acts on the two qubits, the disentanglement of the two qubits is completed, and the first qubit or the second qubit is evolved into the | 0> state.

[0081] In other layers of action timing, a plurality of qubits are re-grouped according to the action relationship between the target quantum logic gate and the qubits in the previous layer of action timing to form a qubit set. The qubits in the qubit set come from the first qubit or the second qubit in the qubit pair in each previous layer of action timing which is not evolved into the | 0> state. The qubits in the qubit set are sequentially grouped from the low bit to the high bit to form a qubit pair.

[0082] After each layer of disentangling quantum logic gate, part of the qubits of the target quantum state are disentangled with each other, until after all the action timing, the initial approximate state | 0> is obtained. n

[0083] In a feasible implementation, referring to FIG. 1, an example of a disentangling quantum circuit with 8-bit qubits is described: Figure 3

[0084] In the first layer of action timing, every two adjacent qubits are grouped to form four qubit pairs, which are [1, 2], [3, 4], [5, 6] and [7, 8] respectively. Each qubit pair is subjected to a unitary matrix (disentangling quantum logic gate). The first qubit in the qubit pair is evolved into the approximate | 0> state, that is, the 1st, 3rd, 5th and 7th qubits are evolved into the approximate | 0> state after being acted upon.

[0085] After the first layer of action timing, the amplitude is approximately present on the 2nd, 4th, 6th and 8th qubits. At this time, in the second layer of action timing, the remaining qubits are re-grouped. This time, the qubit pairs are two, which are [2, 4] and [6, 8]. Each qubit pair is subjected to a unitary matrix (disentangling quantum logic gate). The first qubit in the qubit pair is evolved into the approximate | 0> state, that is, the 2nd and 6th qubits are evolved into the approximate | 0> state after being acted upon.

[0086] ​​After the second layer of action time sequence, the amplitude only exists on the 4th and 8th quantum bits, at this time, in the third layer of action time sequence, only need to act the fourth order unitary matrix on the 4th and 8th quantum bits, so that the quantum state on the 4th and 8th quantum bits can be completely collapsed into the |0> state.

[0087] For n quantum bits, first assume that it is the exponential power of 2, that is, n = 2 m , where m is a positive integer, in the first layer of action time sequence, the quantum bits are grouped, and the quantum bit pairs are: [1, 2], [3, 4], [5, 6]... [2 m -1,2 m ]。

[0088] The first quantum bit in the quantum bit pair is evolved into an approximate |0> state, so after the first layer of action time sequence, the remaining quantum bits with amplitude are the 2nd, 4th, and so on to the 2 m nd quantum bit, in the second layer of action time sequence, these remaining quantum bits are re-grouped to obtain the following quantum bit pairs: [2, 4], [6, 8]... [2 m -2,2 m ]。

[0089] This is done until the last layer, only two quantum bits are grouped, a total of m = 1 og n layers are needed.

[0090] When considering that the n quantum bits are not the exponential of 2, in the first layer of action time sequence, the highest bit quantum bit is not grouped, and in the second layer of action time sequence, the highest bit quantum bit is included in the grouping range.

[0091] Next, take 7 quantum bits as an example:

[0092] In the first layer of action time sequence, the quantum bit pairs are three: [1, 2], [3, 4], [5, 6], and the remaining 7th quantum bit is not grouped.

[0093] In the second layer of action time sequence, the 7th quantum bit is included in the grouping range, and the quantum bit pairs are two: [2, 4], [6, 7].

[0094] In the third layer of action time sequence, the quantum bit pair is [4, 7].

[0095] In the embodiment provided by the application, the specific method for determining the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action time sequence of the target quantum circuit from the action relationship between the target quantum logic gate and the quantum bit in the subsequent layer of action time sequence is:

[0096] Each qubit within the target quantum circuit needs to be uniquely identified; therefore, each qubit is assigned a unique number to distinguish different qubits. In the embodiments provided by this invention, the qubits within the target quantum circuit are numbered sequentially from the least significant bit to the most significant bit. For example, referring to... Figure 4 As shown, the target quantum circuit has 8 qubits, which are numbered sequentially from 1 to 8. Qubit 1 is located at the top of the diagram, which is also the lowest qubit, and qubit 8 is located at the bottom of the diagram, which is the highest qubit. This is the same as the numbering of the unentangled quantum circuit.

[0097] In each layer of the interaction sequence, the qubits are regrouped to form several qubit pairs. Different qubit pairs contain different qubits. Each qubit pair includes a first qubit and a second qubit. The first qubit is in a lower position than the second qubit. In each layer of the interaction sequence, each qubit pair is interacted with a target quantum logic gate.

[0098] In the final layer of the interaction sequence, the qubits from the least significant bit to the most significant bit are grouped sequentially, with each pair of adjacent qubits forming a qubit pair. In the final layer of the interaction sequence, each pair of adjacent qubits is interacted with a target quantum logic gate. Since the target quantum circuit is derived by reverse engineering from the deentangled quantum circuit, the qubit pairs interacted by the target quantum logic gate in the final layer of the interaction sequence are the same as the qubit pairs interacted by the deentangled quantum logic gate in the first layer of the interaction sequence of the deentangled quantum circuit.

[0099] In other layers of interaction, several qubits are regrouped according to the interaction relationship between the target quantum logic gate and the qubits in the next layer of interaction, forming a qubit set. Within each qubit set, the qubits are grouped sequentially from the least significant bit to the most significant bit, forming qubit pairs. This can be derived from deentangled quantum circuits. For example, in the penultimate layer of interaction, the qubit pair interacting with the target quantum logic gate is the same as the qubit pair interacting with the deentangled quantum logic gate in the second layer of interaction of the deentangled quantum circuit. This process is repeated to obtain the qubit pairs for all interaction times of the target quantum circuit.

[0100] After each layer of target quantum logic gate, some of the qubits in the initial state become entangled with each other until the target quantum state is obtained after all the interaction sequences.

[0101] In one feasible implementation, refer to Figure 4 As shown, an example of a target quantum circuit with 8 qubits will be used for illustration:

[0102] In the last layer of action timing, every two adjacent qubits are grouped to form four pairs of qubits, [1, 2], [3, 4], [5, 6] and [7, 8], and each pair of qubits is subjected to the conjugate transpose matrix of a unitary matrix (target quantum logic gate).

[0103] In the second last layer of action timing, the pairs of qubits are two, [2, 4] and [6, 8], and each pair of qubits is subjected to the conjugate transpose matrix of a unitary matrix (target quantum logic gate).

[0104] In the first layer of action timing, the target quantum logic gate is subjected to the 4th and 8th qubits.

[0105] For n qubits, it is assumed to be an exponential power of 2, that is, n = 2 m , where m is a positive integer, and in the last layer of action timing, the qubits are grouped, and the pairs of qubits are: [1, 2], [3, 4], [5, 6]......[2 m -1, 2 m ]。

[0106] The action timing is in the second last layer of action timing, and the qubits are re-grouped to obtain the following pairs of qubits: [2, 4], [6, 8]......[2 m -2, 2 m ]。

[0107] By analogy to the first layer of action timing, only two qubits are left for grouping, and a total of m = logn layers of pairing are required.

[0108] Through the quantum state preparation method provided by the above embodiment, the circuit depth only needs o(logn) layers, which can effectively compress the running time of the quantum computer and more efficiently perform amplitude preparation of the quantum state, and the method can accurately prepare a linear function.

[0109] Meanwhile, the application also provides an improved idea of the method, and the quantum state preparation method provided by the above embodiment does not fully utilize the parallel characteristics under the logarithmic number of layers, that is, there are remaining bits that are not working, and the application realizes more accurate preparation by continuously adding quantum logic gates that work in parallel.

[0110] Specifically, in the disentangling quantum circuit, in addition to the first layer of action timing, in other layers of action timing, a plurality of quantum bits are re-grouped according to the action relationship between the disentangling quantum logic gate and the quantum bit in the previous layer of action timing to form a quantum bit set, the quantum bit set includes a first quantum bit set and a second quantum bit set, the quantum bits in the first quantum bit set come from the first quantum bit in each previous quantum bit pair, and the quantum bits in the first quantum bit set are sequentially grouped from low bits to high bits to form quantum bit pairs; the quantum bits in the second quantum bit set come from the second quantum bit in each previous quantum bit pair, and the quantum bits in the second quantum bit set are sequentially grouped from low bits to high bits to form quantum bit pairs.

[0111] In an implementable embodiment, the disentangling quantum circuit with 8-bit quantum bits is taken as an example for illustration:

[0112] In the first layer of action timing, every two adjacent quantum bits are grouped to form four quantum bit pairs, namely [1, 2], [3, 4], [5, 6] and [7, 8], and each quantum bit pair is acted on by a unitary matrix (disentangling quantum logic gate).

[0113] After the first layer of action timing, in the second layer of action timing, the quantum bits are re-grouped again, and this time, the quantum bit pairs are also four, namely [2, 4], [6, 8], [1, 3] and [5, 7], and each quantum bit pair is acted on by a unitary matrix (disentangling quantum logic gate).

[0114] After the second layer of action timing, in the third layer of action timing, the quantum bits are re-grouped again, and this time, the quantum bit pairs are also four, namely [4, 8], [1, 5], [2, 6] and [3, 7], and each quantum bit pair is acted on by a unitary matrix (disentangling quantum logic gate).

[0115] For n quantum bits, it is assumed to be an exponential power of 2, that is, n = 2 m , where m is a positive integer, in the first layer of action timing, the quantum bits are grouped, and the quantum bit pairs are: [1, 2], [3, 4], [5, 6]... [2 m -1, 2 m ].

[0116] After the first layer of action timing, in the second layer of action timing, a plurality of quantum bits are re-grouped, the quantum bits in the first quantum bit set are 1, 3, 5... 2 m -3 and 2 m-1, the quantum bits in the first set of quantum bits are sequentially grouped from low to high, forming quantum bit pairs: [1,3], [5,6], [9,11]... [2 m -3,2 m -1], the quantum bits in the second set of quantum bits are 2, 4, 5... 2 m -2, and 2 m -2, the quantum bits in the second set of quantum bits are sequentially grouped from low to high, forming quantum bit pairs: [2,4], [6,8], [10,12]... [2 m -2,2 m ], the quantum bit pairs of the first set of quantum bits and the second set of quantum bits of the second layer operation timing are:

[0117] [1,3], [5,6], [9,11]... [2 m -3,2 m -1], [2,4], [6,8], [10,12]... [2 m -2,2 m ].

[0118] The quantum bit pairs of the third layer operation timing are: [1,5], [3,7], [9,13]... [2 m -4,2 m ].

[0119] This continues until the last layer of operation timing is paired with the first and second quantum bits of the previous layer of operation timing, a total of m = logn layers are paired.

[0120] When considering n quantum bits that are not an exponential of 2, they can be padded to the length of 2 m , that is, m = [logn], and then arranged according to the above method. When m layers are arranged, all those that exceed n are deleted.

[0121] The following is an example of 7 quantum bits:

[0122] In the first layer of operation timing, the quantum bit pairs are: [1,2], [3,4], [5,6], [7,8].

[0123] In the second layer of operation timing, the quantum bit pairs are: [1,3], [5,7], [2,4], [6,8].

[0124] In the third layer of operation timing, the quantum bit pairs are: [1,5], [2,6], [3,7], [4,8].

[0125] Removing the quantum bit pair with the 8th quantum bit, we have:

[0126] In the first layer of action timing, the quantum bit pairs are: [1,2], [3,4], [5,6].

[0127] In the second layer of action timing, the quantum bit pairs are: [1,3], [5,7], [2,4].

[0128] In the third layer of action timing, the quantum bit pairs are: [1,5], [2,6], [3,7].

[0129] In the embodiments provided by the present application, in the target quantum circuit, except for the last layer of action timing, in other layers of action timing, a plurality of quantum bits are re-grouped according to the action relationship between the target quantum logic gate and the quantum bits in the next layer of action timing to form a quantum bit set, the quantum bit set includes a first quantum bit set and a second quantum bit set, the quantum bits in the first quantum bit set come from the first quantum bit in each next quantum bit pair, and the quantum bits in the first quantum bit set are sequentially grouped from low bits to high bits to form quantum bit pairs; the quantum bits in the second quantum bit set come from the second quantum bit in each next quantum bit pair, and the quantum bits in the second quantum bit set are sequentially grouped from low bits to high bits to form quantum bit pairs.

[0130] In a feasible implementation, a target quantum circuit with 8 quantum bits is taken as an example for illustration:

[0131] In the last layer of action timing, every two adjacent quantum bits are grouped to form four quantum bit pairs, namely [1,2], [3,4], [5,6] and [7,8], and each quantum bit pair is acted on by a conjugate transpose matrix of a unitary matrix (target quantum logic gate).

[0132] In the second last layer of action timing, the quantum bits are re-grouped, and this time, the quantum bit pairs are also four, namely [2,4], [6,8], [1,3] and [5,7], and each quantum bit pair is acted on by a conjugate transpose matrix of a unitary matrix (target quantum logic gate).

[0133] In the first layer of action timing, the quantum bits are re-grouped, and this time, the quantum bit pairs are also four, namely [4,8], [1,5], [2,6] and [3,7], and each quantum bit pair is acted on by a conjugate transpose matrix of a unitary matrix (target quantum logic gate).

[0134] For n quantum bits, it is first assumed to be an exponential power of 2, that is, n = 2m Where m is a positive integer, in the last layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1, 2], [3, 4], [5, 6]...[2 m -1,2 m ].

[0135] In the penultimate layer of the sequence, several qubits are regrouped, with the qubits in the first set numbered 1, 3, 5...2. m -3 and 2 m -1, the qubits in the first set of qubits are grouped sequentially from least significant bit to most significant bit to form qubit pairs:

[0136] [1,3],[5,6],[9,11]......[2 m -3,2 m -1], the qubits in the second set of qubits are 2, 4, 5...2 m -2 and 2 m The qubits in the second set are grouped sequentially from least significant bit to most significant bit to form qubit pairs: [2,4], [6,8], [10,12]...[2 m -2,2 m The qubit pairs formed by combining the first and second qubit sets of the penultimate layer of the operation sequence are:

[0137] [1,3],[5,6],[9,11]......[2 m -3,2 m -1],[2,4],[6,8],[10,12]......[2 m -2,2 m ].

[0138] The qubit pairs in the third-to-last layer of interaction are: [1,5],[3,7],[9,13]......[2 m -4,2 m ].

[0139] This continues until the first layer of the interaction sequence is paired with the first and second qubits of the next layer of the interaction sequence, requiring a total of m = logn layers of pairing.

[0140] When considering n qubits that are not powers of 2, they can be padded to make them powers of 2. mThe length of the quantum circuit is m = [log n], that is, m = [log n], and then the above method is used for arrangement, and when m layers are arranged, all of which are designed to exceed n are deleted.

[0141] The following is an example of 7 quantum bits:

[0142] In the last layer of the timing sequence, the quantum bit pairs are: [1, 2], [3, 4], [5, 6], [7, 8].

[0143] In the second-to-last layer of the timing sequence, the quantum bit pairs are: [1, 3], [5, 7], [2, 4], [6, 8].

[0144] In the first layer of the timing sequence, the quantum bit pairs are: [1, 5], [2, 6], [3, 7], [4, 8].

[0145] Remove the quantum bit pair with quantum bit No. 8, so we have:

[0146] In the last layer of the timing sequence, the quantum bit pairs are: [1, 2], [3, 4], [5, 6].

[0147] In the second-to-last layer of the timing sequence, the quantum bit pairs are: [1, 3], [5, 7], [2, 4].

[0148] In the first layer of the timing sequence, the quantum bit pairs are: [1, 5], [2, 6], [3, 7].

[0149] Referring to Figure 5 As an embodiment of the present application, a plurality of target matrices are constructed based on partial components of the amplitude, which can include the following steps:

[0150] Step 1021, determining the number of quantum bits n used to prepare the target quantum state based on the number of ground states N of the target quantum state;

[0151] Wherein, the number of quantum bits n satisfies 2 n-1 <N≤2 n .

[0152] Specifically, for n quantum bits, all possible quantum states they can represent are a 2 n dimensional complex vector space, that is, the number of all ground states that n quantum bits can represent is 2 n Then, based on the number of ground states N of the target quantum state determined in the above step 201, the number of quantum bits required for the amplitude preparation quantum circuit can be determined.

[0153] With Figure 3The shown disentangling quantum circuit corresponds to the existing MPS encoding quantum circuit, and a plurality of encoding modules for quantum state amplitude preparation are distributed in a ladder type and sequentially act on every two adjacent quantum bits. Since part of the quantum bits in the quantum circuit are not acted on by quantum logic gates for a long time, the phenomenon of circuit decoherence is prone to occur.

[0154] Therefore, in a specific embodiment, the target quantum circuit includes a plurality of layers of target quantum logic gates connected in series; each layer of target quantum logic gates is sequentially executed based on an action timing, each layer of target quantum logic gates includes a plurality of target quantum logic gates executed in parallel, and each target quantum logic gate is determined based on a conjugate transpose matrix of a unitary matrix.

[0155] With the increase of the number of action layers of the target quantum logic gate, the preparation accuracy of the target quantum circuit preparation is also improved, and accordingly, the classical complexity of the target quantum circuit is higher, which is specifically reflected in that more target quantum logic gates are required. Therefore, in the specific encoding process, a suitable number of action layers of the target quantum logic gate can be selected based on the preparation accuracy requirement, which is not limited here.

[0156] In the present embodiment, compared with the existing matrix product state encoding circuit in which a plurality of target quantum logic gates are distributed in a ladder type, the present scheme does not need to determine the wave function of the target quantum state to be prepared in advance, and the action timing of the quantum gate is more free, a plurality of target quantum logic gates can be executed in parallel, thereby avoiding the case that no quantum gate acts for a long time, thereby reducing the decoherence probability of the circuit and improving the fidelity.

[0157] Step 1022: For each action timing, based on the quantum bit pair acted on by the target quantum logic gate, the amplitudes of the plurality of partial components are rearranged into a 2 2 ×2 n-2 matrix to obtain a plurality of target matrices.

[0158] In a specific embodiment, based on the number of target quantum bits acted on by the target quantum logic gate, the amplitudes of the plurality of partial components are rearranged into a 2 2 ×2 n-2 matrix, which can include:

[0159] The amplitudes of a plurality of ground states with the number of target quantum bits corresponding to positions of |00>, |01>, |10>, and |11> are sequentially taken as the 1st, 2nd, 3rd, and 4th rows of the matrix to rearrange a 2 2 ×2 n-2 matrix; wherein the 2 n-2 amplitudes in each row are arranged based on the binary representation order of the corresponding ground state.

[0160] Specifically, in order to disentangle the first qubit and other qubits as much as possible, a unitary matrix U needs to be applied on the first qubit and the second qubit 12 However, the degree of entanglement between the first qubit and other qubits can be represented by the entanglement entropy of the SVD diagonal element, that is, the goal of applying the unitary matrix U1 is to make the maximum value of the diagonal element of the matrix between the first qubit system and the remaining qubit system tend to 1.

[0161] Suppose that the initial state of n qubits is |ψ>, then the unitary matrix U is applied 12 After that, the quantum state becomes Using the one-dimensional expansion formula The above evolution result can be written as a tensor form, which is:

[0162]

[0163] For convenience of expression, the target quantum state |ψ> can be written into four parts, ω 00 , ψ 01 , ψ 10 , ψ 11 , wherein the subscript of each part represents the state of the first two qubits. In this way, it is divided into four 2 n-2 vectors, which are as follows:

[0164]

[0165] SVD decomposition is performed thereon, and there are At this time, let The SVD decomposition result can be written as:

[0166] |U 12 [ψ1, ψ2, ψ3, ψ4] T >> = [ψ'1, ψ'2, ψ'3, ψ'4] T

[0167] Or,

[0168] |U' 12 [s1v1, s2v2, s3v3, s4v4] T >

[0169] Wherein, s i is arranged from large to small.

[0170] At this time, the goal is to hope that the diagonal element of the diagonal matrix is more concentrated, so as to reduce the entanglement entropy. And the corresponding two rows are orthogonal, so their singular values are And selecting any other non-unit matrix U 12 cannot make the two eigenvalues more concentrated, that is, the SVD entropy is smaller, which means that U 12 is the best choice.

[0171] Further, still taking the above-mentioned target quantum state to be prepared For example, in order to encode it on the amplitude of 6 quantum bits, first, the disentanglement operation needs to be performed on the quantum bit pairs numbered 1, 2; 3, 4; 5, 6 and quantum bit pairs numbered 2, 3; 4, 5. Taking the unitary matrix acting on the quantum bit pair numbered 1, 2 as an example, the amplitudes of multiple partial components need to be rearranged, and the rearranged amplitudes are 2 2 ×2 6-2 sized, that is, the target matrix of 4x16.

[0172] Among them, the first row of the target matrix corresponds to the 16 amplitudes of the | 00) state of the 1 and 2 quantum bit states of the ground state, and the 2nd, 3rd, and 4th rows correspond to the 16 amplitudes of the |01>, |10>, and |11) states of the 1 and 2 quantum bit states of the ground state, respectively. Among them, the 16 amplitudes in each row are arranged in order based on the binary representation of the corresponding ground state, so that the following target matrix C1 can be obtained:

[0173] The first row is:

[0174] α 000000 , α 000100 , α 001000 , α 001100 , α 010000 , α 010100 , α 011000 , α 011100 ,

[0175] α 100000 , α 100100 , α 101000 , α 101100 , α 110000 , α 110100 , α 111000 , α 111100

[0176] The second row is:

[0177] α 000001 , α 000101 , α 001001 , α 001101 , α 010001 , α 010101 , α 011001 , α 011101 ,

[0178] α100001 , a 100101 , a 101001 , a 101101 , a 110001 , a 110101 , a 111001 , a 111101

[0179] The third behavior:

[0180] a 000010 , a 000110 , a 001010 , a 001110 , a 010010 , a 010110 , a 011010 , a 011110 ,

[0181] a 100010 , a 100110 , a 101010 , a 101110 , a 110010 , a 110110 , a 111010 , a 111110

[0182] The fourth behavior:

[0183] a 000011 , a 000111 , a 001011 , a 001111 , a 010011 , a 010111 , a 011011 , a 011111 ,

[0184] a 100011 , a 100111 , a 101011 , a 101111 , a 110011 , a 110111 , a 111011 , a 111111

[0185] As an embodiment of the present application, singular value decomposition is performed on the target matrix to obtain a unitary matrix, which can include the following steps:

[0186] Step 1023: For each target matrix, SVD decomposition is performed on the target matrix to obtain a multiplied left singular vector matrix, a singular value matrix, and a right singular vector matrix, and the left singular vector matrix is taken as a unitary matrix.

[0187] Then, the SVD decomposition is performed on the target matrix C1 of 4x16 size, and a left singular vector matrix of 4x4 unitary matrix U1 is obtained, which is one of the unitary matrices for evolving the target quantum state |ψ> into |0> state; and the conjugate transpose matrix (i.e. inverse matrix ) is the unitary matrix mapped into the target quantum circuit.

[0188] Then, the 3rd and 4th quantum bits can be rearranged as markers in the same way, i.e. the 16 amplitudes corresponding to the |00>, |01>, |10>, |11> states of the 3rd and 4th bits are rearranged into a target matrix C2 of 4x16 size. Then, the SVD decomposition is performed to obtain a unitary matrix U2, which is the second unitary matrix mapped into the amplitude encoding quantum circuit.

[0189] Similarly, the unitary matrix U3 acting on the 5th and 6th quantum bits and the third unitary matrix

[0190] Further, the step 102 can further include the following steps:

[0191] Step 1024, performing simulation evolution on the target quantum state based on the quantum logic gates corresponding to the plurality of unitary matrices by using the quantum virtual machine.

[0192] Step 1025, taking the final state obtained by the simulation evolution as the target quantum state to be prepared, and returning to the step 101 of determining the partial components of the target quantum state to be prepared until the final state obtained by the simulation evolution is |0> n , or the iteration reaches a preset number of times.

[0193] Specifically, the simulation evolution can be performed on the target quantum state |ω> based on the three quantum logic gates U1, U2, U3 of the first layer by using the quantum virtual machine, and the final state obtained by the evolution is taken as the target quantum state to be prepared, and the step of determining the partial components of the target quantum state to be prepared is returned. Then, in the next iteration step, the target becomes to disentangle the final state obtained by the evolution into |0> n , i.e. the unitary matrix encoding is performed again on the basis of the three quantum logic gates U1, U2, U3 of the first layer, and the quantum logic gates of the first layer cannot act on the same pair of quantum bits.

[0194] Based on the above scheme, the two quantum logic gates of the second layer can be calculated, which are U4 acting on the 2nd and 3rd bits and U5 acting on the 4th and 5th quantum bits. Then, the above steps are repeatedly performed until the final state obtained by the simulation evolution is |0> nWhen the iteration reaches a preset number of times, it can be considered that the disentanglement operation has reached a preset precision. That is, the quantum circuit for disentanglement in the present scheme is obtained.

[0195] Then the inverse mapping of the quantum logic gates corresponding to the unitary matrices in the quantum circuit is applied to the 6 quantum bits in the initial state |0> n, and the target quantum circuit obtained can generate the target quantum state |ψ>.

[0196]

Structure of quantum state preparation device

[0197] As shown in Figure 6 The quantum state preparation device comprises:

[0198] The acquisition module is configured to determine each partial component of a target quantum state to be prepared. Each partial component includes a ground state of the target quantum state and an amplitude of the ground state.

[0199] The disentanglement quantum circuit construction module is configured to construct a disentanglement quantum circuit, construct a plurality of target matrices based on the amplitudes of the partial components, perform SVD decomposition on the target matrices to obtain unitary matrices, determine disentanglement quantum logic gates based on the unitary matrices, and apply the plurality of disentanglement quantum logic gates to quantum bits in an initial state of the target quantum state to obtain the disentanglement quantum circuit. The action relationship between the disentanglement quantum logic gates and the quantum bits in the next layer of action timing is determined by the action relationship between the disentanglement quantum logic gates and the quantum bits in the previous layer of action timing.

[0200] The disentanglement quantum logic gates are determined based on the unitary matrices obtained by the decomposition, the plurality of disentanglement quantum logic gates are applied to quantum bits in an initial state of the target quantum state to obtain the disentanglement quantum circuit, and the disentanglement quantum circuit is used to evolve the target quantum state into |0 n .

[0201] The target quantum circuit construction module is configured to determine that the inverse circuit of the disentanglement quantum circuit is the target quantum circuit, and the target quantum circuit has a target quantum logic gate determined based on the conjugate transpose matrix of the unitary matrix. The action relationship between the target quantum logic gate and the quantum bits in the previous layer of action timing is determined by the action relationship between the target quantum logic gate and the quantum bits in the next layer of action timing.

[0202] The inverse circuit of the disentanglement quantum circuit is the target quantum circuit, the number of target quantum logic gates of the target quantum circuit is the same as the number of disentanglement quantum logic gates of the disentanglement quantum circuit, the execution time sequence of the plurality of target quantum logic gates is opposite to that of the plurality of disentanglement quantum logic gates, the disentanglement quantum logic gates of the disentanglement quantum circuit are determined based on the unitary matrix obtained by decomposition, the target quantum logic gates of the target quantum circuit are determined based on the conjugate transpose matrix of the unitary matrix, and the plurality of target quantum logic gates act on the quantum bit with the initial state of |0>n, so that the target quantum state is evolved

[0203] The running module is configured to run the target quantum circuit to prepare the target quantum state.

[0204] The running module is a quantum system capable of running a quantum circuit, and an exemplary quantum hardware including a quantum processor and a quantum control system connected in communication is a system, wherein the quantum processor is a quantum chip, and the quantum control system is configured to provide an analog signal for implementing a quantum logic gate in the quantum circuit, the analog signal acting on the quantum chip to implement running of the quantum circuit.

[0205] Structure of the storage medium

[0206] The embodiment of the application further provides a storage medium, and the storage medium stores a computer program.

[0207] Specifically, in the embodiment, the storage medium can be configured to store a computer program for implementing the following steps:

[0208] Step S101: determining each partial component of a target quantum state to be prepared, each partial component including one ground state of the target quantum state and an amplitude of the ground state.

[0209] Step S102: constructing a plurality of target matrices based on the amplitudes of the partial components, performing SVD decomposition on the target matrices to obtain a unitary matrix, determining disentanglement quantum logic gates based on the unitary matrix, and causing the plurality of disentanglement quantum logic gates to act on quantum bits with the initial state of the target quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gates and the quantum bits in a later layer action time sequence is determined by the action relationship between the disentanglement quantum logic gates and the quantum bits in a previous layer action time sequence.

[0210] Step S103: inversely pushing the disentanglement quantum circuit to obtain a target quantum circuit, the target quantum circuit having a target quantum logic gate, the target quantum logic gate being determined based on a conjugate transpose matrix of the unitary matrix, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action timing is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action timing.

[0211] Step S104: running the target quantum circuit to prepare the target quantum state.

[0212] Structure of electronic device

[0213] The embodiment of the present application further provides an electronic device, comprising a memory and a processor, the memory storing a computer program, and the processor being arranged to run the computer program to realize the steps in any of the method embodiments.

[0214] Specifically, the electronic device can further comprise a transmission device connected with the processor and an input-output device connected with the processor.

[0215] Specifically, in the embodiment, the processor can be arranged to realize the following steps through the computer program:

[0216] Step S101: determining each partial component of a target quantum state to be prepared, each partial component comprising one basis state of the target quantum state and an amplitude of the basis state.

[0217] Step S102: constructing a plurality of target matrices based on the amplitudes of the partial components, performing SVD decomposition on the target matrices to obtain a unitary matrix, determining a disentanglement quantum logic gate based on the unitary matrix, and applying a plurality of disentanglement quantum logic gates on quantum bits with an initial state of the target quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gate and the quantum bit in the next layer of action timing is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer of action timing.

[0218] Step S103: inversely pushing the disentanglement quantum circuit to obtain a target quantum circuit, the target quantum circuit having a target quantum logic gate, the target quantum logic gate being determined based on a conjugate transpose matrix of the unitary matrix, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action timing is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action timing.

[0219] Step S104: running the target quantum circuit to prepare the target quantum state.

[0220] The above detailed description of the structure, features and effects of the present application is based on the embodiments shown in the drawings. The above description is only the preferred embodiments of the present application, but the present application is not limited to the embodiments shown in the drawings. Any changes or modifications made in accordance with the concept of the present application, or equivalent embodiments with equivalent changes, are still within the scope of the present application.

Claims

1. A method of quantum state preparation, comprising: The method comprises: determining each partial component of a target quantum state to be prepared, each of the partial components comprising one basis state of the target quantum state and an amplitude of the basis state; determining a number of qubits for preparing the target quantum state based on a ground state number of the target quantum state; for each action time sequence, rearranging amplitudes of a plurality of partial components into a plurality of target matrices by performing SVD decomposition on the large-scale matrix, a number of qubits; and performing SVD decomposition on the target matrix to obtain a unitary matrix, determining a disentanglement quantum logic gate based on the unitary matrix, and applying a plurality of the disentanglement quantum logic gates to qubits in an initial state of the target quantum state to obtain a disentanglement quantum circuit, wherein an action relationship between the disentanglement quantum logic gate and the qubits in a later layer action time sequence is determined by an action relationship between the disentanglement quantum logic gate and the qubits in a previous layer action time sequence. determining an inverse circuit of the disentanglement quantum circuit as a target quantum circuit; running the target quantum circuit to prepare the target quantum state.

2. The method of claim 1, wherein: The action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action time sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in the former layer of action time sequence, comprising: In each layer of action time sequence, the quantum bits are re-grouped to form a plurality of quantum bit pairs, each quantum bit pair comprising a first bit quantum bit and a second bit quantum bit, the first bit quantum bit being lower than the second bit quantum bit, and each quantum bit pair being acted on by one disentanglement quantum logic gate in each layer of action time sequence; In the last layer of action time sequence, the quantum bits from the lowest bit to the highest bit are sequentially grouped, and each two adjacent quantum bits form a quantum bit pair; In other layers of action time sequence, a plurality of quantum bits are re-grouped according to the action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action time sequence to form a quantum bit set, the quantum bits in the quantum bit set being from the first bit quantum bit or the second bit quantum bit in each latter quantum bit pair, and the quantum bits in the quantum bit set being sequentially grouped from the lowest bit to the highest bit to form the quantum bit pair.

3. The method of claim 2, wherein: The re-grouping of a plurality of quantum bits according to the action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action time sequence to form a quantum bit set comprises: The quantum bit set comprises a first quantum bit set and a second quantum bit set, the quantum bits in the first quantum bit set being from the first bit quantum bit in each latter quantum bit pair, and the quantum bits in the first quantum bit set being sequentially grouped from the lowest bit to the highest bit to form the quantum bit pair; the quantum bits in the second quantum bit set being from the second bit quantum bit in each latter quantum bit pair, and the quantum bits in the second quantum bit set being sequentially grouped from the lowest bit to the highest bit to form the quantum bit pair.

4. The method of claim 1, wherein: The number of qubits Satisfies , The number of ground states of the target quantum state.

5. The method of claim 1, wherein: rearranging amplitudes of the plurality of partial components based on a number of qubits used to prepare the target quantum state a matrix of size n x n, comprising: The amplitudes of a plurality of ground states corresponding to positions of a qubit pair, respectively, are sequentially taken as the first row of a matrix, and the matrix of the size is obtained by rearrangement; wherein each of the amplitudes in each row is arranged based on a binary representation order of the corresponding ground state. ​ 6. The method of claim 5, wherein: The SVD decomposition of the target matrix to obtain a unitary matrix comprises: For each target matrix, the target matrix is subjected to SVD decomposition to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and the left singular vector matrix is taken as the unitary matrix.

7. A quantum state preparation apparatus, comprising: The device comprises: an acquisition module configured to determine each partial component of a target quantum state to be prepared, each of the partial components comprising one basis state of the target quantum state and an amplitude of the basis state; The disentanglement quantum circuit construction module is configured to determine the number of quantum bits for preparing the target quantum state based on the number of basis states of the target quantum state; for each action time sequence, based on the number of quantum bits for preparing the target quantum state, the amplitudes of the plurality of partial components are rearranged into a matrix of a certain scale, to obtain a plurality of target matrices, the number of quantum bits; and performing SVD decomposition on the target matrix to obtain a unitary matrix, determining a disentanglement quantum logic gate based on the unitary matrix, and applying a plurality of disentanglement quantum logic gates to quantum bits in an initial state of the target quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gate and the quantum bits in a later layer action time sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bits in a previous layer action time sequence. a target quantum circuit construction module configured to determine an inverse circuit of the disentanglement quantum circuit as a target quantum circuit; a running module configured to run the target quantum circuit to prepare the target quantum state.

8. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to implement the method in any one of claims 1 to 6 when executed. 9.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to implement the method in any one of claims 1 to 6.

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