Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device, the array substrate comprising: a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines and initial signal lines, the sub-pixel comprising a pixel circuit and a light emitting device electrically connected to the pixel circuit, each scan control line being electrically connected to at least one row of pixel circuits, the scan control line comprising a first scan signal line and a first reset control line, the array substrate further comprising a first GOA circuit and a second GOA circuit, the first GOA circuit comprising a plurality of first GOA units connected in cascade, each first GOA unit providing a first scan signal to a coupled sub-circuit in a row of pixel circuits; the second GOA circuit comprising a plurality of second GOA units connected in cascade, the second GOA unit being arranged on one side of the display area, driving the first reset control line unilaterally, or each second GOA unit providing a first reset control signal to a coupled sub-circuit in two or more rows of pixel circuits.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, the technical field of display, and particularly to an array substrate, a display panel and a display device. BACKGROUND

[0002] For an active-matrix organic light-emitting diode (AMOLED) display device, multiple driving signals are required in each pixel. In order to generate these driving signals which are sequentially turned on and turned off, a gate driver on array (GOA) circuit is required on both sides of an active area (AA) region, which can realize the function of row-by-row scanning driving of the display panel. Generally, the region where the GOA circuit is placed cannot simultaneously place the pixel circuit, thus forming a frame region around the display device which cannot emit light. In order to ensure the quality of the AA region, the number of different driving signals required in the pixel structure is increasing, and the GOA circuit required to exist simultaneously is also increasing, which is not consistent with the design concept of reducing the frame. However, if part of the important driving signals are forced to be unilaterally driven in order to reduce the frame, the screen quality will also be affected. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide an array substrate, comprising a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines and initial signal lines, the sub-pixel comprising a pixel circuit and a light-emitting device electrically connected to the pixel circuit, each scan control line being electrically connected to at least one row of pixel circuits, the scan control line comprising a first scan signal line and a first reset control line, the array substrate further comprising a GOA circuit group for driving the pixel circuit by rows, the GOA circuit group comprising: a first GOA circuit and a second GOA circuit, wherein:

[0005] The pixel circuit comprises a first node, a second node, a third node, a driving sub-circuit and a coupling sub-circuit, the driving sub-circuit being electrically connected to the first node, the second node and the third node respectively and being configured to provide a driving signal to the third node under the control of signals of the first node and the second node; the coupling sub-circuit being connected to the first scan signal line, the first reset control line, the data signal line, the first initial signal line and the third node respectively and being configured to couple the signal of the first initial signal line to the third node under the control of a first reset control signal provided by the first reset control line, and to couple the signal of the data signal line to the third node under the control of a first scan signal provided by the first scan signal line.

[0006] The first GOA circuit comprises a plurality of first GOA units connected in cascade, each of the first GOA units being connected with a first scan signal line and configured to provide a first scan signal to a coupled sub-circuit in a row of pixel circuits.

[0007] The second GOA circuit comprises a plurality of second GOA units connected in cascade, the second GOA units being arranged on one side of the display area and unilaterally driving the first reset control lines, or each of the second GOA units being connected with two or more of the first reset control lines and configured to provide the first reset control signal to coupled sub-circuits in two or more rows of pixel circuits.

[0008] The display panel provided by the embodiments of the present disclosure comprises the array substrate as described in any of the embodiments of the present disclosure.

[0009] The display device provided by the embodiments of the present disclosure comprises the display panel as described in any of the embodiments of the present disclosure.

[0010] The array substrate, the display panel and the display device provided by the embodiments of the present disclosure can achieve the effect of narrow frame without affecting the screen quality by driving part of the GOA circuit in unilateral manner or one-to-many manner.

[0011] Other features and advantages of the present disclosure will be described in the following description, and some will become apparent from the description, or will be learned through practice of the present disclosure. Other advantages of the present disclosure will be realized and obtained by the solutions described in the specification and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0013] Figure 1 FIG. 1 is a structural schematic diagram of a display device;

[0014] Figure 2 FIG. 2 is a structural schematic diagram of a display substrate;

[0015] Figure 3 FIG. 3 is a plan structural schematic diagram of a display area in a display substrate;

[0016] Figure 4 FIG. 4 is a sectional structural schematic diagram of a display area in a display substrate;

[0017] Figure 5 FIG. 5 is a structural schematic diagram of a pixel circuit provided by the embodiments of the present disclosure;

[0018] Figure 6 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0019] Figure 7 for Figure 6 A driving timing diagram of a pixel circuit is provided;

[0020] Figure 8A for Figure 6 Schematic diagram of the effect of the first reset control signal provided by the first reset control line on the driving current at different delay times;

[0021] Figure 8B for Figure 6 Schematic diagram of the effect of the second reset control signal provided by the second reset control line on the driving current at different delay times;

[0022] Figure 8C for Figure 6 Schematic diagram of the effect of the third reset control signal provided by the third reset control line on the driving current at different delay times;

[0023] Figure 8D for Figure 6 Schematic diagram of the effect of the first light emitting control signal provided by the first light emitting control line on the driving current at different delay times;

[0024] Figure 8E for Figure 6 Schematic diagram of the effect of the second light emitting control signal provided by the second light emitting control line on the driving current at different delay times;

[0025] Figure 8F for Figure 6 Schematic diagram of the effect of the first scan signal provided by the first scan signal line on the driving current at different delay times;

[0026] Figure 9 for Figure 6 The pixel circuit shown is a simulation waveform result diagram when the six groups of GOA circuits connected to the corresponding scanning control lines are driven by a one-drive-two scheme;

[0027] Figures 10 to 23 Schematic diagram of driving modes of several GOA circuits according to exemplary embodiments of the present disclosure;

[0028] Figure 24 for Figure 6 The pixel circuit provided uses Figures 18 to 22 The timing diagram corresponding to the signals of each scanning control line when driving in any of the driving modes shown. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically describe the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0030] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0031] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0032] In the present specification, for the convenience of description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0033] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0034] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain terminal, a drain region, or a drain electrode) and the source electrode (a source terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows.

[0035] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having an opposite polarity or in the case of changing the direction of current flowing in a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0036] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0037] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0038] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0039] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0040] In this specification, "about" means not strictly limited to a limit, and a value within a range of a process and measurement error is allowed.

[0041] Figure 1 FIG. 1 is a schematic view of a display device. Figure 1As shown, the display device can include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array, the timing controller being connected to the data signal driver, the scan signal driver, and the light emission signal driver, respectively, the data signal driver being connected to a plurality of data signal lines (D1 to Dn), respectively, the scan signal driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emission signal driver being connected to a plurality of light emission control lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emission unit, the circuit unit can include at least a pixel circuit, the pixel circuit being connected to the scan signal line, the light emission control line, and the data signal line, respectively, the light emission unit can include a light emission device, the light emission device being connected to the pixel circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver can sample the gray scale value using the clock signal, and apply a data voltage corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driver can generate an emission signal to be provided to the light emission control lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driver can sequentially provide the emission signal having an off-level pulse to the light emission control lines E1 to Eo. For example, the light emission signal driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0042] Figure 2FIG. 1 is a schematic diagram of a structure of a display substrate according to an example embodiment. Figure 2 As shown in FIG. 1, the display substrate can include a display area 100, a binding area 200 located at one side of the display area 100, and a frame area 300 located at other side of the display area 100. In an example embodiment, the display area 100 can be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels being configured to display dynamic pictures or static images, and the display area 100 can be referred to as an active display (AA) area. In an example embodiment, the display substrate can employ a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, folded, or rolled up.

[0043] In an example embodiment, the binding area 200 can include, in sequence along a direction away from the display area 100, a fan-out area, a bending area, a driving chip area, and a binding pin area. The fan-out area is connected to the display area 100 and can include at least a plurality of data lead-out lines. The bending area is connected to the fan-out area and can include a composite insulating layer provided with a recess configured to bend the binding area to the back of the display area. The driving chip area can include at least an integrated circuit (IC) configured to be connected to the plurality of data lead-out lines. The binding pin area can include at least a plurality of bonding pads configured to be connected to an external flexible printed circuit (FPC).

[0044] In an example embodiment, the frame area 300 can include at least a circuit area connected to the display area 100 and can include at least a gate drive circuit electrically connected to a pixel circuit in the display area 100.

[0045] In an example embodiment, at least one isolation dam can be provided in the binding area 200 and the frame area 300, the isolation dam can extend along a direction parallel to an edge of the display area, forming a ring structure surrounding the display area 100, and the edge of the display area is an edge of the display area close to the binding area or the frame area.

[0046] Figure 3 FIG. 2 is a schematic diagram of a planar structure of a display area in a display substrate according to an example embodiment. Figure 3As shown, the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel circuit. The pixel circuit is respectively connected to a scan signal line, a light-emitting control line, a data signal line, and a high-potential power line. The pixel circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting control line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0047] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a green subpixel (G) that emits green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal. In some exemplary embodiments, the three subpixels may be arranged horizontally, vertically, or in any other arrangement, which is not limited in this disclosure.

[0048] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a diamond shape to form an RGBG pixel arrangement, or may be arranged horizontally, vertically, or in any other manner, which is not limited in the present disclosure.

[0049] Figure 4 FIG. 1 is a schematic diagram of the cross-sectional structure of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the base 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0050] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, each of which can include at least a pixel circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device that can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel circuit, the organic light-emitting layer being connected to the anode and the cathode respectively, and the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, forming an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0051] Figure 5 A structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the pixel circuit provided by the embodiment of the present disclosure can include a driving sub-circuit 1021 and a coupling sub-circuit 1022. Figure 5

[0052] The driving sub-circuit 1021 is electrically connected to the first node N1, the second node N2, and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of signals of the first node N1 and the second node N2.

[0053] The coupling sub-circuit 1022 is electrically connected to the scan signal line Gate1, the first reset control line Reset1, the data signal line DL, the first initial signal line INIT1, and the third node N3 respectively, and is configured to couple the signal of the first initial signal line INIT1 to the third node N3 under the control of the first reset control signal provided by the first reset control line Reset1, and couple the signal of the data signal line DL to the third node N3 under the control of the first scan signal provided by the first scan signal line Gate1.

[0054] In an example embodiment, the coupling sub-circuit 1022 can include a data writing sub-circuit, a first reset sub-circuit, and a first coupling sub-circuit (not shown in the figure), wherein the data writing sub-circuit is configured to write the signal of the data signal line DL to a fifth node (not shown in the figure) under the control of the first scan signal provided by the first scan signal line Gate1; the first reset sub-circuit is configured to write the signal of the first initial signal line INIT1 to the fifth node under the control of the first reset control signal provided by the first reset control line Reset1; and the first coupling sub-circuit is configured to couple the signal of the fifth node to the third node N3. ​

[0055] In an example embodiment, as shown in Figure 5 The pixel circuit can further include a second reset sub-circuit 1023, wherein the second reset sub-circuit 1023 is electrically connected with the second reset control line Reset2, the second initial signal line INIT2 and the first node N1 respectively, and is configured to provide the signal of the second initial signal line INIT2 to the first node N1 under the control of the second reset control signal provided by the second reset control line Reset2, that is, to reset the first node N1 using the signal of the second initial signal line INIT2.

[0056] In an example embodiment, as shown in Figure 5 The pixel circuit can further include a third reset sub-circuit 1024, wherein the third reset sub-circuit 1024 is electrically connected with the third reset control line Reset3, the third initial signal line INIT3 and the fourth node N4 (i.e. the anode of the light emitting device) respectively, and is configured to provide the signal of the third initial signal line INIT3 to the fourth node N4 under the control of the third reset control signal provided by the third reset control line Reset3, that is, to reset the fourth node N4 using the signal of the third initial signal line INIT3.

[0057] In an example embodiment, as shown in Figure 5 The pixel circuit can further include a holding sub-circuit 1025, wherein the holding sub-circuit 1025 is electrically connected with the first node N1 and the third node N3 respectively, and is configured to store the voltage difference of the signal between the first node N1 and the third node N3.

[0058] In an example embodiment, as shown in Figure 5 The pixel circuit can further include a first light emitting control sub-circuit 1026, wherein the first light emitting control sub-circuit 1026 is electrically connected with the second node N2, the first light emitting control line EM1 and the first power supply line VDD respectively, and is configured to provide the signal of the first power supply line VDD to the second node N2 under the control of the signal of the first light emitting control line EM1.

[0059] In an example embodiment, as shown in Figure 5 The pixel circuit can further include a second light emitting control sub-circuit 1027, wherein the second light emitting control sub-circuit 1027 is electrically connected with the third node N3, the fourth node N4 and the second light emitting control line EM2 respectively, and is configured to turn on the third node N3 and the fourth node N4 under the control of the signal of the second light emitting control line EM2, that is, to turn on the third node N3 and the anode of the light emitting device.

[0060] In an example embodiment, the first power supply line VDD can continuously provide a high-level signal, and the signal of the first power supply line VDD is a direct current signal.

[0061] In the pixel circuit provided in the embodiment of the present disclosure, the second reset sub-circuit 1023 connected with the first node is only electrically connected with the second initial signal line INIT2 and the second reset control line Reset2, which means that the number of transistors connected with the first node N1 is small, and the data signal of the data signal line can be coupled to the third node N3 connected with the driving sub-circuit 1021 by the arrangement of the coupling sub-circuit 1022, thereby reducing the number of transistors directly coupled to the first node N1 connected with the driving sub-circuit 1021, and realizing normal writing of data and threshold compensation. Therefore, the pixel circuit provided in the embodiment of the present disclosure can reduce the parasitic capacitance coupled with the first node N1 under the premise of ensuring normal display, so that the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit 1021 is not easy to deviate, thereby ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0062] In an example embodiment, the pixel circuit is configured to drive the light emitting device L to emit light.

[0063] In an example embodiment, the light emitting device can include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. The anode of the light emitting device is electrically connected with the pixel circuit, and the cathode of the light emitting device is electrically connected with the second power supply end VSS.

[0064] In an example embodiment, the second power supply end VSS can continuously provide a low-level signal, and the signal of the second power supply end VSS is a direct current signal.

[0065] In an example embodiment, the light emitting device can be a current driving type device, and can be a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED), a Mini Light Emitting Diode (Mini LED), an Organic Light Emitting Diode (OLED), or a Quantum Light Emitting Diode (QLED). The typical size (e.g., length) of the Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of the Mini LED can be about 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0066] In an exemplary embodiment, the organic light-emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0067] Figure 6 An equivalent circuit diagram of a pixel circuit of an embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG. 1A, the driving sub-circuit 1021 includes a driving transistor T3. In some exemplary embodiments, the driving transistor T3 can be a single-gate transistor. Wherein the control electrode of the driving transistor T3 is electrically connected with the first node N1, the first electrode of the driving transistor T3 is electrically connected with the second node N2, and the second electrode of the driving transistor T3 is electrically connected with the third node N3. Figure 6

[0068] In other exemplary embodiments, the driving transistor T3 can be a double-gate transistor, and the driving transistor T3 includes a first control electrode and a second control electrode. Wherein the first control electrode of the driving transistor T3 can be electrically connected with the first node N1, and the second control electrode of the driving transistor T3 can be electrically connected with the third node N3 (not shown in the figure). The connection mode of the driving transistor in the present disclosure can improve the output saturation characteristics of the driving transistor T3.

[0069] In an exemplary embodiment, as shown in FIG. 1A, the driving sub-circuit 1021 includes a driving transistor T3. In some exemplary embodiments, the driving transistor T3 can be a single-gate transistor. Wherein the control electrode of the driving transistor T3 is electrically connected with the first node N1, the first electrode of the driving transistor T3 is electrically connected with the second node N2, and the second electrode of the driving transistor T3 is electrically connected with the third node N3. Figure 6 ​As shown, the coupling sub-circuit 1022 may include: a first reset transistor T7, a data write transistor T4, and a second capacitor C2. The control electrode of the first reset transistor T7 is electrically connected to the first reset control line Reset1, the first electrode of the first reset transistor T7 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T7 is electrically connected to the fifth node N5. The control electrode of the data write transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the data write transistor T4 is electrically connected to the data signal line DL, and the second electrode of the data write transistor T4 is electrically connected to the fifth node N5. The first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0070] In an exemplary embodiment, the first initial signal line INIT1 may receive a first initial signal, and the first reset transistor T7 writes the first initial signal into the fifth node N5 under the control of a first reset control signal of a first reset control line Reset1.

[0071] In an exemplary embodiment, the data signal line DL may receive a data signal, and the data write transistor T4 writes the data signal into the fifth node N5 under the control of the first scan signal of the first scan signal line Gate1.

[0072] In an exemplary embodiment, Figure 6 As shown, the second reset sub-circuit 1023 may include a second reset transistor T1. A control electrode of the second reset transistor T1 is electrically connected to the second reset control line Reset2, a first electrode of the second reset transistor T1 is electrically connected to the second initial signal line INIT2, and a second electrode of the second reset transistor T1 is electrically connected to the first node N1.

[0073] In an exemplary embodiment, the second initial signal line INIT2 may receive a second initial signal. The second reset transistor T1 writes the second initial signal into the first node N1 under the control of a second reset control signal of the second reset control line Reset2, ie, resets the first node N1.

[0074] In an exemplary embodiment, Figure 6 As shown, the third reset sub-circuit 1024 may include a third reset transistor T2. A control electrode of the third reset transistor T2 is electrically connected to a third reset control line Reset3, a first electrode of the third reset transistor T2 is electrically connected to a third initial signal line INIT3, and a second electrode of the third reset transistor T2 is electrically connected to a fourth node N4.

[0075] In an exemplary embodiment, the third initial signal line INIT3 can receive a third initial signal. Under the control of a third reset control signal from the third reset control line Reset3, the third reset transistor T2 writes the third initial signal to the fourth node N4, thereby resetting the fourth node N4. In other exemplary embodiments, the third reset transistor T2 can also write the third initial signal to the third node N3, thereby resetting the third node N3, under the control of the third reset control signal from the third reset control line Reset3. Specifically, under the control of the signal from the third reset control line Reset3, the third reset transistor T2 writes the third initial signal to the third node N3 or the fourth node N4, thereby initializing the third node N3 or the fourth node N4. Exemplarily, the third reset transistor T2 can be turned on once or multiple times during a display frame, which is not limited in this disclosure. When the second electrode of the third reset transistor T2 is electrically connected to the third node N3, turning on the third reset transistor T2 can initialize the second electrode of the drive transistor T3 or bias the drive transistor T3. When the second electrode of the third reset transistor T2 is electrically connected to the fourth node N4, the third reset transistor T2 is turned on to initialize the anode of the light emitting device.

[0076] In an exemplary embodiment, Figure 6 As shown, the holding sub-circuit 1025 includes: a first capacitor C1, wherein a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3.

[0077] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal at the first node N1 and improve the reliability of the pixel circuit.

[0078] In an exemplary embodiment, Figure 6 As shown, the first light emission control subcircuit 1026 may include a first light emission control transistor T5. A control electrode of the first light emission control transistor T5 is electrically connected to the first light emission control line EM1, a first electrode of the first light emission control transistor T5 is electrically connected to the first power supply line VDD, and a second electrode of the first light emission control transistor T5 is electrically connected to the second node N2.

[0079] In an exemplary embodiment, Figure 6 As shown, the second light-emitting control subcircuit 1027 may include a second light-emitting control transistor T6. A control electrode of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control line EM2, a first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, and a second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4.

[0080] In an example embodiment, the signal received by the second initial signal line INIT2 connected to the same pixel circuit and the signal received by the first power supply line VDD can be the same signal.

[0081] In an example embodiment, the second initial signal received by the second initial signal line INIT2 is a positive voltage signal, so as to ensure that the driving transistor T3 can be normally turned on, thereby improving the reliability of the pixel circuit.

[0082] In an example embodiment, the signal received by the first initial signal line INIT1 connected to the same pixel circuit and the signal received by the second initial signal line INIT2 can be the same signal.

[0083] In an example embodiment, the voltage value of the third initial signal received by the third initial signal line INIT3 is less than the sum of the voltage value of the signal of the second power supply line VSS and the voltage value between the two electrodes of the light emitting device, so as to ensure that the light emitting device does not emit light when the anode of the light emitting device L is initialized.

[0084] In an example embodiment, the voltage value of the second initial signal received by the second initial signal line INIT2 can be equal to the voltage value of the first initial signal received by the first initial signal line INIT1, and the voltage value of the second initial signal received by the second initial signal line INIT2 can be greater than the voltage value of the third initial signal received by the third initial signal line INIT3.

[0085] In an example embodiment, the signal received by the first reset control line Reset1 connected to the same pixel circuit and the signal received by the first light emitting control line EM1 can be the same signal, or the signal received by the first reset control line Reset1 of the i-th row of pixel circuits and the signal received by the second reset control line Reset2 of the i-1-th row of pixel circuits can be the same signal.

[0086] In an example embodiment, the signal received by at least two signal terminals connected to the pixel circuit can be the same signal, which can reduce the number of signal lines connected to the pixel circuit and can realize high PPI of the display device.

[0087] In an example embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off voltage is a high voltage (for example, 5V, 10V or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage).

[0088] In the example embodiment, the N-type transistor can be an oxide thin film transistor. The active pattern of the oxide thin film transistor adopts oxide semiconductor (Oxide). The oxide thin film transistor has the advantage of low leakage current, which can reduce power consumption and improve display quality.

[0089] In the example embodiment, any of the first capacitor C1 and the second capacitor C2 can be a capacitor device made by a process, for example, the capacitor device can be realized by making a special capacitor electrode, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. Alternatively, any of the first capacitor C1 and the second capacitor C2 can be a parasitic capacitor between multiple devices, which can be realized by the transistor itself and other devices, lines. The connection mode of any of the first capacitor C1 and the second capacitor C2 includes but is not limited to the above-described mode, and can be other applicable connection mode, and can only store the level of the corresponding node. Here, the example embodiment of the present disclosure does not limit this.

[0090] In the example embodiment, Figure 6 At least one of the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 in the pixel circuit 1000 is an N-type transistor. For example, the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 can all be N-type transistors, or the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T6, and the first reset transistor T7 are N-type transistors, and the first light-emitting control transistor T5 is a P-type transistor. The present disclosure does not limit this.

[0091] Figure 7 For Figure 6 A driving timing diagram of the pixel circuit provided. Figure 7 is described by taking the first light-emitting control transistor T5 in the pixel circuit 1000 as an example. Figure 6 is described by taking the first light-emitting control transistor T5 in the pixel circuit 1000 as an example. Figure 7 is described by taking the first reset control line Reset1 connected to the i-th row of pixel circuits and the second reset control line Reset2 connected to the i-1-th row of pixel circuits as an example. As shown in Figure 7 , the first reset control line Reset1 and the second reset control line Reset2 receive the same signal. Figure 6 The working process of the pixel circuit provided can include:

[0092] The signal of the first light-emitting control line EM1, the first reset control line Reset1, the second reset control line Reset2 and the third reset control line Reset3 is a high level signal in the first stage H1, the initialization stage, and the signal of the second light-emitting control line EM2 and the first scanning signal line Gate1 is a low level signal. The first reset transistor T7, the second reset transistor T1 and the third reset transistor T2 are turned on, and the data writing transistor T4, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off.

[0093] The first reset transistor T7 is turned on, the signal of the first initial signal line INIT1 is written to the fifth node N5, and the voltage value VN5 of the signal of the fifth node N5 is Vinit1, wherein Vinit1 is the voltage value of the signal of the first initial signal line INIT1. The second reset transistor T1 is turned on, the signal of the second initial signal line INIT2 is written to the first node N1, and the voltage value VN1 of the signal of the first node N1 is Vinit2, wherein Vinit2 is the voltage value of the signal of the second initial signal line INIT2. The third reset transistor T2 is turned on, the signal of the third initial signal line INIT3 is written to the fourth node N4, and the voltage value VN4 of the signal of the fourth node N4 is Vinit3, wherein Vinit3 is the voltage value of the signal of the third initial signal line INIT3.

[0094] The signal of the first reset control line Reset1, the second reset control line Reset2 and the third reset control line Reset3 is a high level signal in the second stage H2, the threshold compensation stage, and the signal of the first light-emitting control line EM1, the second light-emitting control line EM2 and the first scanning signal line Gate1 is a low level signal. The first reset transistor T7, the second reset transistor T1, the third reset transistor T2 and the first light-emitting control transistor T5 are turned on, and the data writing transistor T4 and the second light-emitting control transistor T6 are turned off.

[0095] The first reset transistor T7 is turned on, the signal of the first initial signal line INIT1 is written to the fifth node N5, and the voltage value VN5 of the signal of the fifth node N5 is Vinit1. The second reset transistor T1 is turned on, the signal of the second initial signal line INIT2 is written to the first node N1, and the voltage value VN1 of the signal of the first node N1 is Vinit2. The third reset transistor T2 is turned on, the signal of the third initial signal line INIT3 is written to the fourth node N4, and the voltage value VN4 of the signal of the fourth node N4 is Vinit3. The first light-emitting control transistor T5 is turned on, the first power supply line VDD charges the third node N3 through the turned-on first light-emitting control transistor T5, the second node N2 and the turned-on driving transistor T3, until the voltage value VN3 of the signal of the third node N3 is Vinit2-Vth, Vth being the threshold voltage of the driving transistor T3, at this time, the voltage value stored by the first capacitor C1 is Vth, and the voltage value stored by the second capacitor C2 is Vinit1-Vinit2+Vth.

[0096] The third stage H3 is a data writing stage, the signals of the first light-emitting control line EM1, the second reset control line Reset2, the third reset control line Reset3 and the first scan signal line Gate1 are high-level signals, and the signals of the second light-emitting control line EM2 and the first reset control line Reset1 are low-level signals. The second reset transistor T1, the third reset transistor T2 and the data writing transistor T4 are turned on, and the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the first reset transistor T7 are turned off.

[0097] The second reset transistor T1 is turned on, the signal of the second initial signal line INIT2 is written to the first node N1, and the voltage value VN1 of the signal of the first node N1 is Vinit2. The third reset transistor T2 is turned on, the signal of the third initial signal line INIT3 is written to the fourth node N4, and the voltage value VN4 of the signal of the fourth node N4 is Vinit3. The data writing transistor T4 is turned on, the signal of the data signal line DL is written to the fifth node N5, and the voltage value VN5 of the signal of the fifth node N5 is Vdata. The voltage value of the signal of the fifth node N5 jumps from Vinit1 to Vdata in the last stage, and the voltage value of the signal of the third node N3 also jumps under the coupling action of the second capacitor C2, VN3=Vinit2-Vth+(Vdata-Vinit1)(C2 / C1+C2), C1 being the capacitance value of the first capacitor C1 and C2 being the capacitance value of the second capacitor C2.

[0098] In the fourth stage H4, the signal of the second light emitting control line EM2 is a high level signal, and the signals of the first light emitting control line EM1, the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3 and the first scan signal line Gate1 are all low level signals. The first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the first reset transistor T7, the second reset transistor T1, the third reset transistor T2 and the data writing transistor T4 are turned off.

[0099] The first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, so that the first power voltage output by the first power line VDD is provided to the first electrode of the light emitting device EL through the turned-on first light emitting control transistor T5, the turned-on driving transistor T3 and the turned-on second light emitting control transistor T6, to drive the driving current of the light emitting device EL to emit light.

[0100] In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 of each pixel circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. The voltage value VN3 of the signal of the third node N3 is Vss+VOLED, and the signal of the first node N1 jumps under the coupling action of the first capacitor C1. The voltage value VN1 of the signal of the first node N1 is Vinit2+Vss+V OLED -[Vinit2-Vth+(Vdata-Vinit1)(C2 / C1+C2)]=Vss+V OLED +Vth-(Vdata-Vinit1)(C2 / C1+C2).

[0101] At this time, the driving current I flowing through the driving transistor T3 (also the driving current of the light emitting device EL) satisfies:

[0102] I=K*(Vgs-Vth) 2

[0103] =K*(V1-V3-Vth) 2

[0104] =K*[(Vinit1-Vdata)(C2 / C1+C2)] 2

[0105] Wherein, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the driving transistor T3.

[0106] The driving current I in the above formula is irrelevant to the first power supply voltage Vdd and the threshold voltage Vth, thereby eliminating the influence of the voltage drop of the first power supply line VDD and the threshold voltage Vth drift of the driving transistor T3 on the driving signal, and ensuring uniform display brightness and improving display effect.

[0107] In the embodiments of the present disclosure, the signal of the third initial voltage line INIT3 is provided to the fourth node N4 through the turned-on third reset transistor T2, so that the fourth node N4 is reset to the third initial voltage Vinit3, on the one hand, the drain current of the second light-emitting control transistor T6 is released from the third reset transistor T2, preventing the drain current of the second light-emitting control transistor T6 from prematurely turning on the light-emitting device; on the other hand, the signal noise generated by the jump of the second light-emitting control signal EM2 can be filtered through the third reset transistor T2, preventing the signal noise from damaging the light-emitting device.

[0108] The array substrate provided by the embodiments of the present disclosure comprises a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines and initial signal lines, the sub-pixel comprises a pixel circuit and a light-emitting device electrically connected to the pixel circuit, each scan control line is electrically connected to at least one row of pixel circuits, the scan control line comprises a first scan signal line Gate1 and a first reset control line Reset1, and the array substrate further comprises a GOA circuit group for driving the pixel circuit in rows, the GOA circuit group comprises a first GOA circuit and a second GOA circuit, wherein:

[0109] The first GOA circuit comprises a plurality of first GOA units connected in cascade, each first GOA unit is connected to one first scan signal line Gate1 and is configured to provide a first scan signal to a coupling sub-circuit 1022 in one row of pixel circuits;

[0110] The second GOA circuit comprises a plurality of second GOA units connected in cascade, each second GOA unit is connected to at least one first reset control line Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in at least one row of pixel circuits, the second GOA unit is arranged on one side of the display area and unilaterally drives the first reset control line Reset1, or each second GOA unit is connected to two or more first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two or more rows of pixel circuits.

[0111] The array substrate of the embodiments of the present disclosure can achieve the desired pixel display effect and realize a narrow frame by driving the GOA circuit connected to part of the scan control lines in a unilateral manner or in a one-to-many manner.

[0112] Exemplarily, each second GOA unit is connected with two or three first reset control lines Reset1 and configured to provide a first reset control signal to the coupled sub-circuit 1022 in two or three rows of pixel circuits.

[0113] In some exemplary embodiments, the GOA circuit group further comprises a third GOA circuit comprising a plurality of third GOA units connected in cascade, each third GOA unit being connected with at least one second reset control line Reset2 and configured to provide a second reset control signal to a second reset sub-circuit 1023 in at least one row of pixel circuits;

[0114] The third GOA unit is arranged on both sides of the display area to drive the second reset control line Reset2 from both sides.

[0115] Exemplarily, each third GOA unit is connected with two or three second reset control lines Reset2 and configured to provide a second reset control signal to the second reset sub-circuit 1023 in two or three rows of pixel circuits.

[0116] In some exemplary embodiments, the GOA circuit group further comprises a fourth GOA circuit comprising a plurality of fourth GOA units connected in cascade, each fourth GOA unit being connected with at least one third reset control line Reset3 and configured to provide a third reset control signal to a third reset sub-circuit 1024 in at least one row of pixel circuits;

[0117] The fourth GOA unit is arranged on one side of the display area to drive the third reset control line Reset3 from one side, or each fourth GOA unit is connected with two or more third reset control lines Reset3 and configured to provide a third reset control signal to the third reset sub-circuit 1024 in two or more rows of pixel circuits.

[0118] Exemplarily, each fourth GOA unit is connected with two or three third reset control lines Reset3 and configured to provide a third reset control signal to the third reset sub-circuit 1024 in two or three rows of pixel circuits.

[0119] In some exemplary embodiments, the GOA circuit group further comprises a fifth GOA circuit comprising a plurality of fifth GOA units connected in cascade, each fifth GOA unit being connected with at least one first emission control line EM1 and configured to provide a first emission control signal to a first emission control sub-circuit 1026 in at least one row of pixel circuits;

[0120] The fifth GOA unit is arranged on one side of the display area to unilaterally drive the first light-emitting control line EM1, or each fifth GOA unit is connected to two or more first light-emitting control lines EM1 and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit 1026 in two or more rows of pixel circuits.

[0121] Exemplarily, each fifth GOA unit is connected to two or three first light emitting control lines EM1 and is configured to provide a first light emitting control signal to the first light emitting control sub-circuit 1026 in two or three rows of pixel circuits.

[0122] In some exemplary embodiments, the GOA circuit group further includes: a sixth GOA circuit, the sixth GOA circuit including a plurality of sixth GOA units connected in cascade, each sixth GOA unit being connected to at least one second emission control line EM2 and configured to provide a second emission control signal to a second emission control sub-circuit in at least one row of pixel circuits;

[0123] The sixth GOA unit is arranged on one side of the display area to unilaterally drive the second light-emitting control line EM2, or each sixth GOA unit is connected to two or more second light-emitting control lines EM2 and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in two or more rows of pixel circuits.

[0124] Exemplarily, each sixth GOA unit is connected to two or three second light emitting control lines EM2 and is configured to provide the second light emitting control signal to the second light emitting control sub-circuits 1027 in two or three rows of pixel circuits.

[0125] Figures 8A to 8F They are Figure 6 Schematic diagram of the effect of the signals provided by the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first light-emitting control line EM1, the second light-emitting control line EM2, and the first scanning signal line Gate1 on the driving current under different delay times, wherein Tr represents the rising edge delay, and Tf represents the falling edge delay. When the GOA circuit connected to a certain scanning control line adopts a unilateral driving scheme, the rising edge delay and falling edge delay corresponding to the input end and the far end of the scanning control line are more different; when the GOA circuit connected to a certain scanning control line adopts a bilateral driving scheme, the left and right sides of the scanning control line are both input ends, and the far end is the center of the screen. Therefore, at this time, the rising edge delay and falling edge delay differences on the left and right sides of the scanning control line are smaller. Figures 8A to 8FAs shown, it is found through simulation that when the GOA circuits corresponding to the second reset control line Reset2 and the first scan signal line Gate1 adopt the single-side driving scheme, the driving current difference between the input position and the opposite side of the input position of the pixel is large, while when the other four groups of GOA circuits (the first emission control line EM1, the second emission control line EM2, the first reset control line Reset1, and the third reset control line Reset3) adopt the single-side driving scheme, the driving current difference between the input position and the opposite side of the input position of the pixel is small, so the four groups of GOA can adopt the single-side driving scheme.

[0126] Figure 9 For Figure 6 As shown in the simulation waveform results of the first node N1 to the fifth node N5 and the gate-source voltage Vgs when the six groups of GOA circuits corresponding to the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first emission control line EM1, the second emission control line EM2, and the first scan signal line Gate1 adopt the one-to-two driving scheme, it can be seen that, if the GOA circuits of the other several scan control lines except the first scan signal line Gate1 adopt the one-to-two driving scheme, the brightness difference between the odd and even rows will be caused in the a time range due to the voltage difference between the second node N2 and the third node N3 (at this time, the driving transistor T3 is in the open state, and the second node N2 is slowly charged to the third node N3), but this problem can be improved by lengthening the a time range. Table 1 shows Figure 9 As shown in the simulation waveform results of the first node N1 to the fifth node N5 and the gate-source voltage Vgs when the six groups of GOA circuits corresponding to the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first emission control line EM1, the second emission control line EM2, and the first scan signal line Gate1 adopt the one-to-two driving scheme, it can be seen that, if the GOA circuits of the other several scan control lines except the first scan signal line Gate1 adopt the one-to-two driving scheme, the brightness difference between the odd and even rows will be caused in the a time range due to the voltage difference between the second node N2 and the third node N3 (at this time, the driving transistor T3 is in the open state, and the second node N2 is slowly charged to the third node N3), but this problem can be improved by lengthening the a time range. Table 1 shows Figure 6 As shown in the simulation waveform results of the first node N1 to the fifth node N5 and the gate-source voltage Vgs when the six groups of GOA circuits corresponding to the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first emission control line EM1, the second emission control line EM2, and the first scan signal line Gate1 adopt the one-to-two driving scheme, it can be seen that, if the GOA circuits of the other several scan control lines except the first scan signal line Gate1 adopt the one-to-two driving scheme, the brightness difference between the odd and even rows will be caused in the a time range due to the voltage difference between the second node N2 and the third node N3 (at this time, the driving transistor T3 is in the open state, and the second node N2 is slowly charged to the third node N3), but this problem can be improved by lengthening the a time range. Table 1 shows

[0127]

[0128] Table 1

[0129] As shown in Table 1, according to the simulation results, when the a time range is lengthened to three or more pixel row scanning times, the pixel circuit of the present disclosure can be driven by the one-to-two and one-to-multiple schemes.

[0130] In some example embodiments, for each row of pixel circuits, the start writing time of the first scan signal and the end writing time of the first reset control signal are different by at least three pixel row scanning times (3H).

[0131] For example, for each row of pixel circuits, the start write time of the first scan signal is different from the end write time of the first reset control signal by four pixel row scanning times (4H).

[0132] Figures 10 to 23 FIG. 1 is a schematic diagram of a driving mode of several GOA circuits of an exemplary embodiment of the present disclosure, Figures 10 to 23 In the figure, each GOA circuit is identified by the scan control line connected thereto, for example, Gate1 in the figure represents a first GOA circuit (or a first GOA unit) connected to the first scan signal line Gate1, Reset1 in the figure represents a second GOA circuit (or a second GOA unit) connected to the first reset control line Reset1, Reset2 in the figure represents a third GOA circuit (or a third GOA unit) connected to the second reset control line Reset2, Reset3 in the figure represents a fourth GOA circuit (or a fourth GOA unit) connected to the third reset control line Reset3, EM1 in the figure represents a fifth GOA circuit (or a fifth GOA unit) connected to the first emission control line EM1, and EM2 in the figure represents a sixth GOA circuit (or a sixth GOA unit) connected to the second emission control line EM2.

[0133] As Figure 10As shown, the pixel circuit of the embodiment of the present disclosure can be driven by six groups of GOA circuits, including a first GOA circuit to a sixth GOA circuit. The first GOA circuit includes a plurality of first GOA units connected in cascade, each first GOA unit is connected with a first scan signal line Gate1 and is configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits. The second GOA circuit includes a plurality of second GOA units connected in cascade, each second GOA unit is connected with a first reset control line Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in a row of pixel circuits. The third GOA circuit includes a plurality of third GOA units connected in cascade, each third GOA unit is connected with a second reset control line Reset2 and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in a row of pixel circuits. The fourth GOA circuit includes a plurality of fourth GOA units connected in cascade, each fourth GOA unit is connected with a third reset control line Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in a row of pixel circuits. The fifth GOA circuit includes a plurality of fifth GOA units connected in cascade, each fifth GOA unit is connected with a first emission control line EM1 and is configured to provide a first emission control signal to the first emission control sub-circuit 1026 in a row of pixel circuits. The sixth GOA circuit includes a plurality of sixth GOA units connected in cascade, each sixth GOA unit is connected with a second emission control line EM2 and is configured to provide a second emission control signal to the second emission control sub-circuit 1027 in a row of pixel circuits. In the embodiment, the first GOA circuit to the sixth GOA circuit are arranged on the left and right sides of the display area, and the respective connected scan control lines are driven from both sides.

[0134] As Figure 11As shown, the pixel circuits of the embodiment of the present disclosure can be driven by five groups of GOA circuits, including a first GOA circuit, a third GOA circuit, a sixth GOA circuit, and a first GOA circuit. The first GOA circuit includes a plurality of first GOA units connected in cascade, each of which is connected to a first scan signal line Gate1 and configured to provide a first scan signal to a coupling sub-circuit 1022 in a row of pixel circuits. The third GOA circuit includes a plurality of third GOA units connected in cascade, each of which is connected to a second reset control line Reset2 and configured to provide a second reset control signal to a second reset sub-circuit 1023 in a row of pixel circuits. The fourth GOA circuit includes a plurality of fourth GOA units connected in cascade, each of which is connected to a third reset control line Reset3 and configured to provide a third reset control signal to a third reset sub-circuit 1024 in a row of pixel circuits. The fifth GOA circuit includes multiple fifth GOA units connected in cascade, each connected to a first emission control line EM1 and configured to provide a first emission control signal to the first emission control sub-circuit 1026 in a row of pixel circuits. The sixth GOA circuit includes multiple sixth GOA units connected in cascade, each connected to a second emission control line EM2 and configured to provide a second emission control signal to the second emission control sub-circuit 1027 in a row of pixel circuits. In this embodiment, the first reset control line Reset1 and the second reset control line Reset2 share a third GOA unit. The first reset control line Reset1 is driven using the advance stage of the second reset control line Reset2, thereby eliminating one set of GOA circuits. In this embodiment, the first through fifth GOA circuits are disposed on the left and right sides of the display area, providing bilateral drive for the scan control lines to which they are connected.

[0135] like Figure 12 As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can be referred to as described above and will not be repeated here. In this embodiment, the second GOA circuit is only provided on one side of the display area (e.g., the left side) and unilaterally drives the first reset control line Reset1. The third GOA circuit is also only provided on one side of the display area (e.g., the right side) and unilaterally drives the second reset control line Reset2. The first, fourth, through sixth GOA circuits are provided on the left and right sides of the display area and bilaterally drive the scan control lines connected to them. Since the second and third GOA circuits are each provided on only one side of the display area, the GOA circuit driving method of the disclosed embodiment can achieve a narrow bezel effect.

[0136] like Figure 13As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the respective connected scan control lines can refer to the foregoing description, and will not be described again here. In the embodiment, the second GOA circuit is only arranged on one side (for example, the right side) of the display area, and unilaterally drives the first reset control line Reset1. The fourth GOA circuit is also only arranged on one side (for example, the left side) of the display area, and unilaterally drives the third reset control line Reset3. The first GOA circuit, the third GOA circuit, the fifth GOA circuit and the sixth GOA circuit are arranged on the left and right sides of the display area, and bilaterally drive the respective connected scan control lines. Since the second GOA circuit and the fourth GOA circuit are respectively arranged on one side of the display area, the GOA circuit driving mode of the embodiment of the present disclosure can achieve the effect of narrow frame.

[0137] In the embodiment of the present disclosure, any one of the first GOA circuit, the fifth GOA circuit and the sixth GOA circuit can also be arranged on one side of the display area, and unilaterally drive the respective connected scan control lines, which is not limited by the present disclosure.

[0138] For example, the second GOA circuit can be arranged on one side (for example, the right side) of the display area, and unilaterally drive the first reset control line Reset1. The fifth GOA circuit is also arranged on one side (for example, the left side) of the display area, and unilaterally drives the first emission control line EM1. The first GOA circuit, the third GOA circuit, the fourth GOA circuit and the sixth GOA circuit are arranged on the left and right sides of the display area, and bilaterally drive the respective connected scan control lines.

[0139] Alternatively, the second GOA circuit can be arranged on one side (for example, the right side) of the display area, and unilaterally drive the first reset control line Reset1. The sixth GOA circuit is also arranged on one side (for example, the left side) of the display area, and unilaterally drives the second emission control line EM2. The first GOA circuit, the third GOA circuit, the fourth GOA circuit and the fifth GOA circuit are arranged on the left and right sides of the display area, and bilaterally drive the respective connected scan control lines.

[0140] Alternatively, the second GOA circuit can be arranged on one side (for example, the right side) of the display area, and unilaterally drive the first reset control line Reset1. The first GOA circuit is also arranged on one side (for example, the left side) of the display area, and unilaterally drives the first scan signal line Gate1. The third GOA circuit to the sixth GOA circuit are arranged on the left and right sides of the display area, and bilaterally drive the respective connected scan control lines.

[0141] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, and the third GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the second reset control line Reset2. The first GOA circuit to the second GOA circuit and the fourth GOA circuit to the fifth GOA circuit are set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them.

[0142] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, and the fourth GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the third reset control line Reset3. The first to third GOA circuits and the fifth GOA circuit are set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them.

[0143] Alternatively, the sixth GOA circuit can be arranged only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, and the fifth GOA circuit can also be arranged only on one side of the display area (such as the left side) to perform unilateral driving on the first light-emitting control line EM1. The first to fourth GOA circuits are arranged on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them.

[0144] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, the first GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the first scanning signal line Gate1, and the second to fifth GOA circuits can be set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them.

[0145] like Figure 14 As shown, the pixel circuit of the disclosed embodiment is driven by five groups of GOA circuits. The correspondence between the five groups of GOA circuits and the scan control lines to which they are connected can be referred to as previously described and will not be repeated here. In this embodiment, the sixth GOA circuit is only provided on one side of the display area (e.g., the right side) to unilaterally drive the second emission control line EM2. The fourth GOA circuit is also only provided on one side of the display area (e.g., the left side) to unilaterally drive the third reset control line Reset3. The first, third, and fifth GOA circuits are provided on the left and right sides of the display area to bilaterally drive the scan control lines to which they are connected. Because the first reset control line Reset1 and the second reset control line Reset2 share the third GOA circuit, and the fourth and sixth GOA circuits are each provided on only one side of the display area, the GOA circuit driving method of the disclosed embodiment can achieve a narrow bezel effect.

[0146] In the embodiments of the present disclosure, any one group of GOA circuits in the second GOA circuit, the fourth GOA circuit to the sixth GOA circuit can be unilaterally driven, so that the effect of narrow frame can be achieved.

[0147] As shown in FIG. 1, the pixel circuit in the embodiments of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the respective connected scan control lines can be referred to the foregoing description, which will not be described here. In the embodiments, the six groups of GOA circuits are respectively arranged on one side of the display area, and the respective connected scan control lines are unilaterally driven, so that the effect of narrow frame can be achieved. Figure 15 As shown in FIG. 2, the pixel circuit in the embodiments of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the respective connected scan control lines can be referred to the foregoing description, which will not be described here. In the embodiments, the six groups of GOA circuits are respectively arranged on the left and right sides of the display area, and the respective connected scan control lines are bilaterally driven. In the embodiments, each first GOA unit is connected with a first scan signal line Gate1 and configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits, each second GOA unit is connected with two first reset control lines Reset1 and configured to provide a first reset control signal to the coupling sub-circuit 1022 in two rows of pixel circuits, each third GOA unit is connected with two second reset control lines Reset2 and configured to provide a second reset control signal to the second reset sub-circuit 1023 in two rows of pixel circuits, each fourth GOA unit is connected with two third reset control lines Reset3 and configured to provide a third reset control signal to the third reset sub-circuit 1024 in two rows of pixel circuits, each fifth GOA unit is connected with two first emission control lines EM1 and configured to provide a first emission control signal to the first emission control sub-circuit 1026 in two rows of pixel circuits, and each sixth GOA unit is connected with two second emission control lines EM2 and configured to provide a second emission control signal to the second emission control sub-circuit 1027 in two rows of pixel circuits. Since the second GOA circuit to the sixth GOA circuit are all driven in one-to-two mode, the arrangement space of the GOA circuit in the column direction is larger, and the space in the row direction can be compressed, so that the effect of narrow frame can be achieved.

[0148] Figure 16 As shown in FIG. 2, the pixel circuit in the embodiments of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the respective connected scan control lines can be referred to the foregoing description, which will not be described here. In the embodiments, the six groups of GOA circuits are respectively arranged on the left and right sides of the display area, and the respective connected scan control lines are bilaterally driven. In the embodiments, each first GOA unit is connected with a first scan signal line Gate1 and configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits, each second GOA unit is connected with two first reset control lines Reset1 and configured to provide a first reset control signal to the coupling sub-circuit 1022 in two rows of pixel circuits, each third GOA unit is connected with two second reset control lines Reset2 and configured to provide a second reset control signal to the second reset sub-circuit 1023 in two rows of pixel circuits, each fourth GOA unit is connected with two third reset control lines Reset3 and configured to provide a third reset control signal to the third reset sub-circuit 1024 in two rows of pixel circuits, each fifth GOA unit is connected with two first emission control lines EM1 and configured to provide a first emission control signal to the first emission control sub-circuit 1026 in two rows of pixel circuits, and each sixth GOA unit is connected with two second emission control lines EM2 and configured to provide a second emission control signal to the second emission control sub-circuit 1027 in two rows of pixel circuits. Since the second GOA circuit to the sixth GOA circuit are all driven in one-to-two mode, the arrangement space of the GOA circuit in the column direction is larger, and the space in the row direction can be compressed, so that the effect of narrow frame can be achieved.

[0149] In the embodiments, the nth second GOA unit is arranged on the left and right sides of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels.

[0150] ​The nth third GOA unit is arranged on the left and right sides of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a second reset control signal to a second reset sub-circuit 1023 in the pixel circuit of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels;

[0151] The nth fourth GOA unit is arranged on the left and right sides of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a third reset control signal to a third reset sub-circuit 1024 in the pixel circuit of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels;

[0152] The nth fifth GOA unit is arranged on the left and right sides of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a first light-emitting control signal to a first light-emitting control sub-circuit 1026 in the pixel circuit of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels;

[0153] The nth sixth GOA unit is arranged on the left and right sides of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a second light-emitting control signal to a second light-emitting control sub-circuit 1027 in the pixel circuit of the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels.

[0154] In the embodiments of the present disclosure, in the second GOA circuit to the sixth GOA circuit, part of the GOA circuits can be driven in one-to-one mode, and part of the GOA circuits can be driven in one-to-two mode. For example, any four groups of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other group of GOA circuits can be driven in one-to-one mode. Alternatively, any three groups of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other two groups of GOA circuits can be driven in one-to-one mode. Alternatively, any two groups of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other three groups of GOA circuits can be driven in one-to-one mode. Alternatively, any one group of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other four groups of GOA circuits can be driven in one-to-one mode.

[0155] In the embodiments of the present disclosure, in the second GOA circuit to the sixth GOA circuit, part of the GOA circuits can be driven in one-to-one mode, and part of the GOA circuits can be driven in one-to-two mode. For example, any four groups of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other group of GOA circuits can be driven in one-to-one mode. Alternatively, any three groups of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other two groups of GOA circuits can be driven in one-to-one mode. Alternatively, any two groups of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other three groups of GOA circuits can be driven in one-to-one mode. Alternatively, any one group of GOA circuits in the second GOA circuit to the sixth GOA circuit can be driven in one-to-two mode, and the other four groups of GOA circuits can be driven in one-to-one mode.

[0156] For example, Figure 17As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can be referred to as described above and will not be repeated here. In this embodiment, the first, fourth, through sixth groups of GOA circuits are each disposed on the left and right sides of the display area, respectively, to drive the scan control lines connected to them on both sides. The second, second, and third groups of GOA circuits are each disposed on only one side of the display area, to drive the scan control lines connected to them on one side. Among them, each first GOA unit is connected to a first scanning signal line Gate1, and is configured to provide a first scanning signal to the coupling sub-circuit 1022 in a row of pixel circuits, each second GOA unit is connected to two first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the two rows of pixel circuits, each third GOA unit is connected to two second reset control lines Reset2, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the two rows of pixel circuits, each fourth GOA unit is connected to two third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the two rows of pixel circuits, each fifth GOA unit is connected to a first light-emitting control line EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit 1026 in a row of pixel circuits, and each sixth GOA unit is connected to two second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the two rows of pixel circuits. Since the second GOA circuit to the third GOA circuit adopt unilateral driving, and the second GOA circuit to the fourth GOA circuit and the sixth GOA circuit adopt a one-drive-two driving method, a narrow frame effect can be achieved.

[0157] In the embodiment of the present disclosure, in the second to sixth GOA circuits, some or all of the GOA circuits may be driven in a one-drive-three manner to achieve a narrow frame effect.

[0158] For example, Figure 18As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the respective connected scan control lines can refer to the foregoing description, and will not be described here. In this embodiment, the first GOA circuit to the sixth GOA circuit in the six groups of GOA circuits are respectively arranged on the left and right sides of the display area, and drive the respective connected scan control lines from both sides. Among them, each first GOA unit is connected with a first scan signal line Gate1, configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits, each second GOA unit is connected with three first reset control lines Reset1, configured to provide a first reset control signal to the coupling sub-circuit 1022 in three rows of pixel circuits, each third GOA unit is connected with three second reset control lines Reset2, configured to provide a second reset control signal to the second reset sub-circuit 1023 in three rows of pixel circuits, each fourth GOA unit is connected with three third reset control lines Reset3, configured to provide a third reset control signal to the third reset sub-circuit 1024 in three rows of pixel circuits, each fifth GOA unit is connected with three first emission control lines EM1, configured to provide a first emission control signal to the first emission control sub-circuit 1026 in three rows of pixel circuits, and each sixth GOA unit is connected with three second emission control lines EM2, configured to provide a second emission control signal to the second emission control sub-circuit 1027 in three rows of pixel circuits. Since the second GOA circuit to the sixth GOA circuit are all driven in one-to-three mode, the arrangement space of the GOA circuit in the column direction becomes larger, and the space in the row direction can be compressed, so that the effect of narrow frame can be achieved.

[0159] In this embodiment, the nth second GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0160] The nth third GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0161] The nth fourth GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0162] The nth fifth GOA unit is arranged on the left and right sides of the 3n-2nd row sub-pixel, the 3n-1st row sub-pixel and the 3nth row sub-pixel, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuit of the 3n-2nd row sub-pixel, the 3n-1st row sub-pixel and the 3nth row sub-pixel;

[0163] The nth sixth GOA unit is arranged on the left and right sides of the 3n-2th row sub-pixel, the 3n-1th row sub-pixel and the 3nth row sub-pixel, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 3n-2th row sub-pixel, the 3n-1th row sub-pixel and the 3nth row sub-pixel.

[0164] In the embodiment of the present disclosure, two or more GOA circuits in the second to sixth GOA circuits may be placed in columns to achieve a narrow frame effect.

[0165] For example, Figure 19 As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can be referred to as described above and will not be repeated here. In this embodiment, the first to sixth GOA circuits of the six groups of GOA circuits are respectively arranged on the left and right sides of the display area, and perform unilateral or bilateral driving on the scan control lines connected to them. Among them, each first GOA unit is connected to a first scan signal line Gate1, and is configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits, each second GOA unit is connected to three first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the three rows of pixel circuits, each third GOA unit is connected to three second reset control lines Reset2, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the three rows of pixel circuits, each fourth GOA unit is connected to three third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the three rows of pixel circuits, each fifth GOA unit is connected to three first light-emitting control lines EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit 1026 in the three rows of pixel circuits, and each sixth GOA unit is connected to three second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the three rows of pixel circuits. In this embodiment, the second to fourth GOA circuits on the left and / or right sides can be placed in columns. Since the second to sixth GOA circuits are all driven in a one-drive-three mode, and the second to fourth GOA circuits are arranged in a column, the arrangement space of the GOA circuits in the column direction and the row direction is increased, and a narrow frame effect can be achieved.

[0166] In this embodiment, the 2n-1th second GOA unit is arranged at the left side of the 6n-5th row of sub-pixels and the 6n-4th row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 6n-5th row, the 6n-3rd row and the 6n-1th row; and the 2nth second GOA unit is arranged at the right side of the 6n-5th row of sub-pixels and the 6n-4th row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 6n-4th row, the 6n-2nd row and the 6nth row.

[0167] The 2n-1th third GOA unit is arranged at the left side of the 6n-3rd row of sub-pixels and the 6n-2nd row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuit of the 6n-5th row, the 6n-3rd row and the 6n-1th row; and the 2nth third GOA unit is arranged at the right side of the 6n-3rd row of sub-pixels and the 6n-2nd row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuit of the 6n-4th row, the 6n-2nd row and the 6nth row.

[0168] The 2n-1th fourth GOA unit is arranged at the left side of the 6n-1th row of sub-pixels and the 6nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuit of the 6n-5th row, the 6n-3rd row and the 6n-1th row; and the 2nth fourth GOA unit is arranged at the right side of the 6n-1th row of sub-pixels and the 6nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuit of the 6n-4th row, the 6n-2nd row and the 6nth row.

[0169] The nth fifth GOA unit is arranged at the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit 1026 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels.

[0170] The nth sixth GOA unit is arranged at the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, wherein n is a natural number greater than or equal to 1.

[0171] For example, Figure 20As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the respective connected scan control lines can refer to the foregoing description, and will not be described here. In this embodiment, the second GOA circuit to the fourth GOA circuit on the left side and the right side are placed in one column, and the second GOA circuit to the fourth GOA circuit all adopt a double-side driving scheme. Since the second GOA circuit to the sixth GOA circuit are all driven by a one-to-three mode and a double-side driving mode, and the second GOA circuit to the fourth GOA circuit are respectively placed in one column, the arrangement space of the GOA circuit in the column direction and the row direction is larger, which can achieve the effect of narrow frame while ensuring the display effect of the pixel.

[0172] In this embodiment, the nth third GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0173] The nth fourth GOA unit is arranged on the left and right sides of the 3n-1th row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1023 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0174] The nth second GOA unit is arranged on the left and right sides of the 3nth row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0175] The nth fifth GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit 1026 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels;

[0176] The nth sixth GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, wherein n is a natural number greater than or equal to 1.

[0177] In the embodiment of the present disclosure, Figure 19 and Figure 20The arrangement order of the second GOA unit, the third GOA unit and the fourth GOA unit in the column direction can be set as needed, and the present disclosure does not limit this. By arranging the second GOA unit, the third GOA unit and the fourth GOA unit in one column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0178] For example, Figure 21 As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can be referred to as described above and will not be repeated here. In this embodiment, the second to fourth GOA circuits on the left and / or right sides are placed in a column, and the fifth to sixth GOA circuits on the left and / or right sides are placed in a column. Since the second to sixth GOA circuits are all driven by a one-drive-three method, and the second to fourth GOA circuits and the fifth to sixth GOA circuits are respectively placed in a column, the arrangement space of the GOA circuits in the column direction and the row direction is increased, and a narrow frame effect can be achieved.

[0179] In this embodiment, the connection method from the second GOA unit to the fourth GOA unit is as described above. Figure 19 The description is not repeated here.

[0180] In this embodiment, the 2n-1th fifth GOA unit is arranged on the left side of the sub-pixels in the 6n-5th row, the 6n-4th row, and the 6n-3th row, and is configured to provide the first light-emitting control signal to the first light-emitting control sub-circuit 1026 in the pixel circuits in the 6n-5th row, the 6n-3th row, and the 6n-1th row. The 2nth second GOA unit is arranged on the right side of the sub-pixels in the 6n-5th row, the 6n-4th row, and the 6n-3th row, and is configured to provide the first light-emitting control signal to the first light-emitting control sub-circuit 1026 in the pixel circuits in the 6n-4th row, the 6n-2th row, and the 6nth row.

[0181] The 2n-1th sixth GOA unit is set on the left side of the 6n-2th row sub-pixel, the 6n-1th row sub-pixel and the 6nth row sub-pixel, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 6n-5th row, the 6n-3th row and the 6n-1th row, and the 2nth sixth GOA unit is set on the right side of the 6n-2th row sub-pixel, the 6n-1th row sub-pixel and the 6nth row sub-pixel, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 6n-4th row, the 6n-2th row and the 6nth row.

[0182] In the embodiment of the present disclosure, the arrangement order of the fifth GOA unit and the sixth GOA unit in the column direction can be set as required, and the present disclosure does not limit this. By setting the second GOA unit, the third GOA unit and the fourth GOA unit in the same column and setting the fifth GOA unit and the sixth GOA unit in the same column, the arrangement space in the row direction can be saved, so that the effect of narrow frame can be achieved.

[0183] As shown in the example, Figure 22 The pixel circuit of the embodiment of the present disclosure adopts six groups of GOA circuit driving, and the corresponding relationship between the six groups of GOA circuit and the respective connected scan control lines can refer to the foregoing description, which will not be described here. In the embodiment, the second GOA circuit to the fourth GOA circuit on the left side and the right side are placed in one column, and the fifth GOA circuit to the sixth GOA circuit on the left side and the right side are placed in one column. Since the second GOA circuit to the sixth GOA circuit all adopt the one-drive-three mode and are driven in the double-side mode, and the second GOA circuit to the fourth GOA circuit and the fifth GOA circuit to the sixth GOA circuit are respectively placed in one column, the arrangement space of the GOA circuit in the column direction and the row direction is increased, so that the effect of narrow frame can be achieved.

[0184] In the embodiment, the connection mode of the second GOA unit to the fourth GOA unit can refer to the description in the foregoing Figure 20 , which will not be described here.

[0185] In the embodiment, the nth fifth GOA unit and the nth sixth GOA unit are arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, the nth fifth GOA unit and the nth sixth GOA unit on the left and right sides are arranged in one column respectively, the nth fifth GOA unit is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and the nth sixth GOA unit is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels.

[0186] In the embodiment of the present disclosure, the arrangement order of the fifth GOA unit and the sixth GOA unit in the column direction can be set as required, and the present disclosure does not limit this. By setting the second GOA unit, the third GOA unit and the fourth GOA unit in the same column and setting the fifth GOA unit and the sixth GOA unit in the same column, the arrangement space in the row direction can be saved, so that the effect of narrow frame can be achieved.

[0187] In the embodiments of the present disclosure, in the first GOA circuit to the sixth GOA circuit, some GOA circuits can be driven in one-to-one mode, some GOA circuits can be driven in one-to-two mode, and some GOA circuits can be driven in one-to-three mode, so as to achieve the effect of narrow frame.

[0188] As shown in the example, Figure 23 As shown in the example, In the embodiments of the present disclosure, the first GOA circuit to the sixth GOA circuit are respectively arranged on the left and right sides of the display area, and drive the scanning control lines connected thereto from both sides. The first GOA circuit is driven in one-to-one mode, the second GOA circuit to the fourth GOA circuit are driven in one-to-two mode, and the fifth GOA circuit to the sixth GOA circuit are driven in one-to-three mode, so as to achieve the effect of narrow frame.

[0189] In the embodiments of the present disclosure, in addition to the first GOA circuit, other groups of GOA circuits can also be designed to be driven in one-to-one mode, so as to ensure the display effect of the pixel and achieve the effect of narrow frame at the same time.

[0190] Figure 24 As shown in the example, Figures 18 to 22 As shown in the example, Figure 24 As shown in the example, for each row of pixel circuits, the start writing time of the first scanning signal and the end writing time of the first reset control signal are different by three or more than three pixel row scanning times (for example, a=3H or a=4H).

[0191] The embodiments of the present disclosure also provide a display panel comprising the array substrate as described in any of the embodiments of the present disclosure.

[0192] The embodiments of the present disclosure also provide a display device comprising the display panel as described in any of the embodiments of the present disclosure.

[0193] In the example embodiments, the display device can be any product or component with display function, such as wearable device, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

[0194] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0195] For clarity, in the drawings used to describe the embodiments of the disclosure, the thickness and size of layers or microstructures are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0196] Although the disclosed embodiments of the present disclosure are as described above, the content described is merely an embodiment adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate includes a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines, and initial signal lines. The sub-pixels include pixel circuits and light-emitting devices electrically connected to the pixel circuits. Each scan control line is electrically connected to at least one row of pixel circuits. The scan control lines include a first scan signal line and a first reset control line. The array substrate also includes a GOA circuit group that drives the pixel circuits in rows. The GOA circuit group includes: a first GOA circuit and a second GOA circuit, wherein: The pixel circuit includes a first node, a second node, a third node, a driving subcircuit, and a coupling subcircuit. The driving subcircuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to provide a driving signal to the third node under the control of signals from the first node and the second node. The coupling subcircuit is connected to a first scan signal line, a first reset control line, a data signal line, a first initial signal line, and the third node, respectively, and is configured to couple the signal of the first initial signal line to the third node under the control of a first reset control signal provided by the first reset control line, and to couple the signal of the data signal line to the third node under the control of a first scan signal provided by the first scan signal line. The first GOA circuit includes a plurality of first GOA units connected in cascade, each of the first GOA units is connected to a first scan signal line and is configured to provide a first scan signal to a coupling sub-circuit in a row of pixel circuits; The second GOA circuit includes a plurality of second GOA units connected in cascade, and the second GOA units are arranged on one side of the display area to unilaterally drive the first reset control line, or each second GOA unit is connected to two or more first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in two or more rows of pixel circuits.

2. The array substrate according to claim 1, wherein: For each row of pixel circuits, a difference between a start time of writing the first scanning signal and an end time of writing the first reset control signal is at least a scanning time of three pixel rows.

3. The array substrate according to claim 2, wherein: For each row of pixel circuits, a difference between a start time of writing the first scanning signal and an end time of writing the first reset control signal is a scanning time of four pixel rows.

4. The array substrate according to claim 1, wherein: The scanning control line further includes a second reset control line, and the pixel circuit further includes a second reset sub-circuit, the second reset sub-circuit being electrically connected to the second reset control line, the second initial signal line, and the first node, respectively, and being configured to provide a signal of the second initial signal line to the first node under the control of a second reset control signal provided by the second reset control line; The first reset control line connected to the pixel circuits in the i-th row is the second reset control line connected to the pixel circuits in the (i-1)th row, where i is a natural number greater than 1.

5. The array substrate according to claim 1, wherein: The scanning control line further includes a second reset control line, and the pixel circuit further includes a second reset sub-circuit, the second reset sub-circuit being electrically connected to the second reset control line, the second initial signal line, and the first node, respectively, and being configured to provide a signal of the second initial signal line to the first node under the control of a second reset control signal provided by the second reset control line; The GOA circuit group further includes: a third GOA circuit, the third GOA circuit including a plurality of third GOA units connected in cascade, each of the third GOA units being connected to at least one second reset control line and configured to provide a second reset control signal to a second reset sub-circuit in at least one row of pixel circuits; The third GOA unit is disposed on the left and right sides of the display area to perform bilateral driving on the second reset control line.

6. The array substrate according to claim 5, wherein: The scanning control line further includes a third reset control line, and the pixel circuit further includes a third reset sub-circuit, the third reset sub-circuit being electrically connected to the third reset control line, the third initial signal line, and the anode of the light-emitting device, respectively, and being configured to reset the anode of the light-emitting device using a signal of the third initial signal line under the control of a third reset control signal provided by the third reset control line; The GOA circuit group further includes: a fourth GOA circuit, the fourth GOA circuit including a plurality of fourth GOA units connected in cascade, each of the fourth GOA units being connected to at least one third reset control line and configured to provide a third reset control signal to a third reset sub-circuit in at least one row of pixel circuits; The fourth GOA unit is arranged on one side of the display area to unilaterally drive the third reset control line, or each of the fourth GOA units is connected to two or more third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuit in two or more rows of pixel circuits.

7. The array substrate according to claim 6, wherein: Each of the second GOA units is connected to three of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in the three rows of pixel circuits; Each of the third GOA units is connected to three of the second reset control lines and is configured to provide the second reset control signal to the second reset sub-circuits in the three rows of pixel circuits; Each of the fourth GOA units is connected to three of the third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuits in the three rows of pixel circuits.

8. The array substrate according to claim 7, wherein: The 2n-1th second GOA unit, the 2n-1th third GOA unit and the 2n-1th fourth GOA unit are arranged in a row to the left of the sub-pixels in the 6n-5th row to the 6nth row, the 2n-1th second GOA unit is configured to provide a first reset control signal to the coupling sub-circuit in the pixel circuits in the 6n-5th row, the 6n-3th row and the 6n-1th row, the 2n-1th third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuits in the 6n-5th row, the 6n-3th row and the 6n-1th row, and the 2n-1th fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuits in the 6n-5th row, the 6n-3th row and the 6n-1th row; The 2nth second GOA unit, the 2nth third GOA unit and the 2nth fourth GOA unit are arranged in a row on the right side of the sub-pixels in the 6n-5th row to the 6nth row, the 2nth second GOA unit is configured to provide a first reset control signal to the coupling sub-circuit in the pixel circuits in the 6n-4th row, the 6n-2th row and the 6nth row, the 2nth third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuits in the 6n-4th row, the 6n-2th row and the 6nth row, and the 2nth fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuits in the 6n-4th row, the 6n-2th row and the 6nth row, wherein n is a natural number greater than or equal to 1.

9. The array substrate according to claim 7, wherein: The nth second GOA unit, the nth third GOA unit and the nth fourth GOA unit are arranged on the left and right sides of the 3n-2 row sub-pixels to the 3n row sub-pixels, and the nth second GOA unit, the nth third GOA unit and the nth fourth GOA unit on the left and right sides are arranged in a row respectively, and the nth second GOA unit is configured to provide a first reset control signal to the coupling sub-circuit in the pixel circuit of the 3n-2 row sub-pixels, the 3n-1 row sub-pixels and the 3n row sub-pixels, the nth third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuit of the 3n-2 row sub-pixels, the 3n-1 row sub-pixels and the 3n row sub-pixels, and the nth fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuit of the 3n-2 row sub-pixels, the 3n-1 row sub-pixels and the 3n row sub-pixels.

10. The array substrate according to claim 6, wherein: Each of the second GOA units is connected to two of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in the two rows of pixel circuits; Each of the third GOA units is connected to two of the second reset control lines and is configured to provide the second reset control signal to the second reset sub-circuits in the two rows of pixel circuits; Each of the fourth GOA units is connected to two of the third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuits in two rows of pixel circuits.

11. The array substrate according to claim 1, wherein: The scan control line further includes a first light-emitting control line and a second light-emitting control line, and the pixel circuit further includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein the first light-emitting control subcircuit is electrically connected to the first light-emitting control line, the first power line, and the second node, respectively, and is configured to provide a signal of the first power line to the second node under the control of a first light-emitting control signal provided by the first light-emitting control line; and the second light-emitting control subcircuit is electrically connected to the second light-emitting control line, the third node, and the anode of the light-emitting device, respectively, and is configured to conduct electricity between the third node and the anode of the light-emitting device under the control of a second light-emitting control signal provided by the second light-emitting control line; The GOA circuit group further includes: a fifth GOA circuit and a sixth GOA circuit, the fifth GOA circuit including a plurality of fifth GOA units connected in cascade, each of the fifth GOA units being connected to at least one first light emission control line and configured to provide a first light emission control signal to a first light emission control sub-circuit in at least one row of pixel circuits; The sixth GOA circuit includes a plurality of sixth GOA units connected in cascade, each of the sixth GOA units is connected to at least one second light emitting control line, and is configured to provide a second light emitting control signal to the second light emitting control sub-circuit in at least one row of pixel circuits; The fifth GOA unit is arranged at one side of the display area to unilaterally drive the first light-emitting control line, or each of the fifth GOA units is connected to two or more first light-emitting control lines and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuits in two or more rows of pixel circuits; The sixth GOA unit is arranged on one side of the display area to unilaterally drive the second light-emitting control line, or each of the sixth GOA units is connected to two or more second light-emitting control lines and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in two or more rows of pixel circuits.

12. The array substrate according to claim 11, wherein: The 2n-1th fifth GOA unit and the 2n-1th sixth GOA unit are arranged in a row to the left of the 6n-5th to 6nth row sub-pixels, the 2n-1th fifth GOA unit is configured to provide a first light-emitting control sub-circuit in the pixel circuit of the 6n-5th, 6n-3th and 6n-1th row sub-pixels, and the 2n-1th sixth GOA unit is configured to provide a second light-emitting control sub-circuit in the pixel circuit of the 6n-5th, 6n-3th and 6n-1th row sub-pixels; The 2nth fifth GOA unit and the 2nth sixth GOA unit are arranged in a row on the left side of the 6n-5th row sub-pixels to the 6nth row sub-pixels, and the 2nth fifth GOA unit is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in the pixel circuit of the 6n-4th row sub-pixels, the 6n-2th row sub-pixels and the 6nth row sub-pixels, and the 2nth sixth GOA unit is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in the pixel circuit of the 6n-4th row sub-pixels, the 6n-2th row sub-pixels and the 6nth row sub-pixels, wherein n is a natural number greater than or equal to 1.

13. The array substrate according to claim 11, wherein: The nth fifth GOA unit and the nth sixth GOA unit are arranged on the left and right sides of the 3n-2th row sub-pixel, the 3n-1th row sub-pixel and the 3nth row sub-pixel, and the nth fifth GOA unit and the nth sixth GOA unit on the left and right sides are arranged in a column respectively, and the nth fifth GOA unit is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in the pixel circuit of the 3n-2th row sub-pixel, the 3n-1th row sub-pixel and the 3nth row sub-pixel, and the nth sixth GOA unit is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in the pixel circuit of the 3n-2th row sub-pixel, the 3n-1th row sub-pixel and the 3nth row sub-pixel, wherein n is a natural number greater than or equal to 1.

14. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 13.

15. A display device, characterized in that: include: The display panel as claimed in claim 14.

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