Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises at least one pixel circuit which comprises a driving transistor, a first capacitor and a second capacitor; the first grid electrode of the driving transistor is connected with the first capacitor, and the first capacitor is used for storing the voltage of the first grid electrode of the driving transistor; a first electrode of the driving transistor is connected with the second capacitor, the second capacitor is used for coupling data voltage to a first grid electrode of the driving transistor, the capacitance value of the second capacitor is larger than that of the first capacitor, the capacitance value of the second capacitor is larger than that of the first capacitor, and the capacitance value of the second capacitor is larger than that of the second grid electrode of the driving transistor. The writing range of data voltage is reduced, the difference of display brightness is improved, and the display uniformity is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements for display quality. However, the display effect of existing display panels is poor and cannot meet the high-quality display requirements. Summary of the invention

[0003] The present invention provides a display panel and a display device, which can reduce the writing range of data voltage, improve the difference of display brightness, and enhance the uniformity of display.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] at least one pixel circuit, the pixel circuit comprising a driving transistor, a first capacitor and a second capacitor;

[0006] The first gate of the driving transistor is connected to the first capacitor, and the first capacitor is used to store the voltage of the first gate of the driving transistor; the first electrode of the driving transistor is connected to the second capacitor, and the second capacitor is used to couple the data voltage to the first gate of the driving transistor, wherein the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

[0007] Optionally, the ratio of the capacitance value of the second capacitor to the capacitance value of the first capacitor is in a range of 1.2-2.4;

[0008] Optionally, a capacitance ratio of the second capacitor to the first capacitor is in a range of 1.6-2.0;

[0009] Optionally, a capacitance ratio of the second capacitor to the first capacitor is 1.8;

[0010] Optionally, the capacitance value of the first capacitor ranges from 50f to 100f; the capacitance value of the second capacitor ranges from 80f to 200f.

[0011] Optionally, the display panel further includes:

[0012] substrate;

[0013] a first conductive layer and a second conductive layer, wherein the first conductive layer is located on one side of the substrate, and the second conductive layer is located on a side of the first conductive layer away from the substrate;

[0014] The first electrode plate of the first capacitor is located in the first conductive layer, and the second electrode plate of the first capacitor is located in the second conductive layer; the first electrode plate of the second capacitor is located in the first conductive layer, and the second electrode plate of the second capacitor is located in the second conductive layer;

[0015] An overlapping area of ​​an orthographic projection of the first electrode plate of the second capacitor on the substrate and an orthographic projection of the second electrode plate of the second capacitor on the substrate is greater than an overlapping area of ​​an orthographic projection of the first electrode plate of the first capacitor on the substrate and an orthographic projection of the second electrode plate of the first capacitor on the substrate;

[0016] Preferably, the first plate of the first capacitor and / or the second plate of the first capacitor include a hole area, and an overlapping position of an orthographic projection of the first plate of the first capacitor on the substrate and an orthographic projection of the second plate of the first capacitor on the substrate at least partially covers the orthographic projection of the hole area on the substrate.

[0017] Optionally, the first gate of the driving transistor is located in the second conductive layer, and the second plate of the first capacitor is reused as the first gate of the driving transistor;

[0018] Optionally, a minimum distance between an orthographic projection of the second plate of the first capacitor on the substrate and an orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the substrate is greater than or equal to 3 μm.

[0019] Optionally, the orthographic projection of the first plate of the second capacitor on the substrate at least covers the orthographic projection of the second plate of the second capacitor on the substrate; the minimum distance between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first plate of the second capacitor on the substrate is greater than or equal to 3 μm.

[0020] Optionally, the display panel further includes:

[0021] a first active layer, the first active layer is located on a side of the second conductive layer away from the substrate, and the first active layer extends along a first direction; a third conductive layer, the third conductive layer is located on a side of the first active layer away from the substrate, the driving transistor comprises a second gate, the second gate is located in the third conductive layer, and the second gate of the driving transistor is connected to the second electrode of the driving transistor;

[0022] The portion of the first active layer located below the orthographic projection of the second gate of the driving transistor is the channel region of the driving transistor, and the orthographic projection of the second plate of the first capacitor on the substrate at least covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0023] Optionally, in the first direction, the orthographic projection of the second plate of the first capacitor on the substrate exceeds the orthographic projection of the channel region of the driving transistor on the substrate by at least a first length dimension;

[0024] Optionally, the first length dimension ranges from 0.4 μm to 2 μm;

[0025] Optionally, the first length dimension is 1 μm;

[0026] Optionally, in a second direction, the orthographic projection of the second plate of the first capacitor on the substrate exceeds the orthographic projection of the channel region of the driving transistor on the substrate by at least a second length dimension; the second direction is perpendicular to the first direction;

[0027] Optionally, the second length dimension ranges from 2 μm to 4 μm;

[0028] Optionally, the second length dimension is 3 μm.

[0029] Optionally, an orthographic projection of the first plate of the first capacitor on the substrate at least partially covers an orthographic projection of the channel region of the driving transistor on the substrate.

[0030] Optionally, the orthographic projection of the second gate of the driving transistor on the substrate at least covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0031] Optionally, the orthographic projection of the second plate of the first capacitor on the substrate at least covers the orthographic projection of the second gate of the driving transistor on the substrate.

[0032] Optionally, the display panel further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, the fourth conductive layer includes a first connecting line, and the second gate of the driving transistor is connected to the second electrode of the driving transistor through the first connecting line;

[0033] Optionally, the second gate of the driving transistor is connected to one end of the first connecting line through a first via hole, and the first electrode of the driving transistor is connected to the other end of the first connecting line through the second via hole;

[0034] Optionally, an orthographic projection of the first connecting line on the substrate at least partially covers an orthographic projection of the second gate of the driving transistor on the substrate.

[0035] Optionally, the display panel further includes:

[0036] a first active layer, the first active layer being located on a side of the second conductive layer away from the substrate, and the first active layer extending along a first direction;

[0037] a third conductive layer, the third conductive layer being located on a side of the first active layer away from the substrate, and the first gate of the driving transistor being located on the third conductive layer; wherein a portion of the first active layer located below the orthographic projection of the first gate of the driving transistor is a channel region of the driving transistor;

[0038] Optionally, an orthographic projection of the first gate of the driving transistor on the substrate at least partially covers an orthographic projection of the channel region of the driving transistor on the substrate;

[0039] Optionally, an orthographic projection of the second plate of the first capacitor on the substrate does not overlap with an orthographic projection of the channel region of the driving transistor on the substrate.

[0040] Optionally, an orthographic projection of the first plate of the first capacitor on the substrate at least partially covers an orthographic projection of the channel region of the driving transistor on the substrate.

[0041] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in any embodiment of the present invention.

[0042] In the display panel provided by the embodiment of the present invention, the data voltage range corresponding to the writing of the display panel from the highest brightness to the black state will be related to the capacitance value c1 of the first capacitor C1 and the capacitance value c2 of the second capacitor C2. By setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1, the data voltage range corresponding to the writing of the display panel from the highest brightness to the black state can be reduced, which is beneficial for the driving chip to provide a more accurate data voltage and reduce the floating of the data voltage, thereby improving the difference in display brightness and improving the uniformity of the display. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0044] Figure 2 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0046] Figure 4 for Figure 3 The cross-sectional structure diagram of the display panel along the cutting line AA' is shown;

[0047] Figure 5 A schematic diagram of a layout structure of a first capacitor provided in an embodiment of the present invention;

[0048] Figure 6 A schematic diagram of a layout structure of another first capacitor provided in an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of a layout structure of another first capacitor provided in an embodiment of the present invention;

[0050] Figure 8 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0051] Fig. 9 for Figure 8 The cross-sectional structure diagram of the display panel along the cutting line BB' is shown;

[0052] Fig.10 For the reason Figure 8 The cross-sectional structure diagram of the display panel along the cutting line CC' is shown;

[0053] Fig.11 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0054] Fig.12 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0055] Fig.13 for Fig.12 The cross-sectional structure diagram of the display panel along the cutting line DD' is shown;

[0056] Fig.14 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] Due to the low mobility of Indium Gallium Zinc Oxide (IGZO) transistors, the threshold voltage compensation process in the pixel circuit takes a long time to be fully completed, which is not conducive to the application of high refresh rate and high resolution display panels. At present, by separating the data writing and threshold voltage compensation processes, the threshold voltage compensation process can be accelerated, but the corresponding pixel circuit will also cause the range of the provided data voltage to increase and the brightness uniformity to deteriorate.

[0059] In view of this, an embodiment of the present invention provides a display panel, the display panel comprising: at least one pixel circuit, Figure 1 A schematic diagram of a pixel circuit according to an embodiment of the present invention is shown in FIG. Figure 1 , comprising: a driving transistor T0, a first capacitor C1 and a second capacitor C2;

[0060] The first gate G1 of the driving transistor T0 is connected to the first capacitor C1, and the first capacitor C1 is used to store the voltage of the first gate G1 of the driving transistor T0;

[0061] The first electrode of the driving transistor T0 is connected to the second capacitor C2, and the second capacitor C2 is used to couple the data voltage to the first gate G1 of the driving transistor T0; wherein the capacitance value of the second capacitor C2 is greater than the capacitance value of the first capacitor C1.

[0062] Specifically, the operation process of the pixel circuit includes at least a compensation phase and a data writing phase. In the compensation phase, the third node N3 can provide a second initial voltage Vref2 to the second plate of the second capacitor C2, so that the voltage of the second plate of the second capacitor C2 is constant. The driving transistor T0 can generate a current flowing from its first pole to the second pole until the voltage difference between the first gate G1 and the first pole of the driving transistor T0 is equal to the threshold voltage of the driving transistor T0, and the driving transistor T0 is turned off. The first plate of the second capacitor C2 stores a voltage associated with the threshold voltage of the driving transistor T0. According to the circuit connection, the voltage stored in the first plate of the second capacitor C2 can be transmitted to the first gate G1 of the driving transistor T0, so that the voltage of the first gate G1 of the driving transistor T0 is associated with the threshold voltage of the driving transistor T0. That is, the voltage of the first gate G1 of the driving transistor T0 can be expressed as Vre1+Vth, so as to achieve threshold compensation for the driving transistor T0.

[0063] In the data writing stage, the third node N3 can provide the data voltage Vdata to the second plate of the second capacitor C2, and the voltage of the second plate of the second capacitor C2 jumps from the second initial voltage Vref2 to the data voltage Vdata. The second initial voltage Vref2 and the data voltage Vdata have a voltage variation, that is, the voltage variation of the third node N3. The second capacitor C2 couples the voltage variation of the third node N3 to the first node N1, and transmits it to the first gate G1 of the driving transistor T0, so that the voltage of the first gate G1 of the driving transistor T0 is associated with the data voltage inputted from the third node N3. At this time, the voltage of the first gate G1 of the driving transistor T0 can be expressed as Vre1+Vth+c2△V / (c1+c2+cgs), thereby realizing data writing. That is to say, under the coupling effect of the second capacitor C2, the voltage variation of the first gate G1 of the driving transistor T0 is c2△V / (c1+c2+cgs), where △V is the voltage variation of the second initial voltage Vref2 and the data voltage Vdata, c1 is the capacitance value of the first capacitor C1, c2 is the capacitance value of the second capacitor C2, and cgs is the capacitance value of the parasitic capacitance between the first gate G1 and the second electrode of the driving transistor T0. Therefore, the data voltage range corresponding to the writing of the display panel from the highest brightness to the black state will be related to the capacitance value c1 of the first capacitor C1 and the capacitance value c2 of the second capacitor C2. Setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1 can reduce the writing range of the data voltage while meeting the display requirements of the display panel from the highest brightness to the black state, which is beneficial for the driver chip to provide a more accurate data voltage and reduce the floating of the data voltage, thereby improving the difference in display brightness and improving the uniformity of display.

[0064] Figure 2 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention can be applied to Figure 1 See the pixel circuit shown in Figure 1 and Figure 2 , wherein the pixel circuit further includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0065] The first transistor T1 is connected between the first gate G1 of the driving transistor T0 and the first node N1. The second electrode of the second transistor T2 is connected to the second node N2, and the second node N2 is also connected to the light emitting diode D1. The gate of the second transistor T2 is connected to the first scanning signal line S1, and the second electrode of the second transistor T2 is connected to the first initialization signal line VRE1. The second transistor T2 is used to initialize the anode of the light emitting diode D1. The first electrode of the third transistor T3 is connected to the second initialization signal line VRE2, the gate of the third transistor T3 is connected to the first light emission control signal line EM1, the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are connected to the third node N3, the first electrode of the fourth transistor T4 is connected to the data line DATA, and the gate of the fourth transistor T4 is connected to the second scanning signal line S2. The first electrode of the fifth transistor T5 is connected to the second electrode of the second transistor T2, the second electrode of the fifth transistor T5 is connected to the first electrode of the second transistor T2, the gate of the fifth transistor T5 is connected to the third scanning signal line S3, and the fifth transistor T5 is used to initialize the light emitting diode D1 within the holding frame to achieve low-frequency driving. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T0, the second electrode of the sixth transistor T6 is connected to the power line VDD, the gate of the sixth transistor T6 is connected to the second light-emitting control signal line EM2, the first electrode of the seventh transistor T7 is connected to the second node N2, the second electrode of the seventh transistor T7 is connected to the first electrode of the driving transistor T0, the gate of the seventh transistor T7 is connected to the first light-emitting control signal line EM1, and the sixth transistor T6 and the seventh transistor T7 are used to control the power supply voltage on the power line VDD to be transmitted to the light-emitting diode D1.

[0066] The working process of the pixel circuit provided in this embodiment includes an initialization phase t1, a compensation phase t2, a data writing phase t3 and a light emitting phase t4.

[0067] In the initialization stage t1, the first scanning signal S1 is at an off level, such as a low level; the second scanning signal S2 is at an off level, such as a low level; the third scanning signal S3 is at an on level, such as a high level; the first light-emitting control signal line EM1 is at an off level, such as a low level; the second light-emitting control signal EM2 is at an off level, such as a low level. Therefore, the fifth transistor T5 is turned on. The first initialization voltage Vref1 is transmitted to the anode of the light-emitting diode D1 via the fifth transistor T5, and the anode of the light-emitting diode D1 is initialized.

[0068] In the compensation stage t2, the first scanning signal S1 is at a conduction level, such as a high level; the second scanning signal S2 is at a turn-off level, such as a low level; the third scanning signal S3 is at a turn-off level, such as a low level; the first light-emitting control signal EM1 is at a conduction level, such as a high level; and the second light-emitting control signal EM2 is at a turn-off level, such as a low level. Therefore, the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on. The first gate G1 of the driving transistor T0 and the first pole are short-circuited to form a diode structure, and a discharge path is formed between the first node N1 and the second transistor T2. When the voltage of the first node N1 drops to Vref1+Vth, the driving transistor T0 is turned off, where Vth is the threshold voltage of the driving transistor T0. At this time, the voltage of the first gate G1 of the driving transistor T0 is also Vref1+Vth. While realizing the threshold compensation, the first initialization voltage Vref1 can also be transmitted to the first gate G1 of the driving transistor T0 to realize the initialization of the first gate G1 of the driving transistor T0. And in the compensation stage t2, the voltage of the anode of the light emitting diode D1 is maintained at the first initialization voltage Vref1, preventing the light emitting diode D1 from emitting light. The second capacitor C2 stores the gate voltage of the first transistor T1.

[0069] In the data writing stage t3, the first scanning signal S1 is at a conduction level, such as a high level; the second scanning signal S2 is at a conduction level, such as a high level; the first light emitting control signal EM1 is at a turn-off level, such as a low level; the second light emitting control signal EM2 is at a turn-off level, such as a low level. Therefore, the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The data voltage Vdata is transmitted to the second plate of the second capacitor C2 via the fourth transistor T4. The voltage of the second plate of the second capacitor C2 jumps from the second initialization voltage Vref2 to the data voltage Vdata. The voltage change of the second plate of the second capacitor C2 is Vdata-Vref2. Since the first transistor T1 is in the on state, under the coupling action of the second capacitor C2, the voltage of the first gate G1 of the driving transistor T0 becomes Vref1+Vth+c1(Vdata-Vref2) / (c1+c2+cgs) and is stored on the second capacitor C2. The voltage of the second electrode of the second capacitor C2 maintains the first initialization voltage Vref1 under the holding action of the second transistor T2. The voltage difference across the second capacitor C2 is Vth+c1(Vdata-Vref2) / (c1+c2+cgs).

[0070] In the light-emitting stage t4, the first scanning signal S1 is at an off level, such as a low level; the second scanning signal S2 is at an off level, such as a low level; the third scanning signal S3 is at an off level, such as a low level; the first light-emitting control signal EM1 is at an on level, such as a high level; and the second light-emitting control signal EM2 is at an on level, such as a high level. Therefore, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned on. The first power supply voltage VDD is transmitted to point D via the sixth transistor T6, and the driving transistor T0 generates a driving current I according to the voltage of the first gate G1 and the first node N1, driving the light-emitting diode D1 to emit light. At the same time, the third transistor T3 transmits the second initialization voltage Vref2 to the first end of the second capacitor C2 to initialize the second capacitor C2.

[0071] The driving current I can be expressed as:

[0072]

[0073] Wherein, μ is the electron mobility of the driving transistor T0, Cox is the channel capacitance per unit area of ​​the driving transistor T0, W / L is the width-to-length ratio of the driving transistor T0, Vth is the threshold voltage of the driving transistor T0, c1 is the capacitance value of the first capacitor C1, c2 is the capacitance value of the second capacitor C2, and cgs is the capacitance value of the parasitic capacitance between the first gate G1 and the second electrode of the driving transistor T0.

[0074] According to the formula of the driving current I, the driving current I is independent of the first power supply voltage VDD, the second power supply voltage VSS, and the threshold voltage Vth of the first transistor T1. The driving current corresponding to the display panel from the highest brightness to the black state is related to the data voltage, the capacitance value c1 of the first capacitor C1, and the capacitance value c2 of the second capacitor C2. Therefore, the capacitance value c2 of the second capacitor C2 is set to be greater than the capacitance value c1 of the first capacitor C1, that is, the ratio of the capacitance value c2 of the second capacitor C2 to the capacitance value c1 of the first capacitor C1 is greater than 1, which can achieve the display requirements of the display panel from the highest brightness to the black state, and reduce the writing range of the data voltage. In some embodiments, the capacitance ratio range of the second capacitor C2 to the first capacitor C1 is 1.2-2.4, which can meet the display requirements of the display panel from the highest brightness to the black state, and can avoid the problem that when the ratio of the capacitance value c2 of the second capacitor C2 to the capacitance value c1 of the first capacitor C1 is too large, the second capacitor C2 needs a larger capacitance area in the layout design, thereby introducing unnecessary parasitic capacitance, causing the brightness uniformity of the display panel to decrease. Further, the capacitance ratio of the second capacitor C2 to the first capacitor C1 may be in the range of 1.6-2.0, preferably, the capacitance ratio of the second capacitor C2 to the first capacitor C1 is 1.8, wherein the capacitance range of the first capacitor C1 may be 50f-100f, such as 50f, 60f, 70f, 80f, 90f or 100f; optionally, the first capacitor C1 is 60f or 80f. The capacitance range of the second capacitor C2 is 80f-200f, such as 80f, 90f, 100f, 110f, 120f, 130f, 140f, 150f, 160f, 170f, 180f, 190f or 200f.

[0075] The display panel provided by the embodiment of the present invention can realize the threshold compensation and data writing processes in different timings, so that the compensation stage is separated from the data writing stage, so that the threshold compensation can be fully compensated even at a high refresh rate, which is beneficial to improving the difference in display brightness and improving the uniformity of the display. In addition, by setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1, it is possible to reduce the writing range of the data voltage while meeting the display requirements of the display panel from the highest brightness to the black state.

[0076] Figure 3 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, see Figure 3 , Figure 4 for Figure 3 The cross-sectional structure diagram of the display panel along the cutting line AA' is shown. The display panel provided in this embodiment further includes:

[0077] Substrate 10;

[0078] A first conductive layer and a second conductive layer, the first conductive layer is located on one side of the substrate 10, and the second conductive layer is located on a side of the first conductive layer away from the substrate 10;

[0079] The first electrode plate 11 of the first capacitor C1 is located in the first conductive layer, and the second electrode plate 12 of the first capacitor C1 is located in the second conductive layer; the first electrode plate 21 of the second capacitor C2 is located in the first conductive layer, and the second electrode plate 22 of the second capacitor C2 is located in the second conductive layer;

[0080] The overlapping area of ​​the orthographic projection of the first electrode plate 21 of the second capacitor C2 on the substrate 10 and the orthographic projection of the second electrode plate 22 of the second capacitor C2 on the substrate 10 is greater than the overlapping area of ​​the orthographic projection of the first electrode plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second electrode plate 12 of the first capacitor C1 on the substrate 10;

[0081] Specifically, the substrate 10 can provide protection and support for the display panel. For example, the substrate 10 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. A first conductive layer is arranged on one side of the substrate 10, and a second conductive layer is arranged on a side of the first conductive layer away from the substrate 10. The first conductive layer and the second conductive layer are insulated and isolated by an insulating layer. A plurality of pixel circuits are formed in the display panel. The pixel circuit includes a first capacitor C1 and a second capacitor C2. The second capacitor C2 is arranged on a side adjacent to the first capacitor C1, wherein the first plate 11 of the first capacitor C1 is located in the first conductive layer, and the second plate 12 of the first capacitor C1 is located in the second conductive layer. The orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10 overlaps at least partially with the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10, and the overlapping area of ​​the two constitutes the effective capacitance of the first capacitor C1.

[0082] The first plate 21 of the second capacitor C2 is located in the first conductive layer, and the second plate 22 of the second capacitor C2 is located in the second conductive layer. The orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10 at least partially overlap, and the overlapping area of ​​the two constitutes the effective capacitance of the second capacitor C2. Among them, according to the capacitance calculation formula, it can be known that the capacitance value of the capacitor is related to the overlapping area of ​​the upper and lower plates. Therefore, by adjusting the overlapping area of ​​the orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10, or adjusting the overlapping area of ​​the orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10, the overlapping area of ​​the orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10 can be made larger than the overlapping area of ​​the orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10, so that the capacitance value c2 of the second capacitor C2 is greater than the capacitance value c1 of the first capacitor C1, and a suitable capacitance value ratio of the second capacitor C2 to the first capacitor C1 is obtained.

[0083] Optionally, Figure 5 A schematic diagram of the layout structure of a first capacitor provided in an embodiment of the present invention, see Figure 5 , the first electrode plate 11 of the first capacitor C1 includes a hole area K0, and the overlapping position of the orthographic projection of the first electrode plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second electrode plate 12 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the hole area K0 on the substrate 10. That is to say, on the first electrode plate 11 of the first capacitor C1, the first conductive layer at the position of the hole area K0 is removed to reduce the overlapping area between the first electrode plate 11 of the first capacitor C1 and the second electrode plate 12 of the first capacitor C1, thereby reducing the overlapping area between the two plates. Therefore, by setting the hole area K0 on the first electrode plate 11 of the first capacitor C1, the capacitance of the first capacitor C1 can be adjusted.

[0084] Optionally, Figure 6 A schematic diagram of a layout structure of another first capacitor provided in an embodiment of the present invention is shown in FIG. Figure 6, the second electrode plate 12 of the first capacitor C1 includes a hole area K0, and the overlapping position of the orthographic projection of the first electrode plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second electrode plate 12 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the hole area K0 on the substrate 10. That is to say, on the second electrode plate 12 of the first capacitor C1, the second conductive layer at the position of the hole area K0 is removed to reduce the overlapping area between the first electrode plate 11 of the first capacitor C1 and the second electrode plate 12 of the first capacitor C1, thereby reducing the overlapping area between the two plates. Therefore, by setting the hole area K0 on the second electrode plate 12 of the first capacitor C1, the capacitance of the first capacitor C1 can be adjusted.

[0085] Optionally, Figure 7 A schematic diagram of a layout structure of another first capacitor provided in an embodiment of the present invention is shown in FIG. Figure 7 , the first electrode plate 11 of the first capacitor C1 and the second electrode plate 12 of the first capacitor C1 both include a hole area K0, and the overlapping position of the orthographic projection of the first electrode plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second electrode plate 12 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the hole area K0 on the substrate 10. That is to say, on the first electrode plate 11 of the first capacitor C1, the first conductive layer at the position of the hole area K0 is removed, and on the second electrode plate 12 of the first capacitor C1, the second conductive layer at the position of the hole area K0 is removed, so as to reduce the overlapping area between the first electrode plate 11 of the first capacitor C1 and the second electrode plate 12 of the first capacitor C1, thereby reducing the overlapping area between the two plates.

[0086] It should be noted that the orthographic projection of the hole area K0 on the first plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the hole area K0 on the second plate 12 of the first capacitor C1 on the substrate 10 may overlap or may not overlap.

[0087] exist Figures 5 to 7 In the figure, it is exemplarily shown that the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 falls within the orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10, that is, the area of ​​the second plate 12 of the first capacitor C1 is smaller than the area of ​​the first plate 11 of the first capacitor C1. In other embodiments, according to the routing relationship between layers, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 may also cover the orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10, that is, the area of ​​the second plate 12 of the first capacitor C1 may also be greater than or equal to the area of ​​the first plate 11 of the first capacitor C1.

[0088] Furthermore, in the following text, when the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 are reused on the same layer, the orthographic projection of the hole area K0 on the second plate 12 of the first capacitor C1 on the substrate 10 does not overlap with the orthographic projection of the channel area 40 of the driving transistor T0 on the substrate 10, thereby avoiding affecting the control capability of the channel of the driving transistor T0.

[0089] Figure 8 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 8 , Fig. 9 for Figure 8 The cross-sectional structure diagram of the display panel along the cutting line BB' is shown in FIG. Figure 6 and Fig. 9 , the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 can be reused in the same layer, or can be independently set in different layers, and then the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 are electrically connected through vias. In the embodiment of the present invention, the second plate 12 of the first capacitor C1 is reused as the first gate G1 of the driving transistor T0, and the driving transistor T0 can be a bottom gate drive type, that is, the first gate G1 of the driving transistor T0 is used as the control electrode, and the second plate 12 of the first capacitor C1 is used as the bottom gate of the driving transistor T0. Figure 8 and Fig. 9 As shown, the first active layer 30 is located on the side of the second conductive layer away from the substrate 10, and the first active layer 30 extends along the first direction X. The third conductive layer is located on the side of the first active layer 30 away from the substrate 10, and the driving transistor T0 includes a second gate G2, and the second gate G2 of the driving transistor T0 is located in the third conductive layer, and the second gate G2 of the driving transistor T0 is connected to the second electrode of the driving transistor T0, wherein the portion of the first active layer 30 located below the orthographic projection of the second gate G2 of the driving transistor T0 is the channel region of the driving transistor T0, the channel region 40 of the driving transistor T0 is located in the first active layer 30, the source region and the drain region of the driving transistor T0 are respectively located on both sides of the channel region 40, and the first gate G1 of the driving transistor T0 is overlapped with the channel region 40 of the driving transistor T0, that is, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 at least covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. It should be noted that the material of the first active layer 30 applied to the driving transistor T0 may be a metal oxide, such as Indium Gallium Zinc Oxide (IGZO). The active layers applied to other transistors, such as the first transistor T1 to the seventh transistor T7, may be provided with a second active layer, and the material of the second active layer may be Low Temperature Poly-Silicon (LTPS).

[0090] Optionally, the minimum distance W1 between the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 and the orthographic projections of the first plate 21 of the second capacitor C2 and the second plate 22 of the second capacitor C2 on the substrate 10 is greater than or equal to 3 μm. In other words, the minimum distance W1 between the edge of each plate of the second capacitor C2 and the edge of the second plate 12 of the first capacitor C1 needs to be greater than 3 μm, so as to reduce the introduction of unnecessary parasitic capacitance between the first plate 21 of the second capacitor C2 and the second plate 22 of the second capacitor C2 and the second plate 12 of the first capacitor C1, thereby affecting the coupling effect of the second capacitor.

[0091] like Figure 8 As shown, in some embodiments, the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10 falls within the orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10, and the first plate 21 of the second capacitor C2 is closer to the second plate 12 of the first capacitor C1 relative to the second plate 22 of the second capacitor C2. Therefore, the minimum distance W1 between the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 and the orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10 needs to be greater than or equal to 3μm to reduce the coupling effect of the parasitic capacitance between the second plate 12 of the first capacitor C1 and the first plate 21 of the second capacitor C2. In other embodiments, the orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10 falls within the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10, then the second plate 22 of the second capacitor C2 is closer to the second plate 12 of the first capacitor C1 relative to the second plate 22 of the second capacitor C2, therefore, a minimum distance W1 between the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10 needs to be greater than or equal to 3 μm to reduce the coupling effect of the parasitic capacitance between the second plate 12 of the first capacitor C1 and the second plate 22 of the second capacitor C2.

[0092] Optionally, in the first direction X, the projection of the second plate 12 of the first capacitor C1 on the substrate 10 exceeds the projection of the channel region 40 of the driving transistor T0 on the substrate 10 by at least a first length dimension W2; that is, in the first direction X, the length dimension of the second plate 12 of the first capacitor C1 is greater than the channel region 40 of the driving transistor T0.

[0093] Optionally, in the second direction Y, the orthogonal projection of the second plate 12 of the first capacitor C1 on the substrate 10 exceeds the orthogonal projection of the channel region 40 of the driving transistor T0 on the substrate 10 by at least a second length dimension W3; the second direction Y is perpendicular to the first direction X; that is, in the second direction Y, the length dimension of the second plate 12 of the first capacitor C1 is greater than the channel region 40 of the driving transistor T0.

[0094] By extending the length of the second plate 12 of the first capacitor C1 relative to the channel region 40 of the driving transistor T0 in the first direction X and the second direction Y, the coverage range of the second plate 12 of the first capacitor C1 on the channel region 40 of the driving transistor T0 is increased, thereby improving the control capability of the channel of the driving transistor T0. If the first length dimension W2 and / or the second length dimension W3 are too large, parasitic capacitance will also be introduced, thereby affecting the brightness uniformity. Therefore, through experimental studies, in the first direction X, the first length dimension W2 ranges from 0.4μm to 2μm, for example, the first length dimension W2 ranges from 0.4μm, 0.8μm, 1μm, 1.2μm, 1.6μm or 2μm, preferably, the first length dimension W2 is 1μm; and or, in the second direction Y, the second length dimension W3 ranges from 2μm to 4μm, for example, the second length dimension W3 is 2μm, 2.5μm, 3μm, 3.5μm or 4μm, preferably, the second length dimension W3 is 3μm, which can meet the control capability of the driving transistor T0 channel while reducing the influence of parasitic capacitance.

[0095] Optionally, the orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10, and the first plate 11 of the first conductive layer is used as the lower plate of the first capacitor C1, and can also be reused as a light shielding layer of the driving transistor T0, which can save layout space and avoid the influence of light on the driving transistor T0, thereby improving the reliability of the pixel circuit and the display panel.

[0096] Continue to see Figure 8 and Fig. 9Optionally, the display panel further includes a third conductive layer, which is located on the side of the first active layer 30 away from the substrate 10, and the driving transistor T0 includes a second gate G2, which is located in the third conductive layer, and the second gate G2 of the driving transistor T0 is connected to the second electrode of the driving transistor T0, wherein the portion of the first active layer 30 located below the orthographic projection of the second gate G2 of the driving transistor T0 is the channel region of the driving transistor T0, and the orthographic projection of the second gate G2 of the driving transistor T0 on the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. The first electrode of the driving transistor T0 may be a drain electrode, and the second electrode of the driving transistor T0 may be a source electrode. The first gate G1 of the driving transistor T0 is used as a bottom gate, the second gate G2 of the driving transistor T0 is used as a top gate, and the bottom gate is used as a control electrode to realize the driving control of the driving transistor T0. The use of a double gate in the driving transistor T0 can enhance the gate's control ability over the channel region 40, which is beneficial to improving the subthreshold swing of the driving transistor T0, and is beneficial to grayscale development, and improving display brightness uniformity.

[0097] like Fig. 9 As shown, in this embodiment, on the first active layer 30, the area covered by the second gate G2 of the driving transistor T0 is used as the channel region 40 of the driving transistor T0, and the orthographic projection of the second gate G2 of the driving transistor T0 on the substrate 10 at least covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10.

[0098] Optionally, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 covers the orthographic projection of the second gate of the driving transistor T0 on the substrate 10. Thus, the orthographic projection of the second plate 12 of the first capacitor C1 can cover the area covered by the second gate G2 of the driving transistor T0, that is, the channel region 40 of the driving transistor T0, wherein, in the first direction X, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 exceeds the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10 by at least the first length dimension W2, and or, in the second direction Y, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 exceeds the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10 by at least the second length dimension W3, which can meet the control capability of the channel of the driving transistor T0 while reducing the influence of parasitic capacitance.

[0099] Optionally, the display panel further includes a fourth conductive layer, which is located on a side of the third conductive layer away from the substrate 10 . The fourth conductive layer includes a first connecting line 111 , and the second gate G2 of the driving transistor T0 is connected to the first electrode of the driving transistor T0 via the first connecting line 111 .

[0100] Specifically, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are isolated from each other by insulating layers. Exemplarily, a capacitor insulating layer 110 is arranged between the first conductive layer and the second conductive layer, a first gate insulating layer 120 is arranged between the second conductive layer and the first active layer 30, a second gate insulating layer 130 is arranged between the first active layer 30 and the third conductive layer, an interlayer insulating layer 140 is arranged between the third conductive layer and the fourth conductive layer, and a first planarization layer 150 is arranged on the side of the fourth conductive layer away from the substrate 10.

[0101] The first connection line 111 is located in the fourth conductive layer, and is used to connect the second gate G2 and the second electrode (the source of the driving transistor T0) of the driving transistor T0. For example, the second gate G2 of the driving transistor T0 is connected to one end of the first connection line 111 through the first via K1, and the second electrode of the driving transistor T0 is connected to the other end of the first connection line 111 through the first via K1. The second gate G2 and the second electrode of the driving transistor T0 are connected in a bridge manner through the first connection line 111. The first via K1 is a via that penetrates the interlayer insulating layer 140 or penetrates the interlayer insulating layer 140 and the second gate insulating layer 130.

[0102] Optionally, the orthographic projection of the first connection line 111 on the substrate 10 at least partially covers the orthographic projection of the second gate G2 of the driving transistor T0 on the substrate 10 to achieve connection between the first connection line 111 as the second gate G2 of the driving transistor T0 and the first electrode of the driving transistor T0.

[0103] Fig.10 For the reason Figure 8 The cross-sectional structure diagram of the display panel along the cutting line CC' is shown in FIG. Fig.10 Optionally, the fourth conductive layer further includes a second connecting line 112, and the second plate 22 of the second capacitor C2 is connected to the first electrode of the driving transistor T0 (the drain of the driving transistor T0) through the second connecting line 112. For example, the second plate 22 of the second capacitor C2 is connected to one end of the second connecting line 112 through the second via K2, and the first electrode of the driving transistor T0 is connected to the other end of the second connecting line 112 through the second via K2, and the second plate 22 of the second capacitor C2 and the first electrode of the driving transistor T0 are connected in a bridge manner through the second connecting line 112. Among them, the first plate 21 of the second capacitor C2 is located in the first conductive layer, and the second plate 22 of the second capacitor C2 is located in the second conductive layer.

[0104] Fig.11 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, Fig.12 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Fig.13 for Fig.12The cross-sectional structure diagram of the display panel along the cutting line DD' is shown in FIG. Figure 11-13 In this embodiment, the first active layer 30 is located on the side of the second conductive layer away from the substrate 10, and the first active layer 30 extends along the first direction X; the third conductive layer is located on the side of the first active layer 30 away from the substrate 10, and the driving transistor T0 is a single-gate transistor, that is, the driving transistor T0 has only the first gate G1, and the first gate G1 of the driving transistor T0 is located in the third conductive layer, wherein the portion of the first active layer 30 located below the orthographic projection of the first gate G1 of the driving transistor T0 is the channel region of the driving transistor T0. Optionally, the orthographic projection of the first gate G1 of the driving transistor T0 on the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10; the second plate 12 of the first capacitor C1 is not reused as the first gate G1 of the driving transistor T0, therefore, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 does not overlap with the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. When the driving transistor T0 is a single-gate transistor, the first connecting line 111 may be omitted, and the connection between the first gate G1 of the driving transistor T0 and the second electrode plate 12 of the first capacitor C1 is achieved through the third connecting line 113 .

[0105] Optionally, the orthographic projection of the first electrode 11 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. By using the first electrode 11 of the first conductive layer as a light shielding layer for the driving transistor T0, the layout space can be saved, and the influence of light on the driving transistor T0 can be avoided, thereby improving the reliability of the pixel circuit and the display panel.

[0106] The first gate G1 of the driving transistor T0 is connected to one end of the third connection line 113 through the third via K3, and the second plate 12 of the first capacitor C1 is connected to the other end of the third connection line 113 through the third via K3, so as to realize the connection between the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1. The second plate 22 of the second capacitor C2 and the first electrode of the driving transistor T0 are connected in a bridge manner through the third connection line 113.

[0107] Optionally, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Fig.14A structural schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not make any special limitation on this.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: at least one pixel circuit, the pixel circuit comprising a driving transistor, a first capacitor and a second capacitor; The first gate of the driving transistor is connected to the first capacitor, and the first capacitor is used to store the voltage of the first gate of the driving transistor; the first electrode of the driving transistor is connected to the second capacitor, and the second capacitor is used to couple the data voltage to the first gate of the driving transistor, wherein the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

2. The display panel according to claim 1, characterized in that: include: The capacitance ratio of the second capacitor to the first capacitor is in the range of 1.2-2.4; Preferably, the capacitance ratio of the second capacitor to the first capacitor is in the range of 1.6-2.0; Preferably, the capacitance ratio of the second capacitor to the first capacitor is 1.8; Preferably, the capacitance value of the first capacitor ranges from 50f to 100f; the capacitance value of the second capacitor ranges from 80f to 200f.

3. The display panel according to any one of claims 1 to 2, characterized in that: Also includes: substrate; a first conductive layer and a second conductive layer, wherein the first conductive layer is located on one side of the substrate, and the second conductive layer is located on a side of the first conductive layer away from the substrate; The first electrode plate of the first capacitor is located on the first conductive layer, and the second electrode plate of the first capacitor is located on the second conductive layer; The first electrode plate of the second capacitor is located on the first conductive layer, and the second electrode plate of the second capacitor is located on the second conductive layer; An overlapping area of ​​an orthographic projection of the first electrode plate of the second capacitor on the substrate and an orthographic projection of the second electrode plate of the second capacitor on the substrate is greater than an overlapping area of ​​an orthographic projection of the first electrode plate of the first capacitor on the substrate and an orthographic projection of the second electrode plate of the first capacitor on the substrate; Preferably, the first plate of the first capacitor and / or the second plate of the first capacitor include a hole area, and an overlapping position of an orthographic projection of the first plate of the first capacitor on the substrate and an orthographic projection of the second plate of the first capacitor on the substrate at least partially covers the orthographic projection of the hole area on the substrate.

4. The display panel according to claim 3, characterized in that: The first gate of the driving transistor is located in the second conductive layer, and the second plate of the first capacitor is reused as the first gate of the driving transistor; Preferably, the minimum distance between the orthographic projection of the second electrode plate of the first capacitor on the substrate and the orthographic projections of the first electrode plate of the second capacitor and the second electrode plate of the second capacitor on the substrate is greater than or equal to 3 μm; Preferably, the orthographic projection of the first electrode plate of the second capacitor on the substrate at least covers the orthographic projection of the second electrode plate of the second capacitor on the substrate; A minimum distance between an orthographic projection of the second electrode plate of the first capacitor on the substrate and an orthographic projection of the first electrode plate of the second capacitor on the substrate is greater than or equal to 3 μm.

5. The display panel according to claim 4, characterized in that: Also includes: a first active layer, the first active layer being located on a side of the second conductive layer away from the substrate, and the first active layer extending along a first direction; a third conductive layer, the third conductive layer being located on a side of the first active layer away from the substrate, the driving transistor comprising a second gate, the second gate being located in the third conductive layer, and the second gate of the driving transistor being connected to the second electrode of the driving transistor; The portion of the first active layer located below the orthographic projection of the second gate of the driving transistor is the channel region of the driving transistor, and the orthographic projection of the second plate of the first capacitor on the substrate at least covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, in the first direction, the orthographic projection of the second plate of the first capacitor on the substrate exceeds the orthographic projection of the channel region of the driving transistor on the substrate by at least a first length dimension; Preferably, the first length dimension ranges from 0.4 μm to 2 μm; Preferably, the first length dimension is 1 μm; Preferably, in the second direction, the orthographic projection of the second plate of the first capacitor on the substrate exceeds the orthographic projection of the channel region of the driving transistor on the substrate by at least a second length dimension; the second direction is perpendicular to the first direction; Preferably, the second length dimension ranges from 2 μm to 4 μm; Preferably, the second length dimension is 3 μm.

6. The display panel according to claim 5, characterized in that: The orthographic projection of the first plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate.

7. The display panel according to claim 5, characterized in that: The orthographic projection of the second gate of the driving transistor on the substrate at least covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the second electrode plate of the first capacitor on the substrate at least covers the orthographic projection of the second gate of the driving transistor on the substrate.

8. The display panel according to claim 7, characterized in that: It also includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, the fourth conductive layer includes a first connecting line, and the second gate of the driving transistor is connected to the second electrode of the driving transistor through the first connecting line; Preferably, the second gate of the driving transistor is connected to one end of the first connecting line through a first via hole, and the first electrode of the driving transistor is connected to the other end of the first connecting line through a second via hole; Preferably, the orthographic projection of the first connecting line on the substrate at least partially covers the orthographic projection of the second gate of the driving transistor on the substrate.

9. The display panel according to claim 3, characterized in that: Also includes: a first active layer, the first active layer being located on a side of the second conductive layer away from the substrate, and the first active layer extending along a first direction; a third conductive layer, the third conductive layer being located on a side of the first active layer away from the substrate, and the first gate of the driving transistor being located on the third conductive layer; wherein a portion of the first active layer located below the orthographic projection of the first gate of the driving transistor is a channel region of the driving transistor; Preferably, the orthographic projection of the first gate of the driving transistor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the second plate of the first capacitor on the substrate does not overlap with the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the first plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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