Gate driving circuit, control method of gate driving circuit and display panel

Abstract

The invention provides a gate drive circuit, a control method of the gate drive circuit and a display panel, the gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises a bidirectional selector, a latch and a shift register unit which are connected in sequence, the latch comprises a latch structure, a first switch module and a second switch module which are electrically connected, a first scanning signal output by a first scanning line connected with the latch structure is used for controlling the voltage of a first node, and the voltage of the first node controls a gate control signal of the shift register by controlling the on or off of the first switch module; and a second scanning signal output by a second scanning line connected with the second switch module controls the connection or disconnection of the shifting register of the current stage and the shifting registers of other stages by controlling the connection or disconnection of the second switch module. According to the gate drive circuit, switching on or switching off of any stage of shift register on the display panel can be realized, so that the power consumption of the shift register is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a control method of the gate driving circuit, and a display panel. Background Art

[0002] When the screen of an existing display screen only displays a partial area, a part of the display area displays a black picture, and the other part of the display area displays a normal picture. At this time, the driving circuits of all the shift register units will work, that is, the gate output signal terminals of all the shift register units will be opened step by step, and the power consumption of the driving circuits of the shift register units is relatively large. Summary of the invention

[0003] The main purpose of the present application is to provide a gate driving circuit, a control method of the gate driving circuit and a display panel, so as to at least solve the problem in the prior art that when the display screen only displays a partial area, the driving circuits of all shift register units are fully operated, resulting in high power consumption.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a gate drive circuit is provided, comprising a plurality of cascaded shift registers, which sequentially output gate control signals through gate control lines, wherein each of the shift registers comprises a bidirectional selector, a latch, and a shift register unit connected in sequence, wherein the latch comprises an electrically connected latch structure, a first switch module, and a second switch module, wherein a control end of the latch structure is connected to a first scan line, and a first scan signal output by the first scan line is used to control a voltage of a first node, wherein the first node is a node where the latch structure is connected to the first switch module, and the voltage of the first node is used to control the gate control signal output by the shift register by controlling the conduction or disconnection of the first switch module, and the shift register unit is electrically connected to the first switch module; a control end of the second switch module is connected to a second scan line, and a second scan signal output by the second scan line is used to control the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module, and the bidirectional selector is electrically connected to the second switch module.

[0005] According to another aspect of the present application, a control method for a gate drive circuit is provided, the method being used to control any one of the gate drive circuits, the method comprising: generating a drive signal set, the drive signal set comprising a plurality of level signals, the plurality of level signals comprising: a first scan signal and a second scan signal; applying the first scan signal to a latch structure to control a voltage of a first node, and by controlling the voltage of the first node, controlling the conduction or disconnection of the first switch module to control a gate control signal output by the shift register; applying the second scan signal to a second switch module to control the connection or disconnection of the shift register of a current stage with the shift registers of other stages by controlling the conduction or disconnection of the second switch module.

[0006] According to another aspect of the present application, a display panel is provided, comprising: any one of the gate driving circuits described above; a first scanning signal generator configured to generate a first scanning signal; and a second scanning signal generator configured to generate a second scanning signal.

[0007] Applying the technical solution of the present application, the gate drive circuit includes a plurality of cascaded shift registers, each of which includes a bidirectional selector, a latch, and a shift register unit connected in sequence, and the latch includes an electrically connected latch structure, a first switch module, and a second switch module, wherein the first scan signal output by the first scan line connected to the latch structure is used to control the voltage of the first node, and the voltage of the first node controls the gate control signal of the shift register by controlling the conduction or disconnection of the first switch module; the second scan signal output by the second scan line connected to the second switch module controls the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module. The gate drive circuit adds a latch to each shift register, and by controlling the signal line, the shift register unit can be triggered from any stage, thereby realizing the opening of the shift register of any stage, and can also realize the closing of the shift register of any stage. In the normal picture display area, the shift register unit works and the shift register is opened and closed step by step; in the black picture display area, the shift register unit does not work and the gate control signal is not output, thereby achieving the purpose of reducing the power consumption of the shift register unit and solving the problem in the prior art that when the display screen only displays a partial area, all the driving circuits of the shift register units work, resulting in high power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0009] Figure 1A schematic diagram showing a first display area and a second display area in a display panel;

[0010] Figure 2 A schematic diagram of the structure of a gate drive circuit provided according to an embodiment of the present application is shown;

[0011] Figure 3 A schematic structural diagram of a latch structure provided according to an embodiment of the present application is shown;

[0012] Figure 4 A schematic structural diagram of another latch structure provided according to an embodiment of the present application is shown;

[0013] Figure 5 A schematic structural diagram of another latch structure provided according to an embodiment of the present application is shown;

[0014] Figure 6 A schematic structural diagram of another gate driving circuit provided according to an embodiment of the present application is shown;

[0015] Figure 7 A schematic diagram of the structure of another gate driving circuit provided according to an embodiment of the present application is shown;

[0016] Figure 8 A schematic flow chart of a gate drive circuit control method provided according to an embodiment of the present application is shown;

[0017] Fig. 9 The embodiment of the present application provides Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the first frame scanning;

[0018] Fig.10 The embodiment of the present application provides Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the second frame scanning;

[0019] Fig.11 The embodiment of the present application provides Figure 1 (b) The timing diagram of each signal in the gate driving circuit during the first frame scanning in the case;

[0020] Fig.12 The embodiment of the present application provides Figure 1 (b) The timing diagram of each signal in the gate driving circuit during the second frame scanning in the case;

[0021] Fig.13 The embodiment of the present application provides Figure 1 (c) Timing diagram of each signal in the gate drive circuit during scanning;

[0022] Fig.14 A schematic diagram of the structure of another gate driving circuit provided according to an embodiment of the present application is shown;

[0023] Fig.15 The embodiment of the present application provides Figure 1 (d) The timing diagram of each signal in the gate driving circuit during the second frame scanning in the case;

[0024] Fig.16 A schematic structural diagram of a display panel provided according to an embodiment of the present application is shown.

[0025] The above drawings include the following reference numerals:

[0026] 01. Bidirectional selector; 02. Latch; 10. Latch structure; 11. First inverter; 12. First switch unit; 121. Third switch module; 122. Fourth switch module; 13. Latch substructure; 131. Second inverter; 132. Third inverter; 20. First switch module; 30. Second switch module; 03. Shift register unit; 04. Abnormal power-off controller; 05. Output buffer; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; M9. First switch device; M10. Second switch device. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] As introduced in the background technology, Figure 1 is a schematic diagram of a first display area and a second display area in a display panel, such as Figure 1 As shown, the first display area is the area displaying the black picture, and the second display area is the area displaying the normal picture. When only part of the screen area displays the normal picture, the shift register will work completely, that is, all gate control signals will be turned on step by step, and the power consumption of the shift register will be relatively large.

[0031] To solve the problem in the prior art that when a display screen displays only a partial area, all driving circuits of all shift register units operate fully, resulting in high power consumption, an embodiment of the present application provides a gate driving circuit, a control method for a gate driving circuit, and a display panel.

[0032] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0033] The embodiment of the present application provides a gate drive circuit, including a plurality of shift registers in cascade, and outputs gate control signals sequentially through gate control lines. A bidirectional selector, also known as a bidirectional multiplexer or a bidirectional switch, is an electronic circuit component whose function is to selectively connect or disconnect a signal path in two directions. It allows data or signals to flow bidirectionally between two different points, that is, it can be selected from input A to output B, or from input B to output A. In the present application, when the bidirectional selection switch is started, the gate drive circuit is described by scanning from top to bottom, and the subsequent description is not repeated. The shift register unit is an electronic circuit component that moves the data signal in a specified direction and timing under the drive of a clock signal. In display technologies such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), the shift register unit is used to generate row-by-row or column-by-column scanning signals to control the refresh of display pixels. A latch is a basic digital circuit unit for storing one bit of binary digital information. In this solution, the latch is suitable for latching the signal of the first node N1. Figure 2 Schematic diagram of a gate drive circuit according to an embodiment of the present application. Figure 2 As shown,

[0034] The present application provides a gate driving circuit, which includes a plurality of cascaded shift registers, each of which includes a bidirectional selector 01, a latch 02, and a shift register unit 03 connected in sequence, and the latch 02 includes an electrically connected latch structure 10, a first switch module 20, and a second switch module 30, wherein a control end of the latch structure 10 is connected to a first scan line, and a first scan signal select1 output by the first scan line is used to control a voltage of a first node N1, and the first node N1 is a node where the latch structure 10 is connected to the first switch module 20, and the voltage of the first node N1 is used to control the conduction or disconnection of the first switch module 20 to control a gate control signal Gout output by the shift register, and the shift register unit 03 is electrically connected to the first switch module 20; a control end of the second switch module 30 is connected to a second scan line, and a second scan signal select2 output by the second scan line is used to control the conduction or disconnection of the second switch module 30 to control the connection or disconnection of the shift register of the current stage with the shift register of other stages, and the bidirectional selector 01 is electrically connected to the second switch module 30.

[0035] The gate drive circuit provided in the present application, during normal operation, that is, during frame scanning, after the first-stage shift register receives the second initial scanning signal STV, the signal is transmitted in sequence through the bidirectional selector, latch, and shift register unit of the first-stage shift register to output a gate control signal, and the gate control signal of the first stage is transmitted to the next-stage shift register for step-by-step scanning.

[0036] When the shift registers of the previous stages are controlled not to work and the shift registers of a certain stage are started to work, the first scanning signal select1 is first controlled to be high level in the previous frame to transmit the high level signal to the first node N1, and the first node N1 of the shift register of a certain stage is latched at a high level through the latch structure. When the first node N1 is at a high level, the first switch module 20 is turned on. Then, when the current frame is scanned, STV is set to a low level. STV is always set to a low level, and no initial scanning signal is provided to the first stage shift register unit, so the gate drive circuit will not scan normally step by step. At this time, since the first node N1 of a certain stage is at a high level, the high level signal of the first initial scanning signal STV' is provided to the shift register unit of a certain stage, and the gate control signal will be scanned step by step from this stage; and when the scanning is stopped at any stage, the connection between the upper and lower shift registers is disconnected by controlling the high and low levels of the second scanning signal select2, and the shift register unit in the next stage shift register will not receive the trigger signal of the previous stage, thereby stopping the scanning of the next gate control signal. The technical solution of the present application is a gate drive circuit, which includes a plurality of cascaded shift registers, each of which includes a bidirectional selector, a latch, and a shift register unit connected in sequence, and the latch includes an electrically connected latch structure, a first switch module, and a second switch module, wherein the first scan signal output by the first scan line connected to the latch structure is used to control the voltage of the first node, and the voltage of the first node controls the gate control signal of the shift register by controlling the conduction or disconnection of the first switch module; the second scan signal output by the second scan line connected to the second switch module controls the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module. The gate drive circuit adds a latch to each shift register, and by controlling the signal of the relevant signal line, the shift register unit can be triggered from any stage, thereby realizing the opening of the shift register of any stage, and can also realize the closing of the shift register of any stage.

[0037] Among them, when the display panel is in a normally black mode, that is, when there is no gate drive signal input, the display panel displays a black picture. When the display panel is in a normally white mode, that is, when there is no gate drive signal input, the display panel displays a white picture. The present application is described with the display panel in a normally black mode. In the normal picture display area, the shift register unit works, and the shift register is opened and closed step by step; in the black picture display area, the shift register unit does not work, and the gate control signal will not be output, thereby achieving the purpose of reducing the power consumption of the shift register unit, and solving the problem in the prior art that when the display screen only displays a partial area, all the driving circuits of the shift register units work, resulting in high power consumption.

[0038] In the embodiment of the present application, a latch is added to each stage of the shift register. By controlling at least the high and low levels of the first scanning signal select1 and the second scanning signal select2, the shift register unit can be triggered from any level in the display panel, thereby realizing the opening of any level of the shift register, and also realizing the closing of any level of the shift register.

[0039] Figure 1 A schematic diagram of a first display area and a second display area in a display panel is shown. In an embodiment, in the second display area displaying a normal picture, the shift register unit works, the gate control signal is output step by step, and the corresponding gate lines are opened step by step; in the first display area displaying a black picture, the shift register unit does not work, and the gate control signal is not output, thereby achieving the purpose of reducing the power consumption of the shift register. Figure 1 4 shows four embodiments of display panels displaying pictures, wherein: Figure 1 (a) The upper half of the display panel (i.e., the rows corresponding to the first n-1 shift registers) displays a black image, and the lower half of the display panel (i.e., the rows corresponding to the shift registers after the nth shift register) displays a normal image. Figure 1 (b) The upper area of ​​the display panel (i.e., the rows corresponding to the first n-1 shift registers) displays a black picture, the middle area of ​​the display panel (i.e., the rows corresponding to the nth to mth shift registers) displays a normal picture, and the lower area of ​​the display panel (i.e., the rows corresponding to the shift registers after the m+1th shift register) displays a black picture. Figure 1 (c) The upper half of the display panel (i.e., the rows corresponding to the first m shift registers) displays a normal image, and the lower half of the display panel (i.e., the rows corresponding to the shift registers after the m+1 shift register) displays a black image. Figure 1 (d) The upper area of ​​the display panel (i.e., the rows corresponding to the first m shift registers) displays a normal image, the middle area of ​​the display panel (i.e., the rows corresponding to the m+1th shift register to the n-1th shift register) displays a black image, and the lower area of ​​the display panel (i.e., the rows corresponding to the shift registers after the nth shift register) displays a normal image.

[0040] It should be noted that in the present application, the first initial scanning signal STV' takes a high level as a valid level signal, the second initial scanning signal STV, the first scanning signal select1, and the second scanning signal select2 all take a high level as a valid level signal, and the shift register outputs a high level as a valid level signal for explanation. Of course, these signals can also take a low level as a valid signal. The present application only takes the first initial scanning signal STV' as a high level as a valid level signal, the second initial scanning signal STV as a high level as a valid level signal, the first scanning signal select1 as a high level as a valid level signal, and the second scanning signal select2 as a high level as a valid level signal, and the shift register outputs a high level as a valid level signal for explanation.

[0041] In addition, the gate control signal Gout (high level or low level) is provided to the gate line of the corresponding row. Generally, when Gout is high level, the corresponding row driving transistor is turned on, and the data signal is applied to the pixel of the row. The Gout signal can also be output as a low level signal. At this time, the driving transistor of the row is not turned on. Of course, if the driving transistor is a P-type transistor, it will be turned on when Gout is low level and turned off when it is high level. This application is explained with Gout outputting a high level as the effective level.

[0042] Optional, Fig. 9 The embodiment of the present application provides Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the first frame scan; Figure 1 , Figure 2 and Fig. 9 , when the display panel is Figure 1In the case of the display image in (a), the first display area, i.e., the first n-1 rows of the display panel, displays a black image, and the second display area, i.e., displays a normal image starting from the nth row, i.e., the first n-1 levels are set to display a black image, i.e., the first n-1 levels of the shift register do not work, and the nth level starts to display a normal image. During the first frame scan, the shift register scans normally, i.e., the second initial scan signal STV first gives a high-level signal to the first-level shift register to drive the first-level shift register to scan normally, and the gate control signal will output a high-level gate control signal step by step from the beginning to the end, so that the corresponding row drive transistor is turned on to allow the data signal to be written. During the first frame scan, the second scan signal select2 is always at a high level, ensuring that the second switch module 30 is always turned on, ensuring that the shift register outputs the gate control signal Gout normally in sequence from levels 1 to n-1. At the same time, when the first frame signal scans to the n-1 level, the n-1 level shift register unit 03 outputs a high level, and at the same time, the high level signal is given to the n-level shift register as the input signal of the n-level shift register. At this time, the first scanning signal select1 signal is pulled high, the output end of the n-level latch will be set high, and the first initial scanning signal STV' is set high at the same time. When the output end of the n-level latch is at a high level, the signal (ln) of the first node N1 of the n-level shift register is at a high level. When the signal (ln) of the first node N1 is at a high level, the first switch module 20 is opened, and the high level of the first initial scanning signal STV' is input to the shift register unit 03. Before the gate control signal of the n-1th stage is pulled low, the first scanning signal select1 is pulled low first. At this time, due to the effect of the latch structure 10, the signal (ln) of the first node N1 of the nth stage shift register will always be latched at a high level, while the potential of the first node N1 of the latch 02 of the other stages of the shift register is latched as a low potential (for example: ln+1, ln+2, where ln+1 is the signal of the first node N1 of the n+1th stage shift register, and ln+2 is the signal of the first node N1 of the n+2th stage shift register). Further, when the gate control signal of the n-1th stage is pulled low, the first initial scanning signal STV' is synchronously pulled low to ensure that the signal input to the other stages of the shift register unit 03 is at a low level, thereby preventing leakage of the other stages of the shift register that may be caused when the first initial scanning signal STV' is at a high level.

[0043] Fig.10 According to the embodiment of the present application, Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the second frame scan, refer to Figure 1 , Figure 2 and Fig.10, during the second frame scanning, the second initial scanning signal STV is always at a low level, that is, the second initial scanning signal STV does not provide a driving signal to the first-stage shift register, and at this time, the first-stage shift register to the n-1-stage shift register does not work, thereby achieving the purpose of reducing the power consumption of the shift register unit. When the normal timing signal scans to the n-1-stage, the first initial scanning signal STV' becomes a high level. Since the signal (ln) of the first node N1 of the n-stage shift register is always locked at a high level, the high-level signal of the first initial scanning signal STV' will be transmitted to the shift register unit 03 of the n-stage shift register through the first switch module 20 of the n-stage shift register, and the n-stage shift register unit 03 starts to trigger. And when the n-th stage shift register is scanned according to the normal timing signal, the second scanning signal select2 is adjusted to a high level signal and applied to the second switch module 30 to control the second switch module 30 to be turned on, thereby controlling the n-th stage shift register to be connected to the n+1-th stage shift register to realize the shift register scanning step by step starting from the n-th stage.

[0044] In addition, if Fig. 9 As shown, the CLK signal and the XCLK signal are both clock signals used to control the shift operation of data. The CLK signal is input to the odd-numbered shift register, and the XCLK signal is input to the even-numbered shift register, which can realize the asynchronous operation of the shift register and ensure the correct generation and output of the scan signal.

[0045] Fig.11 According to the embodiment of the present application, Figure 1 (b) The timing diagram of each signal in the gate drive circuit during the first frame scan. Fig.12 According to the embodiment of the present application, Figure 1 (b) The timing diagram of each signal in the gate drive circuit during the second frame scanning, as shown in Figure 2 , Fig.11 , Fig.12 As shown, when the display panel is Figure 1 In the case of the display screen in (b), the first n-1 rows of the display panel display black screens, the nth to mth rows display normal screens, and the m+1th row and thereafter display black screens. That is, the process of controlling the first n-1 rows of the display panel to display black screens and displaying normal screens starting from the nth row is the same as when the screen of the display panel is Figure 1In the case of the display screen in (a), the first n-1 rows of the display panel are controlled to display a black screen, and the process of displaying a normal screen from the nth row is the same, and the control of displaying a black screen after the m+1th row only needs to be based on the step. When the gate control signal scans to the mth level, that is, before the mth level gate control signal starts to output, the second scanning signal select2 control signal changes from a high level to a low level. Similarly, the m+1th level shift register unit will not be triggered, that is, the gate control signal stops outputting after the mth level is output. In this way, the position on the display panel corresponding to the first n-1 level shift register is controlled to display a black screen, and the position on the display panel corresponding to the nth to mth level shift registers is controlled to display a normal screen, and the nth to mth level shift register units are normally triggered, and the position on the display panel corresponding to the m+1th level shift registers and the m+1th level shift registers and the m+1th level shift registers are not working.

[0046] To summarize, the above-mentioned shift register latches the first node N1 of the shift register that wants to start scanning to a high-level signal through a latch, so that by controlling the high and low levels of the first initial scanning signal STV', the shift register of this level can be made to work or not work, and the shift register unit can be triggered from any level, thereby realizing the opening of any level of shift register.

[0047] In some embodiments of the present application, Figure 3 A schematic diagram of a latch structure provided according to an embodiment of the present application is shown in FIG. Figure 3 As shown, the latch structure includes: a first inverter 11, the input end of the first inverter 11 is electrically connected to the first end of the second switch module; a first switch unit 12, the first end of the first switch unit 12 is electrically connected to the input end of the first inverter 11, the second end of the first switch unit 12 is electrically connected to the output end of the first inverter 11, and the third end of the first switch unit 12 is connected to the first scan line; a latch substructure 13, the first end of the latch substructure 13 is electrically connected to the fourth end of the first switch unit 12 and the first node N1 respectively, and the second end of the latch substructure 13 is electrically connected to the fifth end of the first switch unit 12.

[0048] Among them, the input terminal of the first inverter 11 is Figure 2 The connection point between the input terminal I of the latch structure, the first terminal of the latch substructure 13 and the fourth terminal of the first switch unit 12 is Figure 2The output terminal O of the latch structure is connected to the third terminal of the first switch unit 12, and the third terminal of the first switch unit 12 is connected to the first scan line for inputting the first scan signal select1. Wherein, when the first scan signal select1 is at a high level, the first switch unit 12 is turned on, and the signal inputted from the input terminal I of the latch structure is transmitted to the output terminal O of the latch structure. When the first scan signal select1 is at a low level, the first switch unit 12 is turned off, and the connection between the input terminal I of the latch structure and the output terminal O of the latch structure is disconnected, so that the signal at the input terminal I of the latch structure cannot affect the signal at the output terminal O of the latch structure, thereby realizing the latching of the signal at the output terminal O of the latch structure.

[0049] In some embodiments, Figure 4 FIG. 1 is a schematic diagram of another latch structure provided according to an embodiment of the present application, such as Figure 4 As shown, the first switch unit includes: a third switch module 121, the control end of the third switch module 121 is connected to the first scan line, the first end of the third switch module 121 is electrically connected to the first end of the second switch module 30, and the second end of the third switch module 121 is electrically connected to the first end of the latch substructure 13; a fourth switch module 122, the control end of the fourth switch module 122 is connected to the first scan line, the first end of the fourth switch module 122 is electrically connected to the output end of the first inverter 11, and the second end of the fourth switch module 122 is electrically connected to the second end of the latch substructure 13.

[0050] In which, when the signal at the input terminal I of the latch structure is a high-level signal and the first scanning signal select1 is a high-level signal, the third switch module 121 and the fourth switch module 122 are turned on, and the third switch module 121 transmits the high-level signal at the input terminal I of the latch structure to the first node N1, that is, the signal at the Q point is a high-level signal, and the high-level signal at the input terminal I of the latch structure is converted into a low-level signal through the reverse of the first inverter 11, and is transmitted to the fourth switch module 122. Point, that is The signal of the point is a low level signal.

[0051] When the signal at the input terminal I of the latch structure is a low level signal and the first scanning signal select1 is a high level signal, based on the same principle, the signal at the Q point is a low level signal. The signal of the point is a high level signal.

[0052] When the first scanning signal select1 is a low level signal, the third switch module 121 and the fourth switch module 122 are disconnected. At this time, the signal at the input terminal I of the latch structure cannot affect the Q point and The signal at the input terminal I of the latch structure cannot affect the signal at the first node N1, and the state of the signal at the first node N1 is maintained, thereby realizing the latch function.

[0053] In some embodiments, Figure 4 As shown, the third switch module 121 and the fourth switch module 122 are both N-type switch tubes.

[0054] In some embodiments, Figure 4 As shown, the latch substructure includes: a second inverter 131, the input end of the second inverter 131 is electrically connected to the first node N1 and the second end of the third switch module 121 respectively, and the output end of the second inverter 131 is electrically connected to the first end of the fourth switch module 122; a third inverter 132, the input end of the third inverter 132 is electrically connected to the first end of the fourth switch module 122, and the output end of the third inverter 132 is electrically connected to the first node N1 and the second end of the third switch module 121 respectively.

[0055] Wherein, when the signal at the input terminal I of the latch structure is a high level signal and the first scanning signal select1 is a high level signal, based on the principle, the signal at the Q point is a high level signal. The signal of the point is a low level signal. The low level signal at point Q is input to the second inverter 131, and the inverter reversely outputs a high level signal, which is the same as the signal at point Q. The high and low level signals at point Q are input to the third inverter 132, and the inverter reversely outputs a low level signal, which is the same as the signal at point Q. The signals at the points are the same, thus achieving signal latching.

[0056] In some embodiments, Figure 5 FIG. 1 is a schematic diagram of another latch structure provided according to an embodiment of the present application, such as Figure 5 As shown, the first inverter, the second inverter and the third inverter are each composed of an N-type transistor and a P-type transistor, wherein the gate of the N-type transistor is electrically connected to the gate of the P-type transistor, and the first electrode of the N-type transistor is electrically connected to the second electrode of the P-type transistor.

[0057] Among them, the first transistor M1 and the second transistor M2 form a third inverter, the third transistor M3 and the fourth transistor M4 form a second inverter, the fifth transistor M5 and the sixth transistor M6 form a first inverter, the seventh transistor M7 is a third switch module, the eighth transistor M8 is a fourth switch module, the first transistor M1, the third transistor M3, and the fifth transistor M5 are all P-type TFTs, and the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all N-type TFTs.

[0058] In some embodiments, Figure 5 As shown, a first electrode of the P-type transistor is electrically connected to a first power line, and a second electrode of the N-type transistor is electrically connected to a second power line.

[0059] Specifically, the first power line is used to provide a first reference voltage signal VGH, and the second power line is used to provide a second reference voltage signal VGL.

[0060] Among them, Figure 5 As shown, when the signal at the input terminal I of the latch structure is a high-level signal and the first scanning signal select1 is a high-level signal, the seventh transistor M7 and the eighth transistor M8 are turned on, and the seventh transistor M7 transmits the high-level signal at the input terminal I of the latch structure to the Q point, that is, the signal at the Q point is a high-level signal, and the high-level signal at the Q point controls the third transistor M3 to be turned off and the fourth transistor M4 to be turned on, and the fourth transistor M4 transmits the second reference voltage signal VGL to The high level signal at the input terminal I of the latch structure controls the fifth transistor M5 to turn off and the sixth transistor M6 to turn on. The sixth transistor M6 transmits the second reference voltage signal VGL to the eighth transistor M8. The eighth transistor M8 transmits the second reference voltage signal VGL to point, pull down from both directions at the same time The potential of the point can be pulled down faster The potential of the point is locked quickly. The low-level signal at point Q controls the first transistor M1 to turn on and the second transistor M2 to turn off. The first transistor M1 transmits the first reference voltage signal VGH to point Q, and simultaneously raises the potential of point Q from two directions, which can raise the potential of point Q faster and ensure the high-level signal at point Q, thereby realizing signal transmission and latching.

[0061] In some embodiments, Figure 6 FIG. 1 is a schematic diagram of the structure of another gate driving circuit provided according to an embodiment of the present application, such as Figure 6 As shown, the first switch module 20 includes: a first switch device M9, a control end of the first switch device M9 is electrically connected to the output end of the latch structure 10, a first end of the first switch device M9 is electrically connected to the first initial scan signal line, and a second end of the first switch device M9 is electrically connected to the input end of the shift register unit 03.

[0062] In some embodiments, Figure 6 As shown, the first switch device M9 is an N-type switch tube.

[0063] Among them, when the first node N1 (i.e., the output end of the latch structure 10) is at a high level, the first switch device M9 is turned on, and the first switch device M9 transmits the first initial scan signal STV' to the input end of the shift register unit 03. When the first node N1 (i.e., the output end of the latch structure 10) is at a low level, the first switch device M9 is turned off.

[0064] In some embodiments, Figure 6 As shown, the second switch module includes: a second switch device M10, a control end of the second switch device M10 is connected to the second scan line, a first end of the second switch device M10 is electrically connected to the output end of the bidirectional selector 01, and a second end of the second switch device M10 is electrically connected to the input end of the latch structure 10.

[0065] In some embodiments, Figure 6 As shown, the second switch device M10 is an N-type switch tube.

[0066] Among them, when the second scan signal select2 output by the second scan line is at a high level, the second switch device M10 is turned on, and the first switch device M10 transmits the signal at the output end of the bidirectional selector 01 to the input end of the shift register unit 03. When the second scan signal select2 is at a low level, the second switch device M10 is turned off.

[0067] In some embodiments, Figure 7 FIG. 1 is a schematic diagram of a structure of another gate driving circuit provided according to an embodiment of the present application, such as Figure 7 As shown, the shift register further includes an abnormal power-off controller 04 and an output buffer 05, wherein the abnormal power-off controller is used to disconnect the shift register of the current stage when an abnormality occurs in the shift register of the current stage.

[0068] The embodiment of the present application provides a control method of a gate drive circuit. Figure 8 FIG. 1 is a flow chart of a control method of a gate drive circuit provided according to an embodiment of the present application, such as Figure 8 As shown, the method is used to control any gate drive circuit, and the method includes:

[0069] Step S101, generating a driving signal set, wherein the driving signal set includes a plurality of level signals, and the plurality of level signals include: a first scanning signal and a second scanning signal;

[0070] Step S102, applying a first scanning signal to the latch structure to control the voltage of the first node, and controlling the on or off of the first switch module by controlling the voltage of the first node to control the gate control signal output by the shift register;

[0071] Step S103: applying a second scanning signal to the second switch module to control the connection or disconnection of the shift register of the current stage with the shift registers of other stages by controlling the conduction or disconnection of the second switch module.

[0072] The control method of the gate drive circuit of the present application first generates a drive signal set, which includes multiple level signals, including: a first scan signal and a second scan signal; then the first scan signal is applied to the latch structure to control the voltage of the first node, and by controlling the voltage of the first node, the first switch module is controlled to be turned on or off to control the gate control signal output by the shift register; finally, the second scan signal is applied to the second switch module to control the connection or disconnection of the current level shift register with the shift registers of other levels by controlling the conduction or disconnection of the second switch module. The method controls the signal input to the shift register unit by controlling the first scan signal and the second scan signal input in each frame, thereby triggering the shift register unit from any level, turning on the shift register of any level, and turning off the shift register of any level. In the normal picture display area, the shift register unit works and the shift register is opened and closed step by step; in the black picture display area, the shift register unit does not work and the gate control signal is not output, thereby achieving the purpose of reducing the power consumption of the shift register unit and solving the problem in the prior art that when the display screen only displays a partial area, all the driving circuits of the shift register units work, resulting in high power consumption.

[0073] In some embodiments, Figure 1 1 is a schematic diagram of the positions of the first display area and the second display area of ​​the display panel during the display process. The first display area and the second display area of ​​the display panel may appear alternately for multiple times during the display process, which will not be described one by one here. Figure 1 The following four situations are taken as examples to introduce.

[0074] Fig. 9 According to the embodiment of the present application, Figure 1 (a) The timing diagram of each signal in the gate drive circuit during the first frame scan, as shown in Figure 1 (a) Figure 7 and Fig. 9 As shown, the first display area of ​​the display panel, i.e., the first n-1 rows of the display panel, displays a black picture, and the second display area, i.e., the gate driving circuit outputs a valid level signal (such as a high level signal) from the nth row onwards, and the corresponding rows all display a normal picture. In this case, the method further includes the following steps:

[0075] Step S201, when the n-1th shift register has no signal output (i.e., the display area of ​​the corresponding row displays black) and the nth shift register outputs a valid gate control signal (i.e., the display area of ​​the corresponding row displays a normal picture), when the first frame is scanned to the n-1th shift register, the first scanning signal select1 is adjusted to a high level signal, and the first scanning signal select1 is applied to the latch structure 10 to adjust the voltage of the first node N1 of the nth shift register (i.e., Fig. 9 ln in the figure) is latched to a high level, n≥2;

[0076] Specifically, Figure 7 and Fig. 9 As shown in FIG. 1 , when the n-1th shift register has no signal output and the nth shift register outputs a valid gate control signal, it is necessary to control the shift register units of the previous n-1th shift register to not work, and start working from the nth shift register to drive the current level display. Therefore, it is necessary to first increase the voltage of the first node N1 (such as Fig. 9 In the example shown in Figure 1, the first n-1 shift register is latched to a high level. In this way, when the first n-1 shift registers do not work in the second frame (that is, the first n-1 shift registers have no signal output), the high-level signal of the first node N1 controls the first switch module to be turned on. By controlling the high and low levels of the first initial scanning signal STV', it is possible to directly start scanning from the n-th shift register or not to scan.

[0077] In some embodiments, Figure 7 and Fig. 9 As shown, the multiple level signals also include a first initial scanning signal STV', which is a signal output by a first initial scanning signal line, and the first initial scanning signal line is electrically connected to the first end of the first switch module (ninth transistor M9). When there is no signal output in the n-1th stage shift register and the nth stage shift register outputs a valid gate control signal, the first scanning signal select1 is adjusted to a high level signal when the first frame scans to the n-1th stage shift register, and the first scanning signal select1 is applied to the latch structure 10 to latch the voltage of the first node N1 of the nth stage shift register to a high level. Specifically, the following steps are included:

[0078] Step S2011, when the n-1th stage shift register has no signal output and the n-th stage shift register outputs a valid gate control signal, when the first frame scans to the n-1th stage shift register, the first scanning signal select1 and the first initial scanning signal are both adjusted to high level signals to pull the potential of the first node N1 to a high level;

[0079] Specifically, Figure 7 and Fig. 9As shown, when the n-1th shift register has no signal output and the n-th shift register outputs a valid gate control signal, the first scan signal select1 and the first initial scan signal are first adjusted to high-level signals when the first frame scans to the n-1th shift register. At this time, the latch structure 10 transmits the high-level signal of the first scan signal select1 to the first node N1, and the ninth transistor M9 is turned on by the high-level signal of the first node N1, and transmits the first initial scan signal STV' to the input end of the shift register unit. At this time, the input end of the shift register unit is input with a high-level signal.

[0080] Step S2012, after the potential of the first node N1 is pulled up to a high level, the first scanning signal select1 is adjusted to a low level signal to latch the voltage of the first node N1 of the n-th stage shift register to a high level;

[0081] Specifically, latching the voltage of the first node N1 of the nth stage shift register to a high level can keep the ninth transistor M9 in an on state, so that the input signal of the shift register unit in the nth stage shift register can be controlled by controlling the high and low levels of the first initial scan signal STV'.

[0082] In step S2013, after the voltage of the first node N1 is latched to a high level, the (n-1)th stage shift register outputs a high level signal and adjusts the first initial scanning signal STV' to a low level signal.

[0083] Specifically, Figure 7 and Fig. 9 As shown, since the voltage of the first node N1 is latched to a high level, the ninth transistor M9 is turned on. When the first initial scan signal is a low level signal, the ninth transistor M9 transmits the low level signal of the first initial scan signal STV' to the input end of the shift register unit of the n-th stage shift register. Since the second scan signal select2 is always in a high level state during the first frame scan, the tenth transistor M10 is always turned on during the first frame scan. At this time, the low level signal output by the n-1-th stage shift register is transmitted to the input end of the shift register unit of the n-th stage shift register through the bidirectional selector and the tenth transistor M10, ensuring that the signal at the input end of the shift register unit of the n-th stage shift register is a low level signal, thereby realizing the step-by-step scanning of the first frame.

[0084] In some embodiments, Figure 7 and Fig. 9As shown, the first n-1 levels are set to display a black picture, and the nth level starts to display a normal picture. When scanning the first frame, the second initial scanning signal STV first gives a high-level signal to the first-level shift register to drive the first-level shift register to scan normally. The gate control signal will be output step by step from the beginning to the end. The second scanning signal select2 is always at a high level to ensure that the tenth transistor M10 is always turned on, ensuring that the shift register unit from level 1 to level n outputs the gate control signal Gout normally in sequence. When the first frame signal scans to the n-1 stage, the n-1 stage shift register unit 03 outputs a high level, and the high level signal output by the n-1 stage shift register unit 03 is transmitted to the input end of the n-1 stage shift register unit 03 through the bidirectional selector 01 of the n-stage shift register and the tenth transistor M10. At this time, the first scanning signal select1 is pulled high, and the output end of the n-stage latch will be set high, that is, the signal of the first node N1 of the n-stage shift register is high, and the first initial scanning signal STV' is set high at the same time. When the signal of the first node N1 of the n-stage shift register is high, the ninth transistor M9 is turned on, and the high level of the first initial scanning signal STV' is transmitted to the input end of the shift register unit 03 of the n-stage shift register, ensuring that the signal input to the input end of the shift register unit 03 of the n-stage shift register is a high level signal. Before the gate control signal of the n-1th stage is pulled low, the first scanning signal select1 is pulled low first. At this time, due to the effect of the latch structure 10, the voltage of the first node N1 of the nth stage will be always latched at a high level. Since the first scanning signal select1 is always at a low potential when the signal is transmitted to the first n-1th stage shift register unit, the latch of the first n-1th stage shift register unit does not latch the potential. Therefore, the potential of the first node N1 of the first n-1th stage shift register unit is all low. During the period when the first scanning signal select1 is at a high level, the nth stage shift register has not yet transmitted a signal to the next stage shift register. Therefore, the shift registers after the n+1th stage have no input signals. In this case, even if the first scanning signal select1 is at a high level, no high-level signal can be transmitted to the first node N1 of the shift register after the n+1th stage. Therefore, the potential of the first node N1 of the shift register after the n+1th stage is also at a low level. Therefore, the potentials of the first nodes N1 of the latches of the shift register units at all stages except the nth stage shift register are all latched to a low potential, such as Fig. 9 As shown, Fig. 9Where ln is the potential of the first node N1 of the nth level, ln+1 is the potential of the first node N1 of the n+1th level, and ln+2 is the potential of the first node N1 of the n+2th level. It can be seen that the potentials of the first nodes N1 of the latches of the shift register units of all levels except the first node N1 of the nth level are all low potentials. In addition, when the gate control signal of the n-1th level is pulled low, the first initial scanning signal STV' is pulled low synchronously to ensure that the signal input to the shift register unit 03 is at a low level.

[0085] Fig.12 According to the embodiment of the present application, Figure 1 (b) The timing diagram of each signal in the gate drive circuit during the second frame scanning, refer to Figure 7 and Fig.12 The multiple level signals further include a first initial scanning signal STV', the first initial scanning signal STV' is a signal output by a first initial scanning signal line, the first initial scanning signal line is electrically connected to a first end of a first switch module (a ninth transistor M9), after latching a voltage of a first node of an n-th stage shift register to a high level, the method further includes the following steps:

[0086] Step S301, when the second frame scans to the n-1th stage shift register, the first initial scan signal STV' is adjusted to a high level signal and applied to the first switch module (ninth transistor M9), so that the first initial scan signal STV' is transmitted to the input end of the shift register unit in the nth stage shift register through the first switch module (ninth transistor M9),

[0087] Step S302, when the second frame scans to the nth stage shift register, the second scanning signal select2 is adjusted to a high level signal and applied to the second switch module (the tenth transistor M10) to control the second switch module (the tenth transistor M10) to be turned on.

[0088] Specifically, by controlling STV' to be a high-level signal, the first switch module (the ninth transistor M9) can transmit the high-level signal of STV' to the input end of the shift register unit in the n-th shift register, so that the shift register unit in the n-th shift register begins to have a high-level input signal, thereby making it possible for the n-th shift register to still work normally when the shift register units in the first n-1-th shift register are not working.

[0089] Fig.12 According to the embodiment of the present application, Figure 1 (b) The timing diagram of each signal in the gate drive circuit during the second frame scanning, as shown in Figure 7 and Fig.12 As shown, Fig.12Where ln is the potential of the first node N1 of the nth stage, ln+1 is the potential of the first node N1 of the n+1th stage, ln+2 is the potential of the first node N1 of the n+2th stage, the shift register driver does not work in the 1st to n-1st stages, and the nth stage shift register starts to work normally, that is, the shift register unit in the nth stage shift register outputs a valid signal (such as a high-level signal) to drive the current row display. Since ln is always at a high level, the ninth transistor M9 is turned on. At this time, the input terminal voltage of the shift register unit of the nth stage shift register is related to the first initial scanning signal STV'. When the second frame scans to the n-1th stage shift register, the first initial scanning signal STV' is at a high level, and the ninth transistor M9 of the nth stage shift register transmits the first initial scanning signal STV' to the input terminal of the shift register unit of the nth stage shift register.

[0090] When the second frame scans to the n-th level shift register, it is necessary to scan step by step starting from the n-th level shift register. Therefore, it is necessary to adjust the second scanning signal to a high level signal and apply it to the second switch module when the second frame scans to the n-th level shift register to control the second switch module to be turned on, thereby controlling the n-th level shift register to be connected to the n+1-th level shift register to realize the shift register scanning step by step starting from the n-th level.

[0091] In some embodiments, after the voltage of the first node of the n-th stage shift register is latched to a high level, the second scanning signal select2 is adjusted to a low level signal and applied to the second switch module (the tenth transistor M10) when the second frame scans to the n-1-th stage shift register, so as to control the second switch module (the tenth transistor M10) to be disconnected, thereby controlling the n-th stage shift register to be disconnected from the n-1-th stage shift register, and preventing the n-th stage gate control signal from being transmitted to the n-1-th stage shift register through the bidirectional selector of the n-th stage shift register.

[0092] When the second frame scans to the n-1th shift register, the first initial scan signal STV' is at a high level, and the ninth transistor M9 of the nth shift register transmits the first initial scan signal STV' to the input end of the shift register unit of the nth shift register. If the second scan signal select2 is a high level signal, the second switch module (the tenth transistor M10) may transmit the high level signal at the input end of the shift register unit to the gate signal output end of the n-1th shift register through the bidirectional selector, which will result in the output of the n-1th shift register not needing to output a valid level signal. Therefore, when the second frame scans to the n-1th shift register, the second scan signal select2 is adjusted to a low level signal, and the second switch module (the tenth transistor M10) can be controlled to be disconnected, thereby controlling the nth shift register to be disconnected from the n-1th shift register, and ensuring that the output of the n-1th shift register is not affected by the nth shift register.

[0093] In other embodiments, after the voltage of the first node of the nth shift register is latched to a high level, when the second frame scans the nth shift register, the first initial scanning signal STV' is adjusted to a low level and applied to the first switch module (ninth transistor M9).

[0094] When scanning starts from the nth stage shift register, it is only necessary to provide the nth stage shift register with a high-level driving signal, that is, the first initial scanning signal STV' provides the nth stage shift register with a high-level driving signal to drive the nth stage shift register to work. When the second frame scans to the nth stage shift register, the first initial scanning signal STV' is at a low level. If the first initial scanning signal STV' is kept at a high level for a long time, since the ninth transistor M9 of each stage shift register is connected to the first initial scanning signal line, in some cases the ninth transistor M9 will have leakage, that is, the high level of the first initial scanning signal STV' will leak to the shift register unit. If the ninth transistor M9 of the shift register other than the nth stage has leakage, it will cause the shift register of the stage where the leakage occurs to work. In order to avoid the leakage, the first initial scanning signal is adjusted to a high level signal only when the second frame scans to the n-1th stage shift register, and the first initial scanning signal STV' is adjusted to a low level when the second frame scans to the nth stage shift register.

[0095] In other embodiments, when the second frame scans to the n-1th stage shift register, the second scanning signal is adjusted to a low level signal and applied to the second switch module to control the second switch module to disconnect, thereby controlling the nth stage shift register to disconnect from the n-1th stage shift register; and when the second frame scans to the nth stage shift register, the first initial scanning signal is adjusted to a low level and applied to the first switch module.

[0096] Among them, during the second frame scan, since the voltage of the first node N1 of the n-th shift register is latched to a high level, the ninth transistor M9 of the n-th shift register is turned on, and the first initial scan signal STV' is adjusted to a high level signal, and the ninth transistor M9 of the n-th shift register transmits the first initial scan signal STV' to the input end of the shift register unit of the n-th shift register to control the shift register unit of the n-th shift register to drive the current row display. At this time, the input end voltage of the shift register unit of the n-th shift register is a high level signal. If the second scan signal select2 is a high level signal, the second switch module (the tenth transistor M10) of the n-th shift register will transmit the high level signal of the input end of the shift register unit to the gate signal output end of the n-1-th shift register through the bidirectional selector, which will affect the output of the n-1-th shift register. Therefore, when scanning the second frame, the second scanning signal select2 is adjusted to a low level signal, which can control the second switch module (the tenth transistor M10) of the n-th shift register to be disconnected, thereby controlling the n-th shift register to be disconnected from the n-1-th shift register, ensuring that the output of the n-1-th shift register is not affected by the n-th shift register.

[0097] In some embodiments of the present application, Figure 7 and Fig.12 As shown, the multiple level signals also include a second initial scanning signal STV, the second initial scanning signal STV is a signal output by a second initial scanning signal line, the second initial scanning signal line is electrically connected to the signal input end of the first-stage shift register, the second initial scanning signal is used to drive the first-stage shift register, and the method also includes: during the second frame scanning, the second initial scanning signal STV is always a low-level signal.

[0098] During the second frame scan, the second initial scan signal STV is always at a low level, that is, the second initial scan signal STV does not provide a driving signal to the first-stage shift register. At this time, the first-stage shift register to the n-1-stage shift register do not work, thereby achieving the purpose of reducing the power consumption of the shift register unit. When the normal timing signal scans to the n-1-stage, the first initial scan signal STV' becomes a high level. Since the voltage of the first node N1 of the n-stage shift register is always locked at a high level, the high-level signal of the first initial scan signal STV' is transmitted to the shift register unit 03 of the n-stage shift register through the ninth transistor M9 of the n-stage shift register, and the n-stage shift register unit 03 starts to trigger. Specifically, Fig.12 As shown, G1 is the gate control signal output by the first-stage shift register, G2 is the gate control signal output by the second-stage shift register, ..., Gn-1 is the gate control signal output by the n-1th-stage shift register, Gn is the gate control signal output by the n-th-stage shift register, Gn+1 is the gate control signal output by the n+1th-stage shift register, and Gn+2 is the gate control signal output by the n+2th-stage shift register. It can be seen that the first n-1-stage shift registers do not output any signals, that is, the first-stage shift register to the n-1th-stage shift register do not work, and the nth-stage shift register starts to work, thereby achieving the purpose of reducing the power consumption of the shift register unit.

[0099] In some embodiments, Figure 7 and Fig.12 As shown, when the m-th shift register outputs a valid gate control signal (i.e., the display area of ​​the corresponding row displays a normal picture) and the m+1-th shift register has no signal output (i.e., the display area of ​​the corresponding row displays black), the second scanning signal select2 is adjusted to a low level signal and applied to the second switch module (the tenth transistor M10) to control the second switch module (the tenth transistor M10) to be disconnected, thereby controlling the m-th shift register to be disconnected from the m+1-th shift register, where m≥2.

[0100] In some embodiments, m>n, such as Figure 1 (b) Figure 7 and Fig.12 As shown, the first n-1 rows of the display panel display a black screen (i.e. Figure 1 (b) The first display area in the upper area of ​​the display panel, such as Figure 7 The nth to mth rows display normal images (i.e. Figure 1 (b) The second display area of ​​the display panel, such as Figure 7 The image is shown in area B in the figure), and a black screen is displayed after the m+1th line (i.e. Figure 1 (b) The first display area in the lower area of ​​the display panel, such as Figure 7As shown in area C in the middle, that is, the m-th shift register drives the row for display, and the m+1-th shift register has no signal output. In this case, steps S201, S2011, S2012, S2013, S301, S302, S401 and S302 are first used to control the first n-1 rows of the display panel to display a black picture, and to display a normal picture from the n-th row, that is, to start normal scanning from the n-th row, and then when the second frame scans to the m-th shift register, the second scanning signal select2 is adjusted to a low level signal and applied to the second switch module (the tenth transistor M10) to control the second switch module (the tenth transistor M10) to be disconnected, thereby controlling the m-th shift register to be disconnected from the m+1-th shift register.

[0101] When the gate control signal scans to the mth stage, that is, when the gate control signal of the mth stage is at a high level, the second scanning signal select2 is changed from a high level to a low level, which will disconnect the connection between the mth stage shift register and the m+1th stage shift register, and the gate control signal output by the mth stage shift register will not trigger the shift register unit of the m+1th stage shift register, that is, the gate control signal stops scanning after being output at the mth stage. Fig.12 As shown, Gm is the gate control signal output by the m-th shift register, and Gm+1 is the gate control signal output by the m+1-th shift register. It can be seen that the normal scan starts from the n-th shift register to the m-th shift register, and then the second scanning signal select2 changes from a high level to a low level, disconnecting the connection between the m-th shift register and the m+1-th shift register. There is no signal input to the shift registers after the m+1-th level, that is, the shift registers after the m+1-th level do not work, and there is no gate control signal output, thereby achieving the purpose of reducing the power consumption of the shift register unit.

[0102] Fig.13 According to the embodiment of the present application, Figure 1 (c) The timing diagram of each signal in the gate drive circuit during scanning, such as Figure 1 (c) Figure 7 and Fig.13 As shown, the first m rows of the display panel display normal images (i.e. Figure 1 (c) The second display area, such as Figure 7 The image is shown in the middle area D), and a black screen is displayed after the m+1th line (i.e. Figure 1 (c) The first display area, such as Figure 7As shown in the middle area C, in this embodiment, the second initial scanning signal STV first gives a high level signal to the first-stage shift register to drive the first-stage shift register to scan normally, and the gate control signal will be output step by step from the beginning to the end. The second scanning signal select2 is always at a high level to ensure that the tenth transistor is always turned on. After that, when scanning to the m-th stage shift register, the second scanning signal select2 is adjusted to a low level signal and applied to the second switch module (the tenth transistor M10) to control the second switch module (the tenth transistor M10) to disconnect, thereby controlling the m-th stage shift register to disconnect from the m+1-th stage shift register. At this time, the m+1-th stage shift register has no input signal drive, so the m+1-th stage shift register does not work, and the corresponding row on the display panel displays a black screen.

[0103] In some other embodiments, m+1<n-1, Fig.14 is a schematic structural diagram of another gate driving circuit provided according to an embodiment of the present application, Fig.15 According to the embodiment of the present application, Figure 1 (d) The timing diagram of each signal in the gate drive circuit during the second frame scanning, as shown in Figure 1 (d) Fig. 9 , Fig.14 and Fig.15 As shown, the first m rows of the display panel display normal images (i.e. Figure 1 (d) The second display area in the upper area of ​​the display panel, such as Fig.14 The m+1th row to the n-1th row display a black screen (i.e. Figure 1 (d) The first display area of ​​D, such as Fig.14 The normal screen is displayed after the nth line (i.e. Figure 1 (d) The second display area in the lower area of ​​the display panel, such as Fig.14 In the first frame scan, the signal of the first node N1 of the shift register unit in the nth row is latched to a high level in the same manner as shown in the area C in the middle. Fig. 9 As shown in FIG. 1 , the potential of the first node N1 of the first n-1 shift register units is low level. Fig. 9 As shown in ln+1 and ln+2. Fig.15As shown, during the second frame scanning, the second initial scanning signal STV first gives a high level signal to the first-stage shift register to drive the first-stage shift register to scan normally, the gate control signal will be output step by step from the beginning to the end, the second scanning signal select2 is always high level, to ensure that the tenth transistor is always turned on, and then when scanning to the m-th stage shift register, the second scanning signal select2 is adjusted to a low level signal and applied to the second switch module (the tenth transistor M10) to control the second switch module (the tenth transistor M10) to disconnect, thereby controlling the m-th stage shift register to disconnect from the m+1-th stage shift register. At this time, there is no signal input from the m+1-th stage shift register to the n-1-th stage shift register, the shift register does not work, and the corresponding row on the display panel displays a black screen. When the second frame scans to the n-1th level shift register, the first initial scanning signal STV' becomes a high level. Since the voltage of the first node N1 of the nth level shift register is always locked at a high level, the high level signal of the first initial scanning signal STV' will be transmitted to the shift register unit 03 of the nth level shift register through the ninth transistor M9 of the nth level shift register. The nth level shift register unit 03 starts to trigger, thereby realizing the output of the gate control signal step by step starting from the nth level.

[0104] At the same time, in order to prevent the tenth transistor M10 of the n-th shift register from transmitting the high-level signal of the input end of the n-th shift register unit to the gate signal output end of the n-1-th shift register through the bidirectional selector, thereby affecting the output of the n-1-th shift register. Therefore, when the second frame scans to the n-1-th shift register, the second scanning signal select2 is adjusted to a low-level signal, and the second switch module (the tenth transistor M10) can be controlled to be disconnected, thereby controlling the n-th shift register to be disconnected from the n-1-th shift register, and ensuring that the output of the n-1-th shift register is not affected by the n-th shift register.

[0105] The embodiment of the present application further provides a display panel, Fig.16 A schematic diagram of the structure of a display panel provided according to an embodiment of the present application is shown in FIG. Fig.16 As shown, it includes: any one of the gate driving circuits gr; a first scanning signal generator, configured to generate a first scanning signal; and a second scanning signal generator, configured to generate a second scanning signal.

[0106] Among them, the display panel includes: a display area AA and a non-display area BB; the display area AA includes multiple gate lines G and multiple data lines S insulated and intersecting with the gate lines G; the non-display area BB includes the gate drive circuit gr provided by any embodiment of the present invention, and the gate signal output end of each shift register unit is electrically connected to a gate line G.

[0107] It should be noted that the gate drive circuit can be single-sided drive or double-sided drive. Fig.15 The figure is only a schematic diagram of double-sided driving, and the specific driving method can be adjusted according to actual needs.

[0108] In the specific implementation, in the implementation of the present invention, a display device is also provided, and the display device includes a display panel. The display device provided in this embodiment can be an array substrate or a terminal display device, such as a mobile phone, a computer, a television, or other display devices with display functions. The present invention does not impose specific restrictions on this. The display device provided in the embodiment of the present invention has the beneficial effects of the gate drive circuit provided in the embodiment of the present invention. For details, please refer to each embodiment. The specific description of the gate drive circuit is not repeated in this embodiment.

[0109] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0110] From the above description, it can be seen that the embodiments of the present application achieve the following technical effects:

[0111] 1) The technical solution of the present application is a gate drive circuit, which includes a plurality of cascaded shift registers, each of which includes a bidirectional selector, a latch, and a shift register unit connected in sequence, and the latch includes an electrically connected latch structure, a first switch module, and a second switch module, wherein the first scan signal output by the first scan line connected to the latch structure is used to control the voltage of the first node, and the voltage of the first node controls the gate control signal of the shift register by controlling the conduction or disconnection of the first switch module; the second scan signal output by the second scan line connected to the second switch module controls the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module. The gate drive circuit adds a latch to each shift register, and through the control signal line, it can realize the triggering of the shift register unit from any stage, thereby realizing the opening of any stage of the shift register, and can also realize the closing of any stage of the shift register. In the normal picture display area, the shift register unit works and the shift register is opened and closed step by step; in the black picture display area, the shift register unit does not work and the gate control signal will not be turned on, thereby achieving the purpose of reducing the power consumption of the shift register unit and solving the problem in the prior art that when the display screen only displays a partial area, all the driving circuits of the shift register units work, resulting in high power consumption.

[0112] 2) The control method of the gate drive circuit of the present application first generates a drive signal set, which includes multiple level signals, including: a first scan signal and a second scan signal; then the first scan signal is applied to the latch structure to control the voltage of the first node, and by controlling the voltage of the first node, the first switch module is controlled to be turned on or off to control the gate control signal output by the shift register; finally, the second scan signal is applied to the second switch module to control the connection or disconnection of the current level shift register with the shift registers of other levels by controlling the conduction or disconnection of the second switch module. The method controls the first scan signal and the second scan signal input in each frame, thereby controlling the signal input to the shift register unit, triggering the shift register unit from any level, opening the shift register of any level, and also turning off the shift register of any level. In the normal picture display area, the shift register unit works and the shift register is opened and closed step by step; in the black picture display area, the shift register unit does not work and the gate control signal will not be turned on, thereby achieving the purpose of reducing the power consumption of the shift register unit and solving the problem in the prior art that when the display screen only displays a partial area, all the driving circuits of the shift register units work, resulting in high power consumption.

[0113] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: A plurality of cascaded shift registers are included, and gate control signals are sequentially outputted through gate control lines. Each of the shift registers includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes an electrically connected latch structure, a first switch module, and a second switch module, wherein: The control end of the latch structure is connected to a first scan line, and a first scan signal output by the first scan line is used to control a voltage of a first node, the first node is a node where the latch structure is connected to the first switch module, and the voltage of the first node is used to control the conduction or disconnection of the first switch module to control the gate control signal output by the shift register, and the shift register unit is electrically connected to the first switch module; The control end of the second switch module is connected to the second scan line, and the second scan signal output by the second scan line is used to control the connection or disconnection of the shift register of the current stage with the shift registers of other stages by controlling the conduction or disconnection of the second switch module, and the bidirectional selector is electrically connected to the second switch module.

2. The gate driving circuit according to claim 1, characterized in that: The latch structure comprises: A first inverter, wherein an input terminal of the first inverter is electrically connected to a first terminal of the second switch module; a first switch unit, wherein a first end of the first switch unit is electrically connected to an input end of the first inverter, a second end of the first switch unit is electrically connected to an output end of the first inverter, and a third end of the first switch unit is connected to the first scan line; A latch substructure, wherein a first end of the latch substructure is electrically connected to the fourth end of the first switch unit and the first node respectively, and a second end of the latch substructure is electrically connected to the fifth end of the first switch unit.

3. The gate driving circuit according to claim 2, characterized in that: The first switch unit comprises: a third switch module, wherein a control end of the third switch module is connected to the first scan line, a first end of the third switch module is electrically connected to a first end of the second switch module, and a second end of the third switch module is electrically connected to a first end of the latch substructure; A fourth switch module, wherein a control end of the fourth switch module is connected to the first scan line, a first end of the fourth switch module is electrically connected to the output end of the first inverter, and a second end of the fourth switch module is electrically connected to the second end of the latch substructure.

4. The gate driving circuit according to claim 3, characterized in that: The third switch module and the fourth switch module are both N-type switch tubes.

5. The gate driving circuit according to claim 3, characterized in that: The latch substructure comprises: a second inverter, wherein an input end of the second inverter is electrically connected to the first node and the second end of the third switch module respectively, and an output end of the second inverter is electrically connected to the first end of the fourth switch module; A third inverter, wherein an input end of the third inverter is electrically connected to a first end of the fourth switch module, and an output end of the third inverter is electrically connected to the first node and a second end of the third switch module respectively.

6. The gate driving circuit according to claim 5, characterized in that: The first inverter, the second inverter and the third inverter are each composed of an N-type transistor and a P-type transistor, wherein the gate of the N-type transistor is electrically connected to the gate of the P-type transistor, and the first electrode of the N-type transistor is electrically connected to the second electrode of the P-type transistor.

7. The gate driving circuit according to claim 6, characterized in that: A first electrode of the P-type transistor is electrically connected to a first power line, and a second electrode of the N-type transistor is electrically connected to a second power line.

8. The gate driving circuit according to claim 1, characterized in that: The first switch module comprises: A first switch device, wherein a control end of the first switch device is electrically connected to an output end of the latch structure, a first end of the first switch device is electrically connected to a first initial scan signal line, and a second end of the first switch device is electrically connected to an input end of the shift register unit.

9. The gate driving circuit according to claim 8, characterized in that: The first switch device is an N-type switch tube.

10. The gate driving circuit according to claim 1, characterized in that: The second switch module includes: A second switch device, wherein a control end of the second switch device is connected to the second scan line, a first end of the second switch device is electrically connected to the output end of the bidirectional selector, and a second end of the second switch device is electrically connected to the input end of the latch structure.

11. The gate driving circuit according to claim 10, characterized in that: The second switch device is an N-type switch tube.

12. A control method for a gate drive circuit, characterized in that: The method is used to control the gate drive circuit according to any one of claims 1 to 11, and the method comprises: Generate a driving signal set, wherein the driving signal set includes a plurality of level signals, and the plurality of level signals include: a first scanning signal and a second scanning signal; Applying the first scanning signal to the latch structure to control the voltage of the first node, and controlling the on or off of the first switch module by controlling the voltage of the first node to control the gate control signal output by the shift register; The second scanning signal is applied to the second switch module to control the connection or disconnection of the shift register of the current stage with the shift registers of other stages by controlling the conduction or disconnection of the second switch module.

13. The control method according to claim 12, characterized in that: The method further comprises: When the n-1th shift register has no signal output and the nth shift register outputs a valid gate control signal, the first scanning signal is adjusted to a high level signal when the first frame scans to the n-1th shift register, and the first scanning signal is applied to the latch structure to latch the voltage of the first node of the nth shift register to a high level, n≥2; and / or, When the m-th shift register outputs a valid gate control signal and the m+1-th shift register has no signal output, the second scanning signal is adjusted to a low-level signal and applied to the second switch module to control the second switch module to disconnect, thereby controlling the m-th shift register to disconnect from the m+1-th shift register, m≥2.

14. The control method according to claim 13, characterized in that: The plurality of level signals further include a first initial scanning signal, the first initial scanning signal is a signal output by a first initial scanning signal line, the first initial scanning signal line is electrically connected to a first end of a first switch module, and when no signal is outputted by an n-1-th stage shift register and an n-th stage shift register outputs a valid gate control signal, the first scanning signal is adjusted to a high level signal when the first frame scans to the n-1-th stage shift register, and the first scanning signal is applied to the latch structure to latch the voltage of the first node of the n-th stage shift register to a high level, including: When the n-1th shift register has no signal output and the nth shift register outputs a valid gate control signal, when the first frame scans to the n-1th shift register, the first scanning signal and the first initial scanning signal are both adjusted to high level signals to pull the potential of the first node to a high level; After the potential of the first node is pulled up to a high level, the first scanning signal is adjusted to a low level signal to latch the voltage of the first node of the n-th stage shift register to a high level; After the voltage of the first node is latched to a high level, the (n-1)th stage shift register outputs a high level signal and adjusts the first initial scanning signal to a low level signal.

15. The control method according to claim 13, characterized in that: The plurality of level signals further include a first initial scanning signal, the first initial scanning signal is a signal output by a first initial scanning signal line, the first initial scanning signal line is electrically connected to a first end of a first switch module, and after latching the voltage of the first node of the n-th stage shift register to a high level, the method further includes: When the second frame scans to the n-1th stage shift register, the first initial scanning signal is adjusted to a high level signal and applied to the first switch module, so that the first initial scanning signal is transmitted to the input end of the shift register unit in the nth stage shift register through the first switch module, When the second frame scans to the n-th stage shift register, the second scanning signal is adjusted to a high level signal and applied to the second switch module to control the second switch module to be turned on.

16. The control method according to claim 15, characterized in that: After latching the voltage of the first node of the nth stage shift register to a high level, the method further includes: When the second frame scans to the n-1th stage shift register, the second scanning signal is adjusted to a low level signal and applied to the second switch module to control the second switch module to be disconnected, thereby controlling the nth stage shift register to be disconnected from the n-1th stage shift register; and / or, When the second frame scans to the nth stage shift register, the first initial scanning signal is adjusted to a low level and applied to the first switch module.

17. The control method according to claim 13, characterized in that: The plurality of level signals further include a second initial scanning signal, the second initial scanning signal is a signal output by a second initial scanning signal line, the second initial scanning signal line is electrically connected to a signal input terminal of the first-stage shift register, the second initial scanning signal is used to drive the first-stage shift register, and the method further includes: During the second frame scanning, the second initial scanning signal is always a low level signal.

18. The control method according to claim 13, characterized in that: m+1<n-1, or, m>n.

19. A display panel, characterized in that: include: The gate drive circuit according to any one of claims 1 to 11; A first scanning signal generator configured to generate a first scanning signal; The second scanning signal generator is configured to generate a second scanning signal.

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