Display panel, control method thereof and electronic equipment

Abstract

The invention provides a display panel, a control method thereof and electronic equipment, and relates to the technical field of display control. When the display panel is shut down, the multipath output selector is controlled to connect the data line and the data transmission signal line for a set time length and then disconnect the data line and the data transmission signal line, and within the set time length when the data line and the data transmission signal line are connected, charges on the data line can be fully released through the data transmission line. Therefore, when the display panel is shut down, the purpose of controlling the charge on the data line to be fully released is achieved by controlling the turn-off time of the delay multi-path output selector, so that the performance of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display control technology, and more specifically, to a display panel and a control method thereof and an electronic device. Background Art

[0002] With the development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today; among which the main component of electronic devices to realize the display function is the display panel. When the existing display panel is turned off, the charge in the data line of the display panel cannot be fully released, which affects the performance of the display panel. Summary of the invention

[0003] In view of this, the present application provides a display panel, a control method thereof and an electronic device, which effectively solve the technical problems existing in the prior art. When the display panel is turned off, the data line of the multi-way output selector is controlled to be connected to the data transmission signal line for a set period of time and then disconnected. By controlling the shutdown time of the delayed multi-way output selector, the purpose of controlling the full release of the charge on the data line is achieved, thereby improving the performance of the display panel.

[0004] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0005] A control method for a display panel, the display panel comprising: a plurality of pixel units; a plurality of data lines, the data lines being electrically connected to the pixel units; a plurality of multiplexers, the multiple output ends of the multiplexers being electrically connected to one of the data lines respectively, the control end of the multiplexers being electrically connected to a selection control signal line, and the input end of the multiplexers being electrically connected to a data transmission signal line; wherein the control method comprises:

[0006] When the display panel is turned off, a high-level voltage is applied to the enable control signal line to control the multi-way output selector to connect the data line with the data transmission signal line for a set period of time, and then a ground voltage is applied to the enable control signal line to control the multi-way output selector to disconnect the data line from the data transmission signal line.

[0007] Based on the same inventive concept, the present application also provides a display panel, including:

[0008] A plurality of pixel units;

[0009] A plurality of data lines, wherein the data lines are electrically connected to the pixel units;

[0010] A plurality of multiplexer selectors, wherein a plurality of output ends of the multiplexer selectors are electrically connected to one of the data lines respectively;

[0011] A controller, wherein the controller is electrically connected to the control end of the multi-way output selector through a selection control signal line, and the controller is electrically connected to the input end of the multi-way output selector through a data transmission signal line; the controller is used to output a high-level voltage to the selection control signal line when the display panel is turned off, so as to control the multi-way output selector to connect the data line with the data transmission signal line for a set time, and then output a ground voltage to the selection control signal line to control the multi-way output selector to disconnect the data line from the data transmission signal line.

[0012] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned display panel.

[0013] Compared with the prior art, the technical solution provided by this application has at least the following advantages:

[0014] The present application provides a display panel, a control method thereof and an electronic device, wherein the display panel comprises: a plurality of pixel units; a plurality of data lines, wherein the data lines are electrically connected to the pixel units; a plurality of multi-way output selectors, wherein the plurality of output ends of the multi-way output selectors are electrically connected to one of the data lines respectively, the control end of the multi-way output selector is electrically connected to a selection control signal line, and the input end of the multi-way output selector is electrically connected to a data transmission signal line; wherein the control method comprises: when the display panel is turned off, applying a high-level voltage to the selection control signal line to control the multi-way output selector to connect the data line with the data transmission signal line for a set time, and then applying a ground voltage to the selection control signal line to control the multi-way output selector to disconnect the data line from the data transmission signal line.

[0015] As can be seen from the above content, the technical solution provided by the present application controls the multiplexer to connect the data line with the data transmission signal line for a set time and then disconnect it when the display panel is turned off, and during the set time when the data line is connected to the data transmission signal line, the charge on the data line can be fully released through the data transmission line. Therefore, when the display panel is turned off, by controlling the closing time of the delayed multiplexer, the purpose of controlling the charge on the data line to be fully released is achieved, thereby improving the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0018] Figure 2 A flow chart of a method for controlling a display panel provided in an embodiment of the present application;

[0019] Figure 3 A flowchart of another display panel control method provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0021] Figure 5 A flowchart of another display panel control method provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of a shift register circuit provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0025] Fig. 9 A flowchart of another display panel control method provided in an embodiment of the present application;

[0026] Fig.10 A shutdown timing diagram of a display panel provided in an embodiment of the present application;

[0027] Fig.11 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0028] Fig.12 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0029] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] As described in the background technology, with the development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people at present; among which the main component of electronic devices to realize the display function is the display panel. When the existing display panel is turned off, the charge in the data line of the display panel cannot be fully released, which affects the performance of the display panel.

[0032] Based on this, the embodiments of the present application provide a display panel, a control method thereof, and an electronic device, which effectively solve the technical problems existing in the prior art. When the display panel is turned off, the data line of the multi-way output selector is controlled to be connected to the data transmission signal line for a set period of time and then disconnected. By controlling the delay of the closing time of the multi-way output selector, the purpose of controlling the full release of the charge on the data line is achieved, thereby improving the performance of the display panel.

[0033] To achieve the above purpose, the technical solution provided in the embodiment of the present application is as follows, specifically combined with Figures 1 to 13 The technical solution provided in the embodiments of the present application is described in detail.

[0034] Combination Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application, specifically a wiring diagram of some circuits in a display panel, Figure 2A flow chart of a control method of a display panel provided in an embodiment of the present application. The display panel provided in an embodiment of the present application includes: a plurality of pixel units Pi; a plurality of data lines Di, the data lines Di being electrically connected to the pixel units Pi; a plurality of multiplexer selectors Demux, the multiple output ends of the multiplexer selectors Demux being electrically connected to one of the data lines Di respectively, the control end of the multiplexer selectors Demux being electrically connected to the selection control signal line Sx, and the input end of the multiplexer selectors Demux being electrically connected to the data transmission signal line Dix. In some embodiments, during the display panel display process, the multiplexer selector Demux controls only one data line Di to be connected to the data transmission signal line Dix at the same time; that is, during the display panel display process, when the pixel unit Pi is scanned, the multiplexer selector Demux is controlled according to the control timing to select one of the data lines Di to be connected to the data transmission line signal line Dix, so as to transmit a data voltage to the data line Di through the data transmission signal line Dix, thereby providing the corresponding data voltage to the pixel unit Pi through the data line Di.

[0035] In some embodiments, the type of transistor included in the multi-way output selector Demux provided in the embodiment of the present application is an N-type transistor, specifically a metal oxide thin film transistor, wherein the metal oxide thin film transistor uses metal oxide as the channel layer material of the thin film transistor, and the metal oxide thin film transistor has advantages such as high electron mobility, and can improve the performance of the display panel. Optionally, the selection transistor provided in the embodiment of the present application may be an IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) thin film transistor. The multi-way output selector Demux provided in the embodiment of the present application limits the number of selection transistors included according to the number of its output terminals, such as when the multi-way output selector Demux can be a two-way output selector, or a three-way output selector, or a selector of more output terminals, respectively corresponding to two selection transistors, or three selection transistors, or a larger number of selection transistors, the present application does not make specific restrictions on this, and needs to be specifically selected according to the actual application.

[0036] Continue as Figure 1As shown, the embodiment of the present application takes the multiplexer Demux as a two-way output selector as an example for explanation, and the multiplexer Demux includes a first selection transistor Mux1 and a second selection transistor Mux2, and the first selection transistor Mux1 and the second selection transistor Mux2 are both N-type transistors. In order to be able to independently control the first selection transistor Mux1 and the second selection transistor Mux2, the selection control signal line Sx includes a first sub-selection control signal line Sx1 and a second sub-selection control signal line Sx2, the first sub-selection control signal line Sx1 is electrically connected to the gate of the first selection transistor Mux1, and the second sub-selection control signal line Sx2 is electrically connected to the gate of the second selection transistor Mux2. In addition, the first end of the first selection transistor Mux1 and the second selection transistor Mux2 selection transistor is electrically connected as the input end of the multiplexer Demux, and is electrically connected to the data transmission signal line Dix, the second end of the first selection transistor Mux1 is electrically connected to the first data line Di1, and the second end of the second selection transistor Mux2 is electrically connected to the second data line Di2. During the display process of the display panel, when the pixel unit Pi electrically connected to the first data line Di1 is scanned, a high-level voltage is applied to the first sub-selection signal line Sx1 according to the control timing, thereby controlling the first selection transistor Mux1 to be turned on, so as to connect the first data line Di1 with the data transmission signal line Dix, and the data transmission signal line Dix applies the corresponding data voltage to the corresponding pixel unit Pi through the first data line Di1; and at the same time, a low-level voltage is applied to the second sub-selection signal line Sx2 to control the second selection transistor Mux2 to be turned off.

[0037] It should be noted that the multiplexer output selector Demux and the electrical connection relationship between the multiplexer output selector Demux and the pixel unit Pi provided in the embodiment of the present application are not limited to Figure 1 Connection method shown. Figure 1 The electrical connection method between the multiplexer Demux and the pixel unit Pi shown is only one of all the connection methods applicable to the present application, and needs to be specifically designed according to the actual application.

[0038] Based on the display panel described above, when the display panel provided in the embodiment of the present application is turned off, the corresponding control method includes: S1, applying a high-level voltage to the selection control signal line Sx to control the multiplexer Demux to connect the data line Di with the data transmission signal line Dix for a set time. S2, applying a ground voltage to the selection control signal line Sx to control the multiplexer Demux to disconnect the data line Di from the data transmission signal line Dix. That is to say, the technical solution provided by the embodiment of the present application is that when the display panel is turned off, a high-level voltage of a set duration is applied to the selection control signal line Sx, thereby controlling all the selection transistors in the multi-way output selector Demux to be turned on for the set duration, so as to control the multi-way output selector Demux to connect all the data lines Di with the data transmission signal line Dix for the set duration; thereafter, a ground voltage is applied to the selection control signal line Sx, thereby controlling all the selection transistors in the multi-way output selector Demux to be turned off, so as to control the multi-way output selector Demux to disconnect the data lines Di and the data transmission signal line Dix.

[0039] As can be seen from the above content, the technical solution provided by the embodiment of the present application is that when the display panel is turned off, the multi-way output selector Demux is controlled to connect the data line Di with the data transmission signal line Dix for a set time and then disconnect it, and within the set time when the data line Di is connected to the data transmission signal line Dix, the charge on the data line Di can be fully released through the data transmission line Dix. Therefore, when the display panel is turned off, by controlling the closing time of the delayed multi-way output selector Demux, the purpose of controlling the charge on the data line Di to be fully released is achieved, thereby improving the performance of the display panel. In some embodiments, when the display panel is turned off, and within the set time when the multi-way output selector Demux is controlled to connect the data line Di with the data transmission signal line Dix, an optimized voltage can be applied to the data transmission signal line Dix to improve the efficiency of the data line Di in releasing the charge. Specifically, the control method provided in the embodiment of the present application may include: applying a black screen data voltage to the data transmission signal line Dix within the set time length, wherein the black screen data voltage is close to 0V, while ensuring that the charge on the data line Di is released through the data transmission signal line Dix, it can also improve the charge release efficiency on the data line Di.

[0040] In addition, the technical solution provided in the embodiment of the present application, when controlling the multi-way output selector Demux to disconnect the data line Di from the data transmission signal line Dix, applies a ground voltage to the selection control signal line Sx, thereby being able to fully release the residual charge on the selection control signal line Sx, further improving the performance of the display panel. Furthermore, the voltage applied to the selection control signal line Sx can be slowly reduced from a high-level voltage to a ground voltage; that is, the application of a ground voltage to the selection control signal line Sx provided in the embodiment of the present application includes: after the set time length, the voltage applied to the selection control signal line Sx gradually changes from the high-level voltage to the ground voltage. For specific reference Figure 3 As shown, it is a flow chart of another control method of a display panel provided by an embodiment of the present application, wherein, in step S2, the voltage applied to the gate control signal line Sc gradually changes from a high level voltage to a ground voltage, so as to control the multi-way output selector Demux to disconnect the data line Di from the data transmission signal line Dix, so that the charges on the data line Di and the gate control signal line Sx can be fully released, and the feed-through charges when the gate transistor is turned off can be fully released. In addition, in the process of the voltage on the gate control signal line Sx gradually decreasing to the ground voltage, the gate transistor remains turned on, so that the charges on the data line Di can still be released through the data transmission signal line Dix, which is equivalent to extending the time for the data line Di to release the charges, and further improving the effect of the data line Di releasing the charges.

[0041] It is understandable that the transistor itself has parasitic capacitance. Due to the coupling effect of the parasitic capacitance, when the control signal obtained by the gate of the transistor changes from on to off, the transistor becomes off, but the parasitic capacitance still retains a certain voltage change, which is the feed-through voltage. Therefore, the voltage applied to the selection control signal line Sc in the embodiment of the present application is slowly reduced from a high-level voltage to a ground voltage, which can fully derive the feed-through charge retained during the parasitic capacitance shutdown process of the selection transistor, further improving the performance of the display panel. In addition, applying a gradual voltage to the signal line can also improve the coupling problem between overlapping signal lines, avoiding the signal lines that have released other charges from generating charges again.

[0042] When the display panel is turned off, and within the set time period when the multiplexer output selector Demux is controlled to connect the data line Di with the data transmission signal line Dix, not only can the charge of the data line Di be released, but also the residual charge of the remaining lines of the display panel can be released. For example, in some embodiments, when the multiplexer output selector Demux is controlled to connect the data line Di with the data transmission signal line Dix for a set time period, while controlling the data line Di to release the charge through the data transmission signal line Dix, the scan drive circuit GOA can also be controlled to release the charge. Figure 4 and Figure 5 As shown, Figure 4 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, Figure 5 A flow chart of another control method provided in an embodiment of the present application. The display panel provided in an embodiment of the present application includes: a plurality of scan control signal lines Sc, wherein the scan control signal lines Sc are electrically connected to the pixel units Pi; and a scan drive circuit GOA, wherein the output end of the scan drive circuit GOA is electrically connected to the scan control signal line Sc. During the display process of the display panel, the scan drive circuit GOA outputs a scan control signal to the scan control signal line Sc, and the scan control signal line Sc transmits the scan control signal to the pixel unit Pi for scan-on control, so that the data line Di can transmit the data voltage to the pixel unit Pi. Figure 5 In step S1, the control method provided in the embodiment of the present application includes: controlling the scanning drive circuit GOA to power off within the set time period, so that while the data line Di releases the charge, the line charge in the scanning drive circuit GOA is released, further improving the performance of the display panel.

[0043] refer to Figure 6As shown, it is a structural schematic diagram of a shift register circuit provided in an embodiment of the present application, wherein the scan drive circuit GOA includes a plurality of cascaded shift register circuits, the shift register circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a first capacitor C1 and a second capacitor C2, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are all N-type transistors. Among them, the gate of the first transistor M1 is an opening end (in the cascaded multiple shift register circuits, the gate of the first transistor M1 of the first stage shift register circuit is electrically connected to the opening control signal line STV, and the opening scan control signal line STV is used to transmit the opening scan control signal), the first end of the first transistor M1 is electrically connected to the high power input signal line DIR1, and the high power input signal line DIR1 is used to transmit the high power supply voltage, and the second end of the first transistor M1 is electrically connected to the second end of the second transistor M2, the second end of the third transistor M3, the second end of the fourth transistor M4, the gate of the sixth transistor M6, the first plate of the second capacitor C2 and the gate of the seventh transistor M7. The gate of the second transistor M2 is a shutoff end (in the cascaded multiple shift register circuits, the gate of the second transistor M2 of the previous stage shift register circuit is electrically connected to the output end OUT' of the next stage shift register circuit), and the first end of the second transistor M2 is electrically connected to the low power input signal line DIR2, and the low power input signal line DIR2 is used to transmit the low power supply voltage. The gate of the third transistor M3 is electrically connected to the second plate of the first capacitor C1, the second end of the sixth transistor M6 and the gate of the eighth transistor M8, the first end of the third transistor M3 is electrically connected to the low level signal line VGL, and the low level signal line VGL is used to transmit a low level voltage. The gate of the fourth transistor M4 and the gate of the fifth transistor M5 are both electrically connected to the reset control signal line Reset, and the reset control signal line Reset is used to transmit a reset control signal. The first end of the fourth transistor M4 and the first end of the fifth transistor M5 are both electrically connected to the low level signal line VGL, and the second end of the fifth transistor M5, the second plate of the second capacitor C2, the second end of the seventh transistor M7, the second end of the eighth transistor M8 and the second end of the ninth transistor M9 are all electrically connected to the output end OUT of the shift register circuit. The first end of the sixth transistor M6 is electrically connected to the low level signal line VGL. The first end of the seventh transistor M7 and the first plate of the first capacitor C1 are both electrically connected to the clock control signal line CKB.The first end of the eighth transistor M8 and the first end of the ninth transistor M9 are both electrically connected to the low level signal line VGL, and the gate of the ninth transistor M9 is electrically connected to the clock control signal line CKA. The clock control signal line CKA and the clock control signal line CKB transmit clock signals of opposite phases.

[0044] It should be noted that Figure 6 The shift register circuit of the scan drive circuit GOA shown is the same as the existing circuit, and the present application is not an improvement on the composition and connection relationship of the shift register circuit, so this application will not make redundant descriptions. In addition, the scan drive circuit GOA provided in the embodiment of the present application is not limited to include Figure 6 The shift register circuit shown is one of all the scan drive circuits GOA applicable to the present application. In some other embodiments of the present application, the scan drive circuit GOA may also include other components and connected shift register circuits, or the scan drive circuit GOA is composed of other types of circuits, which is not specifically limited in the present application.

[0045] Combination Figure 6As shown, during the power-off process of the scanning drive circuit GOA provided in the embodiment of the present application, the charge of the pixel unit Pi can be first released through the cooperation of the scanning drive circuit GOA and the data line Di; then the charge of the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line (the level signal line includes the low level signal line VGL) in the scanning drive circuit GOA is released, and the charge of the reset control signal line Reset is incompletely released, so that the scanning drive circuit GOA output is powered off; finally, the charge of the reset control signal line Reset is completely released to complete the complete power-off of the scanning drive circuit GOA. Specifically, the start end of the scanning drive circuit GOA provided in the embodiment of the present application is electrically connected to the start control signal line STV, the clock end of the scanning drive circuit GOA is electrically connected to the clock control signal line CK, the reset end of the scanning drive circuit GOA is electrically connected to the reset control signal line Reset, the high power end of the scanning drive circuit GOA is electrically connected to the high power input signal line DIR1, the low power end of the scanning drive circuit GOA is electrically connected to the low power input signal line DIR2, and the level end of the scanning drive circuit GOA is electrically connected to the level signal line (hereinafter marked as the low level signal line VGL). The set duration includes a first discharge stage T1, wherein the high level voltage is applied to the start control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL in the first discharge stage. In the first discharge stage T1, the start control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL are all applied with a high level voltage, so that the connected transistors are controlled to be turned on, and at the same time, the scanning drive circuit GOA outputs a scanning control signal to the scanning control signal line Sc to scan and turn on the pixel unit Pi, thereby controlling part of the structure in the pixel unit Pi to release charge through the data line Di and the data transmission signal line Dix.

[0046] In an embodiment of the present application, the display panel provided in the embodiment of the present application may be a liquid crystal display panel, and the first discharge stage T1 may be a charge release stage of the pixel electrode Pix. Figure 7As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present application, wherein the display panel provided by the embodiment of the present application can be a liquid crystal display panel, and the pixel unit Pi includes a switch transistor Mk and a pixel electrode Pix electrically connected to the switch transistor Mk. The first end of the switch transistor Mk is electrically connected to the data line Di, the second end of the switch transistor Mk is electrically connected to the pixel electrode Pix, and the gate of the switch transistor Mk is connected to the scan control signal line Sc, wherein the switch transistor Mk is an N-type transistor. When the display panel displays a picture, when scanning the pixel unit Pi, the scan control signal line Sc transmits a scan control signal to the gate of the switch transistor Mk to control the switch transistor Mk to turn on, electrically connect the pixel electrode Pix to the data line Di, and receive the data voltage transmitted by the data line Di. And, in the first discharge stage T1, the switch transistor Mk is controlled to turn on by the high level voltage transmitted by the scan control signal line Sc, and the pixel electrode Pix is ​​connected to the data line Di; at this time, the multiplexer Demux controls the data line Di to be connected to the data transmission signal line Dix, so that the pixel electrode Pix can release the charge through the data line Di and the data transmission signal line Dix. Furthermore, in the first discharge stage T1 , the common electrode of the liquid crystal display panel is no longer applied with a common voltage, but the charge is released by being grounded.

[0047] Alternatively, the display panel provided in the embodiment of the present application may be a self-luminous display panel, and the first discharge stage T1 may be a charge release stage of the pixel circuit XS. Figure 8 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present application, wherein the display panel provided by the embodiment of the present application can also be a self-luminous display panel, the pixel unit Pi includes a pixel circuit XS and a light-emitting diode DL electrically connected to the pixel circuit XS (wherein the light-emitting diode DL can be OLED, microLED or miniLED, which is not limited), and the transistor electrically connected to the scan control signal line Sc in the pixel circuit XS is an N-type transistor. When the display panel displays a picture, when scanning the pixel unit Pi, the scan control signal line Sc transmits a scan control signal to the pixel circuit XS, controls the pixel circuit XS to receive the data voltage transmitted by the data line Di, and drives the light-up state of the light-emitting diode DL when the pixel circuit XS is working. And, in the first discharge stage T1, the pixel circuit XS is controlled to work by the high-level voltage transmitted by the scan control signal line Sc, and the pixel circuit XS is connected to the data line Di; at this time, the multiplexer Demux controls the data line Di to be connected to the data transmission signal line Dix, so that the pixel circuit XS can release the charge through the data line Di and the data transmission signal line Dix. Furthermore, in the first discharge stage T1 , the cathode of the light emitting diode DL of the self-luminous display panel is no longer applied with a corresponding voltage, but the charge is released by being grounded.

[0048] Continue to combine Figure 6 As shown, the set duration provided in the embodiment of the present application includes a second discharge stage T2 after the first discharge stage T1, wherein in the second discharge stage T2, the voltage applied to the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL gradually changes from the high level voltage to the ground voltage; and, in the second discharge stage T2, the voltage applied to the reset control signal line Reset gradually changes from the high level voltage to an intermediate transition voltage, and the intermediate transition voltage is greater than the ground voltage and less than the high level voltage. At this time, in the second discharge stage T2, the voltage applied to the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL gradually changes from the high level voltage to the ground voltage, which can not only fully release the charge on the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL, but also fully release the feed-through charge of the transistor controlled by these lines, thereby improving the performance of the display panel. In addition, since the voltage of the scan control signal line Sc gradually changes from the high level voltage to the ground voltage, the charge of the scan control signal line Sc is released, and the feed-through charge of the transistor controlled by the scan control signal line Sc is also fully released, thereby improving the performance of the display panel. In addition, applying a gradual voltage to the signal line can also improve the coupling problem between overlapping signal lines, thereby avoiding causing other signal lines whose charges have been released to generate charges again.

[0049] Furthermore, the set duration provided in the embodiment of the present application includes a third discharge stage T3 after the second discharge stage T2, wherein the voltage applied to the reset control signal line Reset in the third discharge stage T3 gradually changes from the intermediate transition voltage to the ground voltage, completing the complete power-off of the scan drive circuit GOA. At this time, in the third discharge stage T3, the charge of the reset control signal line Reset is fully released, and at the same time, the feed-through charge of the transistor controlled by the reset control signal line Reset is fully released. In addition, applying a gradual voltage to the reset control signal line Reset can also improve the coupling problem between overlapping signal lines, and avoid causing other signal lines that have already released their charges to generate charges again.

[0050] In some embodiments, before controlling the multiplexer Demux to connect the data line Di with the data transmission signal line Dix for a set time, an initial charge release operation for clearing the charges in the surface of the display panel may be performed. Fig. 9As shown, it is a flow chart of another control method of a display panel provided by an embodiment of the present application, wherein, when the display panel is turned off and before step S1, that is, before the set time, the control method includes: S01, controlling the scan drive circuit GOA to output a scan control signal to the scan control signal line Sc, applying the high level voltage to the selection control signal line Sx, and applying a black screen data voltage to the data transmission signal line Dix. That is to say, when the display panel is turned off and before the set time, the scan drive circuit GOA is controlled to work normally and output a scan control signal to scan the pixel unit Pi normally; and at this time, the multi-way output selector Demux connects all data lines Di with the corresponding data transmission lines Dix, and the data transmission line Dix transmits a black screen data voltage close to 0V to the pixel unit Pi to control the display panel to display a black screen, completing the initial charge release of the in-plane charge situation, and this stage can be defined as the black insertion stage T0.

[0051] From the above, it can be seen that the control method of the display panel provided in the embodiment of the present application may include a black insertion stage T0, a setting time stage (including the first discharge stage T1, the second discharge stage T2 and the third discharge stage T3) in sequence when the display panel is turned off, and an end stage T4 corresponding to step S2. Fig.10 FIG. 1 is a shutdown timing diagram of a display panel provided in an embodiment of the present application. When the display panel is shut down:

[0052] First, the black insertion stage T0 is performed, at which the scan drive circuit GOA works normally to scan the pixel unit Pi in the display panel; wherein the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2, the level signal line VGL and the reset control signal line Reset work normally, so that the scan control signal line Sc transmits the scan control signal normally; and at this time, the multiplexer Demux controls the connection between all data lines Di and the corresponding data transmission signal line Dix, and the data transmission signal line Dix transmits the black screen data voltage, so that the display panel displays a black screen, completing the operation of clearing the initial charge in the surface. The black insertion stage T0 can last for 1 frame or 2 frames.

[0053] Then it enters the set time, in which, in the first discharge stage T1, the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2, the level signal line VGL and the reset control signal line Reset are all applied with a high level voltage, so that the scanning control signal line Sc transmits a high level voltage. The pixel unit Pi is scanned and turned on, and the charge is released through the data line Di and the data transmission signal line Dix; and the common electrode or the cathode of the light emitting diode DL is no longer applied with a corresponding voltage, but is grounded to release the charge.

[0054] In the second discharge stage T2, the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL are all applied with a voltage that gradually changes from a high level voltage to a ground voltage, and the voltage of the reset control signal line Reset is a high level voltage that gradually changes to an intermediate transition voltage. At this time, the charges on the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2, the level signal line VGL and the scan control signal line Sc are fully released, and the transistors controlled by the above lines also release the feed-through charges. However, the charge on the reset control signal line Reset is not completely released.

[0055] In the third discharge stage T3, the voltage of the reset control signal line Reset gradually changes from the intermediate transition voltage to the ground voltage, and the charge of the reset control signal line Reset and the transistor controlled by it is fully released, completing the power-off process of the scan drive circuit GOA.

[0056] Finally, the end stage T4 is entered, at which the gate control signal line Sx is applied with a voltage that gradually changes from a high level voltage to a ground voltage, which not only enables the gate control signal line Sx and the transistor controlled by it to fully release the charge; but also prolongs the charge release time of the data line Di, further improving the performance of the display panel. In addition, applying a gradual voltage to the signal line can improve the coupling problem between overlapping signal lines, and avoid causing other signal lines whose charges have been released to generate charges again.

[0057] Based on the same inventive concept and in combination with the control method of the display panel provided in any of the above embodiments, the embodiment of the present application further provides a display panel. Fig.11As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present application, wherein the display panel provided by the embodiment of the present application includes: a plurality of pixel units Pi; a plurality of data lines Di, the data lines Di are electrically connected to the pixel units Pi; a plurality of multi-way output selectors Demux, the plurality of output ends of the multi-way output selector Demux are electrically connected to one of the data lines Di respectively; and a controller 100, the controller 100 is electrically connected to the control end of the multi-way output selector Demux through a selection control signal line Sx, and the controller 100 is electrically connected to the input end of the multi-way output selector Demux through a data transmission signal line Dix; the controller 100 is used to output a high-level voltage to the selection control signal line Sx when the display panel is turned off, so as to control the multi-way output selector Demux to connect the data line Di with the data transmission signal line Dix for a set time, and then output a ground voltage to the selection control signal line Sx to control the multi-way output selector Demux to disconnect the data line Di from the data transmission signal line Dix.

[0058] The multiplexer output selector Demux provided in the embodiment of the present application may be composed of selection transistors, which is the same as described in the corresponding embodiment of the above control method, so no redundant description is made here. In addition, the controller 100 provided in the embodiment of the present application may be an independent device, or may be integrated into the driver IC of the display panel, and this application does not make any specific restrictions on this.

[0059] In some embodiments, when the display panel is turned off, and within a set time period when the controller 100 controls the multi-way output selector Demux to connect the data line Di with the data transmission signal line Dix, an optimized voltage can be applied to the data transmission signal line Dix to improve the efficiency of releasing the charge of the data line Di. Specifically, within the set time period, the controller 100 provided in the embodiment of the present application outputs a black screen data voltage to the data transmission signal line Dix, wherein the black screen data voltage is close to 0V, which ensures that the charge on the data line Di is released through the data transmission signal line Dix, and can also improve the efficiency of charge release on the data line Di.

[0060] Furthermore, after the set time, the voltage outputted by the controller 100 provided in the embodiment of the present application to the gate control signal line Sx gradually changes from the high level voltage to the ground voltage, and the residual charge on the gate control signal line Sx can be fully released, further improving the performance of the display panel. In addition, during the process in which the voltage on the gate control signal line Sx gradually decreases to the ground voltage, the gate transistor remains turned on, so that the charge on the data line Di can still be released through the data transmission signal line Dix, which is equivalent to extending the time for the data line Di to release the charge, and further improving the effect of the data line Di releasing the charge.

[0061] When the display panel is turned off, and within the set time period when the multiplexer output selector Demux is controlled to connect the data line Di with the data transmission signal line Dix, not only can the charge of the data line Di be released, but also the residual charge of the remaining lines of the display panel can be released. For example, in some embodiments, when the multiplexer output selector Demux is controlled to connect the data line Di with the data transmission signal line Dix for a set time period, while controlling the data line Di to release the charge through the data transmission signal line Dix, the scan drive circuit GOA can also be controlled to release the charge. Fig.12 As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, wherein the display panel provided in the embodiment of the present application includes: a plurality of scan control signal lines Sc, the scan control signal lines Sc are electrically connected to the pixel units Pi; a scan drive circuit GOA, the output end of the scan drive circuit GOA is electrically connected to the scan control signal line Sc; the controller 100 is electrically connected to the scan drive circuit GOA, and the controller 100 is used to control the scan drive circuit GOA to power off within the set time length.

[0062] Continue to refer Fig.12As shown, the controller 100 provided in the embodiment of the present application is electrically connected to the start end of the scan drive circuit GOA through the start control signal line STV, the controller 100 is electrically connected to the clock end of the scan drive circuit GOA through the clock control signal line CK (the clock control signal line includes clock control signal lines CKA and CKB, wherein the phases of CKA and CKB are opposite), the controller 100 is electrically connected to the reset end of the scan drive circuit GOA through the reset control signal line Reset, and the controller 100 is electrically connected to the high power end of the scan drive circuit GOA through the high power input signal line DIR1. The controller 100 is electrically connected to the low power end of the scan drive circuit GOA through the low power input signal line DIR2, and the controller 100 is electrically connected to the level end of the scan drive circuit GOA through the level signal line VGL; wherein the set duration includes a first discharge stage T1, wherein the controller 100 is used to output the high level voltage to the start control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL in the first discharge stage T1. In the first discharge stage T1, the start control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL are all applied with a high level voltage, so that the connected transistors are controlled to be turned on, and at the same time, the scanning drive circuit GOA outputs a scanning control signal to the scanning control signal line Sc to scan and turn on the pixel unit Pi, thereby controlling part of the structure in the pixel unit Pi to release charge through the data line Di and the data transmission signal line Dix.

[0063] The set duration provided in the embodiment of the present application includes a second discharge stage T2 after the first discharge stage T1, wherein the controller 100 is used to output a voltage to the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL in the second discharge stage T2, gradually changing from the high level voltage to the ground voltage; and the controller 100 is used to output a voltage to the reset control signal line Reset in the second discharge stage T2, gradually changing from the high level voltage to the intermediate transition voltage. At this time, in the second discharge stage T2, the voltage applied to the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL gradually changes from the high level voltage to the ground voltage, which can not only fully release the charge on the start control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL, but also fully release the feed-through charge of the transistor controlled by these lines, thereby improving the performance of the display panel. In addition, since the voltage of the scan control signal line Sc gradually changes from the high level voltage to the ground voltage, the charge of the scan control signal line Sc is released, and the feed-through charge of the transistor controlled by the scan control signal line Sc is also fully released, thereby improving the performance of the display panel. In addition, applying a gradual voltage to the signal line can also improve the coupling problem between overlapping signal lines, thereby avoiding causing other signal lines whose charges have been released to generate charges again.

[0064] And, the set duration provided in the embodiment of the present application includes a third discharge stage T3 after the second discharge stage T2, wherein the controller 100 is used to output a voltage to the reset control signal line Reset in the third discharge stage T3 gradually from the intermediate transition voltage to the ground voltage, completing the complete power-off of the scan drive circuit GOA. At this time, in the third discharge stage T3, the charge of the reset control signal line Reset is fully released, and at the same time, the feed-through charge of the transistor controlled by the reset control signal line Reset is fully released. And applying a gradual voltage to the reset control signal line Reset can also improve the coupling problem between overlapping signal lines, and avoid causing other signal lines whose charges have been released to generate charges again.

[0065] In some embodiments, before controlling the multiplexer Demux to connect the data line Di with the data transmission signal line Dix for a set time, an initial charge release operation of clearing the in-plane charge can be performed on the display panel. Specifically, when the display panel is turned off and before the set time, the controller 100 is used to control the scan drive circuit GOA to output a scan control signal to the scan control signal line Sc, output the high level voltage to the selection control signal line Sx, and output a black screen data voltage to the data transmission signal line Dix. That is to say, when the display panel is turned off and before the set time, the scan drive circuit GOA is controlled to work normally and output a scan control signal to scan the pixel unit Pi normally; at this time, the multiplexer Demux connects all the data lines Di with the corresponding data transmission lines Dix, and the data transmission line Dix transmits a black screen data voltage close to 0V to the pixel unit Pi to control the display panel to display a black screen, completing the initial charge release of the in-plane charge situation.

[0066] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes the display panel provided by any one of the above embodiments.

[0067] refer to Fig.13 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, wherein the electronic device 1000 provided in an embodiment of the present application may be a display device for a vehicle. In some other embodiments of the present application, the electronic device 1000 provided in an embodiment of the present application may also be a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, etc., and the present invention does not make any specific limitation on this.

[0068] The embodiment of the present application provides a display panel, a control method thereof and an electronic device, wherein the display panel comprises: a plurality of pixel units; a plurality of data lines, wherein the data lines are electrically connected to the pixel units; a plurality of multi-way output selectors, wherein the plurality of output ends of the multi-way output selectors are electrically connected to one of the data lines respectively, the control end of the multi-way output selector is electrically connected to a selection control signal line, and the input end of the multi-way output selector is electrically connected to a data transmission signal line; wherein the control method comprises: when the display panel is turned off, applying a high-level voltage to the selection control signal line to control the multi-way output selector to connect the data line with the data transmission signal line for a set time, and then applying a ground voltage to the selection control signal line to control the multi-way output selector to disconnect the data line from the data transmission signal line.

[0069] As can be seen from the above content, the technical solution provided by the embodiment of the present application controls the multiplexer to connect the data line with the data transmission signal line for a set time and then disconnect it when the display panel is turned off, and during the set time when the data line is connected to the data transmission signal line, the charge on the data line can be fully released through the data transmission line. Therefore, when the display panel is turned off, by controlling the closing time of the delayed multiplexer, the purpose of controlling the charge on the data line to be fully released is achieved, thereby improving the performance of the display panel.

[0070] In the description of the embodiments of the present application, it needs to be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0071] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0072] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0073] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0074] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0075] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for controlling a display panel, characterized in that: The display panel comprises: a plurality of pixel units; a plurality of data lines, the data lines being electrically connected to the pixel units; a plurality of multiplexer selectors, the multiple output ends of the multiplexer selectors being electrically connected to one of the data lines respectively, the control end of the multiplexer selectors being electrically connected to a selection control signal line, and the input end of the multiplexer selectors being electrically connected to a data transmission signal line; wherein the control method comprises: When the display panel is turned off, a high-level voltage is applied to the enable control signal line to control the multi-way output selector to connect the data line with the data transmission signal line for a set period of time, and then a ground voltage is applied to the enable control signal line to control the multi-way output selector to disconnect the data line from the data transmission signal line.

2. The control method of the display panel according to claim 1, characterized in that: The control method comprises: During the set time period, a black screen data voltage is applied to the data transmission signal line.

3. The control method of the display panel according to claim 1, characterized in that: The applying a ground voltage to the gate control signal line comprises: After the set time period, the voltage applied to the gate control signal line gradually changes from the high level voltage to the ground voltage.

4. The control method of the display panel according to claim 1, characterized in that: The display panel comprises: a plurality of scanning control signal lines, the scanning control signal lines are electrically connected to the pixel units; a scanning driving circuit, the output end of the scanning driving circuit is electrically connected to the scanning control signal lines; wherein the control method comprises: The scan driving circuit is controlled to be powered off within the set time period.

5. The control method of the display panel according to claim 4, characterized in that: When the display panel is turned off and before the set time period, the control method includes: The scan driving circuit is controlled to output a scan control signal to the scan control signal line, apply the high level voltage to the gate control signal line, and apply a black screen data voltage to the data transmission signal line.

6. The control method of the display panel according to claim 4, characterized in that: The start end of the scan driving circuit is electrically connected to the start control signal line, the clock end of the scan driving circuit is electrically connected to the clock control signal line, the reset end of the scan driving circuit is electrically connected to the reset control signal line, the high power end of the scan driving circuit is electrically connected to the high power input signal line, the low power end of the scan driving circuit is electrically connected to the low power input signal line, and the level end of the scan driving circuit is electrically connected to the level signal line; The set duration includes a first discharge phase, wherein the high level voltage is applied to the start control signal line, the clock control signal line, the reset control signal line, the high power input signal line, the low power input signal line and the level signal line in the first discharge phase.

7. The control method of the display panel according to claim 6, characterized in that: The set duration includes a second discharge stage after the first discharge stage, wherein in the second discharge stage, the voltage applied to the start control signal line, the clock control signal line, the high power input signal line, the low power input signal line and the level signal line gradually changes from the high level voltage to the ground voltage; Furthermore, in the second discharge stage, the voltage applied to the reset control signal line gradually changes from the high level voltage to an intermediate transition voltage.

8. The control method of the display panel according to claim 7, characterized in that: The set time length includes a third discharge stage after the second discharge stage, wherein in the third discharge stage, the voltage applied to the reset control signal line gradually changes from the intermediate transition voltage to the ground voltage.

9. A display panel, characterized in that: include: A plurality of pixel units; A plurality of data lines, wherein the data lines are electrically connected to the pixel units; Multiple output terminals of multiple output selectors are electrically connected to one of the data lines respectively; A controller, wherein the controller is electrically connected to the control end of the multi-way output selector through a selection control signal line, and the controller is electrically connected to the input end of the multi-way output selector through a data transmission signal line; the controller is used to output a high-level voltage to the selection control signal line when the display panel is turned off, so as to control the multi-way output selector to connect the data line with the data transmission signal line for a set time, and then output a ground voltage to the selection control signal line to control the multi-way output selector to disconnect the data line from the data transmission signal line.

10. The display panel according to claim 9, characterized in that: Within the set time period, the controller outputs a black screen data voltage to the data transmission signal line.

11. The display panel according to claim 9, characterized in that: After the set time period, the voltage output by the controller to the selection control signal line gradually changes from the high level voltage to the ground voltage.

12. The display panel according to claim 9, characterized in that: The display panel comprises: A plurality of scanning control signal lines, wherein the scanning control signal lines are electrically connected to the pixel units; A scan driving circuit, wherein an output terminal of the scan driving circuit is electrically connected to the scan control signal line; The controller is electrically connected to the scan driving circuit, and is used for controlling the scan driving circuit to power off within the set time period.

13. The display panel according to claim 12, characterized in that: When the display panel is turned off and before the set time, the controller is used to control the scan drive circuit to output a scan control signal to the scan control signal line, output the high level voltage to the selection control signal line, and output a black screen data voltage to the data transmission signal line.

14. The display panel according to claim 12, characterized in that: The controller is electrically connected to the start end of the scan driving circuit through the start control signal line, the controller is electrically connected to the clock end of the scan driving circuit through the clock control signal line, the controller is electrically connected to the reset end of the scan driving circuit through the reset control signal line, the controller is electrically connected to the high power end of the scan driving circuit through the high power input signal line, the controller is electrically connected to the low power end of the scan driving circuit through the low power input signal line, and the controller is electrically connected to the level end of the scan driving circuit through the level signal line; The set duration includes a first discharge stage, wherein the controller is used to output the high-level voltage to the start control signal line, the clock control signal line, the reset control signal line, the high power input signal line, the low power input signal line and the level signal line in the first discharge stage.

15. The display panel according to claim 14, characterized in that: The set duration includes a second discharge stage after the first discharge stage, wherein the controller is used to gradually change the voltage output to the start control signal line, the clock control signal line, the high power input signal line, the low power input signal line and the level signal line from the high level voltage to the ground voltage in the second discharge stage; Furthermore, the controller is used to gradually change the voltage output to the reset control signal line from the high level voltage to an intermediate transition voltage during the second discharge phase.

16. The display panel according to claim 15, characterized in that: The set time length includes a third discharge stage after the second discharge stage, wherein the controller is used to gradually change the voltage output to the reset control signal line from the intermediate transition voltage to the ground voltage during the third discharge stage.

17. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 9 to 16.

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