Display panel, control method thereof and electronic device

Abstract

The application provides a display panel, a control method thereof and an electronic device, and relates to the technical field of display control. When the display panel is powered off, a multiplexed output selector is controlled to be connected with a data line and a data transmission signal line for a set time length, and then disconnected. Within the set time length, the electric charge on the data line can be fully discharged through the data transmission line. Thus, when the display panel is powered off, the closing time of the multiplexed output selector is controlled, so that the electric charge on the data line is fully discharged, and the performance of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display control, more particularly, to a display panel, a control method thereof and an electronic device. BACKGROUND

[0002] With the development of science and technology, more and more electronic devices with display function are widely used in people's daily life and work, which brings great convenience to people's daily life and work and becomes an important tool indispensable to people at present. The main component of the electronic device to realize the display function is a display panel. The existing display panel cannot fully discharge the charge in the data line when it is powered off, which affects the performance of the display panel. SUMMARY

[0003] Therefore, the present application provides a display panel, a control method thereof and an electronic device, which effectively solve the technical problems in the prior art. When the display panel is powered off, the data line of the multi-output selector is connected to the data transmission signal line for a set time length, and then disconnected by controlling the closing time of the delay multi-output selector, so as to fully discharge the charge on the data line and improve the performance of the display panel.

[0004] To achieve the above-mentioned purpose, the technical scheme provided by the present application is as follows:

[0005] A control method of a display panel, the display panel comprising: a plurality of pixel units; a plurality of data lines, the data lines being electrically connected with the pixel units; a plurality of multi-output selectors, a plurality of output ends of the multi-output selectors being respectively electrically connected with one of the data lines, a control end of the multi-output selector being electrically connected with a gate control signal line, and an input end of the multi-output selector being electrically connected with a data transmission signal line; wherein the control method comprises:

[0006] When the display panel is powered off, a high-level voltage is applied to the gate control signal line to control the multi-output selector to connect the data line and the data transmission signal line for a set time length, and then a ground voltage is applied to the gate control signal line to control the multi-output selector to disconnect the data line and the data transmission signal line.

[0007] Based on the same inventive concept, the present application also provides a display panel, comprising:

[0008] a plurality of pixel units;

[0009] a plurality of data lines, the data lines being electrically connected with the pixel units;

[0010] a plurality of multiplexing selectors, a plurality of outputs of the multiplexing selectors are respectively electrically connected with one of the data lines;

[0011] a controller, a control terminal of the multiplexing selector is electrically connected with the gate control signal line, and an input terminal of the multiplexing selector is electrically connected with the data transmission signal line; the controller is configured to output a high voltage to the gate control signal line to control the multiplexing selector to connect the data line and the data transmission signal line for a set time length, and then output a ground voltage to the gate control signal line to control the multiplexing selector to disconnect the data line and the data transmission signal line when the display panel is powered off.

[0012] Based on the same inventive concept, the application further provides an electronic device comprising the display panel.

[0013] Compared with the prior art, the technical solution provided by the application has at least the following advantages:

[0014] The application provides a display panel, a control method thereof and an electronic device. The display panel comprises a plurality of pixel units, a plurality of data lines electrically connected with the pixel units, and a plurality of multiplexing selectors, a plurality of outputs of the multiplexing selectors are respectively electrically connected with one of the data lines, a control terminal of the multiplexing selector is electrically connected with the gate control signal line, and an input terminal of the multiplexing selector is electrically connected with the data transmission signal line. The control method comprises the following steps: when the display panel is powered off, a high voltage is applied to the gate control signal line to control the multiplexing selector to connect the data line and the data transmission signal line for a set time length, and then a ground voltage is applied to the gate control signal line to control the multiplexing selector to disconnect the data line and the data transmission signal line.

[0015] As can be seen from the above, the technical solution provided by the application controls the multiplexing selector to connect the data line and the data transmission signal line for a set time length and then disconnect them when the display panel is powered off, and the electric charge on the data line can be fully discharged through the data transmission line within the set time length when the data line and the data transmission signal line are connected. Therefore, when the display panel is powered off, the closing time of the multiplexing selector is controlled to achieve the purpose of controlling the electric charge on the data line to be fully discharged, thereby improving the performance of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only need to explain the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained on the basis of the provided drawings without creative labor.

[0017] Figure 1 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in the figure.

[0018] Figure 2 A flow chart of a control method of a display panel provided by an embodiment of the present application is shown in the figure.

[0019] Figure 3 A flow chart of another control method of a display panel provided by an embodiment of the present application is shown in the figure.

[0020] Figure 4 A structural schematic diagram of another display panel provided by an embodiment of the present application is shown in the figure.

[0021] Figure 5 A flow chart of another control method of a display panel provided by an embodiment of the present application is shown in the figure.

[0022] Figure 6 A structural schematic diagram of a shift register circuit provided by an embodiment of the present application is shown in the figure.

[0023] Figure 7 A structural schematic diagram of another display panel provided by an embodiment of the present application is shown in the figure.

[0024] Figure 8 A structural schematic diagram of another display panel provided by an embodiment of the present application is shown in the figure.

[0025] Figure 9 A flow chart of another control method of a display panel provided by an embodiment of the present application is shown in the figure.

[0026] Figure 10 A power-off timing diagram of a display panel provided by an embodiment of the present application is shown in the figure.

[0027] Figure 11 A structural schematic diagram of another display panel provided by an embodiment of the present application is shown in the figure.

[0028] Figure 12 A structural schematic diagram of another display panel provided by an embodiment of the present application is shown in the figure.

[0029] Figure 13 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0030] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described, obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0031] As described in the background, with the development of science and technology, more and more electronic devices with display function are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and becomes an important tool indispensable to people at present. The main component of the electronic device to realize the display function is the display panel. The existing display panel cannot fully release the charge in the data line when it is powered off, which affects the performance of the display panel.

[0032] Based on this, the embodiments of the present application provide a display panel and a control method thereof and an electronic device, which effectively solve the technical problems existing in the prior art. When the display panel is powered off, the data line of the multi-output selector is connected with the data transmission signal line for a set time length and then disconnected. By controlling the closing time of the delay multi-output selector, the purpose of fully releasing the charge on the data line is achieved, and the performance of the display panel is improved.

[0033] To achieve the above-mentioned purpose, the technical solutions provided by the embodiments of the present application are as follows, which are specifically combined with Figures 1 to 13 The technical solutions provided by the embodiments of the present application are described in detail.

[0034] Combined with Figure 1 and Figure 2 , Figure 1 A structure diagram of a display panel provided by the embodiments of the present application is shown, specifically a wiring diagram of part of the lines in the display panel, Figure 2A flow chart of a control method of a display panel is provided in the embodiments of the present application. The display panel provided in the embodiments of the present application comprises: a plurality of pixel units Pi; a plurality of data lines Di, the data line Di is electrically connected with the pixel unit Pi; a plurality of multiplexers Demux, a plurality of output terminals of the multiplexer Demux are respectively electrically connected with one of the data lines Di, a control terminal of the multiplexer Demux is electrically connected with a gate control signal line Sx, and an input terminal of the multiplexer Demux is electrically connected with a data transmission signal line Dix. In some embodiments, during the display process of the display panel, the multiplexer Demux only controls one data line Di to be in communication with the data transmission signal line Dix at the same time; that is, during the display process of the display panel, when the pixel unit Pi is scanned, the multiplexer Demux is controlled to select one of the data lines Di to be in communication with the data transmission signal line Dix according to the control timing, so as to transmit the data voltage to the data line Di through the data transmission signal line Dix, thereby providing the corresponding data voltage to the pixel unit Pi through the data line Di.

[0035] In some embodiments, the type of the transistor included in the multiplexer Demux provided in the embodiments of the present application is an N-type transistor, which can be a metal oxide thin film transistor. The metal oxide thin film transistor uses metal oxide as the channel layer material of the thin film transistor, and has the advantages of high electron mobility, which can improve the performance of the display panel. Optionally, the selection transistor provided in the embodiments of the present application can be an IGZO (Indium Gallium Zinc Oxide) thin film transistor. The number of the selection transistors included in the multiplexer Demux is limited by the number of the output terminals of the multiplexer Demux, for example, when the multiplexer Demux is a two-way output selector, or a three-way output selector, or a selector with more output terminals, it corresponds to two selection transistors, or three selection transistors, or a larger number of selection transistors, respectively. The present application does not make specific limitations on this, and the specific selection needs to be made according to the actual application.

[0036] Continue as Figure 1As shown, the embodiment of the present application takes a two-way output selector Demux as an example for description, the multi-way output selector Demux includes a first selection transistor Mux1 and a second selection transistor Mux2, both of which are N-type transistors. In order to be able to independently control the first selection transistor Mux1 and the second selection transistor Mux2, the gate-on control signal line Sx includes a first sub-gate-on control signal line Sx1 and a second sub-gate-on control signal line Sx2, the first sub-gate-on control signal line Sx1 is electrically connected with the gate of the first selection transistor Mux1, and the second sub-gate-on control signal line Sx2 is electrically connected with the gate of the second selection transistor Mux2. In addition, the first end of the first selection transistor Mux1 and the second selection transistor Mux2 is electrically connected as the input end of the multi-way output selector Demux, and is electrically connected with the data transmission signal line Dix, the second end of the first selection transistor Mux1 is electrically connected with the first data line Di1, and the second end of the second selection transistor Mux2 is electrically connected with the second data line Di2. In the display process of the display panel, when the pixel unit Pi electrically connected with the first data line Di1 is scanned, a high-level voltage is applied to the first sub-gate-on control signal line Sx1 according to the control timing, so as to control the first selection transistor Mux1 to be turned on, so as to connect the first data line Di1 with the data transmission signal line Dix, and the data transmission signal line Dix applies the corresponding data voltage to the corresponding pixel unit Pi through the first data line Di1; and at the same time, a low-level voltage is applied to the second sub-gate-on control signal line Sx2, so as to control the second selection transistor Mux2 to be turned off.

[0037] It should be noted that the multi-way output selector Demux and the electrical connection relationship between the multi-way output selector Demux and the pixel unit Pi provided by the embodiment of the present application are not limited to Figure 1 the connection mode shown. Figure 1 The electrical connection mode between the multi-way output selector Demux and the pixel unit Pi shown is only one of all the connection modes applicable to the present application, and the specific design needs to be made according to the actual application.

[0038] According to the display panel and the control method thereof, when the display panel is powered off, a high voltage is applied to the gate control signal line Sx for a set time period, so as to control all the gate transistors in the multiplexing selector Demux to be turned on for the set time period, thereby controlling the multiplexing selector Demux to connect all the data lines Di and the data transmission signal line Dix for the set time period; then, a ground voltage is applied to the gate control signal line Sx, so as to control all the gate transistors in the multiplexing selector Demux to be turned off, thereby controlling the multiplexing selector Demux to disconnect the data lines Di and the data transmission signal line Dix.

[0039] According to the display panel and the control method thereof, when the display panel is powered off, a high voltage is applied to the gate control signal line Sx for a set time period, so as to control all the gate transistors in the multiplexing selector Demux to be turned on for the set time period, thereby controlling the multiplexing selector Demux to connect all the data lines Di and the data transmission signal line Dix for the set time period; then, a ground voltage is applied to the gate control signal line Sx, so as to control all the gate transistors in the multiplexing selector Demux to be turned off, thereby controlling the multiplexing selector Demux to disconnect the data lines Di and the data transmission signal line Dix.

[0040] Further, the technical solution provided by the embodiment of the present application can fully release the residual charges on the gate-on control signal line Sx when the multiplexing output selector Demux is controlled to disconnect the data line Di and the data transmission signal line Dix, and further improve the performance of the display panel. Further, the voltage applied to the gate-on control signal line Sx can be slowly reduced from the high-level voltage to the ground voltage; that is, the application of the ground voltage to the gate-on control signal line Sx provided by the embodiment of the present application includes that, after the set time length, the voltage applied to the gate-on control signal line Sx is gradually changed from the high-level voltage to the ground voltage. For details, refer to Figure 3 As shown in FIG. 10, it is a flow chart of another control method of a display panel provided by the embodiment of the present application, wherein in step S2, the voltage applied to the gate-on control signal line Sx is gradually changed from the high-level voltage to the ground voltage to control the multiplexing output selector Demux to disconnect the data line Di and the data transmission signal line Dix, so that the charges on the data line Di and the gate-on control signal line Sx can be fully released, and the feed-through charges when the gate-on transistor is turned off can also be fully released. Further, during the process that the voltage on the gate-on control signal line Sx is gradually reduced to the ground voltage, the gate-on transistor still remains turned on, and the charges on the data line Di can still be released through the data transmission signal line Dix, which is equivalent to extending the time for releasing the charges on the data line Di, and further improves the effect of releasing the charges on the data line Di.

[0041] It can be understood that the transistor itself has a parasitic capacitor, and due to the coupling effect of the parasitic capacitor, when the control signal obtained by the gate of the transistor is changed from on to off, the transistor becomes off, but the parasitic capacitor still retains a certain amount of voltage change, which is the feed-through voltage. Therefore, the voltage applied to the gate-on control signal line Sx by the embodiment of the present application is slowly reduced from the high-level voltage to the ground voltage, which can fully discharge the feed-through charges retained by the parasitic capacitor of the gate-on transistor during the off process, and further improves the performance of the display panel. Further, the application of the gradually changed voltage to the signal line can also improve the coupling problem between the intersecting and overlapping signal lines, and avoid the generation of charges in the signal line which has been fully released.

[0042] In the process of turning off the display panel, and within the time length of setting the communication between the data line Di and the data transmission signal line Dix controlled by the multiplexing selector Demux, not only the data line Di can be discharged, but also the residual charge of the remaining lines of the display panel can be discharged. In some embodiments, within the time length of setting the communication between the data line Di and the data transmission signal line Dix controlled by the multiplexing selector Demux, the scanning driving circuit GOA can be controlled to discharge the charge while the data line Di is controlled to discharge the charge through the data transmission signal line Dix. In combination with Figure 4 and Figure 5 as shown, Figure 4 another structure diagram of the display panel provided by the embodiments of the present application, Figure 5 a flow chart of another control method provided by the embodiments of the present application. The display panel provided by the embodiments of the present application comprises a plurality of scanning control signal lines Sc, the scanning control signal lines Sc are electrically connected with the pixel units Pi; a scanning driving circuit GOA, the output end of the scanning driving circuit GOA is electrically connected with the scanning control signal lines Sc. In the process of display of the display panel, the scanning driving circuit GOA outputs the scanning control signal into the scanning control signal lines Sc, the scanning control signal lines Sc transmit the scanning control signal to the pixel units Pi for scanning opening control, so that the data line Di can transmit the data voltage into the pixel units Pi. As Figure 5 in step S1, the control method provided by the embodiments of the present application comprises: controlling the scanning driving circuit GOA to be powered off within the time length, so as to discharge the line charge in the scanning driving circuit GOA while realizing the charge discharge of the data line Di, further improving the performance of the display panel.

[0043] Reference Figure 6As shown in the structure diagram of the shift register circuit provided by the embodiment of the present application, the scan driving circuit GOA includes a plurality of shift register circuits connected in cascade, and the shift register circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a first capacitor C1 and a second capacitor C2, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are all N-type transistors. The gate of the first transistor M1 is an opening end (in the plurality of shift register circuits connected in cascade, the gate of the first transistor M1 of the first shift register circuit is electrically connected with an opening control signal line STV, and the opening scan control signal line STV is used for transmitting an opening scan control signal), the first end of the first transistor M1 is electrically connected with a high power input signal line DIR1, the high power input signal line DIR1 is used for transmitting a high power voltage, and the second end of the first transistor M1 is electrically connected with the second end of the second transistor M2, the second end of the third transistor M3, the second end of the fourth transistor M4, the gate of the sixth transistor M6, the first plate of the second capacitor C2 and the gate of the seventh transistor M7. The gate of the second transistor M2 is a closing end (in the plurality of shift register circuits connected in cascade, the gate of the second transistor M2 of the previous shift register circuit is electrically connected with the output end OUT' of the next shift register circuit), the first end of the second transistor M2 is electrically connected with a low power input signal line DIR2, and the low power input signal line DIR2 is used for transmitting a low power voltage. The gate of the third transistor M3 is electrically connected with the second plate of the first capacitor C1, the second end of the sixth transistor M6 and the gate of the eighth transistor M8, the first end of the third transistor M3 is electrically connected with a low level signal line VGL, and the low level signal line VGL is used for transmitting a low level voltage. The gate of the fourth transistor M4 and the gate of the fifth transistor M5 are both electrically connected with a reset control signal line Reset, the reset control signal line Reset is used for transmitting a reset control signal, the first end of the fourth transistor M4 and the first end of the fifth transistor M5 are both electrically connected with the low level signal line VGL, the second end of the fifth transistor M5, the second plate of the second capacitor C2, the second end of the seventh transistor M7, the second end of the eighth transistor M8 and the second end of the ninth transistor M9 are all electrically connected as the output end OUT of the shift register circuit. The first end of the sixth transistor M6 is electrically connected with the low level signal line VGL. The first end of the seventh transistor M7 and the first plate of the first capacitor C1 are both electrically connected with a clock control signal line CKB.The first end of the eighth transistor M8 and the first end of the ninth transistor M9 are electrically connected with a low-level signal line VGL, the gate of the ninth transistor M9 is electrically connected with a clock control signal line CKA, and the clock control signal line CKA and a clock control signal line CKB transmit clock signals of opposite phases.

[0044] It should be noted that, Figure 6 The shift register circuit of the GOA shown is the same as the existing circuit, and the present application is not an improvement on the composition and connection relationship of the shift register circuit, so the present application will not be described in detail. In addition, the GOA provided by the embodiments of the present application is not limited to including Figure 6 The shift register circuit shown is one of all the GOAs applicable to the present application. In some other embodiments of the present application, the GOA can also include other components and connected shift register circuits, or the GOA is composed of other types of circuits, which are not specifically limited by the present application.

[0045] In combination with Figure 6As shown, the power-off process of the scan driving circuit GOA provided in the embodiments of the present application can first release the charges of the pixel units Pi through the cooperation of the scan driving circuit GOA and the data lines Di; then release the charges of the on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line (the level signal line includes the low level signal line VGL) in the scan driving circuit GOA, and release the charges of the reset control signal line Reset incompletely, so as to make the scan driving circuit GOA output power-off; finally, release the charges of the reset control signal line Reset completely, and complete the complete power-off of the scan driving circuit GOA. Specifically, the on end of the scan driving circuit GOA is electrically connected with the on control signal line STV, the clock end of the scan driving circuit GOA is electrically connected with the clock control signal line CK, the reset end of the scan driving circuit GOA is electrically connected with the reset control signal line Reset, the high power end of the scan driving circuit GOA is electrically connected with the high power input signal line DIR1, the low power end of the scan driving circuit GOA is electrically connected with the low power input signal line DIR2, and the level end of the scan driving circuit GOA is electrically connected with the level signal line (all marked as the low level signal line VGL below). The set time length includes a first discharge phase T1, in which the high level voltage is applied to the on control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL. In the first discharge phase T1, the on control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL are all applied as the high level voltage, so as to make the connected transistors controlled to be turned on, and the scan driving circuit GOA outputs the scan control signal to the scan control signal line Sc to scan and open the pixel units Pi, so as to control part of the structures in the pixel units Pi to release the charges through the data lines Di and the data transmission signal lines Dix.

[0046] In an embodiment of the present application, the display panel provided in the embodiments of the present application can be a liquid crystal display panel, and the first discharge phase T1 can be a charge release phase of the pixel electrode Pix. Referring to Figure 7FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application. The display panel provided by the embodiment of the present application may be a liquid crystal display panel. A pixel unit Pi includes a switching transistor Mk and a pixel electrode Pix electrically connected to the switching transistor Mk. A first terminal of the switching transistor Mk is electrically connected to a data line Di, a second terminal of the switching transistor Mk is electrically connected to the pixel electrode Pix, and a gate of the switching transistor Mk is connected to a scan control signal line Sc. The switching transistor Mk is an N-type transistor. When the display panel displays an image, when scanning the pixel unit Pi, the scan control signal line Sc transmits a scan control signal to the gate of the switching transistor Mk to control the switching transistor Mk to turn on, electrically connecting the pixel electrode Pix to the data line Di and receiving the data voltage transmitted by the data line Di. Furthermore, during a first discharge phase T1, the switching transistor Mk is controlled to turn on by the high voltage transmitted by the scan control signal line Sc, connecting the pixel electrode Pix to the data line Di. At this time, the demultiplexer Demux controls the data line Di to connect to the data transmission signal line Dix, so that the pixel electrode Pix can release charge through the data line Di and the data transmission signal line Dix. Furthermore, in the first discharge stage T1 , the common electrode of the liquid crystal display panel is no longer applied with a common voltage, but releases charges by being grounded.

[0047] Alternatively, the display panel provided in the embodiment of the present application may be a self-luminous display panel, and the first discharge stage T1 may be a charge release stage of the pixel circuit XS. Figure 8 FIG. 1 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application, wherein the display panel provided in an embodiment of the present application can also be a self-luminous display panel, wherein the pixel unit Pi includes a pixel circuit XS and a light-emitting diode DL electrically connected to the pixel circuit XS (wherein the light-emitting diode DL can be an OLED, microLED, or miniLED, without limitation), and the transistor electrically connected to the scan control signal line Sc in the pixel circuit XS is an N-type transistor. When the display panel displays an image, when scanning the pixel unit Pi, the scan control signal line Sc transmits a scan control signal to the pixel circuit XS, controlling the pixel circuit XS to receive the data voltage transmitted by the data line Di, thereby driving the light-emitting diode DL to the illuminated state when the pixel circuit XS is operating. Furthermore, in the first discharge phase T1, the pixel circuit XS is controlled to operate by the high-level voltage transmitted by the scan control signal line Sc, connecting the pixel circuit XS to the data line Di; at this time, the multiplexer Demux controls the data line Di to connect to the data transmission signal line Dix, so that the pixel circuit XS can release charge through the data line Di and the data transmission signal line Dix. Furthermore, in the first discharge stage T1 , the cathode of the light emitting diode DL of the self-luminous display panel is no longer applied with a corresponding voltage, but releases the charge by being grounded.

[0048] Continuing with the description Figure 6 As shown, the set time length provided by the embodiments of the present application includes a second discharging phase T2 after the first discharging phase T1, wherein the voltage applied to the turn-on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL gradually changes from the high level voltage to the ground voltage during the second discharging phase T2; and the voltage applied to the reset control signal line Reset gradually changes from the high level voltage to an intermediate transition voltage during the second discharging phase T2, the intermediate transition voltage is greater than the ground voltage and less than the high level voltage. At this time in the second discharging phase T2, the voltage applied to the turn-on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL gradually changes from the high level voltage to the ground voltage, which not only enables the charges on the turn-on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL to be fully discharged, but also enables the feedthrough charges of the transistors controlled by these lines to be fully discharged, thereby improving the performance of the display panel. Moreover, since the voltage of the scan control signal line Sc gradually changes from the high level voltage to the ground voltage, the charges of the scan control signal line Sc are discharged, and at the same time, the feedthrough charges of the transistors controlled by the scan control signal line Sc are fully discharged, thereby improving the performance of the display panel. Moreover, the gradually changing voltage applied to the signal lines also enables the coupling problem between the intersecting and overlapping signal lines to be improved, thereby avoiding the generation of charges in the other signal lines which have been fully discharged.

[0049] Furthermore, the set time length provided by the embodiments of the present application includes a third discharging phase T3 after the second discharging phase T2, wherein the voltage applied to the reset control signal line Reset gradually changes from the intermediate transition voltage to the ground voltage during the third discharging phase T3, thereby completing the full power down of the scan driving circuit GOA. At this time in the third discharging phase T3, the charges of the reset control signal line Reset are fully discharged, and at the same time, the feedthrough charges of the transistors controlled by the reset control signal line Reset are fully discharged. Moreover, the gradually changing voltage applied to the reset control signal line Reset also enables the coupling problem between the intersecting and overlapping signal lines to be improved, thereby avoiding the generation of charges in the other signal lines which have been fully discharged.

[0050] In some embodiments, before the set time length in which the control multi-way output selector Demux is used to connect the data line Di with the data transmission signal line Dix, an initial charge discharge operation of in-plane charge emptying can be performed on the display panel. For details, refer to Figure 9As shown, a flowchart of another display panel control method provided by the embodiments of the present application is shown. Before the display panel is powered off and before step S1, i.e. before the set time period, the control method comprises: S01, controlling the scan driving circuit GOA to output a scan control signal to the scan control signal line Sc, applying the high-level voltage to the gate control signal line Sx, and applying a black picture data voltage to the data transmission signal line Dix. That is, when the display panel is powered off and before the set time period, the scan driving circuit GOA is controlled to normally work to output a scan control signal to normally scan the pixel unit Pi; at this time, the multiplexing selector Demux connects all the data lines Di and the corresponding data transmission line Dix, and the data transmission line Dix transmits a black picture data voltage close to 0V to the pixel unit Pi to control the display panel to display a black picture, and initial charge release of the in-plane charge condition is completed, which can be defined as a black insertion stage T0.

[0051] As can be seen from the above, the display panel control method provided by the embodiments of the present application can comprise the black insertion stage T0, the set time period stage (comprising the first discharge stage T1, the second discharge stage T2 and the third discharge stage T3 in sequence), and the end stage T4 corresponding to step S2 in sequence when the display panel is powered off. Referring to Figure 10 As shown, a display panel power-off timing diagram provided by the embodiments of the present application is shown. When the display panel is powered off:

[0052] First, the black insertion stage T0 is performed, at this time the scan driving circuit GOA normally works to scan the pixel unit Pi in the display panel; wherein the control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2, the level signal line VGL and the reset control signal line Reset normally work, so that the scan control signal line Sc normally transmits the scan control signal; at this time the multiplexing selector Demux controls the connection between all the data lines Di and the corresponding data transmission signal line Dix, and the data transmission signal line Dix transmits the black picture data voltage, so that the display panel displays a black picture and completes the initial charge emptying operation in the plane. The black insertion stage T0 can last for 1 frame or 2 frames of pictures.

[0053] Then, a set time length is entered, in which, in the first discharging stage T1, the control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2, the level signal line VGL and the reset control signal line Reset are all applied with high voltage, so that the scanning control signal line Sc transmits high voltage. The pixel unit Pi is scanned to be turned on, and charges are discharged through the data line Di and the data transmission signal line Dix; and the common electrode or the cathode of the light emitting diode DL is no longer applied with corresponding voltage, but is grounded to discharge charges.

[0054] In the second discharging stage T2, the control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL are all applied with voltage gradually changing from high voltage to ground voltage, and the voltage of the reset control signal line Reset gradually changes from high voltage to intermediate transition voltage. At this time, the charges on the control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2, the level signal line VGL and the scanning control signal line Sc are fully discharged, and the transistors controlled by the above lines also feed through and discharge charges. The charges of the reset control signal line Reset are not fully discharged.

[0055] In the third discharging stage T3, the voltage of the reset control signal line Reset gradually changes from the intermediate transition voltage to ground voltage, and the charges of the reset control signal line Reset and the transistors controlled thereby are fully discharged, and the power-off process of the scanning driving circuit GOA is completed.

[0056] Finally, the end stage T4 is entered, in which the gate control signal line Sx is applied with voltage gradually changing from high voltage to ground voltage, so that not only the charges of the gate control signal line Sx and the transistors controlled thereby are fully discharged, but also the charge discharging time length of the data line Di is prolonged, and the performance of the display panel is further improved. In addition, the gradually changing voltage applied to the signal line can improve the coupling problem between the intersecting and overlapping signal lines, and avoid the generation of charges in the signal lines which have been fully discharged.

[0057] Based on the same inventive concept, and in combination with the control method of the display panel provided in any one of the above embodiments, the embodiments of the present application further provide a display panel. Reference Figure 11As shown, the structure of the display panel provided by the embodiment of the present application is shown, wherein the display panel provided by the embodiment of the present application comprises: a plurality of pixel units Pi; a plurality of data lines Di, the data line Di is electrically connected with the pixel unit Pi; a plurality of demultiplexers Demux, a plurality of outputs of the demultiplexer Demux are respectively electrically connected with a data line Di; and a controller 100, the controller 100 is electrically connected with the control end of the demultiplexer Demux through a gate control signal line Sx, and the controller 100 is electrically connected with the input end of the demultiplexer Demux through a data transmission signal line Dix; the controller 100 is used for outputting a high-level voltage to the gate control signal line Sx when the display panel is powered off, so as to control the demultiplexer Demux to connect the data line Di and the data transmission signal line Dix for a set time length, and then output a ground voltage to the gate control signal line Sx, so as to control the demultiplexer Demux to disconnect the data line Di and the data transmission signal line Dix.

[0058] The demultiplexer Demux provided by the embodiment of the present application can be composed of a selection transistor, which is the same as the description in the above-mentioned embodiment of the control method, and thus is not described here. In addition, the controller 100 provided by the embodiment of the present application can be an independent device, or can also be integrated in the driving IC of the display panel, and the present application does not make specific limitations.

[0059] In some embodiments, when the display panel is powered off, and within the set time length in which the controller 100 controls the demultiplexer Demux to connect the data line Di and the data transmission signal line Dix, an optimized voltage can be applied to the data transmission signal line Dix to improve the efficiency of the charge release of the data line Di. Specifically, within the set time length, the controller 100 provided by the embodiment of the present application outputs a black screen data voltage to the data transmission signal line Dix, wherein the black screen data voltage is close to 0V, which can ensure the charge on the data line Di to be released through the data transmission signal line Dix, and also can improve the efficiency of the charge release on the data line Di.

[0060] Furthermore, after the set duration, the voltage output by the controller 100 to the strobe control signal line Sx gradually changes from the high-level voltage to the ground voltage, thereby fully releasing any residual charge on the strobe control signal line Sx and further improving the performance of the display panel. Furthermore, while the voltage on the strobe control signal line Sx gradually decreases to the ground voltage, the strobe transistor remains on, allowing the charge on the data line Di to continue to be released via the data transmission signal line Dix. This effectively extends the time it takes for the data line Di to release charge, further improving the efficiency of the charge release process.

[0061] When the display panel is turned off, and within a set time period when the multiplexer Demux is controlled to connect the data line Di with the data transmission signal line Dix, not only can the charge on the data line Di be released, but also the residual charge on the other lines of the display panel can be released. For example, in some embodiments, while the multiplexer Demux is controlled to connect the data line Di with the data transmission signal line Dix for a set time period, while the data line Di is controlled to release the charge through the data transmission signal line Dix, the scan drive circuit GOA can also be controlled to release the charge. Figure 12 As shown in FIG, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, wherein the display panel provided in an embodiment of the present application includes: a plurality of scan control signal lines Sc, the scan control signal lines Sc are electrically connected to the pixel units Pi; a scan drive circuit GOA, the output end of the scan drive circuit GOA is electrically connected to the scan control signal line Sc; the controller 100 is electrically connected to the scan drive circuit GOA, and the controller 100 is used to control the scan drive circuit GOA to power off within the set time length.

[0062] Continue to refer Figure 12As shown, the controller 100 is electrically connected to the opening end of the scan driving circuit GOA through an opening control signal line STV, the controller 100 is electrically connected to the clock end of the scan driving circuit GOA through a clock control signal line CK (the clock control signal line includes clock control number lines CKA and CKB, wherein the phases of CKA and CKB are opposite), the controller 100 is electrically connected to the reset end of the scan driving circuit GOA through a reset control signal line Reset, the controller 100 is electrically connected to the high power end of the scan driving circuit GOA through a high power input signal line DIR1, the controller 100 is electrically connected to the low power end of the scan driving circuit GOA through a low power input signal line DIR2, and the controller 100 is electrically connected to the level end of the scan driving circuit GOA through a level signal line VGL; wherein the set time length includes a first discharge phase T1, and the controller 100 is configured to output the high-level voltage to the opening control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL in the first discharge phase T1. In the first discharge phase T1, the opening control signal line STV, the clock control signal line CK, the reset control signal line Reset, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL are all applied as high-level voltage, so that the connected transistors are controlled to be turned on, and at the same time the scan driving circuit GOA outputs a scan control signal to a scan control signal line Sc to scan and open the pixel unit Pi, so as to control part of the structure in the pixel unit Pi to release the charge through the data line Di and the data transmission signal line Dix.

[0063] The set time length provided by the embodiment of the present application includes a second discharge phase T2 after the first discharge phase T1, wherein the controller 100 is configured to gradually change the voltage output to the turn-on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL from the high level voltage to the ground voltage during the second discharge phase T2; and the controller 100 is configured to gradually change the voltage output to the reset control signal line Reset from the high level voltage to an intermediate transition voltage during the second discharge phase T2. At this time, during the second discharge phase T2, the voltage applied to the turn-on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL is gradually changed from the high level voltage to the ground voltage, which not only fully releases the charges on the turn-on control signal line STV, the clock control signal line CK, the high power input signal line DIR1, the low power input signal line DIR2 and the level signal line VGL, but also fully releases the feedthrough charges of the transistors controlled by these lines, thereby improving the performance of the display panel. Moreover, since the voltage of the scan control signal line Sc is gradually changed from the high level voltage to the ground voltage, the charges of the scan control signal line Sc are released, and at the same time, the feedthrough charges of the transistors controlled by the scan control signal line Sc are fully released, thereby improving the performance of the display panel. Moreover, the gradually changed voltage applied to the signal lines can also improve the coupling problem between the intersecting and overlapping signal lines, thereby avoiding the generation of charges in the other signal lines which have been fully released.

[0064] Furthermore, the set time length provided by the embodiment of the present application includes a third discharge phase T3 after the second discharge phase T2, wherein the controller 100 is configured to gradually change the voltage output to the reset control signal line Reset from the intermediate transition voltage to the ground voltage during the third discharge phase T3, thereby completing the complete power-off of the scan driving circuit GOA. At this time, during the third discharge phase T3, the charges of the reset control signal line Reset are fully released, and at the same time, the feedthrough charges of the transistors controlled by the reset control signal line Reset are fully released. Moreover, the gradually changed voltage applied to the reset control signal line Reset can also improve the coupling problem between the intersecting and overlapping signal lines, thereby avoiding the generation of charges in the other signal lines which have been fully released.

[0065] In some embodiments, before the control of the multi-way output selector Demux to connect the data line Di with the data transmission signal line Dix for a set time length, an initial charge release operation of in-plane charge emptying can be performed on the display panel. Specifically, when the display panel is powered off, and before the set time length, the controller 100 is configured to control the scan driving circuit GOA to output a scan control signal to the scan control signal line Sc, output the high-level voltage to the gate control signal line Sx, and output a black picture data voltage to the data transmission signal line Dix. That is, when the display panel is powered off, and before the set time length, the scan driving circuit GOA is controlled to normally work to output a scan control signal to normally scan the pixel unit Pi; at this time, the multi-way output selector Demux connects all the data lines Di with the corresponding data transmission lines Dix, and the data transmission lines Dix transmit the black picture data voltage close to 0V to the pixel unit Pi to control the display panel to display a black picture, and complete the initial charge release of the in-plane charge condition.

[0066] Based on the same inventive concept, the embodiments of the present application also provide an electronic device, which comprises the display panel provided by any of the above embodiments.

[0067] Reference Figure 13 As shown in FIG. 1, the electronic device 1000 provided by the embodiments of the present application can be a display device for a vehicle. In some other embodiments of the present application, the electronic device 1000 provided by the embodiments of the present application can also be a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, etc., and the present application does not make a specific limitation in this regard.

[0068] The embodiments of the present application provide a display panel, a control method thereof and an electronic device. The display panel comprises: a plurality of pixel units; a plurality of data lines, which are electrically connected with the pixel units; a plurality of multi-way output selectors, a plurality of output ends of the multi-way output selectors are respectively electrically connected with one of the data lines, a control end of the multi-way output selector is electrically connected with a gate control signal line, and an input end of the multi-way output selector is electrically connected with a data transmission signal line; wherein the control method comprises: when the display panel is powered off, applying a high-level voltage to the gate control signal line to control the multi-way output selector to connect the data line with the data transmission signal line for a set time length, and then applying a ground voltage to the gate control signal line to control the multi-way output selector to disconnect the data line with the data transmission signal line.

[0069] From the above, the technical scheme provided by the embodiment of the application can control the multi-way output selector to connect the data line and the data transmission signal line for a set time length and then disconnect them when the display panel is powered off, and the electric charge on the data line can be fully discharged through the data transmission line within the set time length when the data line and the data transmission signal line are connected. Thus, when the display panel is powered off, the closing time of the delay multi-way output selector is controlled, so that the electric charge on the data line is fully discharged, thereby improving the performance of the display panel.

[0070] In the description of the embodiments of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0071] In addition, the terms "first", "second", etc. appear only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0072] In the embodiments of the present application, unless otherwise explicitly specified and limited, the terms such as "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected or can communicate with each other; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0073] In the embodiments of the present application, unless specifically defined and limited otherwise, the first feature is "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature is "over", "above" and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the first feature is higher than the second feature in horizontal height. The first feature is "under", "below" and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the first feature is lower than the second feature in horizontal height.

[0074] In the embodiments of the present application, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" as used herein mean that the specific feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The illustrative representations of the above terms in the specification do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, different embodiments or examples described in the specification and the features of different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0075] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method for controlling a display panel, characterized in that: The display panel includes: a plurality of pixel units; a plurality of data lines, the data lines being electrically connected to the pixel units; a plurality of demultiplexers, wherein a plurality of output terminals of the demultiplexers are respectively electrically connected to one of the data lines, a control terminal of the demultiplexer is electrically connected to a selection control signal line, and an input terminal of the demultiplexer is electrically connected to a data transmission signal line; wherein the control method includes: When the display panel is turned off, a high-level voltage is applied to the strobe control signal line to control the multiplexer to connect the data line to the data transmission signal line for a set time, and then a ground voltage is applied to the strobe control signal line to control the multiplexer to disconnect the data line from the data transmission signal line; The set duration includes a first discharge phase, wherein the high-level voltage is applied to the start control signal line, the clock control signal line, the reset control signal line, the high power input signal line, the low power input signal line and the level signal line during the first discharge phase; The set time duration includes a second discharge phase after the first discharge phase, and in the second discharge phase, the voltage applied to the reset control signal line gradually changes from the high level voltage to an intermediate transition voltage.

2. The method for controlling a display panel according to claim 1, wherein: The control method includes: During the set time period, a black screen data voltage is applied to the data transmission signal line.

3. The method for controlling a display panel according to claim 1, wherein: The applying a ground voltage to the gate control signal line comprises: After the set time period, the voltage applied to the selection control signal line gradually changes from the high level voltage to the ground voltage.

4. The method for controlling a display panel according to claim 1, wherein: The display panel includes: a plurality of scan control signal lines, the scan control signal lines being electrically connected to the pixel units; a scan driving circuit, the output end of the scan driving circuit being electrically connected to the scan control signal lines; wherein the control method includes: The scan driving circuit is controlled to be powered off within the set time period.

5. The method for controlling a display panel according to claim 4, wherein: When the display panel is turned off and before the set time period, the control method includes: The scan driving circuit is controlled to output a scan control signal to the scan control signal line, apply the high level voltage to the gate control signal line, and apply a black screen data voltage to the data transmission signal line.

6. The method for controlling a display panel according to claim 4, wherein: The start end of the scan driving circuit is electrically connected to the start control signal line, the clock end of the scan driving circuit is electrically connected to the clock control signal line, the reset end of the scan driving circuit is electrically connected to the reset control signal line, the high power end of the scan driving circuit is electrically connected to the high power input signal line, the low power end of the scan driving circuit is electrically connected to the low power input signal line, and the level end of the scan driving circuit is electrically connected to the level signal line.

7. The method for controlling a display panel according to claim 6, wherein: In the second discharge phase, the voltage applied to the start control signal line, the clock control signal line, the high power input signal line, the low power input signal line and the level signal line gradually changes from the high level voltage to the ground voltage.

8. The method for controlling a display panel according to claim 7, wherein: The set time period includes a third discharge stage after the second discharge stage, wherein the voltage applied to the reset control signal line gradually changes from the intermediate transition voltage to the ground voltage in the third discharge stage.

9. A display panel, characterized in that: include: multiple pixel units; a plurality of data lines, wherein the data lines are electrically connected to the pixel units; Multiple output terminals of multiple demultiplexers are electrically connected to one of the data lines respectively; a controller, the controller being electrically connected to a control end of the demultiplexer via a strobe control signal line, and the controller being electrically connected to an input end of the demultiplexer via a data transmission signal line; the controller being configured to output a high-level voltage to the strobe control signal line when the display panel is turned off, so as to control the demultiplexer to connect the data line to the data transmission signal line for a set period of time, and then output a ground voltage to the strobe control signal line to control the demultiplexer to disconnect the data line from the data transmission signal line; The set duration includes a first discharge phase, wherein the high-level voltage is applied to the start control signal line, the clock control signal line, the reset control signal line, the high power input signal line, the low power input signal line and the level signal line during the first discharge phase; The set time duration includes a second discharge phase after the first discharge phase, and in the second discharge phase, the voltage applied to the reset control signal line gradually changes from the high level voltage to an intermediate transition voltage.

10. The display panel according to claim 9, wherein: During the set time period, the controller outputs a black screen data voltage to the data transmission signal line.

11. The display panel according to claim 9, wherein After the set time period, the voltage output by the controller to the selection control signal line gradually changes from the high level voltage to the ground voltage.

12. The display panel according to claim 9, wherein: The display panel includes: a plurality of scanning control signal lines, wherein the scanning control signal lines are electrically connected to the pixel units; a scan driving circuit, wherein an output terminal of the scan driving circuit is electrically connected to the scan control signal line; The controller is electrically connected to the scan driving circuit, and is used to control the scan driving circuit to power off within the set time period.

13. The display panel according to claim 12, wherein: When the display panel is turned off and before the set time, the controller is used to control the scan drive circuit to output a scan control signal to the scan control signal line, output the high level voltage to the selection control signal line, and output a black screen data voltage to the data transmission signal line.

14. The display panel according to claim 12, wherein: The controller is electrically connected to the start end of the scan drive circuit through the start control signal line, the controller is electrically connected to the clock end of the scan drive circuit through the clock control signal line, the controller is electrically connected to the reset end of the scan drive circuit through the reset control signal line, the controller is electrically connected to the high power end of the scan drive circuit through the high power input signal line, the controller is electrically connected to the low power end of the scan drive circuit through the low power input signal line, and the controller is electrically connected to the level end of the scan drive circuit through the level signal line.

15. The display panel according to claim 14, wherein: The controller is used to gradually change the voltage output to the start control signal line, the clock control signal line, the high power input signal line, the low power input signal line and the level signal line from the high level voltage to the ground voltage in the second discharge stage.

16. The display panel according to claim 15, wherein: The set time duration includes a third discharge stage after the second discharge stage, wherein the controller is configured to gradually change the voltage output to the reset control signal line from the intermediate transition voltage to the ground voltage during the third discharge stage.

17. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 9 to 16.

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