Self-loading storage structure suitable for nonvolatile storage unit

Abstract

The invention discloses a self-loading storage structure suitable for a nonvolatile storage unit, which belongs to the field of integrated circuits and comprises a programming structure, a loading structure, a resetting structure and a reading structure. The programming structure is used for storing configuration data into the nonvolatile storage unit through the programming path; the loading structure is used for loading data stored in the programming structure; the reset structure is used for resetting the loading structure before loading; and the reading structure is used for reading the data in the loading structure. Compared with a traditional SRAM type FPGA, data does not need to be read from an external configuration memory for operation when the FPGA is powered on, the starting speed is high, and higher flexibility is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a self-loading storage structure suitable for a non-volatile storage unit. Background Art

[0002] With the development of my country's communication and medical fields, the demand for highly reliable programmable logic devices (PLDs) has become more and more prominent. How to develop the next generation of high-performance, high-reliability, low-power non-volatile FPGA core configuration units has become one of the hot research topics in the field of integrated circuits.

[0003] There are two types of FPGAs: volatile FPGAs that are SRAM-based and require external non-volatile memory, and non-volatile FPGAs that store their configuration in memory and do not require external non-volatile memory.

[0004] FPGAs based on SRAM technology are volatile FPGAs. They use internal SRAM cells to configure storage information and can be configured and erased an unlimited number of times. This is the current mainstream FPGA configuration technology. However, after the configuration is completed, all configuration information will be lost after power failure and restart. An external non-volatile memory is required to store the configuration information, such as Flash or EEPROM. The configuration information of the external memory is likely to be stolen, resulting in reduced security. The radiation resistance of the external memory also needs to be considered.

[0005] FPGAs based on non-volatile memory cell technology do not require external non-volatile memory. Configuration information is stored in the internal FPGA configuration memory cell switch. After power failure and restart, the configuration information will not be lost. Flash FPGA is a typical non-volatile FPGA. It has the characteristics of SRAM FPGA reprogrammability. In addition, the Flash switch structure greatly reduces the number of Flash FPGA transistors and reduces static power consumption. However, Flash FPGA has certain limitations. The number of times the storage unit of Flash FPGA can be erased and written is limited, only about a few hundred times. Secondly, compared with SRAM FPGA, the process of Flash FPGA is relatively backward, and the device scale and density are also far lower than SRAM FPGA. Summary of the invention

[0006] The object of the present invention is to provide a self-loading storage structure suitable for a non-volatile storage unit to solve the problems in the background technology.

[0007] To solve the above technical problems, the present invention provides a self-loading storage structure suitable for a non-volatile storage unit, including: a programming structure, a loading structure, a reset structure, and a readout structure;

[0008] The programming structure is used to store configuration data in a non-volatile storage unit through a programming path;

[0009] The loading structure is used to load data stored in the programming structure;

[0010] The reset structure is used to reset the loading structure before loading;

[0011] The read structure is used to read the data in the load structure.

[0012] In one embodiment, the programming structure includes a left non-volatile storage unit and a right non-volatile storage unit, a first programming tube and a second programming tube; the first end of the left non-volatile storage unit is connected to the drain of the first programming tube to form a first transmission node, and the second end of the left non-volatile storage unit is connected to the power supply voltage VDD; the first end of the right non-volatile storage unit is connected to the drain of the second programming tube to form a second transmission node, and the second end of the right non-volatile storage unit is connected to the power supply voltage VDD; the gate of the first programming tube is connected to the first input node, the source is connected to the third input node, and the drain is connected to the first transmission node; the gate of the second programming tube is connected to the second input node, the source is connected to the fourth input node, and the drain is connected to the second transmission node.

[0013] In one embodiment, the loading structure includes a first isolation tube and a second isolation tube, a first closed tube and a second closed tube; the first closed tube and the second closed tube constitute a bistable circuit to form a first storage node and a second storage node; the gate of the first closed tube is connected to the first storage node, the source is grounded, and the drain is connected to the second storage node; the gate of the second closed tube is connected to the second storage node, the source is grounded, and the drain is connected to the first storage node; the gate of the first isolation tube is connected to the fifth input node, the source is connected to the first transmission node, and the drain is connected to the second storage node; the gate of the second isolation tube is connected to the fifth input node, the source is connected to the second transmission node, and the drain is connected to the first storage node.

[0014] In one embodiment, the reset structure includes a first reset tube and a second reset tube; wherein the gate of the first reset tube is connected to the sixth input node, the source is grounded, and the drain is connected to the second storage node; the gate of the second reset tube is connected to the sixth input node, the source is grounded, and the drain is connected to the first storage node.

[0015] In one embodiment, the readout structure includes a first inverter and a second inverter; wherein the input end of the first inverter is connected to the first storage node, and the output end is connected to the first output node; the input end of the second inverter is connected to the second storage node, and the output end is connected to the second output node.

[0016] In one embodiment, the self-loading storage structure includes a programming timing and a loading timing; wherein the programming timing is to program the left non-volatile storage unit and the right non-volatile storage unit through a programming path, and store data in the left non-volatile storage unit and the right non-volatile storage unit; the loading timing is to load the data stored in the non-volatile storage unit into the first storage node and the second storage node in the loading structure; the programming path includes a left non-volatile storage unit programming path and a right non-volatile storage unit programming path; wherein the first input node, the first programming tube, the third input node, and the left non-volatile storage unit constitute the left non-volatile storage unit programming path; the second input node, the second programming tube, the fourth input node, and the right non-volatile storage unit constitute the right non-volatile storage unit programming path.

[0017] In one embodiment, the programming sequence includes four states: power on, programming "1", holding, and programming "0";

[0018] When powered on, the first input node and the second input node are both at a low level, the fifth input node is at a high level, and the power supply voltage VDD is raised to the programming voltage;

[0019] When programming "1", the third input node = "0", the fourth input node = "1", the first input node and the second input node are pulled high, the two programming tubes are turned on, and when the voltage difference across the left non-volatile memory cell is higher than the threshold voltage of the left non-volatile memory cell, the left non-volatile memory cell changes from a high impedance state to a low impedance state; at the same time, because the fourth input node = "1", the voltage difference across the right non-volatile memory cell is lower than the threshold voltage of the right non-volatile memory cell, and the right non-volatile memory cell remains in a high impedance state;

[0020] When the power supply voltage VDD is maintained at the programming voltage state, the third input node and the fourth input node become low level, the first input node and the second input node also become low level, the two programming tubes are turned off, and the programming path is disconnected;

[0021] When programming "0", the third input node = "1", the fourth input node = "0", the first input node and the second input node are pulled high, the two programming tubes are turned on, and when the voltage difference across the non-volatile storage unit on the right is higher than the threshold voltage of the non-volatile storage unit on the right, the non-volatile storage unit on the right changes from a high-impedance state to a low-impedance state; at the same time, since the third input node = "1", the voltage difference across the non-volatile storage unit on the left is less than the threshold voltage of the non-volatile storage unit on the left, and the non-volatile storage unit on the left remains in a high-impedance state.

[0022] In one embodiment, the loading sequence includes three states: power-on, reset, and loading;

[0023] When powered on, the first input node, the second input node and the sixth input node are all at a low level, the fifth input node is at a high level, and the power supply voltage is a normal working voltage;

[0024] During reset, the first input node and the second input node remain at a low level, the fifth input node remains at a high level, and the sixth input node becomes a high level, so that the first storage node and the second storage node are reset to a low level;

[0025] During loading, the sixth input node is first changed to a low level to cancel the reset state, and then the fifth input node is changed to a low level to open the data loading path. At this time, due to the different resistance values ​​of the non-volatile storage unit on the left and the non-volatile storage unit on the right, the voltage division of the non-volatile storage unit on the side with the lower resistance value is small, and the storage node voltage on this side is higher than the storage node voltage on the other side. At the same time, due to the bistable structure formed by the first closed-conductor and the second closed-conductor, the storage node on the side with the higher voltage is pulled up to a high level, and the storage node on the side with the lower voltage is pulled down to a low level. The data in the non-volatile storage unit will be loaded into the storage node of the loading structure. At the same time, the first inverter and the second inverter in the read-out structure reversely output the signal of the storage node to the output node to complete the data loading process.

[0026] The present invention provides a self-loading storage structure applicable to a non-volatile storage unit, which has the following beneficial effects:

[0027] (1) Using non-volatile storage units as programming devices can ensure that the data configured in the non-volatile storage unit group will not be lost after the FPGA is powered off;

[0028] (2) Compared with traditional SRAM-based FPGAs, based on the characteristics of non-volatile storage units, there is no need to read data from an external configuration memory when powered on, so the startup speed is fast and the data reliability and confidentiality are high;

[0029] (3) Compared with Flash-type FPGA, based on the characteristics of non-volatile storage cells, it can have a higher number of erase and write times and greater flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The present invention provides a self-loading storage structure diagram suitable for a non-volatile storage unit.

[0031] Figure 2 It is a schematic diagram of the programming principle of MRAM type non-volatile memory cell.

[0032] Figure 3 The present invention is a schematic diagram of a programming operation mode of a self-loading storage structure suitable for a non-volatile storage unit.

[0033] Figure 4The present invention is a schematic diagram of a loading operation mode of a self-loading storage structure suitable for a non-volatile storage unit. DETAILED DESCRIPTION

[0034] The following is a further detailed description of a self-loading storage structure applicable to a non-volatile storage unit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] The present invention provides a self-loading storage structure suitable for a non-volatile storage unit, and its implementation structure is as follows: Figure 1 As shown, it includes programming structure, loading structure, reset structure and readout structure. The programming structure is used to store configuration data into non-volatile storage units through programming paths; the loading structure is used to load data stored in the programming structure; the reset structure is used to reset the loading structure before loading; and the readout structure is used to read out data in the loading structure.

[0036] The programming structure includes: 2 non-volatile storage units and 2 programming tubes; the two non-volatile storage units are the left non-volatile storage unit M1 and the right non-volatile storage unit M2, and the two programming tubes are the first programming tube N1 and the second programming tube N2; the first end of the left non-volatile storage unit M1 is connected to the drain of the first programming tube N1 to form a first transmission node T1, and the second end of the left non-volatile storage unit M1 is connected to VDD; the first end of the right non-volatile storage unit M2 is connected to the drain of the second programming tube N2 to form a second transmission node T2, and the second end of the right non-volatile storage unit M2 is connected to VDD; the gate of the first programming tube N1 is connected to the first input node A1, the source is connected to the third input node BL, and the drain is connected to the first transmission node T1; the gate of the second programming tube N2 is connected to the second input node A2, the source is connected to the fourth input node BLB, and the drain is connected to the second transmission node T2.

[0037] The loading structure includes: 2 isolation transistors and 2 closed transistors; the two isolation transistors are a first isolation transistor P1 and a second isolation transistor P2, and the two closed transistors are a first closed transistor N5 and a second closed transistor N6; the first closed transistor N5 and the second closed transistor N6 constitute a bistable circuit to form a first storage node B1 and a second storage node B2; the gate of the first closed transistor N5 is connected to the first storage node B1, the source is grounded, and the drain is connected to the second storage node B2; the gate of the second closed transistor N6 is connected to the second storage node B2, the source is grounded, and the drain is connected to the first storage node B1; the gate of the first isolation transistor P1 is connected to the fifth input node A4, the source is connected to the first transmission node T1, and the drain is connected to the second storage node B2; the gate of the second isolation transistor P2 is connected to the fifth input node A4, the source is connected to the second transmission node T2, and the drain is connected to the first storage node B1.

[0038] The reset structure includes: 2 reset tubes, namely a first reset tube N3 and a second reset tube N4; wherein the gate of the first reset tube N3 is connected to the sixth input node A3, the source is grounded, and the drain is connected to the second storage node B2; the gate of the second reset tube N4 is connected to the sixth input node A3, the source is grounded, and the drain is connected to the first storage node B1.

[0039] The readout structure includes: 2 inverters, namely a first inverter X1 and a second inverter X2; wherein the input end of the first inverter X1 is connected to the first storage node B1, and the output end is connected to the first output node Z1; the input end of the second inverter X2 is connected to the second storage node B2, and the output end is connected to the second output node Z2.

[0040] The present invention provides a programming sequence of a self-loading storage structure suitable for a non-volatile storage unit, including power-on, programming "1", retention, and programming "0", a total of 4 states. Among them, programming is to program the left non-volatile storage unit M1 and the right non-volatile storage unit M2 through a programming path, and store data in the left non-volatile storage unit M1 and the right non-volatile storage unit M2.

[0041] The programming path includes a programming path for the left non-volatile memory cell M1 and a programming path for the right non-volatile memory cell M2; wherein the programming path for the left non-volatile memory cell M1 includes: a first input node A1, a first programming tube N1, a third input node BL, and the left non-volatile memory cell M1; the programming path for the right non-volatile memory cell M2 includes: a second input node A2, a second programming tube N2, a fourth input node BLB, and the right non-volatile memory cell M2.

[0042] Non-volatile memory cells include flash, MRAM, PCM and other types of cells. Those skilled in the art will understand that flash is a non-volatile memory cell based on a floating gate transistor, which stores data in the form of electric charge in the floating gate. Even after power failure, the electric charge can still be maintained in the floating gate; MRAM is a non-volatile memory cell that uses the magnetization direction of magnetic materials to store data, and realizes data writing and reading by controlling the magnetization direction of the magnetic layer in the magnetic tunnel junction; PCM is a non-volatile memory cell that stores data by the principle of phase change material converting between crystalline and amorphous states.

[0043] The programming principle of non-volatile memory cells such as MRAM is as follows Figure 2 As shown. Those skilled in the art will understand that the MRAM element is a magnetic memory based on electron spin transfer torque. By changing the direction of the write current, the magnetoresistance state of the MTJ (Magnetic Tunneling Junction) can be changed to a "high" resistance state or a "low" resistance state. When the current passes through the isolation layer from the fixed layer, the direction of the magnetic field of the free layer will change. Since the direction of the magnetic field of the fixed layer is fixed, when the magnetization direction of the free layer is the same as that of the fixed layer, the MTJ presents a "low" resistance state to the outside. When the current direction is changed and the magnetization direction of the free layer is opposite to that of the fixed layer, the MTJ presents a "high" resistance state to the outside.

[0044] In this embodiment, there are two non-volatile memory cells (i.e., the left non-volatile memory cell M1 and the right non-volatile memory cell M2). One end of the left non-volatile memory cell M1 is connected to the first transmission node T1, and the other end is connected to VDD. The first transmission node T1 is connected to the third input node BL through the first programming tube N1; one end of the right non-volatile memory cell M2 is connected to the second transmission node T2, and the other end is connected to VDD; the second transmission node T2 is connected to the fourth input node BLB through the second programming tube N2.

[0045] Programming sequence is as follows Figure 3 As shown, there are four states: power on, program "1", hold, and program "0".

[0046] When powered on, the first input node A1 and the second input node A2 are both at a low level, the fifth input node A4 is at a high level, and the power supply voltage VDD is raised to the programming voltage;

[0047] When programming "1", the third input node BL line = "0", the fourth input node BLB line = "1", the first input node A1 and the second input node A2 are pulled high, and the two programming tubes are turned on. When the voltage difference across the left non-volatile memory cell M1 is higher than the threshold voltage of the left non-volatile memory cell, the left non-volatile memory cell M1 will change from a "high" resistance state to a "low" resistance state. At the same time, since the fourth input node BLB line = "1", the voltage difference across the right non-volatile memory cell M2 is lower than the threshold voltage of the right non-volatile memory cell, and the right non-volatile memory cell M2 will remain in a "high" resistance state;

[0048] When holding, the power supply voltage VDD is kept at the programming voltage state, the third input node BL line and the fourth input node BLB line become low level, the first input node A1 and the second input node A2 also become low level, the two programming tubes are turned off, and the programming path is disconnected;

[0049] When programming "0", the third input node BL line = "1", the fourth input node BLB line = "0", the first input node A1 and the second input node A2 are pulled high, and the two programming tubes are turned on. When the voltage difference across the right non-volatile memory cell M2 is higher than the threshold voltage of the right non-volatile memory cell, the right non-volatile memory cell M2 will change from a "high" resistance state to a "low" resistance state. At the same time, since the third input node BL line = "1", the voltage difference across the left non-volatile memory cell M1 is lower than the threshold voltage of the left non-volatile memory cell, and the left non-volatile memory cell M1 will maintain a "high" resistance state.

[0050] In this embodiment, the programming timing includes four states: power-on, programming "1", holding, and programming "0". The timing configuration can be determined based on the programming data, and the configuration data can be stored in the non-volatile storage unit. The data in the non-volatile storage unit can be used through the self-loading timing to load the data into the first storage node B1 and the second storage node B2 in the loading structure.

[0051] In addition, the present invention provides a self-loading timing of a self-loading storage structure suitable for a non-volatile memory cell, which loads the data stored in the non-volatile memory cell into the first storage node B1 and the second storage node B2 in the loading structure, such as Figure 4 As shown, it includes three states: power-on, reset, and loading.

[0052] When powered on, the first input node A1, the second input node A2 and the sixth input node A3 are all at low level, the fifth input node A4 is at high level, and the power supply voltage is the normal working voltage;

[0053] During reset, the first input node A1 and the second input node A2 remain at a low level, and the fifth input node A4 remains at a high level. At this time, the sixth input node A3 becomes a high level, so that the first storage node B1 and the second storage node B2 are reset to a low level.

[0054] During loading, the sixth input node A3 is first changed to a low level to cancel the reset state, and then the fifth input node A4 is changed to a low level to open the data loading path. At this time, due to the different resistance values ​​of the non-volatile memory cell M1 on the left and the non-volatile memory cell M2 on the right, the voltage division of the non-volatile memory cell on the side with the lower resistance value is small, and the storage node voltage on this side is higher than the storage node voltage on the other side. At the same time, due to the bistable structure formed by the first closed transistor N5 and the second closed transistor N6, the storage node on the side with the higher voltage will be pulled up to a high level, and the storage node on the side with the lower voltage will be pulled down to a low level. The data in the non-volatile memory cell will be loaded into the storage nodes of the loading structure (i.e., the first storage node B1 and the second storage node B2). At the same time, the first inverter X1 and the second inverter X2 in the readout structure will reversely output the signal of the storage node to the output node to complete the data loading process.

[0055] The self-loading sequence includes three states: power-on, reset, and load, and the data in the non-volatile storage unit can be loaded into the storage node of the loading structure.

[0056] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A self-loading storage structure suitable for a non-volatile storage unit, characterized in that: include: Programming structure, loading structure, reset structure, and readout structure; The programming structure is used to store configuration data in a non-volatile storage unit through a programming path; The loading structure is used to load data stored in the programming structure; The reset structure is used to reset the loading structure before loading; The read structure is used to read the data in the load structure.

2. The self-loading storage structure applicable to a non-volatile storage unit according to claim 1, characterized in that: The programming structure includes a left non-volatile storage unit and a right non-volatile storage unit, a first programming tube and a second programming tube; The first end of the left non-volatile memory cell is connected to the drain of the first programming tube to form a first transmission node, and the second end of the left non-volatile memory cell is connected to the power supply voltage VDD; The first end of the right non-volatile storage unit is connected to the drain of the second programming tube to form a second transmission node, and the second end of the right non-volatile storage unit is connected to the power supply voltage VDD; the gate of the first programming tube is connected to the first input node, the source is connected to the third input node, and the drain is connected to the first transmission node; The gate of the second programming tube is connected to the second input node, the source is connected to the fourth input node, and the drain is connected to the second transmission node.

3. The self-loading storage structure applicable to a non-volatile storage unit according to claim 2, characterized in that: The loading structure comprises a first isolation tube and a second isolation tube, a first closed conduction tube and a second closed conduction tube; the first closed conduction tube and the second closed conduction tube constitute a bistable circuit to form a first storage node and a second storage node; the gate of the first closed conduction tube is connected to the first storage node, the source is grounded, and the drain is connected to the second storage node; The gate of the second closed transistor is connected to the second storage node, the source is grounded, and the drain is connected to the first storage node; The gate of the first isolation transistor is connected to the fifth input node, the source is connected to the first transmission node, and the drain is connected to the second storage node; The gate of the second isolation transistor is connected to the fifth input node, the source is connected to the second transmission node, and the drain is connected to the first storage node.

4. The self-loading storage structure applicable to a non-volatile storage unit according to claim 3, characterized in that: The reset structure includes a first reset tube and a second reset tube; wherein the gate of the first reset tube is connected to the sixth input node, the source is grounded, and the drain is connected to the second storage node; the gate of the second reset tube is connected to the sixth input node, the source is grounded, and the drain is connected to the first storage node.

5. The self-loading storage structure applicable to a non-volatile storage unit according to claim 4, characterized in that: The readout structure includes a first inverter and a second inverter; wherein the input end of the first inverter is connected to the first storage node, and the output end is connected to the first output node; the input end of the second inverter is connected to the second storage node, and the output end is connected to the second output node.

6. The self-loading storage structure applicable to a non-volatile storage unit according to claim 5, characterized in that: The self-loading storage structure includes a programming sequence and a loading sequence; The programming sequence is to program the left non-volatile storage unit and the right non-volatile storage unit through the programming path, and store data in the left non-volatile storage unit and the right non-volatile storage unit; The loading sequence is to load the data stored in the non-volatile storage unit into the first storage node and the second storage node in the loading structure; the programming path includes a left non-volatile storage unit programming path and a right non-volatile storage unit programming path; The first input node, the first programming tube, the third input node, and the left non-volatile storage unit constitute the left non-volatile storage unit programming path; the second input node, the second programming tube, the fourth input node, and the right non-volatile storage unit constitute the right non-volatile storage unit programming path.

7. The self-loading storage structure applicable to a non-volatile storage unit according to claim 6, characterized in that: The programming sequence includes four states: power on, program "1", hold, and program "0"; When powered on, the first input node and the second input node are both at a low level, the fifth input node is at a high level, and the power supply voltage VDD is raised to the programming voltage; When programming "1", the third input node = "0", the fourth input node = "1", the first input node and the second input node are pulled high, the two programming tubes are turned on, and when the voltage difference across the left non-volatile memory cell is higher than the threshold voltage of the left non-volatile memory cell, the left non-volatile memory cell changes from a high impedance state to a low impedance state; at the same time, since the fourth input node = "1", the voltage difference across the right non-volatile memory cell is lower than the threshold voltage of the right non-volatile memory cell, and the right non-volatile memory cell remains in a high impedance state; When the power supply voltage VDD is maintained at the programming voltage state, the third input node and the fourth input node become low level, the first input node and the second input node also become low level, the two programming tubes are turned off, and the programming path is disconnected; When programming "0", the third input node = "1", the fourth input node = "0", the first input node and the second input node are pulled high, the two programming tubes are turned on, and when the voltage difference across the non-volatile memory cell on the right is higher than the threshold voltage of the non-volatile memory cell on the right, the non-volatile memory cell on the right changes from a high-impedance state to a low-impedance state; at the same time, since the third input node = "1", the voltage difference across the non-volatile memory cell on the left is lower than the threshold voltage of the non-volatile memory cell on the left, and the non-volatile memory cell on the left maintains a high-impedance state.

8. The self-loading storage structure applicable to a non-volatile storage unit according to claim 6, characterized in that: The loading sequence includes three states: power-on, reset, and loading; When powered on, the first input node, the second input node and the sixth input node are all at a low level, the fifth input node is at a high level, and the power supply voltage is a normal working voltage; During reset, the first input node and the second input node remain at a low level, the fifth input node remains at a high level, and the sixth input node becomes a high level, so that the first storage node and the second storage node are reset to a low level; During loading, the sixth input node is first changed to a low level to cancel the reset state, and then the fifth input node is changed to a low level to open the data loading path. At this time, due to the different resistance values ​​of the non-volatile storage unit on the left and the non-volatile storage unit on the right, the voltage division of the non-volatile storage unit on the side with the lower resistance value is small, and the storage node voltage on this side is higher than the storage node voltage on the other side. At the same time, due to the bistable structure formed by the first closed-conductor and the second closed-conductor, the storage node on the side with the higher voltage is pulled up to a high level, and the storage node on the side with the lower voltage is pulled down to a low level. The data in the non-volatile storage unit will be loaded into the storage node of the loading structure. At the same time, the first inverter and the second inverter in the read-out structure reversely output the signal of the storage node to the output node to complete the data loading process.

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