A method and device for improving storage unit test speed

Abstract

The present invention provides a method for improving the test speed of a storage unit, using a multi-array enable signal to perform a multi-array enable operation on the output signal of a storage array decoder on a storage chip, activating all array address signals generated by the storage array decoder, sending the activated array address signal to a row address decoder for decoding to generate a row address selection signal and inputting it into a storage array; and the activated array address signal enters a read / write command storage array address selection module to generate a read / write array address signal, and the read / write array address signal is sent to a row and column address decoder for decoding to generate a column address selection signal and inputting it into a storage array; the storage array tests all storage cells of the storage array simultaneously according to the input row address selection signal and column address selection signal. The present invention also provides a device for improving the test speed of a storage unit.

Description

Technical Field

[0001] The invention belongs to the technical field of dynamic random access memory testing, and in particular relates to a method and a device for improving the testing speed of a storage unit. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory widely used in computers and other digital electronic devices. Dynamic Random Access Memory (DRAM) uses the charge state in capacitors to store binary information. Each storage cell consists of a capacitor and a transistor to store a single bit of data. A typical DRAM chip integrates tens of millions or even billions of such storage cells, which together form a high-density data storage array.

[0003] Since the performance, reliability and life of DRAM are directly affected by the health of these tiny memory cells, ensuring the quality of each memory cell is a key factor in ensuring the stable operation of the entire DRAM chip. Strict quality inspection not only helps to discover potential manufacturing defects, but also improves the long-term reliability of the product, becoming an indispensable step in producing high-quality DRAM.

[0004] There are a large number of memory cells in DRAM. Usually, these memory cells are divided into several memory arrays, and the memory cells in each array are accessed through the memory array address. This means that during chip read and write operations, only the memory cells in one array can be accessed at a time.

[0005] The test of the memory cell in DRAM is usually carried out by writing data into the DRAM and reading the data at the same time, comparing the written data with the read data, and then testing the memory array in the memory cell. However, when testing the memory cell, it is necessary to write data into the memory array and read the data in the memory array, so the test depends on the writing and reading speed of the memory chip. When performing a writing or reading operation, only one memory cell in the array can be accessed at a time, which limits the test speed and causes the efficiency of the memory chip memory cell test to be too slow. Summary of the invention

[0006] The present invention provides a method and device for improving the test speed of a storage unit, which can simultaneously access all storage arrays in a storage chip and improve the test speed of the storage unit.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for improving the test speed of storage cells, which uses a multi-array enable signal to perform a multi-array enable operation on the output signal of a storage array decoder on a storage chip to activate all array address signals generated by the storage array decoder; the activated array address signal enters an activation command storage array address selection module for processing to generate an activation array address signal, the activation array address signal is sent to a row address decoder for decoding to generate a row address selection signal and input into the storage array; and the activated array address signal enters a read / write command storage array address selection module to generate a read / write array address signal, the read / write array address signal is sent to a column address decoder for decoding to generate a column address selection signal and input into the storage array; the storage array tests all storage cells of the storage array simultaneously according to the input row address selection signal and column address selection signal. The beneficial effect of the technical solution is that the storage unit testing method of the present invention shields the signal output by the address decoder through multiple array enable signals, so that all the output array address signals are activated, so that all the storage arrays can be accessed, and there is no need to make major changes to the chip circuit, so that the chip can write and read data normally when working, and all the storage units can be accessed at one time during testing, thereby realizing fast testing.

[0009] The array address signal and the multi-array enable signal output by the storage array decoder are sent to the NAND gate circuit for logic selection, and the activated array address signal is output.

[0010] The timing of multiple signals in the activated array address signal is the same.

[0011] The multi-array enable signal maintains a constant low potential during an operation cycle.

[0012] The test includes, within one operation cycle, writing data to the storage array, reading the written data at the same time, and comparing whether each bit value of the written data and the read data is the same to determine whether the storage unit is normal.

[0013] In one operation cycle, the written data and the read data are respectively input into the comparator, and each data value of the written data and the read data is compared by the comparator, and the comparison result is output when each data value is the same.

[0014] The comparator outputs a result 1 when the comparison results are the same, and outputs a result 0 when the comparison results are different.

[0015] Another embodiment of the present invention provides a device for improving the test speed of a storage unit, comprising a storage array address decoder arranged on a storage chip, wherein the output result of the storage array address decoder is input into a multi-array enable module, wherein the multi-array enable module comprises a plurality of parallel NAND gate logic circuits, wherein the input ends of the NAND gate logic circuits respectively input the array address signal output by the storage array address decoder and the external multi-array enable signal, wherein the activation array address signal output by the multi-array enable module is respectively input into an activation command array address selection module and a read / write command array address selection module; an external activation command is input into the activation command array address selection module and outputs the activation array address signal to a row address decoder, wherein the row address decoder decodes and generates a row address selection signal and inputs the row address selection signal into the storage array; an external read / write command is input into the read / write command array address selection module and outputs the read / write array address signal to a column address decoder, wherein the column address decoder decodes and generates a column address selection signal and inputs the storage array; and the storage array tests the storage units of all storage arrays simultaneously according to the input row address selection signal and column address selection signal.

[0016] It also includes a testing device, which includes a write buffer and a read amplifier that communicate with the storage array; the write data is stored in a write register, and the write register communicates with the write buffer and the comparator respectively; the output end of the read amplifier communicates with the comparator; the comparator compares the written data and the read data within an operation cycle, and outputs a test result based on the comparison result.

[0017] The comparator compares each data value of the written data and the read data, and outputs 1 if the comparison results are the same, and outputs 0 if the comparison results are different.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. By connecting a multi-array enabling module in the chip, the present invention can activate all array address signals, so that all storage arrays can be accessed in one operation, making the test faster and more efficient. At the same time, there is no need to make excessive modifications to the circuit, and the normal read and write operations of the chip are not affected.

[0019] 2. The storage unit test of the present invention compares the written data with the read data through a comparator and outputs a 0 / 1 value as the comparison result, thereby reducing the inconvenience caused by manual comparison and improving the efficiency of the test.

[0020] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 This is a simplified diagram of the storage array of Example 1.

[0023] Figure 2 This is the control timing diagram of the storage array.

[0024] Figure 3 It is a circuit diagram of a device for improving memory cell test speed according to Embodiment 1.

[0025] Figure 4 for Figure 3 The control timing diagram corresponding to the circuit.

[0026] Figure 5 This is a circuit diagram for comparing write data and read data in Example 1. DETAILED DESCRIPTION

[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0028] Example 1

[0029] Embodiment 1 provides a method for improving the test speed of a storage unit, using a multi-array enable signal to perform a multi-array enable operation on the output signal of a storage array decoder on a storage chip, activating all array address signals generated by the storage array decoder; the activated array address signal enters an activation command storage array address selection module for processing, generating an activation array address signal, the activation array address signal is sent to a row address decoder for decoding to generate a row address selection signal and input into a storage array; and the activated array address signal enters a read / write command storage array address selection module to generate a read / write array address signal, the read / write array address signal is sent to a column address decoder for decoding to generate a column address selection signal and input into a storage array; the storage array writes and reads data according to the input row address selection signal and column address selection signal.

[0030] The following is a detailed explanation with reference to the accompanying drawings. Figure 1The memory chip of the present invention is provided with a plurality of memory arrays. Embodiment 1 is described by taking four memory arrays as an example. It should be noted that there are several memory arrays on the actual memory chip, and each memory array has several memory cells. The DRAM structure is a prior art and will not be described in detail here. When writing data to and reading data from the memory array, the memory array address code, read command, write command, activation signal and written data are usually required. The memory array address code is used to locate the specific memory cell position in the memory array. With the activation command, read command or write command, the specific memory cell can be located and the read operation or the write operation can be performed. When the write operation is performed, the data is written.

[0031] See also Figure 3 In the circuit diagram, the 2-bit storage array address code is used as an example for explanation in Example 1, wherein the number of bits of the storage array address code needs to be associated with the number of storage arrays. The specific number of bits of the storage array address code is n, and the number of storage arrays is 2 to the power of n. When searching for the location of a specific storage cell in the storage array, the storage array address code changes. After each encoding value is decoded, only one array address is in an activated low potential state (corresponding to one storage array address). Therefore, when data is written or read, the storage cell in the prior art can only access the storage cell of one storage array at a time, and cannot access multiple storage cells at a time, which leads to low test efficiency when the storage chip is tested.

[0032] Embodiment 1 To solve the above problem, an output array address signal activation operation of a storage array address decoder is adopted to activate all array address signals output by the storage array address decoder, and multiple signals in the activated array address signal have the same timing.

[0033] The activation here corresponds to the subsequent activation command storage array address selection module and the read / write command storage array address selection module. In order to conveniently combine the activation command and the read / write command with the array address signal to find a specific storage array to execute the read command or the write command, the activation command storage array address selection module and the read / write command storage array address selection module usually input the input array address signal and the activation command, or the read / write command into the NAND gate circuit for logical operation to output a signal that can trigger the storage array. Therefore, the activation of all the array address signals output by the storage array address decoder in Example 1 means that all the array address signals are triggered to be the activation command, or the read / write command performs the above-mentioned logical operation (logical operation performed by the NAND gate circuit) to generate a signal that can trigger the logic array. In Example 1, a multi-array enable signal is used to activate all the array address signals to a high potential state, so that all the array address signals are activated. Therefore, within one operation cycle, one data write and one data read operation can be performed on all storage arrays, and the written data is compared with the read data to test whether the storage unit is normal.

[0034] As an optional method, the present invention activates the array address signal through an external multi-array enable signal, and specifically performs a logic operation on the output array address signal and the multi-array enable signal through multiple NAND gate circuits, wherein the multi-array enable signal maintains a constant low potential during the operation cycle.

[0035] The present application adds a multi-array enable signal to a normal memory chip. During normal read and write operations, the multi-array enable signal is pulled high. At this time, only one signal of the activated array address signal will be high (indicating enablement); when the memory chip is tested, when the multi-array enable signal is low, all array address signals are activated to a high potential (indicating activation of all memory arrays). Therefore, the present application sets an additional multi-array enable signal in a normal memory chip, and then controls the multi-array enable signal to achieve normal read and write operations of the chip and a one-time test of the chip, which is convenient to operate and does not affect the normal use of the chip.

[0036] As an optional method, the storage cells in Example 1 are tested by writing data to all storage cells in all storage arrays and reading data from all storage cells in all storage arrays in one operation cycle, and comparing each data value of the written data and the read data. If each data value is accurate, then there is no abnormality in the storage cells of the storage array. If there is an inconsistency in the data values, then there is an abnormality in the storage cells of the storage array.

[0037] In order to simplify the testing process, a comparator is used to compare and analyze each bit of the written data and the read data. In one operation cycle, the written data and the read data are respectively entered into the comparator for comparison. If any bit of data value is the same, the comparator outputs the result 1, and if any bit of data value is different, the comparison result is 0. At this time, the output result of the comparator can more directly find out which storage unit has a problem. Figure 5 For example, if Figure 5 If the test result output is 1111, it means that the four written data A[1], A[2], A[3], A[4] are the same as the four read data B[1], B[2], B[3], B[4], which means that there is no abnormality in the storage unit.

[0038] Example 2

[0039] Embodiment 2 provides a device for improving the test speed of a storage unit, comprising a storage array address decoder on a storage chip, wherein the output result of the storage array address decoder is input into a multi-array enable module, wherein the multi-array enable module comprises a plurality of parallel NAND gate logic circuits, wherein the input ends of the NAND gate logic circuits respectively input the array address signal output by the storage array address decoder and the external multi-array enable signal, wherein the activation array address signal output by the multi-array enable module is respectively input into an activation command array address selection module and a read / write command array address selection module; an external activation command is input into the activation command array address selection module and outputs the activation array address signal to a row address decoder, wherein the row address decoder decodes and generates a row address selection signal which is input into a storage array; an external read / write command is input into the read / write command array address selection module and outputs the read / write array address signal to a column address decoder, wherein the column address decoder decodes and generates a column address selection signal which is input into a storage array; and the storage array writes and reads data according to the input row address selection signal and column address selection signal.

[0040] See also Figure 1-4 The control circuit of the present invention includes a storage array address decoder, a multi-array enabling module, an activation command storage array address selection module, a read / write command storage array address selection module, a row address decoder, a column address decoder and a storage array, wherein the storage array address decoder performs a decoding operation according to the input storage array address code, and outputs an array address signal having the same number as the storage array address, and the address signal is sent to the multi-array enabling module for an activation operation. The activation operation has been explained in the above embodiment 1. In combination with embodiment 1, Figure 3 The control circuit diagram and Figure 4 The timing diagram in the embodiment 2 is used to illustrate that the activation is to activate all array address signals to a high potential. The array address after activation (i.e. Figure 3 The array address [x] in the reverse) enters the activation command storage array selection module and the read / write command storage array address module. The activation command storage array selection module and the read / write command storage array address module are composed of multiple parallel NAND gate circuits, which perform logical operations on the array address signal and the activation command or the read / write command to output to the row address decoder or the column address decoder. The row address decoder and the column address decoder here are prior art and will not be repeated in this application. After all the activated array address signals are decoded by the row address decoder and the column address decoder, the decoding values ​​are output. The memory chip accesses all the storage cells of the entire storage array according to the decoding values ​​to implement the operations of writing data and reading data for all the storage cells of the entire storage array.

[0041] See Figure 4 From the timing diagram, it can be seen that the timing of the activated array address [0], array address [1], array address [2], and array address [3] are the same; the timing of activating array address [0], activating array address [1], activating array address [2], and activating array address [3] are the same; the timing of reading / writing array address [0], reading / writing array address [1], reading / writing array address [2], and reading / writing array address [3] are the same. The timing of these signals is the same, so that the storage array can be read or written at the same time.

[0042] As an alternative, see Figure 5 The schematic diagram of the read-write device includes a write register storing write data and a write buffer. The data in the write register enters the storage array through the write buffer, and the data in the write register and the storage array data read by the read amplifier enter the comparator for comparison to output the test result. The comparator comparison here compares each data value of the written and read data. When the data values ​​are the same, the comparator outputs the result 1, and when the data values ​​are different, the comparison result 0 is output. At this time, through the output result of the comparator, it is possible to more directly find which storage unit has a problem. Figure 5 For example, if Figure 5 If the test result output in is 1111, it means that the four written data A[1], A[2], A[3], A[4] are the same as the four read data B[1], B[2], B[3], B[4], which means that there is no abnormality in the storage unit. Figure 2 The present application can simultaneously output the results of storage array 1_comparator, storage array 2_comparator, storage array 3_comparator, and storage array 4_comparator. Through the output comparator results, it is possible to quickly understand whether the storage chip has defects.

[0043] The above is a detailed introduction to a method and device for improving the test speed of a storage unit provided by the present invention. The structure and working principle of the present invention are described in detail using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for improving the test speed of a storage unit, characterized in that: Using a multi-array enable signal to perform a multi-array enable operation on an output signal of a storage array decoder on a storage chip, activating all array address signals generated by the storage array decoder; Sending the array address signal and the multi-array enable signal output by the storage array decoder to the NAND gate circuit for logic selection, and outputting the activated array address signal, wherein the multi-array enable signal maintains a constant low potential during the operation cycle; The activated array address signal enters the activation command storage array address selection module for processing to generate an activation array address signal, and the activation array address signal is sent to the row address decoder for decoding to generate a row address selection signal and input into the storage array; The activated array address signal enters the read / write command storage array address selection module to generate a read / write array address signal, and the read / write array address signal is sent to the column address decoder for decoding to generate a column address selection signal and input into the storage array; The memory array tests all memory cells of the memory array simultaneously according to the input row address selection signal and column address selection signal.

2. A method for improving the test speed of a storage unit according to claim 1, characterized in that: The timing of multiple signals in the activated array address signal is the same.

3. A method for improving the test speed of a storage unit according to claim 1, characterized in that: The test includes, within one operation cycle, writing data to the storage array, reading the written data at the same time, and comparing whether each bit value of the written data and the read data is the same to determine whether the storage unit is normal.

4. A method for improving the test speed of a storage unit according to claim 3, characterized in that: In one operation cycle, the written data and the read data are respectively input into the comparator, and each data value of the written data and the read data is compared by the comparator, and the comparison result is output when each data value is the same.

5. A method for improving the test speed of a storage unit according to claim 4, characterized in that: The comparator outputs a result 1 when the comparison results are the same, and outputs a result 0 when the comparison results are different.

6. A device for improving the test speed of a storage unit, comprising a storage array address decoder on a storage chip, characterized in that: The output result of the storage array address decoder is input into a multi-array enabling module, which includes a plurality of parallel NAND gate logic circuits, the input ends of which are respectively input with the array address signal output by the storage array address decoder and the external multi-array enabling signal, and the activation array address signal output by the multi-array enabling module is respectively input into the activation command array address selection module and the read / write command array address selection module; An external activation command is input to the activation command array address selection module and outputs an activation array address signal to a row address decoder, and the row address decoder decodes and generates a row address selection signal which is input to a storage array; An external read / write command is input to the read / write command array address selection module and outputs a read / write array address signal to a column address decoder, and the column address decoder decodes and generates a column address selection signal which is input to a storage array; The memory array tests all memory cells of the memory array simultaneously according to the input row address selection signal and column address selection signal.

7. The device for improving the test speed of a storage unit according to claim 6, characterized in that: Also included is a test device including a write buffer and a read amplifier in communication with the memory array; The write data is stored in a write register, and the write register communicates with the write buffer and the comparator respectively; An output of the sense amplifier is in communication with the comparator; The comparator performs comparison based on written data and read data in one operation cycle, and outputs a test result based on the comparison result.

8. The device for improving the test speed of a storage unit according to claim 7, characterized in that: The comparator compares each data value of the written data and the read data, and outputs 1 if the comparison results are the same, and outputs 0 if the comparison results are different.

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