Method for reducing electric leakage of small memory chip

Abstract

The invention provides a method for reducing electric leakage of a small memory chip, and belongs to the technical field of semiconductor chips. The method comprises the following steps: acquiring current electric leakage data, original electric leakage data and function test data corresponding to a to-be-detected chip; according to the original electric leakage data, the current electric leakage data, a pre-established electric leakage analysis model and function test data, determining whether the electric leakage point location of the to-be-detected chip is the polycrystalline silicon spacing; if yes, determining whether the current growth interval of the metal silicide in the to-be-detected chip exceeds the calibrated growth interval or not according to the profile measurement result of the to-be-detected chip; and if yes, thickening the side wall of a second channel of silicon nitride growing outside the original first channel of silicon nitride on the control tube of the to-be-detected chip, adjusting the etching amount of the second channel of silicon nitride, and performing tape-out verification on the adjustment result of the to-be-detected chip to obtain a target adjustment result. The memory chip and the manufacturing method thereof can achieve the effect of inhibiting side penetration of common-length metal silicide between two pieces of polycrystalline silicon in the memory chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a method for reducing leakage of a small storage chip. Background Art

[0002] With the advancement of semiconductor manufacturing technology, chip miniaturization has become the mainstream direction of chip manufacturing. Memory chips, as an integrated circuit chip that stores data, are also called memory chips. Memory chips are an important part of computer systems, mainly used to temporarily or permanently store data and instructions. Memory chips are used to store and retrieve data in computer systems to achieve fast access and data processing functions of computer systems and provide support for the normal operation of computer systems. Among them, small memory chips can allow more chips to be cut from each wafer, thereby reducing the production cost of small memory chips; small memory chips can also shorten the current path and reduce resistance, so that the power consumption and heat generation of small memory chips are reduced. However, the reduction in the area of ​​​​the memory chip may cause the memory chip to leak storage bits, which in turn causes the failure of the small memory chip. Therefore, it is urgent to solve the problem of storage bit leakage caused by the reduction in the area of ​​​​the memory chip to improve the production qualification rate of small memory chips.

[0003] In the related art, a layer of metal silicide is usually grown between two polysilicon strips of the memory chip to realize the source, drain and gate control current of the memory chip. However, when producing small memory chips based on the related art, the distance between the two polysilicon strips is too small, resulting in the side penetration of the metal silicide grown between the two polysilicon strips, which in turn causes the memory chip to leak storage bits. Summary of the invention

[0004] The purpose of the present application is to provide a method for reducing leakage of a small memory chip, which can achieve the effect of suppressing the lateral penetration of the metal silicide between two polysilicon strands in the memory chip.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect of an embodiment of the present application, a method for reducing leakage of a small memory chip is provided, the method comprising:

[0007] Obtain current leakage data, original leakage data and functional test data corresponding to the chip to be tested;

[0008] Determine whether the leakage point of the chip to be tested is the polysilicon spacing based on the original leakage data, the current leakage data, the pre-established leakage analysis model and the functional test data;

[0009] If yes, determining whether the current growth interval of the metal silicide in the chip to be tested exceeds the calibrated growth interval according to the cross-section measurement result of the chip to be tested;

[0010] If so, the sidewall of the second silicon nitride layer grown outside the native first silicon nitride layer on the control tube of the chip to be detected is thickened, and the etching amount of the second silicon nitride layer is adjusted to obtain a target adjustment result, which includes: silicon nitride thickness parameters and silicon nitride etching amount parameters.

[0011] As a possible implementation method, before obtaining the target adjustment result, it includes:

[0012] Based on a preset sidewall thickening step length and a preset silicon nitride morphology, the sidewall thickening and etching amount of the second silicon nitride grown in addition to the native first silicon nitride on the control tube of the chip to be inspected are adjusted multiple times, and leakage data, polysilicon spacing and functional test data of the chip to be inspected after each adjustment are obtained;

[0013] Determine the verification result corresponding to each chip to be verified according to the leakage data, functional test data and polysilicon spacing of each chip to be verified;

[0014] The target adjustment result is determined according to the verification result corresponding to each chip to be verified.

[0015] As a possible implementation method, the sidewall of the second silicon nitride layer grown outside the native first silicon nitride layer on the control tube of the chip to be detected is thickened, and the etching amount of the second silicon nitride layer is adjusted, including:

[0016] adjusting the thickness of the second silicon nitride layer on the control tube of the chip to be inspected based on a preset sidewall thickening step;

[0017] The etching amount of the second silicon nitride after the sidewall adjustment is adjusted based on the preset silicon nitride morphology.

[0018] As a possible implementation method, according to the verification results corresponding to each chip to be verified, the target adjustment result is determined, including:

[0019] If the polysilicon spacing of the target chip to be verified among the chips to be verified reaches the preset value, and the leakage current in the leakage data of the target chip to be verified reaches the preset threshold, and all test items in the functional test data of the target chip to be verified are qualified, then the target chip to be verified is determined to be the target adjustment result.

[0020] As a possible implementation method, the process of obtaining functional test data includes:

[0021] Perform consistency test on the chip to be tested to obtain functional test data of the chip to be tested.

[0022] As a possible implementation method, according to the original leakage data, the current leakage data, the pre-established leakage analysis model and the functional test data, it is determined whether the leakage point of the chip to be tested is the polysilicon spacing, including:

[0023] Determine the leakage direction of the chip to be detected based on the comparison result between the original leakage data and the current leakage data;

[0024] Determine the leakage source of the chip to be tested based on the current leakage data and the pre-established leakage analysis model;

[0025] Determine the leakage point of the chip to be tested based on the functional test data;

[0026] Determine whether the leakage point of the chip to be tested is the polysilicon pitch.

[0027] As a possible implementation method, the leakage direction of the chip to be detected is determined according to the comparison result between the original leakage data and the current leakage data, including:

[0028] Comparing the gate-to-drain leakage data in the original leakage data with the gate-to-drain leakage data in the current leakage data to obtain a first comparison result;

[0029] Comparing the channel leakage data in the original leakage data with the channel leakage data in the current leakage data to obtain a second comparison result;

[0030] Comparing the junction leakage data in the original leakage data with the junction leakage data in the current leakage data to obtain a third comparison result;

[0031] The leakage direction of the chip to be detected is determined according to the maximum value among the first comparison result, the second comparison result and the third comparison result.

[0032] As a possible implementation method, the leakage source of the chip to be tested is determined based on the current leakage data and the pre-built leakage analysis model, including:

[0033] The current leakage data is input into a pre-built leakage analysis model to obtain the leakage source of the chip to be detected. The pre-built leakage analysis model includes: gate-to-drain leakage analysis item, channel leakage analysis item and junction leakage analysis item.

[0034] As a possible implementation method, the leakage point of the chip to be tested is determined according to the functional test data, including:

[0035] According to the qualified rate corresponding to each test item in the functional test data, the leakage point of the chip to be tested is determined, and the leakage point is calibrated on the wafer where the chip to be tested is located.

[0036] As a possible implementation, determining whether the current growth range of the metal silicide in the chip to be detected exceeds the calibrated growth range according to the profile measurement result of the chip to be detected includes:

[0037] Determine the polysilicon spacing and the current growth interval of the metal silicide in the chip to be tested according to the profile measurement result of the chip to be tested;

[0038] According to the comparison result between the current growth interval and the calibrated growth interval, it is determined whether the current growth interval of the metal silicide in the chip to be detected exceeds the calibrated growth interval.

[0039] The beneficial effects of the embodiments of the present application include:

[0040] The embodiment of the present application provides a method for reducing leakage of a small storage chip. The method comprises obtaining the original leakage data of the chip to be detected on the wafer before the area is reduced and the current leakage data after the area is reduced through a data test structure deployed on the wafer, and pre-building a leakage analysis model; performing a functional test on each chip to be detected after the area is reduced on the wafer to obtain the functional test data of each chip to be detected; determining whether the leakage point of the chip to be detected is the polysilicon spacing according to the original leakage data and the current leakage data of the chip to be detected before and after the area is reduced, the pre-built leakage analysis model and the functional test data; when it is determined that the leakage point of the chip to be detected is the polysilicon spacing, it is necessary to further obtain the leakage point of the chip to be detected. The physical profile of the chip to be tested is obtained, and according to the profile measurement results of the chip to be tested, it is determined whether the polysilicon spacing of the chip to be tested is too close and whether the current growth interval of the metal silicide with a normal polysilicon spacing exceeds the calibrated growth interval; when the polysilicon spacing of the chip to be tested is too close, resulting in the current growth interval of the metal silicide with a normal polysilicon spacing exceeding the calibrated growth interval, the side wall of the second silicon nitride grown outside the native first silicon nitride on the control tube of the chip to be tested is thickened, and the etching amount of the second silicon nitride is adjusted, and the memory chip obtained by each optimization is verified by tape-out to obtain the target adjustment result; the target adjustment result is further tested and verified to obtain the best optimization result. In this way, the effect of suppressing the side penetration of the metal silicide with a normal polysilicon spacing between two polysilicons in the memory chip can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1A flow chart of a first method for reducing leakage of a small memory chip provided in an embodiment of the present application;

[0043] Figure 2 A flow chart of a second method for reducing leakage of a small memory chip provided in an embodiment of the present application;

[0044] Figure 3 A flow chart of a third method for reducing leakage of a small memory chip provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the structure of a memory chip before process optimization provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of a first process-optimized memory chip provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of a second process-optimized memory chip provided in an embodiment of the present application;

[0048] Figure 7 A leakage comparison diagram of a memory chip after process optimization provided in an embodiment of the present application;

[0049] Figure 8 A schematic diagram of the results of a memory chip consistency test provided in an embodiment of the present application;

[0050] Fig. 9 A schematic diagram of another memory chip consistency test result provided in an embodiment of the present application;

[0051] Fig.10 A flowchart of a fourth method for reducing leakage of a small memory chip provided in an embodiment of the present application;

[0052] Fig.11 A comparison diagram of leakage data of a memory chip before and after area reduction provided in an embodiment of the present application;

[0053] Fig.12 A flowchart of a fifth method for reducing leakage of a small memory chip provided in an embodiment of the present application;

[0054] Fig.13 A schematic diagram of the structure of a leakage analysis model for a memory chip provided in an embodiment of the present application;

[0055] Fig.14 A flowchart of a sixth method for reducing leakage of a small memory chip provided in an embodiment of the present application;

[0056] Fig.15 A cross-sectional view of a memory chip provided in an embodiment of the present application;

[0057] Fig.16 A cross-sectional view of another memory chip provided in an embodiment of the present application;

[0058] Fig.17 A schematic diagram of wafer consistency test results after process optimization provided in an embodiment of the present application;

[0059] Fig.18 A complete process flow chart for reducing leakage of a small memory chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and listed in the drawings here can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0062] At present, small memory chips can make more memory chips per wafer, thereby reducing the production cost of small memory chips. Small memory chips can shorten the current path of the internal integrated circuit and reduce resistance, so as to reduce the power consumption and heat generation of small memory chips. Among them, a layer of metal silicide will grow between the two polysilicon of the memory chip to achieve the alignment of the source, drain and gate of the memory chip and enhance the conductivity of the source, drain and gate. However, this solution often has the problem that the distance between the two polysilicon is too small, resulting in the side penetration of the metal silicide grown between the two polysilicon, which in turn causes the memory chip to be too conductive, causing the memory chip to leak storage bits.

[0063] To this end, an embodiment of the present application provides a method for reducing leakage of small storage chips, wherein the original leakage data and current leakage data of each chip to be tested deployed on the wafer are obtained through a data test structure laid out on the wafer, and a leakage analysis model is pre-constructed; a functional test is performed on each chip to be tested to obtain functional test data of each chip to be tested; based on the original leakage data, current leakage data, functional test data of each chip to be tested and the pre-constructed leakage analysis model, it is determined whether the leakage point of the chip to be tested is the polysilicon spacing; if so, the chip to be tested is physically sectioned, and based on the cross-sectional measurement results of the chip to be tested, it is determined whether the metal silicide between the two polysilicon of the storage chip is laterally penetrated; if so, the sidewall of the second silicon nitride grown outside the native first silicon nitride on the control tube of the chip to be tested is thickened, and the etching amount of the second silicon nitride is adjusted, and the adjustment result of the chip to be tested is verified to obtain the target adjustment result, and the target adjustment result is further tested to ensure that the performance of the target mask revision result is stable and reliable. In this way, the effect of suppressing the lateral penetration of the metal silicide between two polysilicon in the memory chip can be achieved.

[0064] The method for reducing leakage of a small memory chip provided by an embodiment of the present application is explained in detail below with reference to the accompanying drawings.

[0065] Figure 1 A flowchart of a method for reducing leakage of a small memory chip provided by this application, see Figure 1 , the embodiment of the present application provides a method for reducing leakage of a small memory chip, comprising:

[0066] S101, obtaining current leakage data, original leakage data and functional test data corresponding to the chip to be tested.

[0067] Optionally, each wafer can be cut into multiple memory chips. When the area of ​​the memory chip is reduced, each wafer can be cut into more memory chips on the original basis, by deploying a data test structure on the wafer, and collecting leakage data of each chip to be tested on the wafer through the data test structure. Among them, the number of data test structures deployed on the wafer is much smaller than the number of memory chips cut on the wafer, that is, one data test structure can collect leakage data of multiple memory chips, and this application does not specifically limit the number of data test structures.

[0068] Optionally, the original leakage data of the original chip corresponding to the chip to be tested and the current leakage data of the chip to be tested are obtained through the data test structure deployed on the wafer. The original leakage data is used to indicate the leakage data generated by the storage chip obtained by initial cutting on the wafer under the action of each detection voltage. The original leakage data includes leakage current, leakage resistance and other leakage data of the original chip; the current leakage data is used to indicate the leakage data generated by the original chip after the area is reduced under the action of each detection voltage. It is worth noting that the present application detects the leakage data of the storage chip before and after the area is reduced by multiple detection voltages, and the leakage voltage range of the storage chip can be checked to ensure the reliability of the small storage chip produced in mass production.

[0069] Optionally, a leakage analysis model is constructed based on the original leakage data of the memory chip obtained by a large number of original cuttings and the leakage data of the memory chip obtained after a large number of area reductions. The leakage analysis model includes multiple leakage analysis items. The current leakage data and the original leakage data of the chip to be tested are input into the leakage analysis model, and the leakage direction and leakage source of the chip to be tested can be obtained.

[0070] Optionally, the functional test can be a CP test, in which a CP test is performed on each chip to be tested, and the points of the chip to be tested are calibrated on the wafer according to the functional test data of the chip to be tested. Among them, the functional test of the chip to be tested includes: voltage test, current test, timing test, storage function test, etc. When the test result corresponding to the functional test data of the chip to be tested is qualified, the chip is calibrated as qualified on the wafer; when the test result corresponding to the functional test data of the chip to be tested is failed or unqualified, the chip is calibrated as unqualified on the wafer. It is worth noting that qualified memory chips and unqualified memory chips can be calibrated by different colors, such as marking unqualified memory chips with red and qualified memory chips with blue, etc. This application does not make specific limitations on this.

[0071] S102, determining whether the leakage point of the chip to be tested is a polysilicon pitch according to the original leakage data, the current leakage data, the pre-established leakage analysis model and the functional test data.

[0072] Optionally, a leakage analysis model is constructed based on the original leakage data of the memory chip obtained by a large number of original cuttings and the leakage data of the memory chip obtained after a large number of area reductions. The leakage analysis model includes multiple leakage analysis items. The current leakage data and the original leakage data of the chip to be tested are input into the leakage analysis model, and the leakage direction and leakage source of the chip to be tested can be obtained.

[0073] Optionally, the leakage point of each chip to be tested and whether the leakage source is the polysilicon spacing are determined based on the original leakage data and current leakage data before and after the area of ​​each chip to be tested is reduced, the pre-built leakage analysis model and the functional test data. The polysilicon spacing is used to indicate the spacing between two polysilicons in the memory chip, and the two polysilicons in the memory chip are used to indicate the two control tubes of the memory chip. When the polysilicon spacing is too close, the metal silicide between the two polysilicons of the memory chip may be lateralized, thereby causing a sudden increase in the conductivity of the memory chip, which makes the memory chip have the risk of storage bit leakage.

[0074] In addition, based on the functional test data of each chip to be tested on the wafer, the production yield of the storage chip obtained by cutting the wafer after the area is reduced is determined. According to the ratio of the number of qualified chips to be tested on the wafer to the number of unqualified chips to be tested on the wafer, the failure rate of the wafer is determined. When the failure rate of the wafer is large and the calibration points of the unqualified chips to be tested on the wafer are in pieces, the chips to be tested on the wafer need to be optimized.

[0075] S103 , if yes, determining whether the current growth range of the metal silicide in the chip to be tested exceeds the calibrated growth range based on the cross-section measurement result of the chip to be tested.

[0076] Optionally, the chip to be tested is physically cut to obtain a cross-sectional schematic diagram of each chip to be tested, and the growth interval of the metal silicide in the cross-sectional schematic diagram is measured, that is, the length, width and other information of the metal silicide are measured, and the distance between two polysilicon of each chip to be tested is measured to obtain the cross-sectional measurement result of the chip to be tested. The cross-sectional measurement result of the chip to be tested is used to indicate the measurement result of the distance between two transistors of the chip to be tested and the growth interval of the metal silicide in the chip to be tested.

[0077] Optionally, the position of the metal silicon oxide grown between two transistors in the chip to be tested can be determined by PFA positioning, and the metal silicon oxide grown in the polysilicon spacing can be measured by a measuring tool to obtain the current growth interval of the metal silicon oxide.

[0078] Optionally, the current growth interval is used to indicate the actual growth range of the metal silicide between the two transistors of the chip to be tested at the current moment, that is, information such as the length and width of the metal silicide between the two transistors of the chip to be tested at the current moment; the calibrated growth interval is used to indicate a safe growth interval in which the metal silicide between the two transistors of the chip to be tested will not cause channel leakage of the chip to be tested, that is, if the actual growth interval of the metal silicide between the two transistors of the chip to be tested at the current moment is within the calibrated growth interval, it is determined that the metal silicide has not undergone side penetration.

[0079] Optionally, based on the profile measurement result of the chip to be tested and the comparison result of the calibrated growth interval, it is determined whether the actual growth interval of the metal silicide between two transistors of the chip to be tested at the current moment exceeds the limit of the calibrated growth interval.

[0080] S104, if yes, then thicken the sidewall of the second silicon nitride layer grown outside the native first silicon nitride layer on the control tube of the chip to be detected, and adjust the etching amount of the second silicon nitride layer to obtain a target adjustment result, the target adjustment result includes: silicon nitride thickness parameter and silicon nitride etching amount parameter.

[0081] Optionally, when the polysilicon spacing in the chip to be tested is too close, and the metal silicide between the two transistors is lateralized, which causes leakage in the chip to be tested, the sidewall of the second silicon nitride grown outside the native first silicon nitride on the control tube of the chip to be tested is thickened, and the etching amount of the second silicon nitride is adjusted to obtain an adjusted chip to be tested, and the storage chip produced after each adjustment is used as the chip to be verified, and the chip to be verified obtained after each adjustment is tape-out verified to obtain a target adjustment result. Among them, the target adjustment result is used to indicate that there is no leakage data in the chip to be tested after the process optimization such as thickening the sidewall of the second silicon nitride and adjusting the etching amount, and the functional test data of the adjusted chip to be tested is qualified.

[0082] Optionally, the first silicon nitride is used to indicate a layer of silicon nitride near the control tube in the memory chip, and the second silicon nitride is used to indicate a layer of silicon nitride grown outside the first silicon nitride. The first silicon nitride and the second silicon nitride can be considered to be separated by a gasket.

[0083] Optionally, the etching amount is used to indicate parameters for adjusting the morphology of the second silicon nitride, the sidewall thickening is used to indicate increasing the thickness of the second silicon nitride, the silicon nitride thickness parameter in the target adjustment result is used to indicate the optimal increased thickness value of the second silicon nitride, and the silicon nitride etching amount parameter in the target adjustment result is used to indicate the optimal morphology parameter of the second silicon nitride.

[0084] Optionally, the target adjustment result is tested and verified to verify whether there is leakage current in the optimized chip to be verified under the action of each detection voltage, and to verify the function of the target adjustment result. When there is no leakage data in the adjusted chip to be verified and all functional test data are qualified, small storage chips can be quantified and produced according to the silicon nitride thickness parameters and silicon nitride etching amount parameters in the target adjustment result.

[0085] In an embodiment of the present application, the original leakage data of the chip to be detected on the wafer before the area is reduced and the current leakage data after the area is reduced are obtained through a data test structure deployed on the wafer, and a leakage analysis model is pre-built; a functional test is performed on each chip to be detected after the area is reduced on the wafer to obtain functional test data of each chip to be detected; based on the original leakage data and current leakage data of the chip to be detected before and after the area is reduced, the pre-built leakage analysis model and the functional test data, it is determined whether the leakage point of the chip to be detected is the polysilicon spacing; when it is determined that the leakage point of the chip to be detected is the polysilicon spacing, it is necessary to further obtain a physical cross-sectional view of the chip to be detected, based on the original leakage data and current leakage data of the chip to be detected before and after the area is reduced, the pre-built leakage analysis model and the functional test data. According to the profile measurement results of the chip to be tested, it is determined whether the polysilicon spacing of the chip to be tested is too close and whether the current growth interval of the metal silicide with a normal polysilicon spacing exceeds the calibrated growth interval; when the polysilicon spacing of the chip to be tested is too close, resulting in the current growth interval of the metal silicide with a normal polysilicon spacing exceeding the calibrated growth interval, the side wall of the second silicon nitride grown outside the native first silicon nitride on the control tube of the chip to be tested is thickened, and the etching amount of the second silicon nitride is adjusted, and the memory chip obtained by each optimization is verified by tape-out to obtain the target adjustment result; the target adjustment result is further tested and verified to obtain the best optimization result. In this way, the effect of suppressing the side penetration of the metal silicide with a normal polysilicon spacing between two polysilicons in the memory chip can be achieved.

[0086] In an optional embodiment, see Figure 2 Before obtaining the target adjustment result in step S104, the method further includes:

[0087] S201, based on a preset sidewall thickening step and a preset silicon nitride morphology, the sidewall thickening and etching amount of the second silicon nitride grown in addition to the native first silicon nitride on the control tube of the chip to be tested are adjusted multiple times, and leakage data, polysilicon spacing and functional test data of the chip to be verified after each adjustment are obtained.

[0088] Optionally, the preset sidewall thickening step is a preset thickness parameter for thickening the sidewall of the second silicon nitride layer in addition to the native first silicon nitride layer on the control tube of the storage chip at one time. For example, if the preset sidewall thickening step is 0.01 mm, it means that the thickness of the second silicon nitride layer is only increased by 0.01 mm to the original thickness at one time.

[0089] Optionally, the preset silicon nitride morphology is a morphology that the second silicon nitride is expected to be etched into, which is preset by the user. The preset silicon nitride morphology may be an arc, a bow, etc., and the present application does not make any specific limitation on this.

[0090] Optionally, the sidewalls of the second silicon nitride other than the native first silicon nitride on the control tube of the chip to be detected are thickened multiple times based on a preset sidewall thickening step, and the morphology of the second silicon nitride is adjusted multiple times based on a preset silicon nitride morphology. After each sidewall thickening and morphology adjustment, a corresponding storage chip will be obtained, which is also the chip to be verified. One chip to be detected corresponds to at least one chip to be verified. For example, the thickness of the second silicon nitride grown other than the native first silicon nitride on the control tube of the chip to be detected A after the area is reduced is 0.3 cm, the current growth interval of the metal silicide between the two transistors in the chip to be detected A is 1.2 cm, the distance between the two transistors in the chip to be detected A is 1 cm, and the chip to be detected after the first sidewall thickening and morphology adjustment is The thickness of the second layer of silicon nitride grown in addition to the native first layer of silicon nitride on the control tube is 0.35 cm, and the growth interval of the metal silicide between the two transistors is 1.1 cm, that is, a chip a to be verified is obtained with a second layer of silicon nitride with a thickness of 0.35 cm and a growth interval of 1.1 cm between the two transistors; the thickness of the second layer of silicon nitride grown in addition to the native first layer of silicon nitride on the control tube of the chip to be tested after the second sidewall thickening and morphology adjustment is 0.50 cm, and the growth interval of the metal silicide between the two transistors is 1.0 cm, that is, a chip b to be verified is obtained with a second layer of silicon nitride with a thickness of 0.50 cm and a growth interval of 1.0 cm between the two transistors, etc.

[0091] Optionally, leakage data of the chip to be verified after each sidewall thickening and morphology adjustment is obtained through a data test structure deployed on the wafer, and a consistency test is performed on the chip to be tested after each sidewall thickening and morphology adjustment to obtain functional test data of the chip to be verified after each sidewall thickening and morphology adjustment.

[0092] Optionally, the polysilicon pitch is used to indicate the distance between two control tubes in the memory chip, and the polysilicon pitch of the chip to be tested after each adjustment is obtained through a data test structure deployed on the wafer.

[0093] S202 , determining a verification result corresponding to each chip to be verified according to leakage data, functional test data, and polysilicon spacing of each chip to be verified.

[0094] Optionally, the leakage data of each chip to be verified is input into a pre-built leakage analysis model for leakage analysis, and the performance of each chip to be verified is determined based on the functional test data of each chip to be verified, and the polysilicon spacing is determined based on the cross-sectional measurement results of each chip to be verified, and then it is determined whether the metal silicide between the two transistors is laterally penetrated, and the verification results corresponding to each chip to be verified are obtained based on the leakage data analysis results and the functional test data analysis results of each chip to be verified.

[0095] S203: Determine a target adjustment result according to the verification result corresponding to each chip to be verified.

[0096] Optionally, from the tape-out verification results corresponding to the multiple chips to be verified obtained after the chips to be verified have been subjected to multiple sidewall thickening and the etching amount has been adjusted, a chip to be verified with the best optimization effect is selected as the target adjustment result corresponding to the chip to be verified. The target adjustment result is used to indicate that after the optimization of the chip to be verified, there is no metal silicide lateral penetration between two transistors, which causes the memory chip to have storage bit leakage and function loss.

[0097] For a possible implementation, see Figure 3 In step S104, the specific operation of thickening the sidewall of the second silicon nitride layer grown outside the native first silicon nitride layer on the control tube of the chip to be detected and adjusting the etching amount of the second silicon nitride layer may be:

[0098] S301 , adjusting the thickness of the second silicon nitride layer on the control tube of the chip to be inspected based on a preset sidewall thickening step.

[0099] Optionally, the thickness of the second layer of silicon nitride in addition to the native first layer of silicon nitride on the control tube of the chip to be tested is adjusted based on a preset sidewall thickening step, and the thickness of the second layer of silicon nitride is iteratively adjusted in sequence, so that the problem of metal silicide lateral penetration will no longer occur in the storage chip even when the distance between two polysilicon layers is too small.

[0100] S302, adjusting the etching amount of the second silicon nitride after the sidewall adjustment based on the preset silicon nitride morphology.

[0101] Optionally, the etching amount of the second silicon nitride layer after the thickness is adjusted is adjusted based on the preset silicon nitride morphology, so that the second silicon nitride layer maintains a certain aesthetic appearance under the premise of controlling the lateral penetration of metal silicide.

[0102] Figure 4 This is a schematic diagram of the structure of a memory chip before process optimization provided in this application, see Figure 4 In the memory chip provided in the embodiment of the present application, a layer of metal silicide is generally grown between two polysilicon layers.

[0103] Figure 5 The schematic diagram of the structure of the first process-optimized memory chip provided in this application is shown in FIG. Figure 5 In the embodiment of the present application, the thickness and etching profile of the second silicon nitride layer are adjusted to reduce the growth range of the metal silicide.

[0104] Figure 6The schematic diagram of the structure of the second process optimized memory chip provided in this application is shown in FIG. Figure 6 In the embodiment of the present application, by adjusting the thickness of the second silicon nitride layer to a certain extent, the growth of metal silicide between two crystalline silicon can be completely suppressed.

[0105] In an optional implementation manner, the operation of step S203 may specifically be:

[0106] If the polysilicon spacing of the target chip to be verified among the chips to be verified reaches the preset value, and the leakage current in the leakage data of the target chip to be verified reaches the preset threshold, and all test items in the functional test data of the target chip to be verified are qualified, then the target chip to be verified is determined to be the target adjustment result.

[0107] Optionally, the preset threshold is a current threshold pre-set by the user, and the preset threshold is used to indicate the leakage current limit of the chip to be detected. When the leakage current in the leakage data of the chip to be detected reaches the preset threshold, it is assumed that there is no leakage current in the chip to be detected. The preset threshold can be 0A, 0.01mA, etc., and this application does not make any specific limitations on this.

[0108] Optionally, the preset value is a crystalline silicon spacing limit pre-set by the user. When the second silicon nitride sidewall grown in addition to the native first silicon nitride on the control tube of the chip to be tested is thickened and adjusted, the spacing between the two transistors in the chip to be tested reaches the preset value. It is assumed that the metal silicon oxide between the two transistors of the chip to be tested will not lateral penetrate, thereby causing leakage. The preset value may be 0.5 mm, etc., and the present application does not make any specific limitation on this.

[0109] Optionally, the target chip to be verified is used to indicate the chip to be verified with the best leakage control effect among multiple chips to be verified, which is obtained by multiple sidewall thickening and multiple morphology adjustment optimizations of the second silicon nitride grown on the native first silicon nitride on the control tube of the chip to be tested. One chip to be tested corresponds to at least one chip to be verified. Similarly, one chip to be verified has at least one target chip to be verified with the best leakage control effect.

[0110] Optionally, when the leakage current in the leakage data of the target chip to be verified among the multiple chips to be verified obtained by multiple sidewall thickening and multiple morphology adjustment optimization of the chip to be verified reaches a preset threshold, and the polysilicon spacing of the target chip to be verified meets the preset value, and all test items in the functional test data of the target chip to be verified are qualified, that is, the target chip to be verified has no leakage current, and the voltage detection results, current detection results, timing detection results and functional detection results of the target chip to be verified are all qualified, and there is no metal silicide side penetration in the polysilicon spacing in the target chip to be verified, then the target chip to be verified is used as the target adjustment result of the chip to be verified.

[0111] Figure 7 A leakage comparison diagram of a memory chip after process optimization provided by this application, see Figure 7 The leakage data of the memory chip before and after the mask optimization provided in the embodiment of the present application is significantly reduced.

[0112] In an optional implementation, the process of obtaining functional test data includes:

[0113] Perform consistency test on the chip to be tested to obtain functional test data of the chip to be tested.

[0114] Optionally, a consistency test is performed on the chip to be tested on the wafer to obtain functional test data such as current test results, voltage test results, timing test results, and various functional test data of the chip to be tested.

[0115] Figure 8 A schematic diagram of the results of a memory chip consistency test provided in this application, see Figure 8 , the qualified rate of the chips to be tested distributed on the edge of the wafer is low.

[0116] Fig. 9 Another schematic diagram of the results of the memory chip consistency test provided by this application is shown in FIG. Fig. 9 , the qualified rate of the chips to be tested distributed in the lower right middle area of ​​the wafer is low.

[0117] In an optional embodiment, see Fig.10 The operation of step S102 may specifically be:

[0118] S1001. Determine the leakage direction of the chip to be detected based on the comparison result between the original leakage data and the current leakage data.

[0119] Optionally, based on the comparison result of the leakage current in the original leakage data with the leakage current in the current leakage data, the leakage direction of the chip to be detected can be determined, that is, the leakage current that is significantly increased relative to the original leakage current is taken as the leakage direction of the chip to be detected, that is, the leakage of the chip to be detected becomes more serious.

[0120] It is worth noting that the current leakage data of each detection chip is compared with the original leakage data of the detection chip, and the comparison of the leakage data is based on the comparison of the leakage data under the same detection voltage.

[0121] S1002: Determine the leakage source of the chip to be detected based on the current leakage data and a pre-established leakage analysis model.

[0122] Optionally, the current leakage data of the chip to be detected is input into a pre-built leakage analysis model to determine the leakage source of the chip to be detected. The leakage source of the chip to be detected can be gate-to-drain leakage, channel leakage caused by metal silicide side penetration, or junction leakage, which is not specifically limited in this application. It is worth noting that the leakage source is used to indicate the factor or trigger that causes the leakage of the chip to be detected after being reduced.

[0123] S1003. Determine the leakage point of the chip to be tested according to the functional test data.

[0124] Optionally, the leakage point is used to indicate the physical position of the chip to be tested on the wafer. According to the functional test data of each chip to be tested, the test pass or fail of each chip to be tested is calibrated on the wafer. According to the calibration results of each chip to be tested on the wafer, the leakage point of the chip to be tested is determined.

[0125] S1004, determining whether the leakage point of the chip to be detected is the polysilicon pitch.

[0126] Optionally, according to the leakage points of each chip to be detected calibrated on the wafer, it is determined whether the leakage points of each chip to be detected are at the polysilicon pitch.

[0127] Fig.11 For the comparison of leakage data of memory chips before and after area reduction provided by this application, see Fig.11 ,According to the comparison of leakage data before and after the storage chip area is reduced, ,it can be determined that the current leakage data of the chip to be tested is significantly ,increased compared to the original leakage data.

[0128] In an optional embodiment, see Fig.12 The operation of step S1001 may specifically be:

[0129] S1201. Compare gate-to-drain leakage data in original leakage data with gate-to-drain leakage data in current leakage data to obtain a first comparison result.

[0130] Optionally, the gate-to-drain leakage data is used to indicate leakage data caused by drain leakage caused by the gate in the chip to be detected, and the gate-to-drain leakage data in the current leakage data of the chip to be detected is compared with the gate-to-drain leakage data in the original leakage data of the original chip corresponding to the chip to be detected to determine whether the gate-to-drain leakage data in the current leakage data of the chip to be detected increases after the area is reduced.

[0131] S1202: Compare the channel leakage data in the original leakage data with the channel leakage data in the current leakage data to obtain a second comparison result.

[0132] Optionally, the channel leakage data is used to indicate the leakage data generated by the metal silicide side-penetrating the polysilicon in the chip to be tested, and the channel leakage data in the current leakage data of the chip to be tested is compared with the channel leakage data in the original leakage data of the original chip corresponding to the chip to be tested to determine whether the channel leakage data in the current leakage data of the chip to be tested increases after the area is reduced.

[0133] S1203 . Compare the junction leakage data in the original leakage data with the junction leakage data in the current leakage data to obtain a third comparison result.

[0134] Optionally, the junction leakage data is used to indicate the leakage data generated by PN junction leakage in the chip to be detected, and the junction leakage data in the current leakage data of the chip to be detected is compared with the junction leakage data in the original leakage data of the original chip corresponding to the chip to be detected to determine whether the junction leakage data in the current leakage data of the chip to be detected increases after the area is reduced.

[0135] S1204 , determining the leakage direction of the chip to be detected according to the maximum value among the first comparison result, the second comparison result and the third comparison result.

[0136] In an optional implementation manner, the operation of step S1002 may specifically be:

[0137] The current leakage data is input into a pre-built leakage analysis model to obtain the leakage source of the chip to be detected. The pre-built leakage analysis model includes: gate-to-drain leakage analysis item, channel leakage analysis item and junction leakage analysis item.

[0138] Optionally, the current leakage data of the chip to be detected is input into a pre-built leakage analysis model, so that the specific cause of the leakage data of the chip to be detected can be determined. The pre-built leakage analysis model includes: gate-to-drain leakage analysis item, channel leakage analysis item and junction leakage analysis item. The gate-to-drain leakage analysis item is used to analyze the gate-to-drain leakage data of the chip to be detected, the channel leakage analysis item is used to analyze the channel leakage data of the chip to be detected, the junction leakage analysis item is used to analyze the junction leakage data of the chip to be detected, the gate-to-drain leakage analysis item has the characteristics of the gate of the memory chip causing the drain leakage, the channel leakage analysis item has the characteristics of the metal silicide side penetration of the memory chip causing the leakage, and the junction leakage analysis item has the characteristics of the PN junction of the memory chip causing the memory chip leakage.

[0139] In an optional implementation manner, the operation of step S1003 may specifically be:

[0140] According to the qualified rate corresponding to each test item in the functional test data, the leakage point of the chip to be tested is determined, and the leakage point is calibrated on the wafer where the chip to be tested is located.

[0141] Optionally, each chip to be tested is calibrated on the wafer according to the test results of each test item in the functional test data of the chip to be tested. Only when all test items in the functional test data of the chip to be tested are qualified, can the chip to be tested be calibrated as a qualified storage chip on the wafer.

[0142] Optionally, the chip to be detected is calibrated on the wafer where the chip to be detected is located according to the functional test data or CP test result of the chip to be detected.

[0143] Fig.13 The schematic diagram of the leakage analysis model of the memory chip provided in this application is shown in FIG. Fig.13 According to the leakage current between transistor SG and transistor CG, it is determined that the polysilicon spacing of the chip to be tested is too close, and the metal silicide in the polysilicon spacing is laterally penetrated, causing the chip to be tested to generate leakage data.

[0144] In an optional embodiment, see Fig.14 The operation of step S103 may specifically be:

[0145] S1401. Determine the polysilicon spacing and the current growth range of metal silicide in the chip to be detected according to the cross-section measurement result of the chip to be detected.

[0146] Optionally, the cross-section of the chip to be inspected is measured by means of a measuring tool to obtain the interval between two transistors in the chip to be inspected and the current growth interval of the metal silicide between the two transistors in the chip to be inspected.

[0147] S1402. Determine whether the current growth interval of the metal silicide in the chip to be tested exceeds the calibrated growth interval based on the comparison result between the current growth interval and the calibrated growth interval.

[0148] Optionally, based on the size comparison and position area comparison between the current growth interval and the calibrated growth interval, it can be determined whether the current growth interval of the metal silicide between two transistors in the chip to be tested exceeds the calibrated growth interval, that is, whether the metal silicide between the two transistors is side-penetrated.

[0149] Fig.15 A cross-sectional view of a memory chip provided in this application, see Fig.15 The current growth range of the metal silicide in the distance between two polysilicon wires of the memory chip provided in the embodiment of the present application does not exceed the calibrated growth range, that is, although the polysilicon distance of the memory chip after the area reduction is too close, the metal silicide lateral penetration does not occur.

[0150] Fig.16For a cross-sectional view of another memory chip provided in this application, see Fig.16 The current growth range of the metal silicide generally grown in the distance between two polysilicon wires of the memory chip provided in the embodiment of the present application exceeds the calibrated growth range, that is, the polysilicon distance of the memory chip after the area reduction is too close, and the metal silicide generally grown in the distance between the polysilicon wires penetrates sideways.

[0151] Fig.17 A schematic diagram of wafer consistency test results after process optimization provided in this application, see Fig.17 In the embodiment of the present application, after optimizing the second silicon nitride layer other than the native first silicon nitride layer on the control tube of the chip to be tested on the wafer, the failure rate of the chip to be tested on the wafer is significantly reduced.

[0152] Fig.18 A complete process flow chart for reducing leakage of small memory chips provided in the embodiment of the present application. The specific manufacturing process for reducing leakage of small memory chips provided in the embodiment of the present application is as follows: construct a leakage analysis model based on the leakage data of a large number of memory chips before and after the area is reduced; perform CP test on the memory chips after the area is reduced to obtain the consistency test results of the memory chips after the area is reduced, and determine the wafer yield based on the functional test data of each memory chip after the area is reduced on the wafer; perform physical sectioning on the memory chips after the area is reduced to obtain the cross-sectional structure diagram of the memory chips after the area is reduced, and measure the cross-sectional diagram of the memory chips with the help of measuring tools to obtain the polysilicon spacing in the memory chips after the area is reduced and the current growth interval of the metal silicide of the general length in the polysilicon spacing; determine whether the memory chips after the area is reduced meet the conditions for sidewall thickening optimization based on the leakage data of the memory chips before and after the area is reduced, the pre-constructed leakage analysis model, the cross-sectional measurement results and the functional test data; and perform SACER process optimization on the chip to be tested after the conditions are met, and test and verify the optimized tape-out to obtain the target adjustment result.

[0153] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0154] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reducing leakage of a small memory chip, characterized in that: The method comprises: Obtain current leakage data, original leakage data and functional test data corresponding to the chip to be tested; Determine whether the leakage point of the chip to be tested is a polysilicon pitch according to the original leakage data, the current leakage data, a pre-established leakage analysis model and the functional test data; If yes, determining whether the current growth interval of the metal silicide in the chip to be detected exceeds the calibrated growth interval according to the cross-section measurement result of the chip to be detected; If so, the sidewall of the second silicon nitride grown outside the native first silicon nitride on the control tube of the chip to be tested is thickened, and the etching amount of the second silicon nitride is adjusted to obtain a target adjustment result, wherein the target adjustment result includes: silicon nitride thickness parameters and silicon nitride etching amount parameters.

2. The method for reducing leakage of a small memory chip according to claim 1, characterized in that: Before obtaining the target adjustment result, the method includes: Based on a preset sidewall thickening step length and a preset silicon nitride morphology, the sidewall thickening and etching amount of the second silicon nitride grown in addition to the native first silicon nitride on the control tube of the chip to be inspected are adjusted multiple times, and leakage data, polysilicon spacing and functional test data of the chip to be inspected after each adjustment are obtained; Determine the verification result corresponding to each chip to be verified according to the leakage data, functional test data and polysilicon spacing of each chip to be verified; A target adjustment result is determined according to the verification results corresponding to each of the chips to be verified.

3. The method for reducing leakage of a small memory chip according to claim 1, characterized in that: The step of thickening the sidewall of a second silicon nitride layer grown outside the native first silicon nitride layer on the control tube of the chip to be tested, and adjusting the etching amount of the second silicon nitride layer, comprises: adjusting the thickness of the second silicon nitride layer on the control tube of the chip to be inspected based on a preset sidewall thickening step; The etching amount of the second silicon nitride after the sidewall adjustment is adjusted based on the preset silicon nitride morphology.

4. The method for reducing leakage of a small memory chip according to claim 2, characterized in that: The step of determining the target adjustment result according to the verification result corresponding to each of the chips to be verified includes: If the polysilicon spacing of the target chip to be verified among the chips to be verified reaches a preset value, and the leakage current in the leakage data of the target chip to be verified reaches a preset threshold, and all test items in the functional test data of the target chip to be verified are qualified, then the target chip to be verified is determined to be the target adjustment result.

5. The method for reducing leakage of a small memory chip according to claim 1, characterized in that: The process of obtaining the functional test data includes: A consistency test is performed on the chip to be tested to obtain functional test data of the chip to be tested.

6. The method for reducing leakage of a small memory chip according to claim 1, characterized in that: The determining whether the leakage point of the chip to be tested is a polysilicon pitch according to the original leakage data, the current leakage data, a pre-established leakage analysis model and the functional test data comprises: Determining the leakage direction of the chip to be detected according to a comparison result between the original leakage data and the current leakage data; Determining the leakage source of the chip to be detected according to the current leakage data and a pre-established leakage analysis model; Determining the leakage point of the chip to be tested according to the functional test data; Determine whether the leakage point of the chip to be detected is the polysilicon pitch.

7. The method for reducing leakage of a small memory chip according to claim 6, characterized in that: The step of determining the leakage direction of the chip to be detected according to the comparison result between the original leakage data and the current leakage data includes: Comparing the gate-to-drain leakage data in the original leakage data with the gate-to-drain leakage data in the current leakage data to obtain a first comparison result; Comparing the channel leakage data in the original leakage data with the channel leakage data in the current leakage data to obtain a second comparison result; Comparing the junction leakage data in the original leakage data with the junction leakage data in the current leakage data to obtain a third comparison result; The leakage direction of the chip to be detected is determined according to a maximum value among the first comparison result, the second comparison result and the third comparison result.

8. The method for reducing leakage of a small memory chip according to claim 6, characterized in that: Determining the leakage source of the chip to be detected according to the current leakage data and a pre-built leakage analysis model includes: The current leakage data is input into a pre-built leakage analysis model to obtain the leakage source of the chip to be detected. The pre-built leakage analysis model includes: a gate-induced drain leakage analysis item, a channel leakage analysis item, and a junction leakage analysis item.

9. The method for reducing leakage of a small memory chip according to claim 6, characterized in that: Determining the leakage point of the chip to be tested according to the functional test data includes: According to the qualified rate corresponding to each test item in the functional test data, the leakage point of the chip to be tested is determined, and the leakage point is calibrated on the wafer where the chip to be tested is located.

10. The method for reducing leakage of a small memory chip according to claim 1, characterized in that: The step of determining whether the current growth interval of the metal silicide in the chip to be detected exceeds the calibrated growth interval according to the cross-section measurement result of the chip to be detected includes: Determining the polysilicon spacing and the current growth interval of metal silicide in the chip to be detected according to the cross-section measurement result of the chip to be detected; According to the comparison result between the current growth interval and the calibrated growth interval, it is determined whether the current growth interval of the metal silicide in the chip to be detected exceeds the calibrated growth interval.

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