Flip packaging method based on chip-level hybrid bonding

Abstract

The invention discloses a flip-chip packaging method based on chip-level hybrid bonding. The flip-chip packaging method comprises the following steps: preparing a chip wafer and a carrier wafer, firstly preparing a SiN barrier layer on the surface, then respectively preparing a chip dielectric layer and a carrier dielectric layer which are made of SiO2 materials, respectively preparing a chip metal layer and a carrier metal layer, and carrying out chemical mechanical grinding treatment on the chip wafer and the carrier wafer; performing laser invisible cutting on the chip wafer to obtain single chips; carrying out plasma cleaning and formic acid steam activating treatment on the bonding surface of the chip and the carrier wafer; picking up a chip for multiple times by using a thermocompression welding machine, and placing the chip on a carrier plate wafer for thermocompression pre-bonding after optical alignment; and moving the carrier plate wafer on which the chip is pre-bonded to a muffle furnace for annealing to form a metal bond and finish final bonding. According to the method, the mold opening cost of the hybrid bonding photoetching plate is reduced, and multiplexing and recombination of a mature module in hybrid bonding are allowed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a flip-chip packaging method based on chip-level hybrid bonding. Background Art

[0002] The interconnection and lead-out of integrated circuit electrical signals are usually carried out by welding pin plugs, leads, flat pins, solder balls, solder columns, etc. with holes, bonding fingers, and pads on stacked chips, adapters, substrates or PCB boards, resulting in packaging forms such as direct insertion, surface mount, and ball / column grid array.

[0003] After the 1990s, the flip-chip soldering process based on ball / column grid array has gradually become a high-density welding process in the integrated circuit packaging industry. This process covers the entire two-dimensional surface of the circuit with solder balls or solder columns containing components such as lead (Pb), tin (Sn), silver (Ag), copper (Cu), etc., and interconnects the chip, adapter board, substrate or PCB pads through reflow or hot pressing to complete the melting, infiltration and solidification of the solder. This process can be combined with advanced processes such as screen printing, wafer-level rewiring, and high-density substrates to achieve high-efficiency packaging, providing more possibilities for 2.5D and 3D packaging forms.

[0004] However, due to the preparation process limitations of solder balls and solder pillars, the minimum diameter of the ball and pillar planting process based on the ball / pillar grid array can only reach about 100μm. The minimum diameter of the electroplated solder balls or solder pillars in the wafer-level packaging technology can only reach about 20μm. Smaller sizes will cause more process quality and reliability problems, such as poor coplanarity, cold soldering, bridging, and shedding. As Moore's Law gradually approaches the physical limit, reducing the size of transistor gates has become an industry bottleneck. The extremely high process cost caused by this has limited the development of integrated circuit integration. Breaking through the interconnection density in the packaging field has become a must. More and more packaging design solutions have put forward urgent demands for interface interconnection processes below 10μm. In addition, common solder components in the industry include SnPb, SnAgCu, SnAg, etc. During the welding process, solder joint voids will be generated due to incomplete volatilization of the flux, changes in remelting volume, and component impurities, thereby causing reliability failure problems. Therefore, it is urgent to develop an interconnection interface packaging method that is suitable for extremely small sizes, not prone to voids, and has high reliability.

[0005] Hybrid bonding is a new bonding technology that has emerged in recent years. It uses Damascus wiring process to complete the bonding of Cu as metal and SiO2 as 2 ) as the bonding interface of the dielectric material, the size of the bump-free pad used for interconnection can be as small as sub-micron level, and then the interface roughness is polished to an extremely low level by high-precision chemical mechanical polishing (CMP). Direct permanent bonding without solder is achieved through alignment, hot pressing, annealing and other processes. Cu, SiO2 The principle of bonding between materials is to generate Van der Waals force. Since this technology has extremely high requirements for surface roughness, any contamination will destroy the state of Van der Waals force generation. Therefore, wafer-to-wafer bonding (W2W) is currently widely used. Slicing, which is very easy to produce silicon slag sputtering, is usually performed after bonding. However, this process route greatly limits the flexibility of bonding. The various chips in the package must be fully assembled during the wafer processing stage. If the chips are manufactured with different processes (such as silicon, gallium arsenide, gallium nitride, etc.), they cannot coexist on the same wafer, and bonding cannot be completed using this process. There is an urgent need to develop a more flexible hybrid bonding flip-chip packaging method. Summary of the invention

[0006] The object of the present invention is to provide a flip chip packaging method based on chip-level hybrid bonding to solve the problems in the background technology.

[0007] In order to solve the above technical problems, the present invention provides a flip-chip packaging method based on chip-level hybrid bonding, comprising the following steps:

[0008] Step S11, prepare chip wafer and carrier wafer, first prepare SiN barrier layer on the surface, and then prepare SiO 2 A chip dielectric layer and a substrate dielectric layer of a material are prepared to form a chip metal layer and a substrate metal layer respectively;

[0009] Step S12, performing high-precision chemical mechanical polishing on the chip wafer and the carrier wafer;

[0010] Step S13, laser invisible cutting the chip wafer into individual chips, and the carrier wafer remains in wafer form without cutting;

[0011] Step S14, performing plasma cleaning and formic acid vapor activation treatment on the bonding surfaces of the chip and the carrier wafer;

[0012] Step S15, using a high-precision hot-pressing welding machine to pick up the chips multiple times, and placing them on the carrier wafer for hot-pressing pre-bonding after optical alignment;

[0013] Step S16, move the carrier wafer with the pre-bonded chip to a muffle furnace for annealing. The high-strength covalent bond between the chip dielectric layer and the carrier dielectric layer provides tensile stress, and the chip metal layer and the carrier metal layer expand to produce compressive stress. Under the high temperature and expansion and extrusion environment, copper atoms diffuse to form metal bonds, completing the final bonding.

[0014] In one embodiment, the steps of preparing the chip metal layer and the carrier metal layer include: using photoresist coating, photolithography, SiO 2Through the processes of etching, wet stripping, magnetron sputtering of Ti / Cu seed layer and electroplating, a chip metal layer made of Cu material is prepared on the chip wafer, and a carrier metal layer made of Cu material is prepared on the carrier wafer. The chip metal layer covers the entire chip wafer, and the carrier metal layer covers the entire carrier wafer.

[0015] In one embodiment, in step S12, the standard for completing the high-precision chemical mechanical polishing process is: the root mean square roughness in a 1 μm×1 μm area is ≤ 0.5 nm, and both the chip metal layer and the carrier metal layer form a 2 μm pad recess.

[0016] In one embodiment, the laser invisible cutting of the chip wafer in step S13 includes: using an expanded dicing film to cover the chip dielectric layer and the chip metal layer for surface protection, using a laser to break the Si-Si covalent bonds of the chip wafer, completing the separation of individual chips by expanding the film, and transporting them to a plasma cleaning machine after cutting is completed.

[0017] In one embodiment, during the plasma cleaning and formic acid vapor activation treatment in step S14, a gas flow rate of 200 sccm (0.2 L / min) of H 2 / N 2 Atmosphere, vacuum degree 18.1Pa, power 400W, activation time 10min, after processing, it is transferred to a high-precision hot pressing welding machine.

[0018] In one embodiment, a 50% concentration of formic acid vapor atmosphere is always maintained inside the hot pressure welding machine, and the optical alignment deviation of the equipment is less than ±500nm. After the alignment is completed, a pressure of 2.5MPa is applied to make the interface of the chip dielectric layer and the carrier dielectric layer contact each other, and the chip and the carrier wafer are heated to 100-200°C at a heating rate of 20°C / min, and kept warm for 30 minutes to complete the pre-bonding between the chip dielectric layer and the carrier dielectric layer interface.

[0019] In one embodiment, the annealing conditions in step S16 are: heating rate of 10° C. / min, reaching 300-450° C., keeping warm for 2 hours, and cooling naturally.

[0020] In one embodiment, the chip wafer and the carrier wafer are made of Si, and the thickness of the chip dielectric layer and the carrier dielectric layer are both 300 nm.

[0021] The present invention provides a flip-chip packaging method based on chip-level hybrid bonding. Through a lossless dicing process, the chip wafer is pre-cut into independent chips, and then the chip is welded to a wafer carrier (C2W) or a chip to a single carrier (C2C). This breaks through the conventional W2W form of hybrid bonding, while still retaining the high-density and high-reliability characteristics of the hybrid bonding process, laying the foundation for the heterogeneous and heterogeneous flexibility of core-grain integration, reducing the mold opening cost of the hybrid bonding lithography board, and allowing the reuse and reorganization of mature modules in hybrid bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a flow chart of a flip chip packaging method based on chip-level hybrid bonding;

[0023] Figure 2 It is a schematic diagram of the Damascus wiring structure on the surface of the chip wafer and the carrier wafer;

[0024] Figure 3 It is a schematic diagram of the structure of the chip wafer and the carrier wafer after CMP;

[0025] Figure 4 It is a schematic diagram of the structure of the chip and carrier wafer cut without damage;

[0026] Figure 5 This is a schematic diagram of the structure after multi-chip high-precision pre-bonding

[0027] Figure 6 It is a schematic diagram of the structure after annealing.

[0028] Explanation of the reference numerals: 101 - chip wafer, 102 - carrier wafer, 103 - chip dielectric layer, 104 - carrier dielectric layer, 105 - chip metal layer, 106 - carrier metal layer, 301 - single chip after cutting. DETAILED DESCRIPTION

[0029] The following is a further detailed description of a flip-chip packaging method based on chip-level hybrid bonding proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] The present invention provides a flip chip packaging method based on chip-level hybrid bonding, the process flow is as follows: Figure 1 As shown, the following steps are included:

[0031] Step S11, as Figure 2As shown in the figure, a 12-inch chip wafer 101 and a carrier wafer 102 are prepared, and the surface is processed into a bonding structure using a Damascus process. Both wafers are made of Si material, and a SiN barrier layer (not shown in the figure) is prepared on the surface of the two wafers using plasma enhanced chemical vapor deposition (PECVD), and then SiO 2 The chip dielectric layer 103 and the carrier dielectric layer 104 are made of a material, and the thickness of both dielectric layers is 300nm. 2 The chip metal layer 105 and the carrier metal layer 106 made of Cu are prepared through the processes of etching, wet stripping, magnetron sputtering of Ti / Cu seed layer, and electroplating. Both metal layers cover the entire wafer, and the opening diameter of the etched area is 3 μm.

[0032] Step S12, as Figure 3 As shown, the chip wafer 101 and the carrier wafer 102 are subjected to high-precision CMP processing to make the root mean square roughness in the 1 μm×1 μm area ≤ 0.5 nm, and at the same time, a 2 μm Cu pad recess is formed.

[0033] Step S13, as Figure 4 As shown, the chip wafer 101 is cut into individual chips 301 by laser stealth cutting, and the carrier wafer 102 is kept in wafer form without cutting. During the cutting process, an expanded dicing film is used to cover the chip dielectric layer 103 and the chip metal layer 105 for further surface protection, and the Si-Si covalent bond of the chip wafer 101 is broken by laser, and the individual chips 301 are separated by expanding the film. The cutting process is completed within 2 hours and quickly transported to the plasma cleaning machine.

[0034] Step S14: Plasma cleaning and formic acid vapor activation treatment are performed on the bonding surfaces of the chip 301 and the carrier wafer 102. During the plasma activation, a gas flow rate of 200 sccm (0.2 L / min) of H 2 / N 2 Atmosphere, vacuum degree 18.1Pa, power 400W, activation time 10min. Quickly transfer to high-precision hot press welding machine.

[0035] Step S15, as Figure 5 As shown, a high-precision hot press welder is used to pick up the chip 301 multiple times, and after optical alignment, it is placed on the carrier wafer 102 for hot press pre-bonding. The hot press welder always maintains a 50% concentration of formic acid vapor atmosphere, and the optical alignment deviation of the equipment is less than ±500nm. After the alignment is completed, a pressure of 2.5MPa is applied to make the interface of the chip dielectric layer 103 and the carrier dielectric layer 104 contact. The chip 301 and the carrier wafer 102 are heated to 200°C at a heating rate of 20°C / min, and kept warm for 30 minutes to complete the pre-bonding between the chip dielectric layer 103 and the carrier dielectric layer 104 interface.

[0036] Step S16, Figure 6 As shown, the carrier wafer 102 with the pre-bonded chip 301 is moved to a muffle furnace for annealing, with a heating rate of 10°C / min, reaching 400°C, and kept at this temperature for 2 hours, followed by natural cooling. The high-strength covalent bond between the chip dielectric layer 103 and the carrier dielectric layer 104 provides tensile stress, and the chip metal layer 105 and the carrier metal layer 106 expand to generate compressive stress. Under the high temperature and expansion and extrusion environment, copper atoms diffuse to form metal bonds, completing the final bonding.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A flip chip packaging method based on chip-level hybrid bonding, characterized in that: The steps include: Step S11, prepare a chip wafer and a carrier wafer, first prepare a SiN barrier layer on the surface, then prepare a chip dielectric layer and a carrier dielectric layer made of SiO2, and then prepare a chip metal layer and a carrier metal layer; Step S12, performing high-precision chemical mechanical polishing on the chip wafer and the carrier wafer; Step S13, laser invisible cutting the chip wafer into individual chips, and the carrier wafer remains in wafer form without cutting; Step S14, performing plasma cleaning and formic acid vapor activation treatment on the bonding surfaces of the chip and the carrier wafer; Step S15, using a high-precision hot-pressing welding machine to pick up the chips multiple times, and placing them on the carrier wafer for hot-pressing pre-bonding after optical alignment; Step S16, move the carrier wafer with the pre-bonded chip to a muffle furnace for annealing. The high-strength covalent bond between the chip dielectric layer and the carrier dielectric layer provides tensile stress, and the chip metal layer and the carrier metal layer expand to produce compressive stress. Under the high temperature and expansion and extrusion environment, copper atoms diffuse to form metal bonds, completing the final bonding.

2. The flip chip packaging method based on chip-level hybrid bonding according to claim 2, characterized in that: The steps of preparing the chip metal layer and the carrier metal layer separately include: using photoresist coating, photolithography, SiO2 etching, wet stripping, Ti / Cu material seed layer magnetron sputtering, and electroplating to prepare a chip metal layer of Cu material on the chip wafer, and prepare a carrier metal layer of Cu material on the carrier wafer, the chip metal layer covers the entire chip wafer, and the carrier metal layer covers the entire carrier wafer.

3. The flip chip packaging method based on chip-level hybrid bonding according to claim 1, characterized in that: In step S12, the standard for completing the high-precision chemical mechanical polishing process is: the root mean square roughness in a 1 μm×1 μm area is ≤ 0.5 nm, and a 2 μm pad depression is formed on both the chip metal layer and the carrier metal layer.

4. The flip chip packaging method based on chip-level hybrid bonding according to claim 1, characterized in that: The step S13 of performing invisible laser cutting on the chip wafer includes: using an expanded dicing film to cover the chip dielectric layer and the chip metal layer for surface protection, using a laser to break the Si-Si covalent bonds of the chip wafer, completing the separation of individual chips by expanding the film, and transferring to a plasma cleaning machine after cutting.

5. The flip chip packaging method based on chip-level hybrid bonding according to claim 1, characterized in that: In the plasma cleaning and formic acid vapor activation treatment of step S14, a H2 / N2 atmosphere with a gas flow rate of 200 sccm (0.2 L / min), a vacuum degree of 18.1 Pa, a power of 400 W, an activation time of 10 min is used, and after the treatment, it is transferred to a high-precision hot pressing welding machine.

6. The flip chip packaging method based on chip-level hybrid bonding according to claim 1, characterized in that: The hot-press welding machine always maintains a 50% concentration of formic acid vapor atmosphere, and the optical alignment deviation of the equipment is less than ±500nm. After the alignment is completed, a pressure of 2.5MPa is applied to make the interface of the chip dielectric layer and the carrier dielectric layer contact each other. The chip and the carrier wafer are heated to 100-200°C at a heating rate of 20°C / min and kept warm for 30 minutes to complete the pre-bonding between the chip dielectric layer and the carrier dielectric layer interface.

7. The flip chip packaging method based on chip-level hybrid bonding according to claim 1, characterized in that: The annealing conditions in step S16 are: heating rate 10° C. / min, reaching 300-450° C., keeping warm for 2 hours, and cooling naturally.

8. The flip chip packaging method based on chip-level hybrid bonding according to claim 1, characterized in that: The chip wafer and the carrier wafer are made of Si material, and the thickness of the chip dielectric layer and the carrier dielectric layer are both 300 nm.

Images