Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate, forming a first middle structure layer at the top of the substrate, and forming a first metal structure which penetrates through the first middle structure layer in a first direction perpendicular to the top surface of the first middle structure layer; sequentially forming a first etching stop layer, a second etching stop layer, a second intermediate structure layer and a hard mask layer on the top surface of the first intermediate structure layer; executing an integrated etching process to form an opening penetrating through the second intermediate structure layer until the second etching stop layer is exposed; a dry etching process is executed step by step so as to remove the second etching stop layer and the first etching stop layer, and the dry etching process is further used for removing part of the hard mask layer; forming a second metal structure in the opening, wherein the second metal structure is interconnected with the first metal structure; and performing chemical mechanical polishing to completely remove the hard mask layer. The preparation process of the semiconductor device is optimized, and the performance and the yield of the semiconductor device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] As the size of semiconductor devices decreases, in the back-end process of device manufacturing, it is necessary to form a Damascene structure by etching trenches and holes so that copper can be filled in the trenches and holes to form wires and form conductive paths. Currently, the metal Damascene all-in-one (AIO) etching process has become a more commonly used process.

[0003] However, when using integrated etching to form a Damascus structure, on the one hand, it is easy to cause damage to the underlying metal. For example, due to the inconsistent etching rates of different patterns, the copper surface in the corresponding area is over-etched, forming a "U" or "V" shaped area, which in turn affects the Rc resistance and electron mobility of the wafer. On the other hand, the metal hard mask TiN layer remaining on the top after integrated etching is relatively thick. If the subsequent chemical mechanical polishing (CMP) cannot be completely removed, the TiN residue will also affect the device performance. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a method for manufacturing the same to address the problems in the above-mentioned background technology, which can at least avoid metal damage and metal hard mask residue and improve the performance of the semiconductor device.

[0005] To achieve the above-mentioned object and other related objects, one aspect of the present application provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] Providing a substrate, wherein a first intermediate structure layer is formed on the top of the substrate, and a first metal structure penetrates the first intermediate structure layer along a first direction vertical to a top surface of the first intermediate structure layer;

[0007] sequentially forming a first etch stop layer, a second etch stop layer, a second intermediate structure layer and a hard mask layer on a top surface of the first intermediate structure layer;

[0008] Performing an integrated etching process to form an opening penetrating the second intermediate structure layer until the second etch stop layer is exposed;

[0009] Performing a dry etching process in steps to remove the second etch stop layer and the first etch stop layer respectively, wherein the dry etching process is also used to remove a portion of the hard mask layer;

[0010] forming a second metal structure in the opening, the second metal structure being interconnected with the first metal structure;

[0011] Chemical mechanical polishing is performed to completely remove the hard mask layer.

[0012] In one embodiment, the second etch stop layer includes a tantalum oxide layer or an aluminum oxide layer, the first etch stop layer includes a silicon oxide layer, and the hard mask layer includes a titanium nitride layer.

[0013] In one embodiment, the stepwise performing of the dry etching process to remove the second etch stop layer and the first etch stop layer respectively comprises:

[0014] Performing a first dry etching process using chloride as an etching gas to remove the second etch stop layer and a portion of the hard mask layer;

[0015] A second dry etching process is performed using fluoride as an etching gas to remove the first etching stop layer.

[0016] In one embodiment, the chloride comprises boron chloride gas and the fluoride comprises carbon fluoride gas.

[0017] In one embodiment, the thickness of the second etch stop layer ranges from 30 angstroms to 80 angstroms, and the thickness of the first etch stop layer ranges from 50 angstroms to 150 angstroms.

[0018] In one embodiment, the first intermediate structure layer includes a nitrogen-doped silicon carbide layer and a silicon oxycarbide layer sequentially formed along the first direction, and the second intermediate structure layer includes a nitrogen-doped silicon carbide layer and a low dielectric material layer sequentially formed along the first direction.

[0019] In one embodiment, before forming the hard mask layer, a step of forming a sacrificial layer is further included, the sacrificial layer includes tetraethyl orthosilicate, and the sacrificial layer is removed while the hard mask layer is completely removed.

[0020] In one embodiment, the first metal structure and the second metal structure include copper.

[0021] In one embodiment, the etching gas of the integrated etching process includes fluorinated hydrocarbon gas.

[0022] Another aspect of the present application provides a semiconductor device manufactured using any of the above methods for manufacturing a semiconductor device.

[0023] According to the semiconductor device and preparation method thereof provided by the present invention, two layers of etch stop layers are formed, one layer is used to avoid damage to the underlying metal layer caused by integrated etching, and the other layer is used to avoid new damage to the semiconductor device during the process of removing the etch stop layer. At the same time, the two steps of removing the etch stop layer and chemical mechanical polishing are used to jointly control the retention of the hard mask layer. The hard mask layer can be used to control the morphology of the semiconductor device and avoid residual mask layer, thereby optimizing the preparation process of the semiconductor device and improving the performance and yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to better describe and illustrate the embodiments and / or examples of those applications disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, and the best modes of these applications currently understood.

[0025] Figure 1 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment;

[0026] Figure 2 It is a schematic cross-sectional structure diagram of a structure obtained after forming a first intermediate structure layer and a first metal structure in step S101 of a method for preparing a semiconductor device provided in an embodiment;

[0027] Figure 3 It is a schematic cross-sectional structural diagram of a structure obtained after an opening penetrating the second intermediate structure layer is formed in step S103 of a method for preparing a semiconductor device provided in an embodiment;

[0028] Figure 4 It is a schematic cross-sectional structure diagram of a structure obtained after dry etching the second etch stop layer and the first etch stop layer in step S104 of the method for preparing a semiconductor device provided in an embodiment;

[0029] Figure 5 It is a schematic cross-sectional structural diagram of a structure obtained after forming a second metal structure in step S105 of a method for preparing a semiconductor device provided in an embodiment;

[0030] Figure 6 FIG. 1 is a schematic cross-sectional view of a structure obtained after chemical mechanical polishing is performed in step S107 of a method for preparing a semiconductor device provided in an embodiment.

[0031] Description of reference numerals:

[0032] 210, first intermediate structure layer; 211, first nitrogen-doped silicon carbide layer; 212, silicon carbide oxide layer; 220, first metal structure; 231, first etch stop layer; 232, second etch stop layer; 240, second intermediate structure layer; 241, second nitrogen-doped silicon carbide layer; 242, low dielectric material layer; 250, sacrificial layer; 260, hard mask layer; 270, second metal structure. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing, and the zones shown in the figures are schematic in nature, and their shapes are not intended to display the actual shapes of the zones of the device and are not intended to limit the scope of the application.

[0039] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0040] The present invention provides a method for preparing a semiconductor device, such as Figure 1 As shown, the following steps are included:

[0041] Step S101: providing a substrate, wherein a first intermediate structure layer is formed on the top of the substrate, and a first metal structure penetrates the first intermediate structure layer along a first direction perpendicular to a top surface of the first intermediate structure layer;

[0042] Step S102: forming a first etch stop layer, a second etch stop layer, a second intermediate structure layer and a hard mask layer in sequence on the top surface of the first intermediate structure layer;

[0043] Step S103: performing an integrated etching process to form an opening penetrating the second intermediate structure layer until the second etching stop layer is exposed;

[0044] Step S104: performing a dry etching process in steps to remove the second etch stop layer and the first etch stop layer respectively, and the dry etching process is also used to remove a portion of the hard mask layer;

[0045] Step S105: forming a second metal structure in the opening, wherein the second metal structure is interconnected with the first metal structure;

[0046] Step S106: performing chemical mechanical polishing to completely remove the hard mask layer.

[0047] First, execute step S101, refer to Figure 2 As shown, a substrate is provided, a first intermediate structure layer 210 is formed on the top of the substrate, and a first metal structure 220 penetrates the first intermediate structure layer along a first direction vertical to the top surface of the first intermediate structure layer.

[0048] In one embodiment, the substrate may be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Preferably, the substrate is a single crystal silicon substrate.

[0049] In one embodiment, the first intermediate structural layer 210 includes a first nitrogen-doped silicon carbide layer 211 (NDC) and a silicon oxycarbide layer 212 (SiCO) sequentially formed along the first direction. In one embodiment, the thickness of the first nitrogen-doped silicon carbide layer 211 ranges from 300Å to 400Å, such as 300Å, 350Å, 400Å, preferably 350Å. The silicon oxycarbide layer 212 is formed on the top surface of the first nitrogen-doped silicon carbide layer 211, and the thickness of the silicon oxycarbide layer 212 ranges from 1500Å to 2000Å, such as 1500Å, 1650Å, 2000Å, preferably 1650Å. The method of forming the first nitrogen-doped silicon carbide layer 211 and the silicon oxycarbide layer 212 may adopt chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).

[0050] Exemplarily, the first metal structure 220 penetrates the first intermediate structure layer 210 along a first direction perpendicular to the top surface of the first intermediate structure layer 210. In one embodiment, the first metal structure 220 includes one of a contact plug (CT), a metal wiring (Metal Wiring), or a combination of a contact plug and a metal wiring. Both the contact plug and the metal wiring can be made of materials such as tungsten, copper, and aluminum, preferably copper.

[0051] Next, execute step S102, referring to Figure 3 As shown, a first etch stop layer 231 , a second etch stop layer 232 , a second intermediate structure layer 240 and a hard mask layer 260 are sequentially formed on the top surface of the first intermediate structure layer 210 .

[0052] Exemplarily, the second etch stop layer 232 includes, but is not limited to, a metal oxide layer such as tantalum oxide (TA2O5) or aluminum oxide (Al2O3), and the first etch stop layer 231 includes a silicon oxide layer (SiO2). In one embodiment, the first etch stop layer 231 is first formed on the top surface of the first intermediate structure layer 210 and the first metal structure 220 using a process technology familiar to those skilled in the art, such as chemical vapor deposition (CVD). Specifically, silane (SiH4) is used as a source gas, and a gas mixed with silane diluted by nitrogen (N2) and excess oxygen (O2) is heated to 250°C~450°C, and silane reacts with oxygen to generate silicon oxide (SiO2) and is deposited on the surface of the first intermediate structure layer 210 to form the first etch stop layer 231. The thickness of the first etch stop layer 231 ranges from 50Å to 150Å, for example, 50Å, 100Å, 150Å, preferably 100Å. Next, a second etch stop layer 232 is formed on the top surface of the first etch stop layer 231. Specifically, a tantalum halogen compound such as tantalum chloride (TaCl5) or an organic compound of tantalum such as Ta(OC2H5)5 is used as a precursor, mixed with oxygen O2, and an inert gas (for example, nitrogen N2, argon Ar, etc.) is used as a load gas to deposit a tantalum oxide (Ta2O5) film. The thickness of the second etch stop layer 232 ranges from 30Å to 80Å, for example, 30Å, 50Å, 80Å, preferably 50Å. The method for forming the second etch stop layer 232 can be chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer chemical vapor deposition (ALCVD).

[0053] In one embodiment, the second etch stop layer 232 is a metal oxide layer, and the second etch stop layer and the second intermediate structure layer formed subsequently have a high etching selectivity ratio, so as to serve as an etch stop layer for the subsequent integrated etching step, that is, when the integrated (AIO) etching is performed, the etching endpoint stops at the upper surface of the second etch stop layer 232. The first etch stop layer 231 is a non-metal oxide layer, and the first etch stop layer, the second etch stop layer, and the first metal structure all have a high etching selectivity ratio, so as to serve as an etch stop layer for the subsequent removal of the second etch stop layer, that is, when the second etch stop layer 232 is removed by dry etching, the etching endpoint stops at the upper surface of the first etch stop layer 231, and when the first etch stop layer 231 is further removed by dry etching, the surface of the first metal structure 220 will not be damaged.

[0054] Further, a second intermediate structure layer 240 is formed on the second etch stop layer 232, and the second intermediate structure layer 240 includes a second nitrogen-doped silicon carbide layer 241 (NDC) and a low dielectric material layer 242 formed in sequence along the first direction. In one embodiment, a second nitrogen-doped silicon carbide layer 241 is first formed on the top surface of the second etch stop layer 232. The thickness of the second nitrogen-doped silicon carbide layer 241 ranges from 300Å to 400Å, such as 300Å, 350Å, 400Å, preferably 350Å. Then, a low dielectric material layer 242 is formed on the top surface of the second nitrogen-doped silicon carbide layer 241, and the low dielectric material layer 242 can well reduce the signal attenuation caused by the impedance and capacitive delay of the circuit itself when the electrical signal propagates. The material of the low dielectric material layer 242 includes but is not limited to black diamond (black diamond, bd), bd is a dielectric material composed of C, H, O, Si elements, and the K value is 2.5 to 3.3. The thickness of the low dielectric material layer 242 ranges from 3000Å ​​to 4000Å, such as 3000Å, 3350Å, 4000Å, and preferably 3350Å.

[0055] Next, a sacrificial layer 250 is formed on the top surface of the low dielectric material layer 242, and the material of the sacrificial layer 250 includes but is not limited to tetraethyl orthosilicate (TEOS). The thickness of the sacrificial layer 250 ranges from 200Å to 400Å, such as 200Å, 300Å, 400Å, and preferably 300Å. The method for forming the second nitrogen-doped silicon carbide layer 241, the low dielectric material layer 242 and the sacrificial layer 250 can adopt chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).

[0056] Further, a hard mask layer 260 is formed on the top surface of the sacrificial layer 250. The hard mask layer 260 can not only protect the morphology of the second intermediate structure layer 240 during the integrated etching process, but also protect the second intermediate structure layer 240 from bombardment damage during the formation of the second metal structure, and keep the morphology unchanged. The material of the hard mask layer 260 includes but is not limited to silicon nitride (TiN). The thickness of the hard mask layer 260 ranges from 200Å to 400Å, such as 200Å, 300Å, 400Å, preferably 300Å. The method of forming the hard mask layer 260 can be completed by a process technology familiar to those skilled in the art such as chemical vapor deposition (CVD), which will not be described in detail here.

[0057] Next, execute step S103, referring to Figure 3As shown, an integrated etching process is performed to form an opening penetrating the second intermediate structure layer 240 until the second etch stop layer 232 is exposed.

[0058] In one embodiment, an all-in-one (AIO) etching process is used, where the three steps of through-hole etching, photoresist removal, and trench etching are completed in the same process step. The all-in-one etching process is performed using CxHyFz as an etching gas, and the hard mask layer 260, the sacrificial layer 250, and the second intermediate structure layer 240 (the second nitrogen-doped silicon carbide layer 241, the low dielectric material layer 242) are all etched to form an opening of a damascene structure, wherein a through hole is formed in a portion of the second nitrogen-doped silicon carbide layer 241 and the low dielectric material layer 242, and a trench is formed in another portion of the low dielectric material layer 242, the sacrificial layer 250, and the hard mask layer 260. Since the integrated etching has a high etching selectivity for the second etch stop layer 232 and the second nitrogen-doped silicon carbide layer 241, the low dielectric material layer 242, the sacrificial layer 250 and the hard mask layer 260, the integrated etching stops at the surface of the second etch stop layer 232, avoiding over-etching damage to the surface of the first metal structure 220 caused by the integrated etching process.

[0059] Next, execute step S104, such as Figure 4 As shown, the dry etching process is performed step by step to remove the second etch stop layer 232 and the first etch stop layer 231 respectively. The dry etching process is also used to remove a portion of the hard mask layer 260 .

[0060] Illustratively, the step-by-step dry etching process to respectively remove the second etch stop layer 232 and the first etch stop layer 231 includes: using chloride as an etching gas to perform a first dry etching process to remove the second etch stop layer 232 and a portion of the hard mask layer 260; and using fluoride as an etching gas to perform a second dry etching process to remove the first etch stop layer 231.

[0061] In one embodiment, in order to avoid undercut caused by wet etching to remove the etch stop layer, which in turn causes the bottom void problem caused by subsequent metal filling, dry etching is used to remove the etch stop layer. Specifically, BCl3 is first used as an etching gas to perform a first dry etching. Since the first dry etching has a high etching selectivity ratio for the second etch stop layer 232 and the first etch stop layer 231, the first dry etching stops on the surface of the first etch stop layer 231. Then, CF-based gas is used as an etching gas to perform a second dry etching. Since the second dry etching has a high etching selectivity ratio for the first etch stop layer 231 and the first metal structure 220, the second dry etching stops on the surface of the first metal structure 220 and will not cause damage to the first metal structure 220.

[0062] In one embodiment, in order to avoid incomplete removal of the hard mask layer 260 and residues due to the thick hard mask layer 260 when the hard mask layer 260 is subsequently removed by chemical mechanical polishing (CMP), it is necessary to remove part of the hard mask layer 260 by a dry etching step. At the same time, in order to avoid bombardment damage to the sacrificial layer 250 and the second intermediate structure layer 240 during the formation of the second metal structure, part of the hard mask layer 260 needs to be retained to protect the morphology (profile) of the sacrificial layer 250 and the second intermediate structure layer 240. In summary, in this embodiment, the first dry etching is also used to remove part of the hard mask layer 260. Specifically, the thickness of the hard mask layer 260 is reduced from about 300Å to about 200Å.

[0063] Next, execute step S105, such as Figure 5 As shown, a second metal structure 270 is formed in the opening, and the second metal structure 270 is interconnected with the first metal structure 220 .

[0064] In one embodiment, a metal material layer is formed, and the metal material layer fills the opening and covers the top surface of the hard mask layer 260. The metal material filling the opening forms a second metal structure 270, and the bottom surface of the second metal structure 270 is connected to the top surface of the first metal structure 220, so that the second metal structure 270 is interconnected with the first metal structure 220. The material of the second metal structure 270 is preferably copper, and the method of forming the second metal structure can be one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic vapor deposition (ALD).

[0065] Reference Figure 5 As shown, during the process of forming the second metal structure, the surface of the hard mask layer 260 is bombarded and damaged, and the thickness of the hard mask layer 260 is further reduced from about 200Å to less than 100Å.

[0066] Next, execute step S106, such as Figure 6 As shown, chemical mechanical polishing is performed to completely remove the hard mask layer 260 .

[0067] In one embodiment, chemical mechanical polishing (CMP) is performed to first remove the metal material layer on the top surface of the hard mask layer 260 through chemical mechanical polishing, and then remove the hard mask layer 260. In order to avoid TiN residue in the hard mask layer 260, the sacrificial layer 250 is also removed through chemical mechanical polishing, remaining on the top surface of the second intermediate structure layer 240.

[0068] So far, the introduction of the relevant steps of the method for preparing a semiconductor device according to an embodiment of the present invention has been completed. It can be understood that the method for preparing a semiconductor device according to this embodiment not only includes the above steps, but also may include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method according to this embodiment.

[0069] Reference Figure 6 , which shows a schematic cross-sectional view of a semiconductor device provided according to the present invention. The semiconductor device is manufactured by the above method.

[0070] like Figure 6 As shown, the semiconductor device includes:

[0071] A first metal structure 220 , penetrating the first intermediate structure layer 210 along a first direction vertical to a top surface of the first intermediate structure layer 210 ;

[0072] A second metal structure 270, interconnected with the first metal structure 220, and penetrating the second intermediate structure layer 240 along the first direction;

[0073] The etch stop layer is located between the first intermediate structure layer 210 and the second intermediate structure layer 240 .

[0074] In one embodiment, the first intermediate structural layer 210 includes a first nitrogen-doped silicon carbide layer 211 (NDC) and a silicon oxycarbide layer 212 (SiCO) sequentially formed along the first direction. In one embodiment, the thickness of the first nitrogen-doped silicon carbide layer 211 ranges from 300Å to 400Å, such as 300Å, 350Å, 400Å, preferably 350Å. The silicon oxycarbide layer 212 is formed on the top surface of the first nitrogen-doped silicon carbide layer 211, and the thickness of the silicon oxycarbide layer 212 ranges from 1500Å to 2000Å, such as 1500Å, 1650Å, 2000Å, preferably 1650Å.

[0075] In one embodiment, the first metal structure 220 penetrates the first intermediate structure layer 210 along a first direction perpendicular to the top surface of the first intermediate structure layer 210. In one embodiment, the first metal structure 220 includes one of a contact plug (CT), a metal wiring, or a combination of a contact plug and a metal wiring, and both the contact plug and the metal wiring can be made of materials such as tungsten, copper, and aluminum, preferably copper.

[0076] In one embodiment, the second intermediate structure layer 240 includes a second nitrogen-doped silicon carbide layer 241 (NDC) and a low dielectric material layer 242 formed in sequence along the first direction. The thickness of the second nitrogen-doped silicon carbide layer 241 ranges from 300Å to 400Å, such as 300Å, 350Å, 400Å, preferably 350Å. The material of the low dielectric material layer 242 includes but is not limited to black diamond (BD), BD is a dielectric material composed of C, H, O, and Si elements, and the K value is 2.5 to 3.3. The thickness of the low dielectric material layer 242 ranges from 3000Å ​​to 4000Å, such as 3000Å, 3350Å, 4000Å, preferably 3350Å. The low dielectric material layer 242 can well reduce the signal attenuation caused by the impedance and capacitive delay of the circuit itself when the electrical signal propagates.

[0077] In one embodiment, the second metal structure 270 penetrates the second intermediate structure layer 240 along a first direction perpendicular to the top surface of the second intermediate structure layer 240. The second metal structure 270 includes but is not limited to a Damascus structure, and the Damascus structure can be made of materials such as tungsten, copper, and aluminum, preferably copper. The bottom surface of the second metal structure 270 is connected to the top surface of the first metal structure 220, so that the second metal structure 270 is interconnected with the first metal structure 220.

[0078] In one embodiment, the first etch stop layer 231 is disposed on the top of the first intermediate structure layer 210, the second etch stop layer 232 is disposed on the top of the first etch stop layer 231, and the second intermediate structure layer 240 is disposed on the top of the second etch stop layer 232. The first etch stop layer 231 includes a silicon oxide layer (SiO2). The thickness of the first etch stop layer 231 ranges from 50Å to 150Å, such as 50Å, 100Å, 150Å, preferably 100Å. The second etch stop layer 232 includes, but is not limited to, a metal oxide layer such as tantalum oxide (TA2O5) or aluminum oxide (Al2O3). The thickness of the second etch stop layer 232 ranges from 30Å to 80Å, such as 30Å, 50Å, 80Å, preferably 50Å. Among them, the second etch stop layer 232 and the second intermediate structure layer 240 have a high etching selectivity, and the first etch stop layer 231 and the first metal structure 220 have a high etching selectivity.

[0079] The specific structure of the semiconductor device can refer to the description of the corresponding part in the above text, and will not be repeated here for the sake of brevity.

[0080] According to the semiconductor device and preparation method thereof provided by the present invention, two layers of etch stop layers are formed, one layer is used to avoid damage to the underlying metal layer caused by integrated etching, and the other layer is used to avoid new damage to the semiconductor device during the process of removing the etch stop layer. At the same time, the two steps of removing the etch stop layer and chemical mechanical polishing are used to jointly control the retention of the hard mask layer. The hard mask layer can be used to control the morphology of the semiconductor device and avoid residual mask layer, thereby optimizing the preparation process of the semiconductor device and improving the performance and yield of the semiconductor device.

[0081] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0082] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0083] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein a first intermediate structure layer is formed on the top of the substrate, and a first metal structure penetrates the first intermediate structure layer along a first direction vertical to a top surface of the first intermediate structure layer; sequentially forming a first etch stop layer, a second etch stop layer, a second intermediate structure layer and a hard mask layer on a top surface of the first intermediate structure layer; Performing an integrated etching process to form an opening penetrating the second intermediate structure layer until the second etch stop layer is exposed; Performing a dry etching process in steps to remove the second etch stop layer and the first etch stop layer respectively, wherein the dry etching process is also used to remove a portion of the hard mask layer; forming a second metal structure in the opening, the second metal structure being interconnected with the first metal structure; Chemical mechanical polishing is performed to completely remove the hard mask layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: The second etch stop layer includes a tantalum oxide layer or an aluminum oxide layer, the first etch stop layer includes a silicon oxide layer, and the hard mask layer includes a titanium nitride layer.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The stepwise performing of the dry etching process to remove the second etch stop layer and the first etch stop layer respectively comprises: Performing a first dry etching process using chloride as an etching gas to remove the second etch stop layer and a portion of the hard mask layer; A second dry etching process is performed using fluoride as an etching gas to remove the first etching stop layer.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The chloride includes boron chloride gas, and the fluoride includes carbon fluoride gas.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The thickness of the second etch stop layer ranges from 30 angstroms to 80 angstroms, and the thickness of the first etch stop layer ranges from 50 angstroms to 150 angstroms.

6. The method for preparing a semiconductor device according to claim 1, wherein: The first intermediate structure layer includes a nitrogen-doped silicon carbide layer and a silicon oxycarbide layer sequentially formed along the first direction, and the second intermediate structure layer includes a nitrogen-doped silicon carbide layer and a low dielectric material layer sequentially formed along the first direction.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: Before forming the hard mask layer, the method further includes the step of forming a sacrificial layer, wherein the sacrificial layer includes tetraethyl orthosilicate, and the sacrificial layer is removed while the hard mask layer is completely removed.

8. The method for preparing a semiconductor device according to claim 1, wherein: The first metal structure and the second metal structure include copper.

9. The method for preparing a semiconductor device according to claim 1, wherein: The etching gas of the integrated etching process includes fluorinated hydrocarbon gas.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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