Semiconductor device

Abstract

A semiconductor device includes functional blocks each configured to provide at least one predetermined function, where the functional blocks include at least: a first functional block; and a second functional block, and wherein the first functional block and the second functional block are coupled in series with a predetermined current flowing through the first functional block and the second functional block. Therefore, power consumption can be reduced in a series connection mode, and the semiconductor device is stable in operation and suitable for required application scenes.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] SiP (System in Package or System-in-a-Package) includes one or more integrated circuits packaged in a single module (e.g., a single package). A SiP can perform many (or all) functions of an electronic system. An example of a SiP may include several dies combined with passive components (e.g., resistors and capacitors) mounted on a single substrate. Mounting all components on a single substrate provides a complete functional unit that can be built into a multi-die package and requires very few external components to make the device work.

[0003] For electronic systems in which one or more SiP packages, chips or SoCs (System on Chip) are integrated, how to reduce power consumption is always a concern. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor device which can greatly reduce power consumption compared with conventional designs.

[0005] According to a first aspect of the present invention, a semiconductor device is disclosed, comprising:

[0006] functional blocks, each of which is configured to provide at least one predetermined function,

[0007] The functional block at least includes:

[0008] a first functional block; and

[0009] A second functional block, and

[0010] The first functional block and the second functional block are coupled in series, and a predetermined current flows through the first functional block and the second functional block.

[0011] According to a second aspect of the present invention, a semiconductor device is disclosed, comprising:

[0012] Printed circuit boards; and

[0013] functional blocks, each of which is disposed on the printed circuit board and configured to provide at least one predetermined function,

[0014] The functional block at least includes:

[0015] a first functional block; and

[0016] The second functional block,

[0017] wherein the first functional block and the second functional block are coupled in series, wherein a first predetermined current flows through the first functional block and the second functional block, and

[0018] Wherein, at least one control signal received from the first functional block is relayed to the second functional block.

[0019] According to a third aspect of the present invention, a semiconductor device is disclosed, comprising:

[0020] semiconductor dies, each of which is configured to provide at least one predetermined function,

[0021] The semiconductor crystal grain at least comprises:

[0022] A first semiconductor die having a first power pad and a first ground pad; and

[0023] The second semiconductor die has a second power pad and a second ground pad,

[0024] The first power pad of the first semiconductor die and the second ground pad of the second semiconductor die are electrically connected to each other and have the same potential.

[0025] The semiconductor device of the present invention has the first functional block and the second functional block coupled in series, wherein a predetermined current flows through the first functional block and the second functional block. Therefore, power consumption can be reduced by the series connection, and the semiconductor device operates stably and is suitable for the required application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a top view of a semiconductor package (or semiconductor device) according to an embodiment of the first aspect of the present invention.

[0027] Figure 2 FIG. 4 is an equivalent circuit diagram of two semiconductor crystal grains switched in series according to an embodiment of the first aspect of the present invention.

[0028] Figure 3 According to an embodiment of the first aspect of the present invention, Figure 1 A residual cross-sectional view of a semiconductor package is shown.

[0029] Figure 4 is a layout of an on-chip series power supply system according to an embodiment of the second aspect of the present invention.

[0030] Figure 5 Schematic diagram of two chips connected in series on a PCB according to an embodiment of the present invention.

[0031] Figure 6is a schematic diagram of two chips connected in series on a PCB according to another embodiment of the present invention.

[0032] Figure 7 is a schematic diagram of six chips on a PCB according to an embodiment of the present invention.

[0033] Figure 8 is a top view of a semiconductor package according to another embodiment of the present invention.

[0034] Fig. 9 is a top view of a semiconductor package according to yet another embodiment of the present invention.

[0035] Fig.10 is a schematic diagram of six chips on a PCB according to another embodiment of the present invention.

[0036] Fig.11 FIG. 4 is a schematic diagram of six chips on a PCB according to yet another embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to reduce power consumption, embodiments of the present invention provide a novel structural design of a semiconductor device for implementing a serial power system.

[0038] According to an embodiment of the present invention, a semiconductor device may include a plurality of functional blocks. Each functional block is configured to provide at least one predetermined function. For example, each functional block may be configured to provide a CHF (cryptographic hash function) calculation function, such as a SHA (Secure Hash Algorithm) calculation function. According to an embodiment of the present invention, a functional block may be a circuit, a semiconductor die, an IC (Integrated Circuit), a chip, a SoC (System-on-a-Chip) die, a SoC package, a SiP package, a semiconductor package (or a semiconductor device), or a package assembly.

[0039] The functional block includes at least a first functional block and a second functional block. According to an embodiment of the present invention, the first functional block and the second functional block are coupled in series, wherein a predetermined current flows through the first functional block and the second functional block. Therefore, the current flowing through the first functional block and the second functional block is equal or the same.

[0040] In a first aspect of the present invention, the functional block is a semiconductor die packaged in a semiconductor package. In an embodiment of the present invention, the semiconductor die packaged in a semiconductor package (such as a SiP (system-in-package) package) can be coupled in series between a power node and a ground node, wherein a predetermined current flows between the power node and the ground node.

[0041] Figure 1 1 is a top view of a semiconductor package (or semiconductor device) according to an embodiment of the first aspect of the present invention. In this embodiment, the semiconductor device 100 may be a semiconductor package or a chip. The semiconductor device (or semiconductor package or semiconductor chip) 100 includes two semiconductor dies 110 and 120 encapsulated therein. The semiconductor dies 110 and 120 may be configured to provide the same functions. The pins marked with the leading term “D1” (e.g., pins marked 1 to 38) are pins associated with the semiconductor die 110, and the pins marked with the leading term “D2” are pins associated with the semiconductor die 120. It should be noted that Figure 1 The pin diagram shown is merely a schematic diagram, and the present invention is not limited thereto.

[0042] According to an embodiment of the present invention, semiconductor die 110 and 120 are coupled in series by electrically connecting a power supply pad of semiconductor die 110 to a ground pad of semiconductor die 120. Figure 1 As shown, the power pad (or related (e.g., electrically connected) power pin) DVDD_1 of the semiconductor die 110 is electrically connected to the ground pad (or related ground pin) DVSS_2 of the semiconductor die 120. In addition, the power pad (or related power pin) DVDD_2 of the semiconductor die 120 can be configured to receive power from an external power source via a power node or a power pin of the semiconductor device 100, and the ground pad (or related ground pin) DVSS_1 of the semiconductor die 110 can be further coupled to a ground node.

[0043] Since the power pad DVDD_1 of the semiconductor die 110 is electrically connected to the ground pad DVSS_2 of the semiconductor die 120 , the power pad DVDD_1 of the semiconductor die 110 and the ground pad DVSS_2 of the semiconductor die 120 are at the same potential.

[0044] According to an embodiment of the present invention, the semiconductor die 110 / 120 may include at least one computing circuit (e.g., a computing circuit configured to perform CHF or SHA calculations), at least one PLL (Phase-Locked Loop) circuit configured to generate an internal clock signal, at least one I / O pad, and may also include some peripheral or supplementary components. These components may be triggered by different power supplies. For example, power DVDD may be provided to trigger the computing circuit, power AVDD1V8 may be provided to trigger the PLL circuit, and power AVDD0V75 may be provided to trigger the I / O pad.

[0045] In the prior art, each die generally receives the same power supply (e.g., the same V_Power), so the current in each die is relatively large, which may not be suitable for some application scenarios, such as AI computing scenarios. In an embodiment of the present invention, a series power supply system is implemented by coupling the power supply DVDD for triggering the computing circuit in series, wherein the computing circuit (or may be referred to as the computing unit circuit) provides the main functions of the semiconductor device 100. Among them, the semiconductor die 110 and 120 in the present invention may have the same computing unit circuit, that is, the computing unit circuit in the semiconductor die 110 may be the same as the computing unit circuit in the semiconductor die 120. Therefore, the semiconductor die 110 and 120 in the present invention may be coupled in series, so that the voltage division of each semiconductor die 110 and 120 is the same, so that each semiconductor die 110 and 120 can operate stably and reduce the power consumption of the package, which is particularly suitable for scenarios such as AI computing. The semiconductor crystal grains 110 and 120 may be in the same semiconductor package or chip, and the computing unit circuits in each of the semiconductor crystal grains 110 and 120 may be arranged in series or parallel as required.

[0046] Figure 2 is an equivalent circuit diagram of two semiconductor crystal grains coupled in series according to an embodiment of the first aspect of the present invention. Figure 2 As shown, semiconductor die 110 and 120 are coupled in series between a power node for receiving power V_Power and a ground node. The power V_Power may be provided to a power pad P2 of semiconductor die 120, and a ground pad G1 of semiconductor die 110 may be electrically connected to the ground node. When the power V_Power is provided, a predetermined current I (i.e., the same current) may flow through semiconductor die 120 and 110, i.e., the currents flowing through semiconductor die 120 and 110 are the same, i.e., the predetermined current I.

[0047] According to an embodiment of the present invention, the power pad P1 of the semiconductor die 110 and the ground pad G2 of the semiconductor die 120 are electrically connected to each other in the semiconductor package. Figure 1 As shown, the power pad DVDD_1 of the semiconductor die 110 and the ground pad DVSS_2 of the semiconductor die 120 may be formed as a whole (ie, Figure 1 The black line between the power pad DVDD_1 and the ground pad DVSS_2 in FIG. 1 should be deleted). It should be understood that Figure 1 The black line between the power pad DVDD_1 and the ground pad DVSS_2 in FIG. 1 is shown to allow the reader to easily distinguish between the two blocks, and thus, the present invention is not limited thereto.

[0048] According to another embodiment of the present invention, the power pad DVDD_1 of the semiconductor die 110 and the ground pad DVSS_2 of the semiconductor die 120 may be electrically connected to each other via at least one connecting element on a printed circuit board (PCB), an interposer, and / or a substrate. According to an embodiment of the present invention, the connecting element may be, for example, but not limited to, a redistribution layer (RDL) trace, a PCB trace, a connection bump (e.g., a solder ball), a bonding wire, a through silicon via (TSV), or other structures.

[0049] Figure 3 According to an embodiment of the first aspect of the present invention, Figure 1 Schematic cross-sectional view of a semiconductor package shown. In one embodiment of the present invention, a semiconductor package with exposed die is provided. Molding compound 24 encapsulates semiconductor die 310 and 320. Stiffening ring 22 can be provided along the periphery of package substrate (or substrate) 26. The semiconductor package can be a land grid array (LGA) type package.

[0050] The semiconductor package can be mounted on the PCB 28 or the system board through the connection elements 32, 34, 36 and 38. According to the embodiment of the present invention, for example, the connection element 32 is associated with the ground pad DVSS_1 of the semiconductor die 310 (the association is, for example, electrically connected), the connection element 34 is associated with the power pad DVDD_1 of the semiconductor die 310, the connection element 36 is associated with the ground pad DVSS_2 of the semiconductor die 320, and the connection element 38 is associated with the power pad DVDD_2 of the semiconductor die 320. In addition, the semiconductor die 310 and 320 can be electrically connected through the PCB or the system board, or can be connected through wiring, etc. in the package.

[0051] According to an embodiment of the present invention, connection elements 34 and 36 are electrically connected to each other via substrate 26 and / or PCB 28. Ground pad DVSS_1 is electrically connected to a ground node and power pad DVDD_2 is electrically connected to a power node.

[0052] In addition to implementing the series power system in a semiconductor package as in the embodiment of the first aspect of the present invention shown above, in the second aspect of the present invention, the series power system can also be implemented in a semiconductor die. In the second aspect of the present invention, the semiconductor device can be a semiconductor die.

[0053] Figure 4 4 is a block diagram showing an on-die series power supply system according to an embodiment of the second aspect of the present invention. In this embodiment, the functional block may be a computing circuit macro, and each computing circuit macro may include one or more computing circuits. According to an embodiment of the present invention, the semiconductor die 410 may include a plurality of computing circuit macros, such as computing circuit macros M1 to M4. For example, computing circuit macro M1 M4 are connected in series. Each calculation circuit macro may include one or more calculation circuits. Each calculation circuit is configured to provide a predetermined function, such as CHF calculation, SHA calculation or others. Therefore, the calculation circuit macro M1 M4 may be configured to provide the same function. According to an embodiment of the present invention, when more than one computing circuit is included in one computing circuit macro, these computing circuits may be coupled in parallel or in series.

[0054] like Figure 4 As shown, a power node of the computing circuit macro M4 for receiving the provided power is coupled to a power node PWR or a power pad (or an associated power pin) of the semiconductor die 410. A node of the computing circuit macro M3 is coupled to a ground node of the computing circuit macro M4. A power node of the computing circuit macro M2 is coupled to a ground node of the computing circuit macro M3. A power node of the computing circuit macro M1 is coupled to a ground node of the computing circuit macro M2. A ground node of the computing circuit macro M1 is coupled to a power node GND or a ground pad (or an associated ground pin) of the semiconductor die 410.

[0055] In this embodiment, in two adjacent computing circuit macros coupled in series, the power supply node of the lower computing circuit macro and the ground node of the upper computing circuit macro are equipotential. In addition, when power is supplied, a predetermined current (i.e., the same current) will flow through the computing circuit macro M4. M1.

[0056] In the third aspect of the present invention, the series power supply system can also be implemented on a PCB. In the third aspect of the present invention, the functional blocks coupled in series in the semiconductor device can be semiconductor packages, ICs or chips.

[0057] Figure 5 Schematic diagram showing two chips coupled in series on a PCB according to an embodiment of the present invention. Figure 5 As shown, semiconductor device 55 may include chips 510 and 520, which are mounted on PCB 500 and coupled in series between a power node and a ground node for receiving power V_Power. The power pin of chip 520 is electrically connected to the power node. The ground pin of chip 510 is electrically connected to the ground node. The power pin of chip 510 is electrically connected to the ground pin of chip 520. The power pin of chip 510 and the ground pin of chip 520 are equipotential. Chips 510 and 520 can be electrically connected to each other via at least one connecting element of the substrate on PCB / and / or thereof. When power V_Power is provided, a predetermined current (i.e., the same current) will flow through chips 520 and 510.

[0058] According to an embodiment of the present invention, chips 510 and 520 may include one or more semiconductor dies packaged therein, such as semiconductor dies 530 and 540, and are configured to provide the same function. When more than one semiconductor die is packaged in a chip, as in the embodiment of the first aspect of the present invention described above, the semiconductor dies may be coupled in series between a power node and a ground node. In addition, each semiconductor die may further include one or more computing circuits or one or more computing circuit macros. When more than one computing circuit or more than one computing circuit macro is included in a semiconductor die, as in the embodiment of the second aspect of the present invention described above, the computing circuit or computing circuit macro may be coupled in series between a power node and a ground node.

[0059] According to one embodiment of the present invention, preferably, the functional blocks are coupled in series and the currents flowing therethrough have similar characteristics. More specifically, in a first aspect of the present invention, the semiconductor grains coupled in series preferably have similar characteristics. In a second aspect of the present invention, the computing circuits or computing circuit macros coupled in series preferably have similar characteristics. In a third aspect of the present invention, the chips coupled in series preferably have similar characteristics.

[0060] According to an embodiment of the present invention, the above-mentioned characteristic may be, for example but not limited to, an equivalent impedance, a conduction current or a leakage temperature of a chip, a semiconductor die, a computing circuit macro or a calculation.

[0061] Here, “similar” may mean that the difference between two corresponding values ​​is less than a predetermined value.

[0062] As an example, according to an embodiment of the present invention, the difference between the equivalent impedance of the semiconductor crystal grain 110 and the equivalent impedance of the semiconductor crystal grain 120 is less than a predetermined value (that is, the two are almost the same, for example, the operation unit circuits of the two are the same). As another example, the computing circuit macro M1 The difference between the equivalent impedances of any two of M4 is less than a predetermined value. As another example, the difference between the equivalent impedance of chip 510 and the equivalent impedance of chip 520 is less than a predetermined value.

[0063] According to an embodiment of the present invention, based on the proposed structure as described above and the corresponding routing on the PCB, one or more control signals may be relayed between functional blocks.

[0064] Figure 6 1 is a schematic diagram showing two chips (or semiconductor packages) coupled in series on a PCB according to another embodiment of the present invention, wherein each chip has two semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in series. In this embodiment, a functional block is a chip disposed on a PCB and configured to provide at least one predetermined function (e.g., the functional blocks are configured to provide the same function).

[0065] like Figure 6 As shown, the semiconductor device 65 may include chips 610 and 620, which are mounted on the PCB 600 and coupled in series between a power node and a ground node for receiving a power supply V_Power. The power pin of the chip 620 is electrically connected to the power node. The ground pin of the chip 610 is electrically connected to the ground node. The power pin of the chip 610 is electrically connected to the ground pin of the chip 620. The chips 610 and 620 may be electrically connected to each other via at least one connecting element of the PCB and / or a substrate thereon. When the power supply V_Power is provided, a predetermined current (i.e., the same current) will flow through the chips 620 and 610.

[0066] According to an embodiment of the present invention, the chips 610 and 620 respectively include two semiconductor dies packaged therein, for example, semiconductor dies 610-1 and 610-2 and semiconductor dies 620-1 and 620-2. The structure of the semiconductor dies coupled in series and packaged in the chips 610 and / or 620 is similar to Figure 1 Therefore, the description of the circuit structure in a chip or semiconductor package having semiconductor dies coupled in series can refer to Figure 1 The description of the chips or semiconductor packages coupled in series on the PCB is omitted here for brevity. Figure 5Therefore, the description of the circuit structure of the semiconductor device having chips or semiconductor packages coupled in series can refer to Figure 5 The description is omitted here for brevity.

[0067] According to an embodiment of the present invention, at least one control signal, such as a clock signal or a strobe signal, is relayed from one chip (e.g., chip 610) (or one semiconductor package) to another chip (e.g., chip 620) (or another semiconductor package). In one embodiment of the present invention, at least one control signal output pin of chip 610 is electrically connected to a control signal input pin of chip 620 via at least one connecting element of a PCB and / or a substrate thereon.

[0068] like Figure 6 As shown, the pin 36 of the clock signal output pin D2CLKO of the chip 610 is electrically connected to the pin 29 of the clock signal input pin D1CLKI of the chip 620 .

[0069] In addition, according to an embodiment of the present invention, at least one control signal, such as a clock signal or a strobe signal, is relayed from one semiconductor die to another semiconductor die within the same chip (or semiconductor package). For example, at least one control signal output pad of one semiconductor die is electrically connected to a control signal input pad of another semiconductor die within the same chip via at least one connecting element on a PCB and / or a substrate thereon.

[0070] like Figure 6 As shown, pin 17 of the clock signal output pin D1CLKO of chip 610 is electrically connected to pin 10 of the clock signal input pin D2CLKI of chip 610, wherein pin 17 is a pin associated with semiconductor die 610-1 and electrically connected to the corresponding control signal output pad of semiconductor die 610-1, and pin 10 is a pin associated with semiconductor die 610-2 and electrically connected to the corresponding control signal input pad of semiconductor die 610-2.

[0071] Through the wiring on the PCB 600 and the internal signal transmission path within the chip, such as Figure 6 As shown, a control signal (e.g., clock signal CLK) received from an external device (e.g., CPU (central processing unit) or external clock source) can be routed or transmitted to semiconductor die 610-2 via lead 29 of pin 29 of chip 610, then routed or transmitted to semiconductor die 620-1, and finally routed or transmitted to semiconductor die 620-2. For another signal to be transmitted from semiconductor device 65 to an external device (e.g., CPU), the signal can be routed or transmitted to the external device in the reverse direction.

[0072] by Figure 6 Taking the pins shown as an example, the clock signal CLK received from the external device through the pin 29 of the chip 610 can be routed or transmitted to the pin 17 of the chip 610 through the internal signal transmission path inside the chip 610, and then routed or transmitted to the pin 10 of the chip 610 through the signal transmission path on the PCB 600 (for example, the connecting element shown above). The clock signal CLK can be further routed or transmitted to the pin 36 of the chip 610 through another internal signal transmission path within the chip 610, and then routed or transmitted to the pin 29 of the chip 620 through another signal transmission path on the PCB 600 (for example, the connecting element shown above).

[0073] The clock signal CLK may be further routed or transmitted in a similar manner within the chip 620. In this manner, a control signal received from an external device may be relayed from the semiconductor die 610-1 to the semiconductor die 610-2 and the semiconductor die 620-1, and then to the semiconductor die 620-2.

[0074] In the embodiments of the present invention, based on the proposed structure, a smooth layout of the package-substrate wiring and a simple layout of the PCB wiring can be achieved, for example Figure 6 Wiring shown.

[0075] It should be noted that, in addition to control signals, input / output signals can also be relayed from one chip to another chip and from one semiconductor die to another semiconductor die based on the wiring on the PCB and the proposed structure. Figure 6 As shown, receive / transmit output pins associated with one semiconductor die (e.g., pins labeled with the ending term "RXO" or "TXO") can be electrically connected to receive / transmit input pins (e.g., pins labeled with the ending term "RXI" or "TXI"). Additionally, receive / transmit output pins of one chip can be electrically connected to receive / transmit input pins of another chip within the same semiconductor device. Figure 6 The die arrangement shown can make the wiring more orderly, facilitate the wiring within the package, and reduce the crosstalk caused by chaotic wiring. In addition, Figure 6 The arrangement shown has a more reasonable layout, so the package size is smaller than that of the traditional structure, and can also save the BOM (Bill of Materials) list (due to reasonable wiring and fewer components) and circuit area on the PCB (due to reasonable wiring and less area).

[0076] In some embodiments of the present invention, control signals may also be relayed between more than two functional blocks.

[0077] Figure 7 700 is a schematic diagram showing six chips (or semiconductor packages) on a PCB according to an embodiment of the present invention, wherein each chip has two semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in series. The semiconductor dies or chips disposed on the PCB 700 are configured to provide the same function.

[0078] In this embodiment, the semiconductor device 75 may include a chip 710 mounted on a PCB 700. 760. Chips 710 and 720, 730 and 740, and 750 and 760 are respectively coupled in series between a power node and a ground node to receive a power supply V_Power. In addition, the semiconductor device 75 may further include a parallel structure in which three chipsets (i.e., a chipset including chips 710 and 720, a chipset including chips 730 and 740, and a chipset including chips 750 and 760) are coupled in parallel.

[0079] The power pins of chips 720, 740 and 760 are electrically connected to the power node. The ground pins of chips 710, 730 and 750 are electrically connected to the ground node. The power pin of chip 710 is electrically connected to the ground pin of chip 720 via at least one connecting element of PCB 700 and / or the substrate thereon. When power V_Power is provided, a predetermined current (i.e., the same current) will flow through chips 720 and 710. Similarly, the power pin of chip 730 is electrically connected to the ground pin of chip 740 via at least one connecting element of PCB 700 and / or the substrate thereon. When power V_Power is provided, a predetermined current (i.e., the same current) will flow through chips 740 and 730. Similarly, the power pin of chip 750 is electrically connected to the ground pin of chip 760 via at least one connecting element of PCB 700 and / or the substrate thereon. When power V_Power is provided, a predetermined current (i.e., the same current) will flow through chips 760 and 750.

[0080] According to an embodiment of the present invention, chip 710 760 respectively include two semiconductor dies packaged therein, such as semiconductor dies 710-1 and 710-2, 720-1 and 720-2, 730-1 and 730-2, 740-1 and 740-2, 750-1 and 750-2, 760-1 and 760-2. The semiconductor dies are coupled in series and packaged in chip 710 The structure of the semiconductor grains in 760 is similar to Figure 1 Therefore, the description of the circuit structure in a chip or semiconductor package having semiconductor dies coupled in series can refer to Figure 1The description of the chips or semiconductor packages coupled in series on the PCB is omitted here for brevity. Figure 5 Therefore, the description of the circuit structure in a chip or semiconductor package having semiconductor dies coupled in series can refer to Figure 5 description and is omitted here for brevity.

[0081] In addition, the signal transmission paths within the chip, between different chips, and between pin connections are similar to Figure 6 The embodiment shown. For those skilled in the art, it is easy to understand the derivation of the signal transmission path. Figure 6 Description, in Figure 7 In the chip and in Figure 7 Therefore, the details of the description can be referred to Figure 6 description and is omitted here for brevity.

[0082] exist Figure 7 In the illustrated embodiment, the control signal output pin (e.g., pin 36) of the chip 710 is electrically connected to the control signal input pin (e.g., pin 29) of the chip 720 via at least one connection element on the PCB 700 and / or the substrate thereon. In addition, another control signal output pin (e.g., pin 17) of the chip 710 is electrically connected to the control signal input pin (e.g., pin 29) of the chip 730 via at least one connection element on the PCB 700 and / or the substrate thereon. Similarly, the control signal output pin (e.g., pin 17) of the chip 720 is electrically connected to the control signal input pin (e.g., pin 29) of the chip 740 via at least one connection element on the PCB 700 and / or the substrate thereon. The rest can be deduced by analogy.

[0083] exist Figure 7 In the embodiment shown, via the wiring on the PCB 700 and Figure 7As shown in the internal signal transmission path within the chip, a control signal (e.g., a clock signal CLK) received from an external device via pin 29 of chip 710 can be routed or transmitted from semiconductor die 710-1 to semiconductor die 730-1, semiconductor die 750-1, and then routed or transmitted to semiconductor die 750-2, semiconductor die 730-2, and then semiconductor die 710-2. In addition, the control signal can be further routed or transmitted from semiconductor die 710-2 to semiconductor die 720-1, semiconductor die 740-1, semiconductor die 760-1, and then routed or transmitted to semiconductor die 760-2, semiconductor die 740-2, and semiconductor die 720-2. For another signal to be transmitted from semiconductor device 75 to an external device (e.g., a CPU), the signal can be routed or transmitted to the external device in the opposite direction. Figure 7 In the illustrated embodiment, chip 710 is connected in series with chip 720, chip 730 is connected in series with chip 740, and chip 750 is connected in series with chip 760; the combination of chip 710 and chip 720, the combination of chip 730 and chip 740, and chip 750 and chip 760 form a parallel structure. In addition, semiconductor dies 710-1, 710-2, 720-1, 720-2, 730-1, 730-2, 740-1, 740-2, 750-1, 750-2, 760-1, 760-2 may have the same operation unit circuit to ensure stable package operation.

[0084] In some embodiments of the present invention, a semiconductor package may further include more than two semiconductor dies coupled in series.

[0085] Figure 8 8 is a top view of a semiconductor package according to another embodiment of the present invention. In this embodiment, the semiconductor device 800 may be a semiconductor package or a chip. The semiconductor device 800 includes three semiconductor dies 810, 820, and 830 packaged therein and coupled in series. The semiconductor dies 810, 820, and 830 may be configured to provide the same function. The pins marked with the leading term "D1" (e.g., marked as 1 Pins labeled with a leading term “D3” are pins associated with semiconductor die 810 , pins labeled with a leading term “D2” are pins associated with semiconductor die 820 , and pins labeled with a leading term “D3” are pins associated with semiconductor die 830 .

[0086] like Figure 8As shown, the power pad (or related power pin) DVDD_1 of the semiconductor die 810 is electrically connected to the ground pad (or related ground pin) DVSS_2 of the semiconductor die 820. The pad (or related power pin) DVDD_2 of the semiconductor die 820 is electrically connected to the ground pad (or related ground pin) DVSS_3 of the semiconductor die 830. In addition, the power pad DVDD_3 of the semiconductor die 830 can be configured to receive power from an external power source via a power node or power pin of the semiconductor device 800, and the ground pad (or related ground pin) DVSS_1 of the semiconductor die 810 can be further coupled to a ground node.

[0087] In this embodiment, in two adjacent semiconductor dies coupled in series, the power pad (or related power pin) of the lower semiconductor die and the ground pad (or related ground pin) of the upper semiconductor die are at the same potential. In addition, when the power supply V_Power is provided, a predetermined current (i.e., the same current) will flow through the semiconductor die 830. 810.

[0088] Fig. 9 9 is a top view of a semiconductor package according to another embodiment of the present invention. In this embodiment, the semiconductor device 900 may be a semiconductor package or a chip. The semiconductor device 900 includes four semiconductor dies 910, 920, 930, and 940 packaged therein and coupled in series. The semiconductor dies 910, 920, 930, and 940 may be configured to provide the same function. The pins (e.g., numbered 1) marked with the leading term "D1" The pins marked with a leading term “D3” are pins associated with the semiconductor die 930, and the pins marked with a leading term “D4” are pins associated with the semiconductor die 940.

[0089] like Fig. 9As shown, the power pad (or related power pin) DVDD_1 of the semiconductor die 910 is electrically connected to the ground pad (or related ground pin) DVSS_2 of the semiconductor die 920, the power pad (or related power pin) DVDD_2 of the semiconductor die 920 is electrically connected to the ground pad (or related ground pin) DVSS_3 of the semiconductor die 930, and the power pad (or related power pin) DVDD_3 of the semiconductor die 930 is electrically connected to the ground pad (or related ground pin) DVSS_4 of the semiconductor die 940. In addition, the power pad DVDD_4 of the semiconductor die 940 may be configured to receive power from an external power source via a power node or power pin of the semiconductor device 900, and the ground pad (or related ground pin) DVSS_1 of the semiconductor die 910 may be further coupled to a ground node.

[0090] In this embodiment, in two adjacent semiconductor dies coupled in series, the power pad (or related power pin) of the lower semiconductor die and the ground pad (or related ground pin) of the upper semiconductor die are at the same potential. In addition, when the power supply V_Power is supplied, a predetermined current (i.e., the same current) will flow through the semiconductor die 940. 910.

[0091] Fig.10 1000 is a schematic diagram showing six chips (or semiconductor packages) on a PCB according to another embodiment of the present invention, wherein each chip has three semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled thereto in sequence. The semiconductor dies or chips disposed on the PCB 1000 are configured to provide the same function.

[0092] In this embodiment, the semiconductor device 105 may include chips 1010-1060 mounted on the PCB 1000 and / or the substrate. The chip 1010 includes semiconductor dies 1010-1, 1010-2, and 1010-3 packaged therein. The chip 1020 includes semiconductor dies 1020-1, 1020-2, and 1020-3 packaged therein. The chip 1030 includes semiconductor dies 1030-1, 1030-2, and 1030-3 packaged therein. The chip 1040 includes semiconductor dies 1040-1, 1040-2, and 1040-3 packaged therein. The chip 1050 includes semiconductor dies 1050-1, 1050-2, and 1050-3 packaged therein. The chip 1060 includes semiconductor dies 1060-1, 1060-2, and 1060-3 packaged therein.

[0093] Chips 1010 and 1020, 1030 and 1040, and 1050 and 1060 are respectively coupled in series between a power node for receiving a power source V_Power and a ground node. In addition, the semiconductor device 105 may further include a parallel structure in which three chipsets (i.e., a chipset including chips 1010 and 1020, a chipset including chips 1030 and 1040, and a chipset including chips 1050 and 1060) are coupled in parallel. The semiconductor chips 1010-1, 1010-2, 1010-3, 1020-1, 1020-2, 1020-3, 1030-1, 1030-2, 1030-3, 1040-1, 1040-2, 1040-3, 1050-1, 1050-2, 1050-3, 1060-1, 1060-2, 1060-3 may have the same operation unit circuit to ensure stable package operation.

[0094] exist Fig.10 , an exemplary signal routing path within semiconductor device 105 is shown. Through the routing on PCB 1000 and the internal signal transmission paths within the chip, the signal received from the external device via chip 1010 can be routed or transmitted sequentially from one semiconductor die to another semiconductor die, and can be routed or transmitted sequentially from one chip to another semiconductor die, such as Fig.10 As shown by the arrow in . For another signal to be transmitted from the semiconductor device 105 to an external device (eg, a CPU), the signal may be routed or transmitted to the external device in the opposite direction.

[0095] The signal transmission paths within the chip, between different chips, and between pin connections are similar to Figure 7 and Figure 8 The embodiment shown. For those skilled in the art, it is easy to understand the signal transmission path. Figure 7 and Figure 8 Description, in Fig.10 Between different chips in the chip and between Fig.10 Therefore, the details of the description can refer to Figure 7 and Figure 8 description and is omitted here for brevity.

[0096] Fig.11 1100 is a schematic diagram showing six chips (or semiconductor packages) on a PCB according to another embodiment of the present invention, wherein each chip has four semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in series. The semiconductor dies or chips arranged on the PCB 1100 are configured to provide the same function.

[0097] In this embodiment, the semiconductor device 115 may include chips 1110-1160 mounted on the PCB 1100. The chip 1110 includes semiconductor dies 1110-1, 1110-2, 1110-3, and 1110-4 packaged therein. The chip 1120 includes semiconductor dies 1120-1, 1120-2, 1120-3, and 1120-4 packaged therein. The chip 1130 includes semiconductor dies 1130-1, 1130-2, 1130-3, and 1130-4 packaged therein. The chip 1140 includes semiconductor dies 1140-1, 1140-2, 1140-3, and 1140-4 packaged therein. The chip 1150 includes semiconductor dies 1150-1, 1150-2, 1150-3, and 1150-4 packaged therein. The chip 1160 includes semiconductor dies 1160 - 1 , 1160 - 2 , 1160 - 3 , and 1160 - 4 packaged therein.

[0098] Chips 1110 and 1120, 1130 and 1140, and 1150 and 1160 are respectively coupled in series between a power node for receiving a power source V_Power and a ground node. In addition, the semiconductor device 115 may further include a parallel structure in which three chipsets (i.e., a chipset including chips 1110 and 1120, a chipset including chips 1130 and 1140, and a chipset including chips 1150 and 1160) are coupled in parallel. Semiconductor chips 1110-1, 1110-2, 1110-3, 1110-4, 1120-1, 1120-2, 1120-3, 1120-4, 1130-1, 1130-2, 1130-3, 1130-4, 1140-1, 1140-2, 1140-3, 1140-4, 1150-1, 1150-2, 1150-3, 1150-4, 1160-1, 1160-2, 1160-3, 1160-4 may have the same operation unit circuit to ensure stable package operation.

[0099] exist Fig.11 , an exemplary signal routing path within semiconductor device 115 is shown. Through the routing on PCB 1100 and the internal signal transmission path within the chip, the signal received from the external device via chip 1110 can be routed or transmitted sequentially from one semiconductor die to another semiconductor die, and can be routed or transmitted sequentially from one chip to another semiconductor die. In addition, as shown Fig.11 As shown by the arrow in . For another signal sent from the semiconductor device 115 to an external device (eg, a CPU), it can be routed or sent to the external device in the opposite direction.

[0100] The signal transmission paths within the chip, between different chips, and between pin connections are Figure 7 and Fig. 9 The embodiment shown is similar. For ordinary technicians in this field, it is easy to understand the signal transmission path. Figure 7 and Fig. 9 description, in one chip and Fig.11 Therefore, the details of the description can refer to Figure 7 and Fig. 9 description and is omitted here for the sake of brevity.

[0101] It should be noted that although in the embodiments of the present invention, a series power supply system having a plurality of functional blocks (e.g., computing circuits, computing circuit macros, semiconductor dies, semiconductor packages or chips) coupled in series is proposed, the functional blocks can also run simultaneously after initialization and stabilization. When a large number of functional blocks (e.g., computing circuits) start to perform corresponding functions simultaneously, it can provide huge computing power.

[0102] In addition, in an embodiment of the present invention, since the same current will flow through the functional blocks coupled in series, the power consumption can be greatly reduced. For example, for a structure having two dies connected in series in one package compared to a structure having two dies coupled in parallel, the current is half and the power consumption is half. In addition, the package size of the proposed structure (e.g., two or more dies connected in series in one package) is smaller than the package size of a conventional structure having a single die in one package. Therefore, the BOM (Bill of Materials) and the circuit area on the PCB can also be saved.

[0103] In addition, as described above, in the embodiments of the present invention, based on the proposed structure, a smooth layout of the package-substrate wiring and a simple layout of the PCB wiring can be achieved.

[0104] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: Printed circuit boards; as well as functional blocks, each of which is disposed on the printed circuit board and configured to provide at least one predetermined function, The functional block at least includes: a first functional block; and The second functional block, The first functional block and the second functional block are coupled in series, a first predetermined current flows through the first functional block and the second functional block, and wherein at least one control signal received from the first functional block is relayed to the second functional block; The power pin of the first chip is electrically connected to the ground pin of the second chip via a first connecting element of the printed circuit board and / or a substrate thereon.

2. The semiconductor device according to claim 1, wherein At least one control signal output pin of the first chip is electrically connected to a control signal input pin of the second chip via a second connection element of the printed circuit board and / or a substrate thereon.

3. The semiconductor device according to claim 1, wherein: The functional block also includes a third functional block and a fourth functional block, the third functional block and the fourth functional block are coupled in series, a second predetermined current flows through the third functional block and the fourth functional block, and the at least one control signal received from the first functional block is further relayed from the first functional block to the third functional block, and from the second functional block to the fourth functional block.

4. The semiconductor device according to claim 3, wherein: The third functional block is a third chip, the fourth functional block is a fourth chip, and a power pin of the third chip is electrically connected to a ground pin of the fourth chip via a second connecting element on the printed circuit board.

5. The semiconductor device according to claim 3, wherein: The third functional block is a third chip, the fourth functional block is a fourth chip, the first control signal output pin of the first chip is electrically connected to the control signal input pin of the second chip via the second connecting element on the printed circuit board, the second control signal output pin of the first chip is electrically connected to the control signal input pin of the third chip via the third connecting element on the printed circuit board, and the control signal output pin of the second chip is electrically connected to the control signal input pin of the fourth chip via the fourth connecting element on the printed circuit board.

6. The semiconductor device according to claim 1, wherein: The first functional block is a first chip, which includes a first semiconductor grain and a second semiconductor grain. The second functional block is a second chip, which includes a third semiconductor grain and a fourth semiconductor grain. The power pad of the first semiconductor grain is electrically connected to the ground pad of the second semiconductor grain, and the power pad of the third semiconductor grain is electrically connected to the ground pad of the fourth semiconductor grain.

7. A semiconductor device, characterized in that: include: Printed circuit boards; as well as functional blocks, each functional block being arranged on the printed circuit board and configured to provide at least one predetermined function, The functional block at least includes: a first functional block; and The second functional block, The first functional block and the second functional block are connected in series, and a first predetermined current flows through the first functional block and the second functional block. wherein at least one control signal received from the first functional block is relayed to the second functional block, The first functional block is a first semiconductor chip, the second functional block is a second semiconductor chip, the first semiconductor chip and the second semiconductor chip are packaged in one semiconductor package, and a power pad of the first semiconductor chip is electrically connected to a ground pad of the second semiconductor chip.

8. The semiconductor device according to claim 7, wherein: The power pad of the first semiconductor chip and the ground pad of the second semiconductor chip are electrically connected to each other in the semiconductor package.

9. The semiconductor device according to claim 7, wherein: The power pad of the first semiconductor chip and the ground pad of the second semiconductor chip are electrically connected to each other through at least one connecting element on the printed circuit board.

10. A semiconductor device, characterized in that: include: Printed circuit boards; as well as functional blocks, each functional block being arranged on the printed circuit board and configured to provide at least one predetermined function, The functional block at least includes: a first functional block; and The second functional block, The first functional block and the second functional block are connected in series, and a first predetermined current flows through the first functional block and the second functional block. at least one control signal received from the first functional block is relayed to the second functional block, The first functional block is a first chip, which includes a first semiconductor grain and a second semiconductor grain. The second functional block is a second chip, which includes a third semiconductor grain and a fourth semiconductor grain. The power pad of the first semiconductor grain is electrically connected to the ground pad of the second semiconductor grain, and the power pad of the third semiconductor grain is electrically connected to the ground pad of the fourth semiconductor grain.

11. A semiconductor device comprising: functional blocks, each functional block being configured to provide at least one predetermined function, The functional block at least includes: a first functional block; and A second functional block, and The first functional block and the second functional block are connected in series, and a first predetermined current flows through the first functional block and the second functional block, wherein each functional block includes a plurality of computing circuit macros connected in series, and each computing circuit macro includes a plurality of computing circuits; the first functional block includes at least a first computing circuit macro and a second computing circuit macro, and a power supply node of the first computing circuit macro is coupled to a ground node of the second computing circuit macro.

12. The semiconductor device according to claim 11, wherein Each computing circuit is configured to provide the at least one predetermined function.

13. The semiconductor device according to claim 11, wherein The power node of the first computing circuit macro and the ground node of the second computing circuit macro are at the same potential, and when powered on, the first predetermined current flows through the first computing circuit macro and the second computing circuit macro.

14. The semiconductor device according to claim 11, wherein A difference between an equivalent impedance of the first computing circuit macro and an equivalent impedance of the second computing circuit macro is less than a predetermined value.

15. The semiconductor device according to claim 11, wherein The first functional block is a first semiconductor die, the second functional block is a second semiconductor die, and the power pad of the first semiconductor die is electrically connected to the ground pad of the second semiconductor die.

16. The semiconductor device according to claim 15, wherein: Also includes: Printed circuit boards; A first chip, disposed on the printed circuit board, includes the first semiconductor crystal grain and the second semiconductor crystal grain; as well as a second chip, disposed on the printed circuit board, comprising a third semiconductor die and a fourth semiconductor die, wherein the third semiconductor die and the fourth semiconductor die are configured to provide the at least one predetermined function, and a power pad of the third semiconductor die is electrically connected to a ground pad of the fourth semiconductor die, and The power pin of the first chip is electrically connected to the ground pin of the second chip through at least one connector of the printed circuit board and / or a substrate thereon.

17. A semiconductor device, characterized in that: include: Printed circuit boards; as well as functional blocks, each functional block being arranged on the printed circuit board and configured to provide at least one predetermined function, The functional block at least includes: a first functional block; and The second functional block, The first functional block and the second functional block are connected in series, and a first predetermined current flows through the first functional block and the second functional block. At least one control signal received from the first functional block is relayed to the second functional block, wherein each functional block includes a plurality of computing circuit macros coupled in series, each computing circuit macro including a plurality of computing circuits; the first functional block includes at least a first computing circuit macro and a second computing circuit macro, a power supply node of the first computing circuit macro being coupled to a ground node of the second computing circuit macro.

18. The semiconductor device according to claim 17, wherein: Each computing circuit is configured to provide the at least one predetermined function.

19. The semiconductor device according to claim 17, wherein: The power node of the first computing circuit macro and the ground node of the second computing circuit macro are at the same potential, and when powered on, the first predetermined current flows through the first computing circuit macro and the second computing circuit macro.

20. The semiconductor device according to claim 17, wherein The first functional block is a first semiconductor die, the second functional block is a second semiconductor die, the first semiconductor die and the second semiconductor die are packaged in a semiconductor package, and the power pad of the first semiconductor chip is electrically connected to the ground pad of the second semiconductor chip.

21. The semiconductor device according to claim 20, wherein: The power pad of the first semiconductor die and the ground pad of the second semiconductor die are electrically connected to each other in the semiconductor package or through at least one connecting element on the printed circuit board.

22. The semiconductor device according to claim 20, wherein: Further including: A first chip, disposed on the printed circuit board, includes the first semiconductor crystal grain and the second semiconductor crystal grain; as well as a second chip, disposed on the printed circuit board, comprising a third semiconductor die and a fourth semiconductor die, the third semiconductor die and the fourth semiconductor die being configured to provide the at least one predetermined function, and a power pad of the third semiconductor die being electrically connected to a ground pad of the fourth semiconductor die, and The power pin of the first chip is electrically connected to the ground pin of the second chip through at least one connector of the printed circuit board and / or a substrate thereon.

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